A four-terminal addressable test circuit for large scale MOS devices

Abstract

The application relates to a four-terminal addressable test circuit for large-scale MOS devices, which comprises an address decoding circuit for generating a row address and a column address; a row addressing circuit and a column addressing circuit for receiving the row address and the column address respectively, and controlling a switch circuit to select a MOS to be tested from a plurality of MOSes to be tested according to the received address signals; the row addressing circuit and the column addressing circuit control the transmission gate to couple signals of a VG signal end, a VD signal end, a VS signal end and a VB signal end to corresponding ends of the selected MOS to be tested through corresponding switch circuits; and a sensing circuit connected to the four terminals of each MOS to be tested, for detecting actual working voltages VG SENSE , VD SENSE , VS SENSE , VB SENSE of the four terminals G, D, S and B of the selected MOS to be tested.

Description

Technical Field

[0001] This invention relates to the field of semiconductor wafer testing technology, and in particular to a four-terminal addressable test circuit for large-scale MOS devices. Background Technology

[0002] With the rapid development of the integrated circuit industry and the continuous advancement of process nodes, manufacturing processes and procedures are becoming increasingly complex, leading to a growing problem of declining yield. In the context of advanced processes, statistical fluctuations pose multiple challenges to model accuracy, primarily in areas such as device performance prediction accuracy, precise device model characterization, device reliability assessment, and circuit design optimization. To address these challenges, large-scale data measurement has become a crucial approach. By collecting massive amounts of device performance data, more precise statistical analysis of process fluctuations can be performed, helping not only identify the main sources of fluctuations but also revealing the underlying physical mechanisms. For example, by analyzing the distribution characteristics of device performance data, the most significant fluctuation factors affecting device performance can be identified, thereby guiding targeted process optimization. Based on accurate statistical modeling and large-scale dataset analysis, a deeper understanding of the impact mechanism of process fluctuations on device performance can be achieved, providing a scientific basis for process optimization and circuit design. Summary of the Invention

[0003] To address the aforementioned deficiencies and shortcomings of existing technologies, this invention provides a large-scale MOS four-terminal addressable test circuit. This circuit aims to achieve systematic and efficient testing of the electrical characteristics of distributed test devices on wafer surfaces through large-scale four-terminal addressing of MOS transistors. This solution can quickly and comprehensively acquire process deviation data from different spatial locations, providing crucial information for improving chip manufacturing yield. Simultaneously, the high-precision, high-density measured parameters acquired can be directly used for accurate calibration and verification of process models, significantly improving the accuracy of design simulation and ensuring a high degree of consistency between the final product performance and design expectations. Furthermore, compared to traditional serial testing methods, this addressable solution significantly increases test throughput and data dimensionality, providing core data support for rapid characterization of advanced processes, model iteration, and accelerated process development, forming a closed-loop technology chain from manufacturing testing to design optimization.

[0004] To achieve the above objectives, the technical solution of the present invention includes:

[0005] To achieve the above objectives, the present invention provides a large-scale MOS device four-terminal addressable test circuit, comprising:

[0006] Address decoding circuit, used to generate row address and column address;

[0007] The row addressing circuit and the column addressing circuit are used to receive the row address and the column address, respectively, and control the switching circuit according to the received address signal to select the MOS to be tested from multiple MOS to be tested;

[0008] The row addressing circuit and column addressing circuit control the transmission gate through corresponding switching circuits to couple the signals of the VG signal terminal, VD signal terminal, VS signal terminal and VB signal terminal to the corresponding terminal of the selected MOS to be tested;

[0009] The sensing circuit is connected to the four terminals of each MOS to be tested, and is used to detect the actual operating voltage VG of the four terminals (G, D, S, B) of the selected MOS to be tested. SENSE VD SENSE VS SENSE VB SENSE .

[0010] A further improvement of the present invention is that: each of the four terminals of the MOS under test is connected to the corresponding signal terminal through two transmission gates, and the two transmission gates are controlled to be turned on and off by the switching circuits corresponding to the row addressing circuit and the column addressing circuit, respectively; when the MOS under test is selected, each of its four terminals is controlled to be turned on, and the driving signals of each signal terminal (VG signal terminal, VD signal terminal, VS signal terminal and VB signal terminal) are coupled to the corresponding terminals (G, D, S and B terminals) of the selected MOS under test.

[0011] A further improvement of the present invention is that the switching circuit includes a transmission gate and a pull-down transistor.

[0012] A further improvement of the present invention is that: when the address signal is given, the pull-down transistor in the switching circuit of the selected address is turned off, the transmission gate is opened, and the input voltage is transmitted to the MOS under test; the pull-down transistor in the switching circuit of the unselected address is turned on, and the output voltage is 0.

[0013] A further improvement of the present invention is that the sensing circuit includes a transmission gate connected to the G, D, S, and B terminals of the MOS under test, to acquire and output the actual operating voltage VG. SENSE VD SENSE VS SENSE and VB SENSE .

[0014] A further improvement of the present invention is that: each of the MOS under test is integrated on a single wafer, and the wafer is provided with address PADs for inputting the row address and column address; the VG signal terminal, VD signal terminal, VS signal terminal and VB signal terminal are all PADs on the wafer; all MOS under test share the VG signal terminal, VD signal terminal, VS signal terminal and VB signal terminal to excite the selected MOS with a four-terminal input voltage.

[0015] A further improvement of the present invention is that the plurality of MOS to be tested are divided into several groups in the array, and any two groups of MOS to be tested have different width-to-length ratios.

[0016] A further improvement of this invention is that the type of the MOS to be tested includes NMOS and PMOS. Compared with the prior art, the technical solution of this invention has the following technical effects:

[0017] (1) In this invention, all paths under test share the PAD of four VG, VD, VS and VB signal terminals, which can significantly increase the number of tests per unit area.

[0018] (2) The present invention provides a circuit that allows for large-scale testing of MOS with different width-to-length ratios, and supports efficient all-round monitoring of MOS.

[0019] (3) In this invention, a sensing circuit is used to sense the voltage drop of the four terminals G, D, S and B of the MOS under test. This can accurately detect the actual terminal voltage of the G, D, S and B terminals of the MOS under test, ensuring accurate analysis of subsequent test data. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the large-scale MOS four-terminal addressable test circuit of the present invention;

[0021] Figure 2 This is a schematic diagram of the sensing circuit in this invention;

[0022] Figure 3 This is a schematic diagram of the transmission gate in the switching circuit of the present invention. Detailed Implementation

[0023] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0024] like Figure 1 As shown, an embodiment of the present invention provides a large-scale MOS four-terminal addressable test circuit, mainly composed of a decoder, addressing circuit, switching circuit, excitation circuit, sensing circuit, and array under test. The addressing circuit includes row addressing circuit and column addressing circuit. Figure 1 As shown, in this embodiment, both the row address and the column address are 4 bits. The row and column addresses are RA[0:3] and CA[0:3], respectively, which are converted into 16-bit R[0:15] and C[0:15] by a decoder, thus enabling the testing of 16×16=256 addresses.

[0025] The decoder, implemented using NAND gates, translates the row and column addresses into one-to-one corresponding addresses before transmitting them to the addressing circuit. The row and column addressing circuits are connected to the switching circuit. Furthermore, the switching circuit is also connected to the external input signal terminals VG, VD, VS, and VB. The row and column addressing circuits control the switching circuit to select the MOS to be tested from the array of multiple MOS devices under test (DUTs), applying the signals from the VG, VD, VS, and VB terminals to the G, D, S, and B terminals of that MOS, respectively. In this way, the power supply VDD and input signals of the path under test can be specified simultaneously, enabling more comprehensive multi-dimensional testing of the path under test.

[0026] like Figure 1 , Figure 2 As shown, each MOSFET under test is connected to a sensing circuit via a transmission gate controlled by a switching circuit, which is used to sense the actual voltage VG at the G, D, S, and B terminals of each MOSFET under test. SENSE VD SENSE VS SENSE VB SENSE .

[0027] Since the gate (G), drain (D), source (S), and base (B) terminals of the MOSFET under test all have varying degrees of current, the voltage drop caused by the transmission gate needs to be considered. Therefore, a sensing circuit is set up, that is, a transmission gate is connected to the gate (G), drain (D), source (S), and base (B) terminals of the MOSFET to obtain the signal VG. SENSE VD SENSE VS SENSE and VB SENSE Because the sensing circuit for measuring voltage has a high internal resistance and a low current, its transmission gate voltage drop is small. In this embodiment, each transmission gate connected between the sensing circuit and the MOS under test is also controlled by the switching circuits corresponding to the row addressing circuit and column addressing circuit. Specifically, each terminal of the MOS under test can be connected to the sensing circuit using two series dual transmission gates, and each transmission gate is controlled by two switching circuits. When the MOS under test is selected, both transmission gates at each terminal of the MOS under test are controlled to conduct, so that the voltage signal of the MOS under test is coupled to the sensing circuit. Alternatively, each terminal of the MOS under test can be connected to the sensing circuit using a single transmission gate. The control terminal of the transmission gate is connected to two switching circuits through a logic circuit. When the MOS under test is selected, the signals from the two switching circuits cause the logic circuit (AND gate) to control the corresponding transmission gate to conduct, so that the terminal voltage of the selected MOS under test is coupled to the sensing circuit.

[0028] Multiplexing a single power supply PAD and input signal PAD for each path under test can effectively improve chip area utilization. In this embodiment, multiplexing is achieved through addressing circuits and switching circuits.

[0029] Each of the MOS devices under test is integrated on a single wafer. This wafer has address PADs and four-terminal input signals VG, VD, VS, and VB (VG signal terminals, VD signal terminals, VS signal terminals, and VB signal terminals), used to select the MOS device to be tested from the MOS array and to stimulate the four-terminal input voltage of the selected MOS device. Multiplexing the four-terminal input signal PADs for each path under test can effectively improve chip area utilization. In this embodiment, multiplexing is achieved through addressing circuits and switching circuits.

[0030] like Figure 3 As shown, the switching circuit is implemented using a combination of a transmission gate and a pull-down transistor. When At that time, the pull-down tube closes and the transmission gate opens. Otherwise, the pull-down switch is active. In the addressing circuit, a row-column addressing method is used. R[0:15] and C[0:15] can each generate 16 signals. R[0:15] controls the input signals VG and VS, generating 16 sets of VG. R[i] and VS R[i] C[0:15] controls the input signals VD and VB, generating 16 sets of VD. C[j] and VB C[j] 16 VG groups R[i] VS R[i] and 16 sets of VD C[j] VB C[j] These are combined into 256 groups. When the address signal is given, the switching circuits controlled by the row addressing circuit and the column addressing circuit are driven. Both transmission gates on the four-terminal switching circuit of the MOS corresponding to the address are selected, stimulating the four-terminal input voltage of the MOS under test at the selected address: VG R[i]C[j] VS R[i]C[j] and 16 sets of VD R[i]C[j] VB R[i]C[j] Because other MOS transistors in the array under test are not selected, the transmission gate of the switching circuit is not activated, and the voltages at all four terminals are pulled down to the same potential, making it impossible to input excitation to all four terminals. At this time, the I measured by the external device... G I D I S I B This refers to the current across the four terminals of the currently selected MOS under test.

[0031] Large-scale MOS four-terminal addressable test circuits, through their precise independent addressing capabilities, enable systematic and efficient testing of the electrical characteristics of distributed test devices on wafer surfaces. This approach can quickly and comprehensively acquire process deviation data from different spatial locations, providing crucial evidence for improving chip manufacturing yield. Simultaneously, the high-precision, high-density measured parameters acquired can be directly used for precise calibration and verification of process models, significantly improving the accuracy of design simulations and ensuring a high degree of consistency between the final product performance and design expectations. Furthermore, compared to traditional serial testing methods, this addressable solution significantly increases test throughput and data dimensionality, providing core data support for rapid characterization of advanced processes, model iteration, and accelerated process development, forming a closed-loop technology chain from manufacturing testing to design optimization.

[0032] The core of this invention lies in improving the integration of the test circuit by sharing the signal ports of all units under test (DUTs) and outputting the results in digital form. Other alternatives include changing the number of DUTs, changing the number of parallel test arrays, changing the number of row and column address bits, and changing the structure of the switching circuit, all of which do not exceed the scope of protection of this invention.

[0033] The key point of this invention lies in large-scale four-terminal addressable testing of MOS transistors to monitor their output characteristics. The large-scale test circuit utilizes a switching circuit module to share the four-terminal input voltages VG, VD, VS, and VB of all MOS transistors under test, improving area utilization during rapid and accurate testing of different paths. Therefore, the point to be protected is that when performing large-scale MOS testing using the addressing method, all paths share the VG, VD, VS, and VB signals, and I... G I D I S I B Design of current-based output.

[0034] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A four-terminal addressable test circuit for large-scale MOS devices, characterized in that... include: Address decoding circuit, used to generate row address and column address; The row addressing circuit and the column addressing circuit are used to receive the row address and the column address, respectively, and control the switching circuit according to the received address signal to select the MOS to be tested from multiple MOS to be tested; The row addressing circuit and column addressing circuit control the transmission gate through corresponding switching circuits to couple the signals of the VG signal terminal, VD signal terminal, VS signal terminal and VB signal terminal to the corresponding terminal of the selected MOS to be tested; The sensing circuit is connected to the four terminals of each MOS to be tested, and is used to detect the actual operating voltage VG of the four terminals (G, D, S, B) of the selected MOS to be tested. SENSE VD SENSE VS SENSE VB SENSE .

2. The large-scale MOS device four-terminal addressable test circuit according to claim 1, characterized in that: Each of the four terminals of the MOS under test is connected to the corresponding signal terminal through two transmission gates. The two transmission gates are controlled to be turned on and off by the switching circuits corresponding to the row addressing circuit and the column addressing circuit, respectively. When the MOS under test is selected, each of its four transmission gates is turned on, and the driving signal of each signal terminal is coupled to the corresponding terminal of the selected MOS under test.

3. The large-scale MOS device four-terminal addressable test circuit according to claim 1, characterized in that: The switching circuit includes a transmission gate and a pull-down transistor.

4. The large-scale MOS device four-terminal addressable test circuit according to claim 3, characterized in that: When the address signal is given, the pull-down transistor in the switching circuit of the selected address is turned off, the transmission gate is opened, and the input voltage is transmitted to the MOS under test; the pull-down transistor in the switching circuit of the unselected address is turned on, and the output voltage is 0.

5. The large-scale MOS device four-terminal addressable test circuit according to claim 1, characterized in that: The sensing circuit includes a transmission gate connected to the G, D, S, and B terminals of the MOS under test to acquire and output the actual operating voltage VG. SENSE VD SENSE VS SENSE and VB SENSE .

6. The large-scale MOS device four-terminal addressable test circuit according to claim 1, characterized in that: Each of the MOS devices under test is integrated on a single wafer, which is provided with address PADs for inputting the row address and column address; the VG signal terminal, VD signal terminal, VS signal terminal and VB signal terminal are all PADs; All MOS devices under test share the VG, VD, VS, and VB signal terminals to provide four-terminal input voltage excitation for the selected MOS device.

7. The large-scale MOS device four-terminal addressable test circuit according to claim 1, characterized in that: The multiple MOS devices under test are divided into several groups in the array, and any two groups of MOS devices under test have different width-to-length ratios.

8. The large-scale MOS device four-terminal addressable test circuit according to claim 1, characterized in that: The types of MOS to be tested include NMOS and PMOS.

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