Pixel unit and preparation method, pixel array, image sensor and electronic device

Abstract

Embodiments of the present application provide a pixel unit and a preparation method thereof, a pixel array, an image sensor and an electronic device, comprising a photosensitive region and a transfer gate region, in a direction parallel to the substrate, the transfer gate region is located on at least two sides of the periphery of the photosensitive region and forms an electrical connection with the photosensitive region. By setting the transfer gate region on multiple sides of the photosensitive region, a more comprehensive control electric field can be formed around the photosensitive region, the electric field control capability is enhanced, the charge transfer efficiency is improved, and the lateral leakage is reduced. Moreover, the charges can be extracted from multiple directions of the photosensitive region, effectively shortening the average path length of the charges moving to the transfer gate region, thereby accelerating the overall charge transfer speed. Based on this, it is ensured that more complete charge emptying is achieved within a limited reading time, the image trailing phenomenon caused by charge residue is reduced, and the imaging quality is improved.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a pixel unit and its fabrication method, a pixel array, an image sensor, and an electronic device. Background Technology

[0002] A CIS image sensor (CMOS Image Sensor) converts incident light signals into electrical signals through a photosensitive area, thereby outputting an image.

[0003] Pixel charges need to move to the floating diffusion node for sampling under the action of an electric field. Electrons on the side away from the transmission transistor are less affected by the electric field and drift more slowly. If the pixel charge is transferred slowly within the limited time of the transmission transistor, image trailing will easily occur, affecting the imaging quality. Summary of the Invention

[0004] The pixel unit and its fabrication method, pixel array, image sensor and electronic device provided in the embodiments of this application are used to improve imaging quality.

[0005] In a first aspect, embodiments of this application provide a pixel unit, including:

[0006] Substrate;

[0007] The photosensitive area is located in the substrate;

[0008] The transmission gate region is located on at least two sides of the periphery of the photosensitive region in a direction parallel to the substrate and is electrically connected to the photosensitive region.

[0009] Optionally, the transmission gate region is disposed around the perimeter of the photosensitive region;

[0010] And / or, when the size of the pixel unit is greater than or equal to a preset size, the transmission gate region is a planar gate region; when the size of the pixel unit is less than the preset size, the transmission gate region is a vertical gate region.

[0011] And / or, the transmission gate region overlaps with the projection portion of the photosensitive region in a direction perpendicular to the substrate;

[0012] And / or, the width of the transmission gate region on the side closer to the floating diffusion region is greater than the width of the side farther from the floating diffusion region.

[0013] Optionally, it also includes: a floating diffusion region located in the substrate and electrically connected to the transmission gate region;

[0014] And / or, a clamping region, located in the substrate and covering the surface of the photosensitive region near the transmission gate region, wherein the doping type of the clamping region is different from that of the photosensitive region.

[0015] Optionally, when the size of the pixel unit is greater than or equal to a preset size, a shallow trench isolation region is further included, wherein the shallow trench isolation region is located in the substrate and between the photosensitive areas of adjacent pixel units;

[0016] When the size of the pixel unit is smaller than a preset size, it also includes a first ion-doped isolation region, which is located in the substrate and between the photosensitive areas of adjacent pixel units.

[0017] Optionally, the photosensitive region includes a second doped region and a first doped region stacked along a direction close to the transmission gate region, wherein the doping concentration of the first doped region is greater than the doping concentration of the second doped region.

[0018] Optionally, the pixel unit further includes a deep trench isolation region, which is disposed on the side of the first ion-doped isolation region away from the transmission gate region and surrounds the photosensitive region;

[0019] And / or, the pixel unit further includes: a second ion-doped isolation region located in the substrate, on the side of the shallow trench isolation region away from the transmission gate region, and surrounding the photosensitive region.

[0020] Optionally, the pixel unit includes a photodiode, and the photodiode includes the photosensitive area and the substrate;

[0021] And / or, the pixel unit further includes a transmission transistor, the transmission transistor including the transmission gate region, the photosensitive region and the floating diffusion region;

[0022] And / or, the pixel unit further includes a floating diffusion node, the floating diffusion node including the floating diffusion region.

[0023] Optionally, the pixel unit further includes a reset transistor; the drain of the reset transistor receives a power supply voltage, and the source of the reset transistor is connected to a floating diffusion node;

[0024] And / or, the pixel unit further includes a source follower amplifier; the gate of the source follower amplifier is connected to the floating diffusion node, and the drain of the source follower amplifier receives the power supply voltage;

[0025] And / or, the pixel unit further includes: a row selection transistor; the source of the row selection transistor is connected to the source of the source follower amplifier, and the drain of the row selection transistor is connected to the column bus.

[0026] Optionally, during the reset phase, the reset transistor and the source follower amplifier are controlled to be in the on state, while the transmission transistor and the row selection transistor are in the off state, so as to reset the floating diffusion node.

[0027] During the illumination integration phase, the source follower amplifier is kept on while the reset transistor, the transmission transistor, and the row selection transistor are off, so that the photodiode can perform photoelectric conversion and accumulate charge.

[0028] During the charge transfer and sampling phase, the reset transistor is kept off, while the transfer transistor, the source follower amplifier, and the row selection transistor are on to transfer the accumulated charge to the floating diffusion node and read out the voltage change of the floating diffusion node through the source follower amplifier.

[0029] Secondly, this application provides a method for fabricating a pixel unit, the method comprising:

[0030] Provide substrate;

[0031] A photosensitive area is formed in the substrate;

[0032] On the substrate, at least two sides of the periphery of the photosensitive area are formed a transmission gate region electrically connected to the photosensitive area.

[0033] Optionally, forming the photosensitive area in the substrate includes:

[0034] The photosensitive area is formed by implanting doped ions of a first conductivity type into the substrate through an ion implantation process.

[0035] And / or, the formation of a transmission gate region electrically connected to the photosensitive region on at least two sides of the periphery of the photosensitive region on the substrate includes:

[0036] A gate dielectric layer and a gate electrode material layer are sequentially formed on the surface of the substrate;

[0037] The gate dielectric layer and the gate electrode material layer are patterned and etched to form the transmission gate regions located on at least two sides of the periphery of the photosensitive area;

[0038] And / or, the method further includes: after forming the photosensitive region and before forming the transmission gate region, implanting doped ions of a second conductivity type into a surface region of the photosensitive region near the transmission gate region by an ion implantation process to form a clamping region, wherein the doping type of the clamping region is different from that of the photosensitive region;

[0039] And / or, the method further includes: implanting doped ions of a first conductivity type into the substrate by an ion implantation process to form a floating diffusion region electrically connected to the transport gate region;

[0040] And / or, the method further includes: implanting doped ions of a second conductivity type into a region between photosensitive areas in the substrate via an ion implantation process to form a first ion-doped isolation region.

[0041] Thirdly, this application provides a pixel array comprising a plurality of pixel units as described in the first aspect, or a plurality of pixel units prepared by the preparation method described in the second aspect.

[0042] Optional, also includes:

[0043] Ion-doped regions are located between adjacent pixel units and are used to isolate pixel units;

[0044] And / or, multiple pixel units share a floating diffusion region.

[0045] Fourthly, this application provides an image sensor, comprising: the pixel unit described in the first aspect, or the pixel unit prepared in the second aspect, or the pixel array described in the third aspect.

[0046] Fifthly, this application provides an electronic device including the image sensor described in the fourth aspect.

[0047] The pixel unit and fabrication method, pixel array, image sensor, and electronic device provided in this application include a photosensitive area and a transfer gate area. In a direction parallel to the substrate, the transfer gate area is located on at least two sides of the periphery of the photosensitive area and forms an electrical connection with it. By providing transfer gate areas on multiple sides of the photosensitive area, a more comprehensive control electric field can be formed around the photosensitive area, enhancing electric field control capability, improving charge transfer efficiency, and reducing lateral leakage. Furthermore, charge can be extracted from multiple directions of the photosensitive area, effectively shortening the average path length of charge movement to the transfer gate area, thereby accelerating the overall charge transfer speed. Based on this, more thorough charge clearing is ensured within a limited readout time, reducing image trailing caused by charge residue and improving imaging quality. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0049] Figure 1 This is a circuit diagram of a pixel unit;

[0050] Figure 2 This is a top-view diagram of the pixel unit structure;

[0051] Figure 3 This is a schematic diagram of charge transport.

[0052] Figure 4 A top view of the pixel unit provided in this application;

[0053] Figure 5 for Figure 4 A schematic diagram of the longitudinal section along the A-A' direction and the transverse section along the B-B' direction;

[0054] Figure 6 Cross-sectional view of the pixel unit provided in this application Figure 1 ;

[0055] Figure 7 Schematic diagram of charge transfer in pixel unit provided in this application Figure 1 ;

[0056] Figure 8 Schematic diagram of the cross-sectional structure of the pixel unit provided in this application Figure 2 ;

[0057] Figure 9 Schematic diagram of charge transfer in pixel unit provided in this application Figure 2 ;

[0058] Figure 10 Schematic diagram of charge transfer in pixel unit provided in this application Figure 3 ;

[0059] Figure 11 Schematic diagram of the pixel unit fabrication method provided in this application Figure 1 ;

[0060] Figure 12 Schematic diagram of the pixel unit fabrication method provided in this application Figure 2 ;

[0061] Figure 13 Potential diagrams of the photosensitive area and the buoyancy diffusion area provided in this application;

[0062] Figure 14 This is a schematic diagram of the pixel array provided in this application.

[0063] Figure label:

[0064] 1-Photosensitive area; 2-Transmission gate area; 3-Floating diffusion area; 4-Shallow trench isolation area; 5-Substrate; 6-Clamping area; 7-Deep trench isolation area; 8-First ion-doped isolation area; 9-Second ion-doped isolation area.

[0065] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0066] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0067] A CIS image sensor (CMOS image sensor) converts incident light signals into electrical signals through a photosensitive area, thereby outputting an image. The photosensitive area is the photodiode within the pixel unit.

[0068] Traditional pixel units consist of a 4T structure comprised of a photosensitive photodiode and four transistors, such as... Figure 1 and Figure 2 As shown.

[0069] During the exposure process at a pixel unit, a photodiode collects photons and converts them into photoelectrons. Then, a transfer transistor turns on to perform pixel charge transfer, moving electrons from the photodiode to a floating diffusion (FD) sampling node. The floating sampling node samples the electronic signal. The sampled electronic signal is amplified into a voltage signal by a source follower and then output to the circuitry for processing into an image signal. Therefore, the pixel charge transfer stage plays a fundamental role in the final output image signal.

[0070] Ideally, electrons in the photodiode are completely transferred to the floating sampling node within the reset time. In practical operation, such as... Figure 3 As shown, when the transfer gate transistor is turned on for charge transfer, photoelectrons near the transfer gate region in the photosensitive area are preferentially transferred to the floating diffusion region. Photoelectrons on the other side or bottom of the photosensitive area, far from the transfer gate region, need to first move to a region near the transfer gate region via a potential gradient, and then transfer to the floating diffusion region through the transfer gate region. When the photosensitive area is large and the signal readout time is short, the transfer rate of electrons far from the transfer gate region and at the bottom of the photosensitive area is slow, making incomplete charge transfer more likely. This results in electrons remaining in the photosensitive area, causing image lag and affecting image quality.

[0071] To address this, this application proposes a pixel unit in which the transfer gate region is located on at least two sides of the photosensitive area, forming an electrical connection with the photosensitive area. By setting the transfer gate region on multiple sides of the photosensitive area, a more comprehensive control electric field can be formed around the photosensitive area, enhancing the electric field control capability, improving charge transfer efficiency, and reducing lateral leakage. Furthermore, charge can be extracted from multiple directions of the photosensitive area, effectively shortening the average path length of charge movement to the transfer gate region, thereby accelerating the overall charge transfer speed. Based on this, more thorough charge clearing is ensured within a limited readout time, reducing image trailing caused by charge residue and improving image quality.

[0072] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0073] Figure 4 and Figure 5 This is a schematic diagram of the structure of the pixel unit provided in this application. Figure 4 This is a top-view diagram of the pixel unit structure. Figure 5 for Figure 4 The longitudinal cross-section along the A-A' direction and the transverse cross-section along the B-B' direction, as shown... Figure 4 and Figure 5 As shown, the pixel unit includes:

[0074] Substrate 5;

[0075] Photosensitive area 1 is located in substrate 5;

[0076] The transmission gate region 2 is located on at least two sides of the periphery of the photosensitive region 1 in a direction parallel to the substrate 5 and is electrically connected to the photosensitive region 1.

[0077] In this embodiment, the photosensitive area 1 generates photogenerated charge based on the photoelectric effect after receiving incident photons, thereby realizing the conversion of optical signals into electrical signals and providing a signal source for subsequent image information acquisition.

[0078] By providing transfer gate regions 2 on at least two sides of the photosensitive area 1, a more comprehensive control electric field can be formed around the photosensitive area 1, thereby enhancing the electric field modulation capability and improving charge transfer efficiency. This structure supports the simultaneous extraction of charge from multiple directions of the photosensitive area 1, effectively shortening the average path length of charge movement to the transfer gate region 2, and thus accelerating the overall charge transfer speed.

[0079] In addition, after the charge transfer is completed, the transistor is turned off to a negative voltage state, which on the one hand shuts off the transmission channel between the photosensitive area and the floating diffusion area, and on the other hand, the transistors between adjacent pixels form electrical isolation under negative voltage to prevent lateral leakage of adjacent photosensitive areas.

[0080] Based on the above design, more thorough charge clearing can be achieved within a limited reading time, reducing image trailing caused by residual charge and ultimately improving image quality.

[0081] For example, substrate 5 can be a semiconductor substrate, such as a silicon substrate, a silicon carbide substrate, etc. The substrate can have a first conductivity type, such as a P-type substrate. In other examples, the substrate can also be an N-type substrate, or an epitaxial layer with a specific doping concentration formed by epitaxial growth on a base substrate.

[0082] For example, the photosensitive region 1 can be formed by performing an ion implantation or diffusion process on the substrate 5 to create a doped region with a second conductivity type. For instance, in a P-type substrate, an N-type doped region is formed as the photosensitive region 1 by implanting N-type impurities such as phosphorus or arsenic, thereby forming a PN junction photodiode with the surrounding P-type region. The doping concentration, junction depth, and lateral dimensions of the photosensitive region 1 can be designed according to the performance requirements of the pixel, such as photosensitivity and full-well capacity.

[0083] For example, the photosensitive area 1 can be a regular shape or an irregular shape.

[0084] For example, the transfer gate region 2 includes a gate dielectric layer and a gate electrode thereon. The gate dielectric layer may include silicon oxide, silicon nitride, a high-k dielectric material (such as hafnium oxide, aluminum oxide), or a stacked structure thereof, formed on the substrate surface and / or trench sidewalls. The gate electrode may include polysilicon, a metal (such as titanium, tungsten, aluminum), or a silicide thereof, or a metal nitride.

[0085] The transfer gate region 2, in a direction parallel to the substrate 5, can be specifically implemented as two discrete gates located on opposite sides of the photosensitive region 1, or an L-shaped gate located on adjacent sides of the photosensitive region 1, or a U-shaped gate surrounding three or more sides of the photosensitive region 1, or a closed ring gate structure. When the voltage applied to the gate electrode exceeds a threshold, a conductive channel is formed below the edge of the photosensitive region 1 to control charge transfer.

[0086] In some embodiments, such as Figure 4 and Figure 5 As shown, the transfer gate region 2 is disposed around the photosensitive region 1. By adopting a full-circle surround structure, the electric field control of the photosensitive region 1 can be maximized and homogenized, so that the charge at any position within the photosensitive region 1 can be extracted by the nearest gate region along the shortest and substantially equal path, such as... Figure 7As shown, this design significantly improves the consistency of charge transfer in different directions, helping to reduce intra-pixel response inhomogeneity caused by differences in the transfer path, thereby effectively improving image uniformity and reducing fixed pattern noise. Furthermore, the surrounding structure physically forms a complete "fence," maximally confining the signal charge within photosensitive area 1 and preventing its diffusion to adjacent pixels or device areas. When the transistor is turned off to a negative voltage state after charge transfer is complete, it prevents lateral leakage from adjacent photosensitive areas, further suppressing lateral leakage.

[0087] In other embodiments, the transmission gate region 2 may also be located on both sides, three sides, or the periphery of the photosensitive region 1.

[0088] In some examples, when the size of the pixel unit is greater than or equal to a preset size, the transfer gate region 2 is a planar gate region (PTG). In this case, the transfer gate region 2 is located on the surface of the substrate 5, such as... Figures 4-6 As shown.

[0089] For pixel arrays with a large photosensitive area 1, the transfer gate region 2 can be disposed on at least both sides of the photosensitive area 1, for example, arranged around the photosensitive area 1. When the transfer gate transistor is turned on, the all-around gate structure can form a more uniform electric field distribution, thereby accelerating charge transfer and enabling electrons to migrate to the nearest transfer gate region 2 in a shorter integration time, and then transfer to the floating diffusion region 3. This helps to prevent electrons far from the gate region from remaining in the photosensitive area 1 due to incomplete transfer. When the transfer gate transistor is turned off, a negative voltage is applied to the transfer gate region 2, which can form a negative potential around the photosensitive area 1, further enhancing electrical isolation and optimizing crosstalk between the floating diffusion regions 3.

[0090] In other examples, when the size of the pixel unit is smaller than a preset size, the transfer gate region 2 is a vertical transfer gate (VTG). In this case, the transfer gate region 2 is not only located on the surface of the substrate 5, but also extends at least partially along the sidewall of the photosensitive region 1 in a direction perpendicular to the substrate 5, such as... Figure 8 As shown, Figure 8 (a) in the image is a longitudinal cross-sectional view of a pixel unit along the AA' direction. Figure 8 (b) in the figure is a cross-sectional view of the pixel unit along the BB' direction.

[0091] For pixel arrays with a small photosensitive area 1, a 4 PDshare-FD (Tetracell) structure is typically used, where four pixels share a single floating diffusion region 3, to increase the photosensitive area and aperture ratio, and to extend the dynamic range (HDR) using dual conversion gain. As pixel size shrinks, photosensitive area 1 needs to store more electrons vertically to improve full well capacity (FWC), but the size of the transfer transistor TX is limited, resulting in insufficient horizontal charge transfer efficiency and difficulty in fully transferring electrons deep within photosensitive area 1. To improve charge transfer capability, small pixels can employ a vertical transfer gate structure, allowing charge to transfer vertically from photosensitive area 1 to floating diffusion region 3, such as... Figure 11 As shown.

[0092] Traditional vertical transfer gate structures typically place the vertical gate only on one side between the photosensitive region 1 and the floating diffusion region 3. This can lead to uneven charge transfer and incomplete transfer during the reset time as charge migrates from the deeper layers of the photosensitive region 1 to the gate. In this example, vertical gates are placed on at least two sides of the photosensitive region 1, for example, vertical gates are placed around the entire periphery of the photosensitive region 1, forming an enclosed layout. The portion of the vertical gate embedded in the silicon substrate is vertically planar, and the side closest to the floating diffusion region 3 can be either a vertical planar surface or a vertical aperture. Before etching the silicon substrate and depositing polysilicon, ions with the opposite doping type to those in the photosensitive region 1 can be implanted in the etched area (e.g., if the photosensitive region 1 is N-type, P-type ions are implanted). High-concentration inversion ions are used to isolate the polysilicon gates of adjacent photosensitive regions 1, while no such ion implantation is performed inside the photosensitive region 1. Applying a negative voltage to the vertical gate during integration simultaneously achieves electrical isolation above adjacent photosensitive regions 1.

[0093] It should be noted that when the size of a pixel unit is greater than or equal to the preset size, the pixel unit can be called a large pixel, and when the size of a pixel unit is less than the preset size, the pixel unit can be called a small pixel.

[0094] For example, the preset size can be 1.4µm, or it can be determined according to the actual situation of the pixel unit.

[0095] For example, for small-sized pixel units, the charge storage capacity (full-well capacity) is limited due to the reduced physical size of the photosensitive region 1. This can be addressed by employing deep trench or deep ion implantation processes to perform deeper N-type doping in the depth direction of the substrate 5, thereby forming a photosensitive region 1 with a significantly increased vertical dimension. This approach greatly expands the depletion region in the vertical direction within a limited lateral area, effectively improving the full-well capacity of the pixel unit and alleviating the trade-off between miniaturization and dynamic range.

[0096] To match the aforementioned vertically extended photosensitive area structure and to address the issues of low charge transport efficiency and residue buildup in deep regions, the transfer transistor is designed as a vertical gate structure. Specifically, the transfer gate region 2 extends vertically along the sidewall of the photosensitive area 1, forming a three-dimensional gate structure surrounding at least a portion of the sidewall of the photosensitive area 1.

[0097] When an on-state voltage (e.g., 3.3V) is applied to the vertically surrounding gate, its surrounding structure synchronously generates a uniform electric field distribution along the longitudinal depth and lateral periphery of the photosensitive area 1. This uniform electric field can effectively exert a longitudinal traction force on the photogenerated charges stored at different depths in the photosensitive area 1, driving the charges to transfer rapidly and synchronously from the deep region to the shallow region and finally to the floating diffusion region 3. This three-dimensional global charge collection mechanism significantly reduces the risk of incomplete charge transfer due to uneven electric field coverage or insufficient intensity, thereby effectively suppressing image ghosting.

[0098] Optionally, the pixel unit also includes a floating diffusion region 3 (FD), which is located in the substrate 5 and electrically connected to the transfer gate region 2. The floating diffusion region 3 is electrically connected to the photosensitive region 1 (typically a photodiode PD) through the transfer gate region 2. When the transfer gate is turned on, the photogenerated charge accumulated in the photosensitive region 1 is transferred to the floating diffusion region 3, and the voltage of the floating diffusion region 3 changes linearly with the amount of injected charge. This voltage change is read and amplified by a subsequent source follower amplifier, thereby converting the optical signal (charge) into a measurable electrical signal (voltage).

[0099] In some embodiments, such as Figure 6 As shown, when the size of the pixel unit is greater than or equal to a preset size, i.e., for large pixels, the pixel unit also includes a shallow trench isolation region 4. The shallow trench isolation region 4 is formed in the substrate 5 and located between the photosensitive areas 1 of the pixel unit, so as to electrically isolate the photosensitive areas 1 from adjacent pixel units. The shallow trench isolation region 4 can prevent the photogenerated charge generated by the photosensitive area 1 of this pixel from diffusing to the photosensitive area 1 or circuit area of ​​adjacent pixels, thereby effectively preventing charge leakage between adjacent pixels.

[0100] In other embodiments, such as Figure 8 As shown, when the pixel unit size is smaller than a preset size, i.e., for small-sized pixels, the pixel unit also includes a first ion-doped isolation region 8. The first ion-doped isolation region 8 is located in the substrate 5 and between the photosensitive areas 1 of adjacent pixel units. The first ion-doped isolation region 8 is a doped isolation region formed by ion implantation. In small-sized pixels, using ion-doped isolation instead of shallow trench isolation (STI) can avoid the additional dark current introduced by the interface defects of the sidewalls of shallow trench isolation, thereby improving the signal-to-noise ratio of the pixel.

[0101] For example, the first ion-doped isolation region 8 can be a highly concentrated P-type doped region (P+ isolation well), which can overlap with a portion of the channel region below the surrounding transmission gate region 2. When the transmission transistor TX is off, this overlapping structure helps maintain the potential barrier between adjacent pixel photosensitive regions 1 at a higher level, thereby more effectively suppressing charge leakage (i.e., electrical crosstalk) between pixels.

[0102] In some examples, such as Figure 8 As shown, for large-size pixels, the pixel unit also includes a deep trench isolation region 7. The deep trench isolation region 7 is disposed on the side of the first ion-doped isolation region 8 away from the transmission gate region 2 and surrounds the photosensitive region 1. The deep trench isolation region 7 provides a physical insulation barrier for the main body, achieving excellent electrical isolation.

[0103] In other examples, such as Figure 6 As shown, for small-sized pixels, the pixel unit also includes a second ion-doped isolation region 9, which is located in the substrate and on the side of the shallow trench isolation region 4 away from the transmission gate region 2, and surrounds the photosensitive region 1.

[0104] Based on the above embodiments, for large pixels, a shallow trench isolation region 4 and a second ion-doped isolation region 9 are formed connected in the depth direction of the substrate; for small pixels, a first ion-doped isolation region 8 and a deep trench isolation region 7 are formed connected in the depth direction of the substrate, thereby creating a non-uniform doping concentration distribution in the depth direction of the substrate 5. The isolation regions closer to the surface have a higher doping concentration to form a strong potential barrier in the shallow region (typically corresponding to the charge collection region of the photosensitive region 1) to isolate adjacent pixels; while the isolation regions below have a relatively lower doping concentration to provide necessary isolation in deeper regions, while avoiding excessive doping that could adversely affect the depletion region width and capacitance of the photosensitive region 1. This gradient doping structure optimizes the full-well capacity and photoelectric properties of the pixel while ensuring effective electrical isolation.

[0105] For example, the pixel unit includes a third ion-doped isolation region surrounding the photosensitive region 1. The projections of the third ion-doped isolation region and the deep trench isolation region 7 in the direction perpendicular to the substrate 5 at least partially overlap, for example, the third ion-doped isolation region surrounds the deep trench isolation region 7.

[0106] The third ion-doped isolation region can effectively passivate the interface defects introduced by deep trench etching, suppress the resulting dark current and noise, and at the same time help adjust the potential near the channel, stabilize the electron transport channel under the vertical gate transistor, and smooth the vertical transport potential.

[0107] Optional, such as Figure 6As shown, the photosensitive area 1 includes a first doped region (e.g., [missing information]) stacked in a depth direction perpendicular to the substrate 5. Figure 6 N+ in the middle) and the second doped region (such as Figure 6 The first doped region is closer to the transport gate region 2 than the second doped region, and the doping concentration of the first doped region is higher than that of the second doped region. This concentration gradient forms a built-in electric field pointing towards the transport gate region 2 within the photosensitive region 1, thereby assisting the directional drift of photogenerated charges towards the transport gate region 2, further improving charge transport efficiency and speed.

[0108] Optional, such as Figure 6 As shown, the pixel unit also includes a clamping region 6, which is formed in the substrate 5 and covers the upper surface of the photosensitive region 1 near the transmission gate region 2. The doping type of the clamping region 6 is opposite to that of the photosensitive region 1, and its doping concentration is higher than that of the photosensitive region 1.

[0109] By setting a clamping region 6 that forms a PN junction with the photosensitive region 1, a built-in electric field pointing towards the interior of the substrate 5 can be established on the surface of the photosensitive region 1. This electric field can effectively repel minority carriers in the photosensitive region 1 from moving to the interface region with high defect density, thereby significantly suppressing the dark current caused by interface state generation and recombination, and thus improving the signal-to-noise ratio, dynamic range and low-light imaging performance of the pixel unit.

[0110] For example, the clamping region 6 at least partially overlaps with the transfer gate region 2 in a direction perpendicular to the surface of the substrate 5. This overlapping structure helps to optimize the continuity of the surface potential below the transfer gate, ensuring that the potential barrier on the charge transport path is effectively controlled.

[0111] Optionally, the projection of the transfer gate region 2 onto the photosensitive region 1 in the direction perpendicular to the substrate 5 partially overlaps with that of the corresponding area of ​​the photosensitive region 1. In other words, from a top-down view, the transfer gate region 2 not only surrounds the periphery of the photosensitive region 1, but its inner edge also extends upwards and covers a portion of the photosensitive region 1.

[0112] This overlapping structure is the electrical basis for ensuring the formation of an effective charge transport channel. By controlling the voltage of the transport gate region 2, an inversion layer or a strong accumulation layer can be formed beneath it, on the surface of the photosensitive region 1, thereby constructing a low-resistance conductive path connecting the photosensitive region 1 and the floating diffusion region 3. Without this overlap, the gate electric field cannot effectively modulate the charge at the edge of the photosensitive region 1, which may lead to failure of the transport function or low efficiency.

[0113] Optionally, the transmission gate region 2 is configured to have a non-uniform lateral width. Specifically, in the gate structure surrounding the photosensitive region 1, the width of the portion of the gate closest to the floating diffusion region 3 is designed to be greater than or equal to the width of the other portions of the gate.

[0114] Because the photogenerated charges overflowing from various points within photosensitive area 1 must ultimately converge and pass through the channel below the gate closest to floating diffusion area 3 before entering floating diffusion area 3, widening this final exit channel is equivalent to increasing its cross-sectional area, thereby significantly reducing the series resistance at the end of the charge transport path. This design effectively alleviates the charge congestion effect at the end of the transport path, improving the overall charge transfer speed and efficiency, and is particularly beneficial for large pixels or rapid clearing under high illumination.

[0115] Optional, such as Figure 1 As shown, the pixel unit includes a photodiode PD, which includes a photosensitive area 1 and a substrate 5; the floating diffusion node includes a floating diffusion area 3, that is, the floating diffusion area 3 serves as a floating diffusion node.

[0116] Photosensitive region 1 is the core area for photodiode (PD) to achieve photon-to-electron conversion. Incident light is absorbed by the semiconductor material in photosensitive region 1, and valence band electrons gain energy to transition to the conduction band, generating electron-hole pairs. Under the influence of the built-in electric field in the depletion region, electrons and holes are rapidly separated and drift towards the poles, forming a photocurrent. Substrate 5 forms a PN junction with photosensitive region 1, providing a built-in electric field for photosensitive region 1. Simultaneously, substrate 5 leads out electrodes (back electrodes) to guide the separated charge carriers from photosensitive region 1, forming a complete circuit loop.

[0117] Optionally, the pixel unit includes a transfer transistor TX, which is connected to a photodiode PD. For example, the source of the transfer transistor TX is connected to the cathode of the photodiode PD. The transfer transistor TX includes a transfer gate region 2, a photosensitive region 1, and a floating diffusion region 3. The transfer transistor TX acts as a switch between the photodiode PD and the signal readout circuit, enabling stable storage of charge during exposure and efficient transfer of charge after exposure.

[0118] For example, the photodiode PD continuously generates photoelectrons (signal charge) under illumination and stores them in its depletion region (this stage is the exposure period). When the transmission transistor TX is not turned on (low voltage applied to the gate), the channel between its source (connected to the cathode of the photodiode PD) and drain (connected to the floating diffusion region 3) is in a cut-off state, which prevents the charge stored in the photodiode PD from leaking into the floating diffusion region 3 or the substrate 5 in advance, ensuring that the charge is generated only by illumination and completely corresponds to the exposure amount of the pixel, thus avoiding signal distortion.

[0119] After exposure, the charge stored in the photodiode PD needs to be read out and converted into an electrical signal. This is achieved by applying a high voltage to the gate of the transfer transistor TX, turning it on. Once TX is on, a conductive channel forms between its source and drain, creating a potential difference between the photodiode PD and the floating diffusion region 3 (typically, the floating gate transistor is pre-charged to a high potential by the reset transistor RST). Under the influence of the electric field, photogenerated electrons stored in the photodiode PD are rapidly and completely transferred along the channel to the floating gate transistor. By controlling the timing of the gate voltage (synchronized with the exposure and readout timing of the entire pixel unit), the charge transfer of all pixels is ensured to proceed in an orderly manner, avoiding charge crosstalk between different pixels.

[0120] In some examples, the pixel unit includes a plane transfer gate (PTG) transistor, which includes a plane gate region (i.e., the aforementioned transfer gate region 2 is a plane gate region), a photosensitive region 1, and a floating diffusion region 3.

[0121] In other examples, the pixel unit includes a vertical transfer gate (VTG) transistor, which includes a vertical gate region (i.e., the aforementioned transfer gate region 2 is a vertical gate region), a photosensitive region 1, and a floating diffusion region 3.

[0122] It should be noted that both planar transfer gate transistors and vertical transfer gate transistors are four-terminal devices. In addition to the substrate 5 end, they also include the source terminal (i.e., photosensitive area 1), the gate terminal (i.e., gate region), and the drain terminal (i.e., floating diffusion region 3) connected to the photodiode PD.

[0123] Optionally, the pixel unit also includes a reset transistor RST (Reset Gate, RST), the drain of which receives the power supply voltage, and the source of which is connected to a floating diffusion node.

[0124] One end of the reset transistor RST is coupled to the power supply voltage. Its main function is to reset the voltage of the floating diffusion node according to the reset control signal. Before each exposure, the reset transistor RST is turned on to clear the residual charge on the floating diffusion node, restoring the voltage of the node to its initial state, thus preparing for the accurate accumulation and measurement of photogenerated charge during the next exposure.

[0125] Optionally, the pixel unit also includes a source follower amplifier (SF) and a row select transistor (SEL). The gate of the source follower amplifier (SF) is connected to a floating diffusion node, and the drain of the source follower amplifier (SF) receives the power supply voltage. The source of the row select transistor (SEL) is connected to the source of the source follower amplifier (SF), and the drain of the row select transistor (SEL) is connected to the column bus.

[0126] The source follower amplifier (SF) is used to buffer and amplify the voltage signal of the floating diffusion node in the pixel unit and achieve impedance conversion. It can convert the high impedance input signal into a low impedance output, improve the signal driving capability, so as to better match the subsequent circuits, and reduce the attenuation and distortion during signal transmission, so that the signal can be transmitted to the subsequent circuits more efficiently.

[0127] The row selection transistor (SEL) is used to select a specific row of pixels for readout. When the row selection signal is active, the SEL is turned on, allowing the signal output from the source follower amplifier (SF) to be transmitted to the column bus, where it is then acquired and processed by the subsequent readout circuitry. When the row selection signal is inactive, the transistor is turned off, and the corresponding row of pixels is disconnected from the column bus and does not participate in the current signal transmission.

[0128] The branch consisting of the source follower amplifier (SF) and the row selection transistor (SEL) buffers and impedance-matches the signal generated by the pixel unit, improving signal quality and driving capability. Then, the row selection transistor (SEL) selects the appropriate pixel row as needed, accurately transmitting the signal to the column bus. This ensures signal stability and accuracy during transmission, facilitating subsequent circuitry for further amplification, analog-to-digital conversion, and other processing of the specific pixel signal, thereby achieving correct image signal acquisition and imaging.

[0129] Optionally, during the reset phase, the reset transistor RST and the source follower amplifier SF are turned on, while the transfer transistor TX and the row selection transistor SEL are turned off to reset the floating diffusion node. During the illumination integration phase (i.e., the exposure phase), the source follower amplifier SF is kept on, while the reset transistor RST, transfer transistor TX, and row selection transistor SEL are turned off to enable the photodiode PD to perform photoelectric conversion and accumulate charge. During the charge transfer and sampling phase, the reset transistor RST is kept off, while the transfer transistor TX, source follower amplifier SF, and row selection transistor SEL are turned on to transfer the accumulated charge to the floating diffusion node and read out the voltage change of the floating diffusion node through the source follower amplifier SF. Based on this, photoelectric conversion can be achieved.

[0130] For example, firstly, the floating diffusion node is reset to a preset high potential (such as the power supply voltage VDD) by turning on the reset transistor RST to clear its stored charge. At the same time, the transfer transistor TX is in the off state, ensuring that the photodiode PD enters a defined initial state.

[0131] During the exposure integration phase: The transfer transistor TX is kept off. Under illumination, electron-hole pairs are continuously generated inside the photodiode PD, where photogenerated electrons (as signal charges) are collected and stored in their depletion region. During this phase, the effective off-state of the transfer transistor TX prevents any leakage of charge to the floating diffusion node, ensuring a strict correspondence between the integrated charge and the exposure amount.

[0132] During the charge transfer and readout stage: After exposure, an enable voltage is applied to the surrounding transfer gate, turning on the transfer transistor TX. Since the transfer gate region 2 surrounds the photosensitive region 1, it simultaneously forms a uniform lateral electric field in multiple directions around the photosensitive region 1. Under the action of this uniform electric field, photogenerated electrons stored throughout the photosensitive region 1 are simultaneously and rapidly driven towards the floating diffusion node at the center (or in a specified direction), achieving efficient and global charge collection and transfer. This process significantly improves charge transfer efficiency and minimizes charge residue within the photosensitive region 1 after transfer.

[0133] Subsequently, the transfer transistor TX is turned off. For example, a negative bias can be applied to its gate to put it in a deep off state. This negative bias state creates a higher barrier in the channel region between the photodiode PD and the floating diffusion node, ensuring complete electrical isolation between them, preventing any leakage during integration or storage, and further strengthening the electrical isolation between pixels by expanding the depletion region induced by the negative bias between adjacent pixel units. This effectively suppresses charge leakage (i.e., dark current crosstalk) between photosensitive areas of adjacent pixels caused by thermal excitation or edge electric fields, thereby improving image purity and color fidelity.

[0134] For example, such as Figure 9 and Figure 10 As shown, for the vertical transfer gate transistor (VTMT): when the VTMT is turned on, its three-dimensional gate structure surrounding the sidewall of the photosensitive region forms a uniform and strong vertical electric field across the entire longitudinal depth of the photosensitive region 1. This electric field can generate a direct longitudinal traction force on the photogenerated electrons stored deep within the photosensitive region 1, driving them to rapidly and synchronously transfer to the floating diffusion node along the gate sidewall direction. This significantly improves the efficiency of collecting charge from the deep depletion region and reduces the risk of image lag.

[0135] After charge transfer is complete, a negative bias voltage is applied to the gate of the vertical transfer gate transistor, putting it into a deep off state. This negative bias voltage effectively raises the potential barrier of the potential parasitic channel region formed by the vertical gate sidewalls between adjacent pixel photosensitive areas 1, thereby completely shutting off the parasitic transistor path. This fundamentally prevents lateral charge leakage through the gate sidewalls and significantly optimizes the level of dark current crosstalk between pixels. Through the modulation of the negative bias voltage, the potential barrier between adjacent photosensitive areas 1 is always higher than the potential barrier between the current pixel photosensitive area 1 and the floating diffusion node.

[0136] Therefore, when excessive photocharge is generated in photosensitive area 1 due to overexposure, this excess charge will preferentially be discharged to the floating diffusion node through the transmission channel of this pixel, rather than overflowing to adjacent pixels. This mechanism effectively suppresses the overflow phenomenon in highlight scenes and improves the dynamic range and highlight reproduction capability of the image.

[0137] The pixel unit provided in this application embodiment has a transmission gate region 2 located on at least two sides of the periphery of the photosensitive region 1, forming an electrical connection with the photosensitive region 1. By providing transmission gate regions 2 on multiple sides of the photosensitive region 1, a more comprehensive control electric field can be formed around the photosensitive region 1, enhancing the electric field control capability, improving charge transfer efficiency, and reducing lateral leakage. Furthermore, charge can be extracted from multiple directions of the photosensitive region 1, effectively shortening the average path length of charge movement to the transmission gate region 2, thereby accelerating the overall charge transfer speed. Based on this, more thorough charge clearing is ensured within a limited reading time, reducing image trailing caused by charge residue and improving imaging quality.

[0138] Figure 11 and Figure 12 A schematic diagram illustrating the manufacturing method of the pixel unit provided in this application, as shown below. Figure 11 and Figure 12 As shown, the manufacturing method provided in this application includes:

[0139] S101, Provide substrate 5.

[0140] For example, a semiconductor substrate, such as a P-type silicon substrate, is provided.

[0141] Optionally, an epitaxial layer with the same or different doping types can be grown on the substrate 5.

[0142] S102, A photosensitive area 1 is formed in the substrate 5.

[0143] Optionally, doped ions of a first conductivity type are implanted into the substrate 5 via an ion implantation process to form the photosensitive region 1.

[0144] For example, using photoresist as a barrier layer, N-type impurities are implanted into a predetermined area by ion implantation to form photosensitive area 1.

[0145] For example, for small-sized pixels, after the photosensitive area 1 is formed, a first ion-doped isolation area 8 can be formed between the photosensitive areas 1 of adjacent pixel units.

[0146] Optionally, by means of an ion implantation process, doped ions of a second conductivity type are implanted into the region between the photosensitive regions 1 in the substrate 5 to form a first ion-doped isolation region 8.

[0147] For example, using photoresist as a mask, doped ions of a second conductivity type (e.g., P-type) are implanted into the region surrounding the photosensitive region 1 to form a P-type isolation well. Multiple implantations at different depths and concentrations can be performed to form an isolation region 4 with a gradient doping concentration.

[0148] Optionally, for small pixels: To maximize the area of ​​the photosensitive region 1 while achieving effective isolation, deep trench isolation can be used. Specifically, deep trenches are etched in the region between adjacent pixel units, followed by doping on the inner walls of the trenches, and finally the trenches are filled with an insulating material (such as oxide).

[0149] The shallow isolation region 4, traditionally located on the side of photosensitive region 1, is moved between the surrounding gates of adjacent pixels. The traditional deep P-type isolation implantation is eliminated, and deep trench isolation is used instead to suppress deep crosstalk. P-type ion implantation, performed after trench etching and before filling in the deep trench isolation, serves as electrical isolation between adjacent photosensitive regions 1; it also passivates the trench sidewalls, suppressing dark current and noise introduced by etching defects; and it stabilizes the channel potential beneath the subsequently formed vertical gate transistor.

[0150] Optionally, after forming the photosensitive region 1, a high-concentration doped ions of a second conductivity type are implanted into the surface region of the photosensitive region 1 near the transmission gate region 2 via an ion implantation process to form a clamping region 6. The doping type of the clamping region 6 is different from that of the photosensitive region 1. This clamping region 6 and the photosensitive region 1 form a PN junction to suppress surface dark current.

[0151] Optionally, doped ions of a first conductivity type (e.g., N-type) are implanted at predetermined locations in the substrate 5 via an ion implantation process to form a floating diffusion region 3 electrically connected to the transport gate region 2.

[0152] S103. On the substrate 5, at least two sides of the periphery of the photosensitive region 1 are formed, and the transmission gate region 2 is electrically connected to the photosensitive region 1.

[0153] Optionally, a gate dielectric layer and a gate electrode material layer are sequentially formed on the surface of the substrate 5; the gate dielectric layer and the gate electrode material layer are patterned and etched to form a transmission gate region 2 located on at least two sides of the periphery of the photosensitive region 1.

[0154] For example, after forming the photosensitive area 1, a polysilicon gate is deposited, and a ring-shaped polysilicon gate structure is etched using photoresist as a barrier layer.

[0155] This application also provides a pixel array comprising a plurality of the pixel units described above, or a plurality of pixel units prepared by the preparation method described above.

[0156] It should be noted that, due to the clamping effect of the gates surrounding both sides, the potential barrier between adjacent photosensitive regions 1 is higher than the potential barrier height below the transistor between photosensitive region 1 and floating diffusion region 3. Therefore, electrons in photosensitive region 1 preferentially escape through floating diffusion, preventing blooming. Figure 13 As shown.

[0157] Optionally, for small pixels, a first ion-doped isolation region is also included, located between adjacent pixel units, to isolate the pixel units. Using ion-doped isolation instead of shallow trench isolation (STI) technology can avoid the additional dark current introduced by the interface defects of the sidewalls of shallow trench isolation, thereby improving the signal-to-noise ratio of the pixel.

[0158] Optionally, multiple pixel units share a floating diffusion region 3, such as Figure 14 As shown, for example, four pixel units share a floating diffusion region. By having multiple pixel units (such as a 2×2 array) share a single readout circuit, the average peripheral circuit area occupied by each pixel can be significantly reduced.

[0159] This application also provides an image sensor, including the pixel unit described above, or the pixel unit prepared by the above preparation method, or the pixel array described above.

[0160] This application also provides an electronic device including the image sensor described above.

[0161] For example, electronic devices may include vehicles, digital cameras, smartphones, security monitors, medical imaging equipment, and vehicle cameras.

[0162] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A pixel unit, characterized in that, include: Substrate (5); The photosensitive area (1) is located in the substrate (5); The transmission gate region (2) is located on at least two sides of the periphery of the photosensitive region (1) in a direction parallel to the substrate (5) and is electrically connected to the photosensitive region (1).

2. The pixel unit according to claim 1, characterized in that, The transmission gate region (2) is disposed around the photosensitive region (1); And / or, when the size of the pixel unit is greater than or equal to a preset size, the transmission gate region (2) is a planar gate region; when the size of the pixel unit is less than the preset size, the transmission gate region (2) is a vertical gate region; And / or, the transmission gate region (2) overlaps with the projection portion of the photosensitive region (1) in a direction perpendicular to the substrate (5); And / or, the width of the transmission gate region (2) on the side near the floating diffusion region (3) is greater than the width of the side away from the floating diffusion region (3).

3. The pixel unit according to claim 1, characterized in that, Also includes: The floating diffusion region (3) is located in the substrate (5) and is electrically connected to the transmission gate region (2); And / or, a clamping region (6) located in the substrate (5) and covering the surface of the photosensitive region (1) near the transmission gate region (2), wherein the doping type of the clamping region (6) is different from that of the photosensitive region (1).

4. The pixel unit according to claim 2, characterized in that, When the size of the pixel unit is greater than or equal to a preset size, a shallow trench isolation region (4) is also included. The shallow trench isolation region (4) is located in the substrate (5) and between the photosensitive areas (1) of adjacent pixel units. When the size of the pixel unit is smaller than a preset size, it also includes a first ion-doped isolation region (8), which is located in the substrate (5) and between the photosensitive areas (1) of adjacent pixel units.

5. The pixel unit according to claim 4, characterized in that, The photosensitive region (1) includes a second doped region and a first doped region stacked along a direction close to the transmission gate region (2), wherein the doping concentration of the first doped region is greater than the doping concentration of the second doped region.

6. The pixel unit according to claim 4, characterized in that, The pixel unit further includes a deep trench isolation region (7), which is disposed on the side of the first ion-doped isolation region (8) away from the transmission gate region (2) and surrounds the photosensitive region (1). And / or, the pixel unit further includes: a second ion-doped isolation region (9) located in the substrate and on the side of the shallow trench isolation region (4) away from the transmission gate region (2), and surrounding the photosensitive region (1).

7. The pixel unit according to claim 3, characterized in that, The pixel unit includes a photodiode, and the photodiode includes the photosensitive area and the substrate; And / or, the pixel unit further includes a transmission transistor, the transmission transistor including the transmission gate region, the photosensitive region and the floating diffusion region; And / or, the pixel unit further includes a floating diffusion node, the floating diffusion node including the floating diffusion region.

8. The pixel unit according to claim 7, characterized in that, The pixel unit further includes a reset transistor; the drain of the reset transistor receives a power supply voltage, and the source of the reset transistor is connected to a floating diffusion node. And / or, the pixel unit further includes a source follower amplifier; the gate of the source follower amplifier is connected to the floating diffusion node, and the drain of the source follower amplifier receives the power supply voltage; And / or, the pixel unit further includes: a row selection transistor; The source of the row select transistor is connected to the source of the source follower amplifier, and the drain of the row select transistor is connected to the column bus.

9. The pixel unit according to claim 8, characterized in that, During the reset phase, the reset transistor and the source follower amplifier are controlled to be in the on state, while the transmission transistor and the row selection transistor are in the off state, so as to reset the floating diffusion node. During the illumination integration phase, the source follower amplifier is kept on while the reset transistor, the transmission transistor, and the row selection transistor are off, so that the photodiode can perform photoelectric conversion and accumulate charge. During the charge transfer and sampling phase, the reset transistor is kept off, while the transfer transistor, the source follower amplifier, and the row selection transistor are on to transfer the accumulated charge to the floating diffusion node and read out the voltage change of the floating diffusion node through the source follower amplifier.

10. A method for fabricating a pixel unit, characterized in that, The method includes: Provide substrate; A photosensitive area is formed in the substrate; On the substrate, at least two sides of the periphery of the photosensitive area are formed a transmission gate region electrically connected to the photosensitive area.

11. The method according to claim 10, characterized in that, The formation of the photosensitive area in the substrate includes: The photosensitive area is formed by implanting doped ions of a first conductivity type into the substrate through an ion implantation process. And / or, the formation of a transmission gate region electrically connected to the photosensitive region on at least two sides of the periphery of the photosensitive region on the substrate includes: A gate dielectric layer and a gate electrode material layer are sequentially formed on the surface of the substrate; The gate dielectric layer and the gate electrode material layer are patterned and etched to form the transmission gate regions located on at least two sides of the periphery of the photosensitive area; And / or, the method further includes: after forming the photosensitive region and before forming the transmission gate region, implanting doped ions of a second conductivity type into a surface region of the photosensitive region near the transmission gate region by an ion implantation process to form a clamping region, wherein the doping type of the clamping region is different from that of the photosensitive region; And / or, the method further includes: implanting doped ions of a first conductivity type into the substrate by an ion implantation process to form a floating diffusion region electrically connected to the transport gate region; And / or, the method further includes: implanting doped ions of a second conductivity type into a region between photosensitive areas in the substrate via an ion implantation process to form a first ion-doped isolation region.

12. A pixel array comprising a plurality of pixel units according to any one of claims 1-9, or a plurality of pixel units prepared by the preparation method according to claim 10 or 11.

13. The pixel array according to claim 12, characterized in that, Multiple pixel units share a floating diffusion region.

14. An image sensor, characterized in that, include: The pixel unit according to any one of claims 1-9, or the pixel unit prepared according to claim 10 or 11, or the pixel array according to claim 12 or 13.

15. An electronic device, characterized in that, Including the image sensor of claim 14.

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