A multi-beam pulse compression method and system based on FPGA
By preprocessing radar data and rearranging it twice, the FPGA resource consumption of the radar system is reduced, the problems of large data volume and insufficient resources in multi-beam radar echo are solved, and efficient multi-beam pulse compression is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 成都玖锦科技有限公司
- Filing Date
- 2026-03-19
- Publication Date
- 2026-06-09
Smart Images
Figure CN122172148A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic countermeasures technology, specifically to the field of radar signal processing, and discloses a multi-beam pulse compression method and system based on FPGA. Background Technology
[0002] Pulse compression technology is commonly used in modern radar systems to effectively improve their detection capabilities, measurement accuracy, and resolution. Common methods for digital pulse compression include time-domain convolution and frequency-domain fast multiplication. Time-domain convolution involves convolving the echo with the sample signal in the time domain; it is simple to implement, but consumes significant multiplier resources when dealing with a large number of matching sample data. Frequency-domain fast multiplication, on the other hand, compresses pulses by multiplying the echo with the sample signal in the frequency domain, enabling efficient processing of long pulses and wide pulse widths. Considering real-time requirements and FPGA resource constraints, frequency-domain fast multiplication is generally used in engineering to implement pulse compression.
[0003] Currently, with the development of high-speed ADC devices, signal bandwidth can reach over 1GHz, significantly increasing the amount of echo data received by radar. When a radar system processes multiple beam echo signals simultaneously, the FPGA resource consumption for pulse compression increases exponentially with the number of beams. For example, if pulse compression of eight beams needs to be completed simultaneously, it will consume eight times the FPGA resources. Due to the limited FPGA resources, it is crucial to avoid excessive consumption of pulse compression resources when the number of multi-beam pulses increases. Summary of the Invention
[0004] The purpose of this invention is to provide a multi-beam pulse compression method and system based on FPGA. By completing the processing of radar data deceleration and rearrangement, it can simultaneously perform pulse compression processing on multiple beam echo signals with only limited FPGA resources, and save a lot of FPGA resources.
[0005] On the one hand, the present invention provides a multi-beam pulse compression method based on FPGA, specifically including the following steps: S1. Acquire multiple radar beam pulse echo signals, perform data preprocessing on the multiple radar beam pulse echo signals, and output the preprocessed echo signals of multiple radar beams. S2. The preprocessed echo signal is rearranged according to the beam channel number to obtain the first rearranged multi-beam data. S3. Perform time-delay alignment on the first rearranged multibeam data to obtain delayed data; S4. The delayed data is rearranged a second time according to the parity of the beam channel number to obtain odd-numbered channel data and even-numbered channel data. S5. Perform frequency domain pulse compression processing on the odd-numbered channel data and the even-numbered channel data respectively, and output a multi-beam pulse compressed signal.
[0006] In some specific implementation schemes, the data preprocessing process is as follows: S11. Perform down-conversion processing on multiple radar beam pulse echo signals to obtain the first I / Q signal; S12. The first I / Q signal and the DDS signal are mixed. The carrier frequency of the DDS signal is the same as that of the first I / Q signal to obtain a zero intermediate frequency I / Q signal. S13. Extract the I / Q signal from the zero intermediate frequency, perform low-pass filtering on the extracted signal, and output the pre-processed echo signal of multiple radar beams.
[0007] In some specific implementations, the carrier frequency of the radar beam pulse echo signal is F0, the sampling rate is Fs, and the carrier frequencies of the first I / Q signal and the DDS signal are both F0-3*Fs / 4.
[0008] In some specific implementation plans, the process of the first data rearrangement is as follows: S21. In the FIFO storage space of the FPGA, divide the FIFO storage space into several subspaces corresponding to the beam channels according to the number of beam channels. S22. Sample the preprocessed echo signal sequentially according to the beam channel number to obtain N sampling data points under each beam channel. Store the N sampling data points in the corresponding subspaces in order according to the beam channel number they were sampled. S23. Arrange several subspaces, each containing N sampling data points, in order of beam channel number to obtain the first rearranged multibeam data.
[0009] In some specific implementations, the delay alignment process is as follows: the first rearranged multibeam data is delayed by N sampling data points to obtain the delayed data.
[0010] In some specific implementation schemes, the process of the second data alternation rearrangement is as follows: S41. Expand the sampling data points in each subspace to 2N, and obtain several extended subspaces corresponding to the beam channels. S42. Classify the extended subspace according to the beam channel number corresponding to the extended subspace, and divide the extended subspace into odd space and even space. S43. Arrange all the data in the odd-numbered spaces in order to obtain the odd-numbered channel data, and arrange all the data in the even-numbered spaces in order to obtain the even-numbered channel data.
[0011] In some specific implementation schemes, the specific process of outputting the multi-beam pulse compression signal is as follows: S51. Window the pulse compression sample data, and perform FFT transformation on the windowed data to obtain the frequency domain filter coefficients. S52. Perform FFT transformation on the odd-channel data and even-channel data respectively to obtain odd-channel transformed data and even-channel transformed data; S53. Multiply the odd-numbered channel transformed data and the even-numbered channel transformed data with the frequency domain filter coefficients respectively, and then perform IFFT transformation to obtain the multi-beam pulse compressed signal.
[0012] In some specific implementation schemes, the specific process of step S53 is as follows: S531. Multiply the odd-channel transformed data and the even-channel transformed data with the frequency domain filter coefficients respectively to obtain the odd-channel multiplied data and the even-channel multiplied data. S532. Perform N-point IFFT transformation on the odd-numbered channel dot product data and the even-numbered channel dot product data respectively to obtain the IFFT transformation data corresponding to each beam channel. S533. Select the first N data points from the IFFT transform data corresponding to each beam channel as frequency domain filtering data. S534. Output the frequency domain filtering data corresponding to each beam channel in sequence according to the beam channel number.
[0013] In some specific implementations, the FFT transform is always an N-point FFT transform.
[0014] Secondly, this application provides an FPGA-based multi-beam pulse compression system, comprising: The echo data preprocessing module is used to acquire multiple radar beam pulse echo signals, perform data preprocessing on the multiple radar beam pulse echo signals, output multiple radar beam preprocessed echo signals, and perform the first data rearrangement on the preprocessed echo signals according to the beam channel number to obtain the first rearranged multi-beam data. The delay alignment module is used to perform delay alignment on the first rearranged multibeam data to obtain delayed data. The pulse compression processing module is used to perform a second data alternation rearrangement on the delayed data according to the parity of the beam channel number, to obtain odd-numbered channel data and even-numbered channel data. Frequency domain pulse compression processing is then performed on the odd-numbered channel data and even-numbered channel data respectively, and a multi-beam pulse compressed signal is output.
[0015] The inventive concept of this application is as follows: Existing pulse compression techniques that employ the frequency-domain fast product method consume significant FPGA computing resources. Given the limited resources available to FPGAs, it is crucial to reduce FPGA processing load and improve resource efficiency. To address this, this application proposes an improved FPGA-based multi-beam pulse compression method. First, the radar multi-beam pulse echo signal undergoes data preprocessing to reduce the amount of data the FPGA needs to compute. Then, the preprocessed echo signal is rearranged twice. Finally, frequency-domain pulse compression is performed on the rearranged data, further reducing the amount of data the FPGA needs to process while conserving substantial FPGA resources.
[0016] The beneficial effects of this invention are as follows: This application reduces the data rate of radar beam pulse echo signals by performing data preprocessing on multiple radar beam pulse echo signals, effectively solving the problem of excessive data volume of multi-beam radar echo signals in radar systems under high-speed ADC devices; then, by performing two data rearrangements, frequency domain pulse compression of multiple radar beam pulse echo signals can be completed with only 2 sets of FPGA resources, effectively solving the problem of excessive FPGA resource consumption for pulse compression as the number of targets in the radar system increases; This invention avoids the problem of data aliasing caused by frequency domain filtering by dividing the data into odd and even channels during the second rearrangement, effectively solving the problem of efficient FPGA implementation of pulse compression technology. Attached Figure Description
[0017] Figure 1 A flowchart of a multi-beam pulse compression method based on FPGA provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the preprocessed echo signal arrangement provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the first rearrangement of multibeam data arrangement provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the delay data arrangement provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the data arrangement after the second rearrangement provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the data arrangement after pulse compression processing provided in an embodiment of the present invention. Detailed Implementation
[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps described in these embodiments do not limit the scope of the invention.
[0020] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.
[0021] Furthermore, for clarity and brevity, descriptions of well-known structures, functions, and configurations may have been omitted. Those skilled in the art will recognize that various changes and modifications can be made to the examples described herein without departing from the spirit and scope of this disclosure.
[0022] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0023] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.
[0024] Example 1 like Figure 1 As shown, this embodiment provides a multi-beam pulse compression method based on FPGA, which specifically includes the following steps: S1. Acquire multiple radar beam pulse echo signals, perform data preprocessing on the multiple radar beam pulse echo signals, and output the preprocessed echo signals of multiple radar beams. Specifically, the carrier frequency of the radar beam pulse echo signal is F0, the sampling rate is Fs, and the specific data preprocessing process is as follows: S11. Perform 3*Fs / 4 down-conversion processing on multiple radar beam pulse echo signals to obtain the first I / Q signal with a carrier frequency of F0-3*Fs / 4. S12. Mix the first I / Q signal with the DDS signal. The carrier frequency of the DDS signal is the same as that of the first I / Q signal, which is F0-3*Fs / 4, to obtain the zero intermediate frequency I / Q signal. S13. Extract the I / Q signal from the zero intermediate frequency, perform low-pass filtering on the extracted signal, and output the pre-processed echo signal of multiple radar beams.
[0025] S2. The preprocessed echo signal is rearranged according to the beam channel number to obtain the first rearranged multi-beam data. The specific process of the first data rearrangement is as follows: S21. In the FIFO storage space of the FPGA, divide the FIFO storage space into several subspaces corresponding to the beam channels according to the number of beam channels. S22. Sample the preprocessed echo signal sequentially according to the beam channel number to obtain N sampling data points under each beam channel. Store the N sampling data points in the corresponding subspaces in order according to the beam channel number they were sampled. S23. Arrange several subspaces, each containing N sampling data points, in order of beam channel number to obtain the first rearranged multibeam data.
[0026] S3. Perform time-delay alignment on the first rearranged multibeam data to obtain delayed data; The specific process of delay alignment is as follows: after delaying the entire multibeam data from the first rearrangement by N sampling data points, the delayed data is obtained.
[0027] S4. The delayed data is rearranged a second time according to the parity of the beam channel number to obtain odd-numbered channel data and even-numbered channel data. Specifically, the process of the second data alternation rearrangement is as follows: S41. Expand the sampling data points in each subspace to 2N, and obtain several extended subspaces corresponding to the beam channels. S42. Classify the extended subspace according to the beam channel number corresponding to the extended subspace, and divide the extended subspace into odd space and even space. S43. Arrange all the data in the odd-numbered spaces in order to obtain the odd-numbered channel data, and arrange all the data in the even-numbered spaces in order to obtain the even-numbered channel data.
[0028] S5. Perform frequency domain pulse compression processing on the odd-numbered channel data and the even-numbered channel data respectively, and output a multi-beam pulse compressed signal.
[0029] Specifically, the process of outputting the multi-beam pulse compression signal is as follows: S51. Window the pulse compression sample data, and perform FFT transformation on the windowed data to obtain the frequency domain filter coefficients. S52. Perform FFT transformation on the odd-channel data and even-channel data respectively to obtain odd-channel transformed data and even-channel transformed data; S53. Multiply the odd-numbered channel transformed data and the even-numbered channel transformed data with the frequency domain filter coefficients respectively, and then perform IFFT transformation to obtain the multi-beam pulse compressed signal.
[0030] In some specific implementations, the FFT transformation process described below is an N-point FFT transformation, and the specific process of step S53 is as follows: S531. Multiply the odd-channel transformed data and the even-channel transformed data with the frequency domain filter coefficients respectively to obtain the odd-channel multiplied data and the even-channel multiplied data. S532. Perform N-point IFFT transformation on the odd-numbered channel dot product data and the even-numbered channel dot product data respectively to obtain the IFFT transformation data corresponding to each beam channel. S533. Select the first N data points from the IFFT transform data corresponding to each beam channel as frequency domain filtering data. S534. Output the frequency domain filtering data corresponding to each beam channel in sequence according to the beam channel number.
[0031] To better understand the working principle of this application, it is assumed that the sampling rate of the radar system is Fs, the radar operating frequency is F0, the radar signal bandwidth is B, the FPGA can simultaneously transmit and receive 8 radar beam pulse echo signals, and the number of frequency domain filtering points is 256. When the radar sends a pulse compression sample signal to the target, after reflection from the target, the radar beam pulse echo signal is received by the FPGA. The FPGA-based multi-beam pulse compression method in this embodiment mainly consists of two parts: an echo data preprocessing process and a pulse compression processing process, specifically: 1. Echo data preprocessing process First, the radar beam pulse echo signals reflected from the target are preprocessed to reduce the amount of radar data. The preprocessing process involves down-converting the multiple radar beam pulse echo signals, mixing the down-converted radar signals to zero intermediate frequency (IF), performing polyphase decimation and filtering on the zero IF echo signals, outputting preprocessed echo data for multiple beams, and finally sorting the preprocessed echo data to output the first rearranged multi-beam data. The specific steps are as follows: 1) The collected radar beam pulse echo signals with a carrier frequency of F0 are digitally downconverted by 3*Fs / 4 to become the first I / Q signal with a carrier frequency of F0-3*Fs / 4. 2) The first I / Q signal after down-conversion is mixed with the DDS signal with a carrier frequency of F0-3*Fs / 4 to become a zero intermediate frequency I / Q signal; 3) The zero-IF I / Q signal is decimated by 8 times, and the decimated signal is low-pass filtered to output preprocessed echo signals for multiple radar beams. The preprocessed echo signal data stream is as follows: Figure 2 As shown, Clk is the data sampling clock, Channel is the beam channel number (1~8), and Data is the sampling data point. The sampling data points in the preprocessed echo signal are numbered starting from 1 according to the number of frequency domain filter points. For example, if the number of frequency domain filter points is 256, and one beam channel collects 256 sampling points, during sampling, if 8 identical sampling data points are collected at once through 8 beam channels, then the 256 points need to be output sequentially according to the beam channel number. 1~256 represent the 1st to 256th sampling data points; from... Figure 2 As can be seen, each sampled data point in the preprocessed echo signal is arranged sequentially according to the beam channel number corresponding to each sampling. In order to facilitate the subsequent 256-point FFT frequency domain pulse compression processing, it is necessary to summarize all sampled data points under the same beam channel number. Therefore, it is necessary to rearrange the sampled data points in the preprocessed echo signal. 4) A FIFO space is allocated in the FPGA and divided into 8 equal subspaces. The 8 subspaces have the same number as the 8 beam channels. The preprocessed echo signal data stream is written into the 8 subspaces according to the channel number, with different sampling data points written into each subspace. The data is then read out sequentially according to the channel number, completing the first data rearrangement. The data is then output in real time at 256 points, alternating between beam channel numbers. The data after the first rearrangement is as follows: Figure 3 As shown, each beam channel number (1~8) corresponds to a subspace containing 256 sampled data points (numbered 1~256). The first data rearrangement is mainly to complete the subsequent 256-point FFT frequency domain pulse compression processing.
[0032] 2. Pulse compression processing To avoid aliasing in the filtered data due to frequency domain filtering, the multi-beam data after the first rearrangement is rearranged a second time. The beam channel numbers are alternately output in real time as 512 data points. The frequency domain filtering coefficients are transformed into the frequency domain and stored in the FPGA's RAM. Pulse compression is achieved by multiplying the frequency domain filtering coefficients in the frequency domain and RAM of the data after the second rearrangement. This reduces the amount of radar data and saves a significant amount of FPGA resources. The specific steps are as follows: 1) First, the pulse compressed sample data is windowed, then a 256-point FFT transform is performed on the windowed data to obtain frequency domain filtering coefficients. These coefficients are then stored in the FPGA's RAM. The frequency domain filtering coefficients are the processed pulse compressed sample data, and the number of frequency domain filtering points refers to the number of points in the frequency domain filtering coefficients, which have 256 data points. The pulse compressed sample data is the signal transmitted by the radar. After being transmitted, the pulse compressed sample data is reflected by the target to obtain multiple radar beam pulse echo signals. 2) After aligning the first rearranged multibeam data with a delay of 256 points, the resulting delayed data, including the delayed beam channel numbers Channel_dly and the sampled data points Data_dly stored in the subspace corresponding to each beam channel number, is arranged 256 sample points backward compared to the sampled data points Data of the first rearranged multibeam data. Figure 4 As shown; 3) Select the delayed data and output it in real time with 512 data points (set to twice the number of frequency domain filter points to ensure no aliasing in frequency filtering) according to the beam channel number to complete the second data rearrangement. That is, expand the sampling data points corresponding to each beam channel to twice the original number, and divide the expanded data points according to the odd or even number of the beam channel number, such as... Figure 5 As shown, odd-numbered channels ChannelEven and even-numbered channels Channeloddd are obtained, along with corresponding odd-numbered channel data DataEven and even-numbered channel data Dataodd. Each beam channel has 512 sampled data points stored in its corresponding subspace. 4) Perform a 256-point FFT transformation on the odd-numbered channel data DataEven and the even-numbered channel data Dataodd after the second rearrangement, and then multiply the FFT-transformed data by the frequency domain filter coefficients in RAM. 5) Perform a 256-point IFFT transform on the dot-multiplied data to obtain the IFFT transformed data for the odd-numbered channels and the IFFT transformed data for the even-numbered channels, such as... Figure 6 As shown, the IFFT transform data IFFTDataEven corresponding to odd-numbered channels includes the data of odd-numbered channels ChannelEven1, 3, 5, and 7 after IFFT transformation, while the IFFT transform data IFFTDataOdd corresponding to even-numbered channels includes the data of even-numbered channels ChannelOdd2, 4, 6, and 8 after IFFT transformation. Since frequency domain filtering can cause aliasing in the filtered data, it is necessary to select the first 256 points of non-aliased data from each channel for output. The number of points selected depends on the number of frequency domain filtering points. The first 256 points of data after IFFT transformation for each channel are selected from the IFFT transform data IFFTDataEven and IFFTDataOdd respectively; these are the frequency domain filtered data. The selected frequency domain filtered data are then rearranged according to the beam channel number to obtain the multi-beam pulse compression signal IFFTData. The multi-beam pulse compression signal IFFTData is then output sequentially according to the beam channel number, with 256 points from each beam channel output sequentially.
[0033] Understandably, after the above steps, multi-beam pulse compression is completed in the FPGA. Through data preprocessing, the data rate of radar multi-beam signals is reduced, effectively solving the problem of excessive multi-beam radar echo data in radar systems under high-speed ADC devices. By rearranging the data twice, frequency domain pulse compression of multiple target echo signals can be completed by consuming only 2 sets of FPGA resources, effectively solving the problem of excessive consumption of FPGA resources for pulse compression in radar systems as the number of targets increases. By dividing the channel into odd and even channels through data re-memory, the problem of data aliasing caused by frequency domain filtering is avoided, effectively solving the problem of efficient FPGA implementation of pulse compression technology.
[0034] Example 2 This application provides a multi-beam pulse compression system based on FPGA, including: The echo data preprocessing module is used to acquire multiple radar beam pulse echo signals, perform data preprocessing on the multiple radar beam pulse echo signals, output multiple radar beam preprocessed echo signals, and perform the first data rearrangement on the preprocessed echo signals according to the beam channel number to obtain the first rearranged multi-beam data. The delay alignment module is used to perform delay alignment on the first rearranged multibeam data to obtain delayed data. The pulse compression processing module is used to perform a second data alternation rearrangement on the delayed data according to the parity of the beam channel number, to obtain odd-numbered channel data and even-numbered channel data. Frequency domain pulse compression processing is then performed on the odd-numbered channel data and even-numbered channel data respectively, and a multi-beam pulse compressed signal is output.
[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Based on the technical essence of the present invention, any simple modifications, equivalent substitutions, and improvements made to the above embodiments within the spirit and principles of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A multi-beam pulse compression method based on FPGA, characterized in that, Specifically, the following steps are included: S1. Acquire multiple radar beam pulse echo signals, perform data preprocessing on the multiple radar beam pulse echo signals, and output the preprocessed echo signals of multiple radar beams. S2. The preprocessed echo signal is rearranged according to the beam channel number to obtain the first rearranged multi-beam data. S3. Perform time-delay alignment on the first rearranged multibeam data to obtain delayed data; S4. The delayed data is rearranged a second time according to the parity of the beam channel number to obtain odd-numbered channel data and even-numbered channel data. S5. Perform frequency domain pulse compression processing on the odd-numbered channel data and the even-numbered channel data respectively, and output a multi-beam pulse compressed signal.
2. The FPGA-based multi-beam pulse compression method according to claim 1, characterized in that, The specific process of data preprocessing is as follows: S11. Perform down-conversion processing on multiple radar beam pulse echo signals to obtain the first I / Q signal; S12. The first I / Q signal and the DDS signal are mixed. The carrier frequency of the DDS signal is the same as that of the first I / Q signal to obtain a zero intermediate frequency I / Q signal. S13. Extract the I / Q signal from the zero intermediate frequency, perform low-pass filtering on the extracted signal, and output the pre-processed echo signal of multiple radar beams.
3. The FPGA-based multi-beam pulse compression method according to claim 2, characterized in that, The carrier frequency of the radar beam pulse echo signal is F0, and the sampling rate is Fs. The carrier frequencies of the first I / Q signal and the DDS signal are both F0-3*Fs / 4.
4. The FPGA-based multi-beam pulse compression method according to claim 1, characterized in that, The specific process of the first data rearrangement is as follows: S21. In the FIFO storage space of the FPGA, divide the FIFO storage space into several subspaces corresponding to the beam channels according to the number of beam channels. S22. Sample the preprocessed echo signal sequentially according to the beam channel number to obtain N sampling data points under each beam channel. Store the N sampling data points in the corresponding subspaces in order according to the beam channel number they were sampled. S23. Arrange several subspaces, each containing N sampling data points, in order of beam channel number to obtain the first rearranged multibeam data.
5. The FPGA-based multi-beam pulse compression method according to claim 4, characterized in that, The specific process of delay alignment is as follows: after delaying the entire multibeam data from the first rearrangement by N sampling data points, the delayed data is obtained.
6. The FPGA-based multi-beam pulse compression method according to claim 4, characterized in that, The specific process of the second data alternation rearrangement is as follows: S41. Expand the sampling data points in each subspace to 2N, and obtain several extended subspaces corresponding to the beam channels. S42. Classify the extended subspace according to the beam channel number corresponding to the extended subspace, and divide the extended subspace into odd space and even space. S43. Arrange all the data in the odd-numbered spaces in order to obtain the odd-numbered channel data, and arrange all the data in the even-numbered spaces in order to obtain the even-numbered channel data.
7. The FPGA-based multi-beam pulse compression method according to claim 6, characterized in that, The specific process of outputting a multi-beam pulse compression signal is as follows: S51. Window the pulse compression sample data, and perform FFT transformation on the windowed data to obtain the frequency domain filter coefficients. S52. Perform FFT transformation on the odd-channel data and even-channel data respectively to obtain odd-channel transformed data and even-channel transformed data; S53. Multiply the odd-numbered channel transformed data and the even-numbered channel transformed data with the frequency domain filter coefficients respectively, and then perform IFFT transformation to obtain the multi-beam pulse compressed signal.
8. The FPGA-based multi-beam pulse compression method according to claim 7, characterized in that, The specific process of step S53 is as follows: S531. Multiply the odd-channel transformed data and the even-channel transformed data with the frequency domain filter coefficients respectively to obtain the odd-channel multiplied data and the even-channel multiplied data. S532. Perform N-point IFFT transformation on the odd-numbered channel dot product data and the even-numbered channel dot product data respectively to obtain the IFFT transformation data corresponding to each beam channel. S533. Select the first N data points from the IFFT transform data corresponding to each beam channel as frequency domain filtering data. S534. Output the frequency domain filtering data corresponding to each beam channel in sequence according to the beam channel number.
9. The FPGA-based multi-beam pulse compression method according to claim 7, characterized in that, All FFT transformations are N-point FFT transformations.
10. A multi-beam pulse compression system based on FPGA, characterized in that, include: The echo data preprocessing module is used to acquire multiple radar beam pulse echo signals, perform data preprocessing on the multiple radar beam pulse echo signals, output multiple radar beam preprocessed echo signals, and perform the first data rearrangement on the preprocessed echo signals according to the beam channel number to obtain the first rearranged multi-beam data. The delay alignment module is used to perform delay alignment on the first rearranged multibeam data to obtain delayed data. The pulse compression processing module is used to perform a second data alternation rearrangement on the delayed data according to the parity of the beam channel number, to obtain odd-numbered channel data and even-numbered channel data. Frequency domain pulse compression processing is then performed on the odd-numbered channel data and even-numbered channel data respectively, and a multi-beam pulse compressed signal is output.