Chained communication method, chained communication system, and computer-readable storage medium

Abstract

The application provides a chain communication method, a chain communication system and a computer readable storage medium, and belongs to the technical field of communication. The chain communication method comprises the following steps: receiving a preamble field of a target data frame and forwarding, determining a first baud rate based on a preamble edge interval; receiving valid data bits and writing into a FIFO memory; when the FIFO memory is empty and no valid data bits have been sent, sending preset empty bits; when the FIFO memory is not empty, reading the FIFO memory and sending the valid data bits based on the first baud rate; in the sending process, determining a deviation indication quantity according to the writing rate and the reading rate of the valid data bits in the FIFO memory, and compensating the first baud rate based on the deviation indication quantity to obtain a target baud rate for subsequent valid data sending. The application can realize adaptive adjustment of the sending rate in the chain cascade forwarding process, and improve the data transmission stability and reliability of the chain communication.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a chained communication method, a chained communication system, and a computer-readable storage medium. Background Technology

[0002] With the continuous development of communication technology, chained communication (such as serial communication and bus communication) has been widely used in many fields. The basic characteristic of chained communication is that multiple devices form a communication link through serial connection. Each device not only receives data from the upstream device but also forwards data to the downstream device. In this process, the communication rate (baud rate) and clock synchronization have a significant impact on the stability and performance of the communication system. Especially in chained communication systems with a large number of devices and long links, baud rate deviation and clock drift often lead to signal transmission errors, thus affecting the reliability and performance of the entire system.

[0003] In existing chained communication systems, instability in data transmission and increased bit error rates often occur due to differences in device clocks and the accumulation of errors during link transmission. This is especially true when devices are cascaded extensively and signal transmission distances are long, as timing errors and baud rate deviations accumulate at each stage of the communication link, leading to significant discrepancies between the received and actual data. To ensure accurate data transmission, edge alignment techniques and special encoding methods are typically used to reduce errors, but these methods cannot completely eliminate the impact of baud rate deviations and clock drift on data transmission.

[0004] Therefore, in chain communication systems, how to effectively suppress the accumulation of errors caused by baud rate deviation and clock drift, while improving the stability and reliability of data transmission, has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a chain communication method, a chain communication system, and a computer-readable storage medium to solve the problem of error accumulation caused by baud rate deviation and clock drift in existing chain communication methods.

[0006] In a first aspect, this application provides a chained communication method applied to a chained communication system, the chained communication system including a master device and multiple slave devices; the multiple slave devices are cascaded in series, the first slave device in the cascaded series is connected to the output terminal of the master device, and the last slave device in the cascaded series is connected to the input terminal of the master device, the slave device is used to receive a target data frame from an upper-level device and forward the target data frame to a lower-level device, the target data frame includes a preamble field and a valid data field, the valid data field includes multiple valid data bits, and the method includes: The device receives the preamble field sent by the superior device; The slave device sends the preamble field to the lower-level device and determines the first baud rate of the target data frame based on the edge spacing of the preamble field; The slave device receives the valid data bits sent by the upper-level device and writes the valid data bits into the first-in-first-out (FIFO) memory corresponding to the slave device. When the slave device has the valid data bits in the FIFO memory, it reads the valid data bits from the FIFO memory and sends the valid data bits to the lower-level device based on the first baud rate. During the transmission of the valid data bits, the slave device determines a deviation indicator based on the write rate and read rate of the valid data bits in the FIFO memory. The deviation indicator is used to indicate the magnitude relationship and degree of deviation between the write rate and the read rate. The slave device compensates for the first baud rate based on the deviation indication to obtain a target baud rate, and treats the target baud rate as the first baud rate, and cyclically executes the step of the slave device receiving the valid data bits sent by the upper-level device.

[0007] In one possible design, the method further includes: If the slave device has no valid data bits in the FIFO memory and has not sent any valid data bits, it sends a preset empty bit to the lower-level device.

[0008] In one possible design, the effective data bits are encoded and transmitted using Biphase Marker Code (BMC). The process of receiving the valid data bits sent by the superior device from the slave device includes: The device receives the encoded signal corresponding to the valid data field sent by the superior device; The slave device determines the bit period for making a decision on the encoded signal based on the first baud rate; wherein the encoded signal is divided into multiple encoded signal segments in time according to the bit period; The slave device makes a decision on the encoded signal segment corresponding to the bit period based on the level switching characteristics in the first half of the bit period, and obtains the effective data bits corresponding to the encoded signal segment.

[0009] In one possible design, the slave device compensates for the first baud rate based on the deviation indication to obtain a target baud rate, including: When the deviation indicator is used to indicate that the write rate is greater than the read rate, the slave device detects the remaining depth of the FIFO memory and increases the first baud rate based on the remaining depth to obtain a second baud rate, where the second baud rate is the target baud rate. When the deviation indicator is used to indicate that the read rate is greater than the write rate, the slave device determines the transmit lead time and reduces the first baud rate based on the transmit lead time to obtain a third baud rate, wherein the third baud rate is the target baud rate; wherein the transmit lead time is the time lead of the read rate relative to the write rate.

[0010] In one possible design, the slave device increases the first baud rate based on the remaining depth of the FIFO memory to obtain the second baud rate, including: The device detects the remaining depth of the FIFO memory; The slave device determines whether the remaining depth is less than a first threshold. When the remaining depth is less than the first threshold, the slave device reduces the baud rate count corresponding to the first baud rate by a target number to obtain a fourth baud rate; The slave device determines whether the remaining depth is less than a second threshold, where the second threshold is less than the first threshold. When the remaining depth is less than the second threshold, the slave device reduces the baud rate count corresponding to the fourth baud rate by the target number to obtain the fifth baud rate; When the remaining depth is greater than or equal to the second threshold, the slave device determines the fourth baud rate as the second baud rate; The slave device determines whether the remaining depth is less than a third threshold, wherein the third threshold is less than the second threshold; When the remaining depth is less than the third threshold, the slave device reduces the baud rate count corresponding to the fifth baud rate by the target number to obtain a sixth baud rate, and determines the sixth baud rate as the second baud rate; When the remaining depth is greater than or equal to the third threshold, the slave device determines the fifth baud rate as the second baud rate.

[0011] In one possible design, the slave device reduces the first baud rate based on the transmission lead time to obtain the third baud rate, including: The device determines the transmission lead time; The slave device determines whether the transmission lead time is greater than a fourth threshold. When the transmission lead time is greater than the fourth threshold, the slave device increases the baud rate count corresponding to the first baud rate by a target number to obtain the seventh baud rate; The slave device determines whether the transmission lead time is greater than a fifth threshold, wherein the fifth threshold is greater than the fourth threshold; When the transmission lead time is greater than the fifth threshold, the slave device increases the baud rate count corresponding to the seventh baud rate by the target number to obtain the eighth baud rate; When the transmission lead time is less than or equal to the fifth threshold, the slave device determines the seventh baud rate as the third baud rate; The slave device determines whether the transmission lead time is greater than a sixth threshold, wherein the sixth threshold is greater than the fifth threshold; When the transmission lead time is greater than the sixth threshold, the slave device increases the baud rate count corresponding to the eighth baud rate by the target number to obtain the ninth baud rate, and determines the ninth baud rate as the third baud rate; When the transmission lead time is less than or equal to the sixth threshold, the slave device determines the eighth baud rate as the third baud rate.

[0012] In one possible design, the fourth threshold is one-eighth, the fifth threshold is one-quarter, and the sixth threshold is three-eighths.

[0013] In one possible design, the target quantity is 1; The baud rate count of the target baud rate is used to determine the target baud rate, and the baud rate count of the target baud rate is inversely proportional to the target baud rate.

[0014] In one possible design, when the deviation indicator is used to indicate that the read rate is greater than the write rate, the method further includes: When the valid data bits in the FIFO memory are empty, the slave device bypasses and sends the valid data bits to the lower-level device, and controls the valid data bits not to be written into the FIFO memory. Secondly, this application provides a chain-like communication system, including a master device and multiple slave devices; The plurality of slave devices are cascaded in series, with the first slave device in the cascade connected to the output terminal of the master device, and the last slave device in the cascade connected to the input terminal of the master device. The slave device is used to implement the method described in the first aspect or various possible designs of the first aspect.

[0015] Thirdly, this application provides an electronic device, including: a memory and at least one processor; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method described in the first aspect or various possible designs of the first aspect.

[0016] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed, implement the method described in the first aspect or various possible designs of the first aspect.

[0017] Fifthly, this application provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to implement the method described in the first aspect or various possible designs of the first aspect.

[0018] In a sixth aspect, this application provides a chip, comprising: an interface circuit and a logic circuit, wherein the interface circuit is configured to receive signals from other chips outside the chip and transmit them to the logic circuit, or to send signals from the logic circuit to other chips outside the chip, and the logic circuit is configured to implement the method described in the first aspect or various possible designs of the first aspect.

[0019] This application provides a chain communication method, a chain communication system, and a computer-readable storage medium. In this chain communication method, for each slave device, firstly, the slave device receives and directly forwards the preamble field to the next lower-level device. Simultaneously, the first baud rate of the target data frame is determined based on the edge interval of the preamble field, thereby providing the slave device with an initial transmission rate matching the target data frame. Secondly, during the valid data field transmission phase, the received valid data bits are written into a FIFO memory, decoupling the writing on the receiving side and the reading and transmission on the sending side of the slave device in time. Therefore, clock deviations and link jitter of the upper-level device are primarily manifested as data accumulation or insufficiency in the FIFO memory of the slave device, rather than directly affecting the transmission waveform of the slave device. Simultaneously, when the slave device's FIFO... When valid data bits exist in the FIFO memory, the slave device reads valid data bits from the FIFO memory and sends them to the next-level device according to the first baud rate, so that the transmission timing is output based on the determined first baud rate. Finally, during the transmission process, the slave device counts the write rate and read rate of valid data bits in the FIFO memory and forms a deviation indicator. Based on the deviation indicator, it compensates the first baud rate to obtain the target baud rate and updates the target baud rate to the new first baud rate. This causes the transmission rate to be dynamically pulled back to a range more consistent with the receiving side as the deviation occurs. In this way, the timing error accumulation caused by baud rate deviation and clock drift is continuously suppressed at each slave device level, preventing the error from spreading to valid data and causing communication anomalies, thereby improving the data transmission stability and reliability of chain communication. Attached Figure Description

[0020] Figure 1 A schematic diagram of the structure of a chain communication system provided for related technologies; Figure 2 A schematic diagram of transmit and receive waveforms for an edge-aligned method provided for related technologies; Figure 3 A schematic diagram of a data frame transmission and reception structure using a special encoding method provided for related technologies; Figure 4 A flowchart illustrating a chain communication method provided in an embodiment of this application; Figure 5 This application provides a schematic diagram of a device receiving and sending target data frames. Figure 6 A schematic diagram of the transceiver timing of a slave device provided in an embodiment of this application; Figure 7 A schematic diagram of a BMC waveform provided in an embodiment of this application; Figure 8 A flowchart illustrating another chain communication method provided in an embodiment of this application; Figure 9A flowchart illustrating yet another chain communication method provided in an embodiment of this application; Figure 10 A schematic diagram of the structure of a slave device is provided for an embodiment of this application; Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion.

[0023] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B can exist simultaneously, and B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0025] Furthermore, the terms "first," "second," etc., in the specification and claims of this application or in the aforementioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0026] In the description of this application, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0027] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, "connected" or "linked" can refer not only to a physical connection, but also to an electrical connection or a signal connection. For instance, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is connected. It can also refer to the internal connection between two components. A signal connection can refer not only to a signal connection through a circuit, but also to a signal connection through a medium, such as radio waves. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, different technical features in this application can be combined with each other.

[0029] Figure 1 A schematic diagram of a chain-type communication system provided for related technologies. For example... Figure 1 As shown, the chain communication system includes a master device 100 and N serially cascaded slave devices. The input terminal of the first serially cascaded slave device is connected to the output terminal of the master device 100, and the output terminal of the last serially cascaded slave device is connected to the input terminal of the master device 100.

[0030] Where N is a positive integer greater than or equal to 2, and the N slave devices are slave device 101, slave device 102, ..., slave device 10N in the cascaded order.

[0031] For each slave device, it receives data sent by its superior device and simultaneously sends data to its subordinate devices. The superior device of a slave device is the device adjacent to and preceding the slave device; the subordinate device of a slave device is the device adjacent to and following the slave device.

[0032] For example, the superior device of device 101 is the master device, and the subordinate device of device 101 is the slave device 102.

[0033] For example, the superior device of device 102 is device 101, and the subordinate device of device 102 is device 103.

[0034] For example, the superior device of device 10N is device 10(N-1), and the subordinate device of device 10N is master device 100.

[0035] In use Figure 1 When the chained communication system shown communicates, due to differences in the local clocks of each device and transmission errors introduced by the inter-stage connections, the communication signal may experience distortions such as edge jitter and bit width drift during cascaded transmission. When the communication link is long, these distortions accumulate step by step during transmission, leading to increased timing errors at the end of the communication link and causing communication anomalies. To address these issues, related technologies typically employ edge alignment or special encoding methods to synchronize and encode the communication signal during transmission.

[0036] Specifically, existing edge alignment methods typically require the use of specific line codes, such as Return-to-Zero (RZ) codes, to ensure that a valid edge for synchronization is generated within each bit period, meaning that each bit of data undergoes a level transition at a preset time position. At the receiving end, the device determines bit boundaries or bit phases by detecting valid edges and uses these valid edges as a reference for timing recovery of the received data. At the transmitting end, the valid edges serve as the alignment reference, and the corresponding coded waveform (e.g., ...) is output within a bit time window defined by adjacent valid edges. Figure 2 As shown, Figure 2 The waveform above is the received signal waveform. Figure 2 The waveform below is the transmitted signal waveform, where bit 0 to bit 4 represent continuous bit periods, and the vertical dashed lines indicate the boundary moments of each bit period. Since each bit relies on a valid edge for alignment, a single-stage device can achieve retiming and forwarding of the input signal to a certain extent. However, this edge alignment method has the following limitations: First, it requires a fixed line code and demands that each bit have a valid edge, which limits the communication protocol and encoding method, resulting in poor versatility. Second, in chained cascaded transmission, timing drift may still be introduced due to factors such as period / baud rate deviation, edge detection jitter, and line transmission distortion, causing errors to accumulate after multiple stages of transmission, making it difficult to fundamentally avoid the accumulation of periodic errors during communication.

[0037] Existing special encoding methods require special encoding of the communication protocol, periodically inserting invalid bits (or padding bits / alignment bits) that do not carry valid information into the data frame. During transmission and reception, the device receives and sends data frames containing invalid bits at a predetermined rate. When there is a certain timing error or baud rate deviation in the link, the error will gradually manifest as bit boundary offset during continuous transmission. The inserted invalid bits can serve as a reserved "buffer," allowing the error to be reflected primarily in the invalid bits. After detecting an invalid bit, the device can realign the transmission and reception timing according to preset rules and discard the invalid bit, thereby maintaining the parsing of subsequent valid bits within a limited error range. However, this special encoding method also has shortcomings: First, it requires modification of the protocol frame format and the introduction of additional invalid bits, resulting in a decrease in the effective payload ratio and the occupation of data bandwidth; second, when the baud rate deviation or transmission distortion of the chained communication exceeds the range that the invalid bits can absorb, the error may still cross over to the valid bits and cause parsing errors, and the insertion position and frequency of invalid bits need to be balanced between bandwidth overhead and error tolerance.

[0038] Figure 3 A schematic diagram of a data frame transmission and reception structure for a special encoding method provided for related technologies, such as... Figure 3 As shown, Figure 3 The data frame structure above shows the structure of the data frames received by the device. Figure 3 The data frame structure below is the structure of the data frame sent by the device. In addition to the valid bits bit0 to bit3, the data frame also inserts invalid bits (invalid bits) at preset positions. The dashed lines indicate the bit boundaries / alignment reference times. The device receives and forwards the data frame at the agreed rate, and discards the invalid bit after detecting it. At the same time, the boundary corresponding to the invalid bit is used as the reference for re-aligning the transmission and reception timing.

[0039] Therefore, in chained communication systems, how to effectively suppress the accumulation of timing errors caused by baud rate deviation and clock drift during multi-level cascading forwarding, and avoid the spread of errors to valid bits leading to communication abnormalities, thereby improving the stability and reliability of data transmission, has become an urgent technical problem to be solved.

[0040] Based on the problems existing in related technologies, this application provides a chained communication method. Addressing the issue of timing errors caused by baud rate deviation and clock drift accumulating step-by-step in chained communication, firstly, the slave device uses the preamble edge interval to estimate the initial baud rate of the target data frame in real time as the transmission reference baud rate. Secondly, during the valid data phase, the obtained valid data bits are written into a First-In-First-Out (FIFO) memory buffer and sent to the next-level device according to the transmission reference baud rate. Simultaneously, the difference between the write rate and read rate of the FIFO memory is monitored in real time to form a deviation indicator, and the transmission reference baud rate is dynamically adjusted based on the deviation indicator: when the write rate is faster than the read rate, causing the FIFO to become congested, the transmission reference baud rate is increased to accelerate reading and transmission; when the read rate is faster than the write rate, causing the transmitting side to lead, the transmission reference baud rate is decreased to reduce the lead. This mechanism, which uses a preamble to determine the transmission reference baud rate, a FIFO memory for decoupling and forwarding, and a closed-loop compensation mechanism for the transmission reference baud rate during communication, enables each slave device to continuously pull the transmit and receive rates back to the matching range without relying on strict edge alignment or inserting invalid bit alignment. This suppresses the accumulation of errors in the cascaded link and effectively improves the stability and reliability of chained communication.

[0041] Next, through some specific embodiments and accompanying drawings, this application describes in detail how, in a chain communication system, the timing errors caused by baud rate deviation and clock drift are suppressed to accumulate step by step, thereby improving the stability and reliability of data transmission, through a transmit / receive decoupling and baud rate compensation mechanism.

[0042] Figure 4 This is a flowchart illustrating a chain communication method provided in an embodiment of this application. Figure 4 As shown, the chain communication method provided in this application embodiment specifically includes S401 to S407, and S401 to S407 will be described in detail below.

[0043] The execution subject of the chain communication method provided in this application embodiment is any slave device in the above-mentioned chain communication system.

[0044] It should be noted that the device receives the target data frame from the superior device and forwards the target data frame to the subordinate device. The target data frame includes a preamble field and a valid data field.

[0045] S401, Receive the preamble field sent by the superior device from the device.

[0046] Specifically, the device sends the preamble field from the target data frame to the upstream device, and correspondingly, the device receives the preamble field sent by the upstream device through its receiving interface.

[0047] It should be noted that the target data frame is a serial data frame sent by the upper-level device according to a preset frame format. The preamble field is located at the beginning of the target data frame and is used to provide a reference for the decision of subsequent fields and the configuration of the transmission rate (for example, to estimate the first baud rate of the target data frame).

[0048] The length of the preamble field can be a preset fixed length or a variable length configured according to the protocol; this embodiment does not specifically limit this. The slave device can determine that the preamble field reception is complete and proceed to the next step when the received count reaches a preset length threshold or when a preamble end marker is detected.

[0049] For example, the preamble field is 4 consecutive bits of data 1.

[0050] In one implementation, the slave device samples and shapes the input signal on the receiving link and performs edge detection to identify the start of the preamble field. When a signal feature that conforms to a preset preamble pattern (such as a preset continuous bit sequence or a preset level-flipping sequence) is detected, the slave device determines that the currently received bit sequence is the preamble field and records the edge information or edge timestamp of the preamble field during the receiving process so as to determine the first baud rate of the target data frame in subsequent S402.

[0051] S402. The device sends a preamble field to the lower-level device and determines the first baud rate of the target data frame based on the edge spacing of the preamble field.

[0052] After receiving the preamble field from the target data frame, the slave device forwards the preamble field directly to the next-level device. The preamble field does not need to be written into the slave device's FIFO memory before being sent. Accordingly, the next-level device can prepare to receive subsequent fields based on the preamble field.

[0053] It should be noted that the first baud rate is used to characterize the communication rate parameter of the target data frame at the slave device. It can be used as the basis for configuring the initial transmission rate of the slave device for subsequent transmission of valid data bits, and is used to determine the bit period required for subsequent valid data bit decisions.

[0054] In one implementation, the slave device drives a counter with a local reference clock, starts counting when the first valid edge of the preamble field is detected, and stops counting when the next valid edge is detected, to obtain a count value that characterizes the edge interval, and uses the count value as the baud rate count; the slave device can determine the first baud rate based on the baud rate count.

[0055] It should be noted that the method for determining the first baud rate based on baud rate counting by the device is an existing method, and this embodiment does not specifically limit it.

[0056] Optionally, the slave device can count multiple adjacent edge intervals in the preamble field separately, and perform averaging, filtering, or median processing on the multiple count values ​​to obtain a baud rate count used to determine the first baud rate.

[0057] S403: The slave device receives valid data bits sent by the superior device and writes the valid data bits into the FIFO memory corresponding to the slave device.

[0058] In this process, after the upper-level device completes the transmission of the preamble field of the target data frame, it continues to transmit the valid data field in the target data frame; correspondingly, the slave device receives the valid data bits transmitted by the upper-level device through its receiving interface and writes the valid data bits into the corresponding first-in-first-out FIFO memory of the slave device.

[0059] It should be noted that the valid data field includes multiple valid data bits. Valid data bits are bit units in the target data frame used to carry valid information. This embodiment does not specifically limit the number of bits in the valid data field.

[0060] In one implementation, after determining the first baud rate of the target data frame, the slave device determines the bit period based on the first baud rate, and samples and decides on the input signal on the receiving link within the bit period to obtain the corresponding valid data bits. The slave device can then write each valid data bit obtained from the decision into its corresponding FIFO memory in the order of reception.

[0061] Each slave device corresponds to a FIFO memory, which can be a hardware FIFO, a circular queue implemented with on-chip memory, or other first-in-first-out cache structures. This embodiment does not specifically limit this.

[0062] Furthermore, the slave device can update the write pointer, record the write count, or maintain the remaining depth of the FIFO memory when writing to the FIFO memory.

[0063] S404. Determine whether the valid data bits in the FIFO memory are empty from the device.

[0064] If the valid data bits in the FIFO memory are empty, execute the method steps shown in S405; if the valid data bits in the FIFO memory are not empty, execute the method steps shown in S407.

[0065] S405. If the valid data bits in the FIFO memory are empty, determine whether the slave device has sent valid data bits.

[0066] If the valid data bits in the FIFO memory are empty, and the slave device has already sent valid data bits, it means that the sending side of the slave device has started forwarding valid data bits. However, the FIFO is currently empty, indicating that the sending side of the slave device is ahead of the receiving side. This is an underflow / undersupply state in the transmission process, rather than the start-up phase. Therefore, the slave device executes the method steps shown in S501.

[0067] If the valid data bits in the FIFO memory are empty and no valid data bits have been sent, it means that the slave device has not yet entered the valid data forwarding stage. It has not yet received and cached valid data bits in the FIFO from the upper-level device. Therefore, the slave device executes the method steps shown in S406.

[0068] S406. If the slave device has not sent any valid data bits, send a preset empty bit to the lower-level device.

[0069] In the initial stage of the valid data field, the slave device has not yet received valid data bits from the upper-level device that can be written into the FIFO, and the FIFO memory is empty. To avoid uncertain sampling or synchronization states caused by the lower-level device not receiving data for a long time, the slave device sends a preset empty bit to the lower-level device when the valid data bits in the FIFO memory are empty and the slave device has not sent any valid data bits, until the switching conditions are met. This ensures that the transmission link maintains continuous output before the valid data bits enter the forwarding stage.

[0070] It should be noted that the preset empty bit is a pre-set placeholder bit that does not carry valid information of the target data frame and is used to maintain continuous output of the transmission link when the FIFO memory is empty.

[0071] In this embodiment, the preset empty bit is set to logic "1".

[0072] It should be noted that the switching condition is that the slave device writes at least one valid data bit into the FIFO memory; when the switching condition is met, the slave device stops sending the preset empty bit and enters S407 to read the valid data bit in the FIFO memory for transmission.

[0073] S407. If the device has valid data bits in the FIFO memory, it reads the valid data bits from the FIFO memory and sends the valid data bits to the lower-level device based on the first baud rate.

[0074] The FIFO memory is a first-in, first-out (FIFO) structure. When reading from the FIFO memory, the data bits are read out sequentially according to the writing order of the valid data bits to maintain the consistency of the timing order of the valid data bits in the target data frame.

[0075] In one implementation, after the slave device detects that the FIFO memory has changed from empty to non-empty, it stops sending preset empty bits to the lower-level device and switches to reading valid data bits from the FIFO memory for transmission.

[0076] Specifically, the slave device can perform a read operation once when the preset transmission time is reached in each bit cycle, read out one valid data bit, and output the valid data bit to the lower-level device according to the transmission timing corresponding to the first baud rate.

[0077] S408. During the process of sending valid data bits, the slave device determines the deviation indication amount based on the write rate and read rate of valid data bits in the FIFO memory.

[0078] The deviation indicator is used to indicate the relationship between the write rate and the read rate and the degree of deviation.

[0079] It should be noted that the write rate is used to characterize the number of valid data bits written to the FIFO memory per unit time, and the read rate is used to characterize the number of valid data bits read from and sent from the FIFO memory per unit time; the deviation indicator is used to indicate the magnitude relationship and degree of deviation between the write rate and the read rate, so as to reflect the relative speed of the write rate on the receiving side and the read rate on the sending side of the device.

[0080] In one implementation, a preset statistics window is set on the device. Within the statistics window, the number of valid data bits written to the FIFO memory and the number of valid data bits read from the FIFO memory are counted respectively. The write rate and read rate are determined based on the statistics results.

[0081] For example, the device can clear the write counter and read counter to zero at the beginning of the statistics window, obtain the write count value and read count value at the end of the statistics window, and calculate the write rate and read rate by the ratio of the count value to the window duration.

[0082] In this embodiment, the statistics window can be a fixed duration window, a sliding window, or a window based on a preset number of bits. This embodiment does not limit the specific form of the statistics window.

[0083] Furthermore, the device can determine the type and value of the deviation indicator based on the write rate and the read rate: when the write rate is greater than the read rate, the deviation indicator is used to indicate the state of "write is faster than read"; when the read rate is greater than the write rate, the deviation indicator is used to indicate the state of "read is faster than write"; at the same time, the deviation indicator can also include magnitude information to characterize the degree of deviation, such as the difference, ratio or normalized difference between the write rate and the read rate.

[0084] S409. The device compensates for the first baud rate based on the deviation indication to obtain the target baud rate, and regards the target baud rate as the first baud rate, and repeatedly executes the method steps shown in S403.

[0085] The target baud rate is used to characterize the compensated communication rate parameter. The slave device can use the target baud rate as the updated value of the transmission rate and perform bit period timing and data output according to the target baud rate in the subsequent transmission process.

[0086] In one implementation, the slave device performs baud rate compensation based on the relationship between the write rate and read rate indicated by the deviation indicator. When the deviation indicator indicates that the write rate is greater than the read rate, the slave device increases the first baud rate; when the deviation indicator indicates that the read rate is greater than the write rate, the slave device decreases the first baud rate to obtain a target baud rate for subsequent transmission of valid data bits. This embodiment does not limit the specific stepping method of the increase or decrease process; the stepping method can be a fixed step, a graded step, or a stepping method adaptively determined based on the deviation magnitude.

[0087] This application provides a chained communication method. For each slave device, firstly, the slave device receives and directly forwards the preamble field to the next lower-level device. Simultaneously, the first baud rate of the target data frame is determined based on the edge interval of the preamble field, thus providing the slave device with an initial transmission rate matching the target data frame. Secondly, during the valid data field transmission phase, the received valid data bits are written into a FIFO memory, decoupling the writing on the receiving side and the reading and transmission on the sending side of the slave device in time. Therefore, clock deviations and link jitter from the upper-level device are primarily manifested as data backlog or insufficiency in the slave device's FIFO memory, rather than directly affecting the slave device's transmission waveform. Furthermore, when the slave device's FIFO memory is empty and no valid data bits have been transmitted, the slave device sends a preset empty bit to ensure continuous output of the transmission link before valid data enters the forwarding phase, avoiding... This prevents lower-level devices from experiencing uncertain sampling or synchronization states due to prolonged periods without receiving data. Subsequently, once the FIFO memory changes from empty to non-empty, the slave device reads valid data bits from the FIFO memory and sends them to the lower-level device according to the first baud rate, ensuring that the transmission timing is output based on the determined first baud rate. Finally, during the transmission process, the slave device statistically analyzes the write and read rates of valid data bits in the FIFO memory to form a deviation indicator. Based on the deviation indicator, it compensates for the first baud rate to obtain the target baud rate and updates the target baud rate to the new first baud rate. This dynamically pulls the transmission rate back to a range more consistent with the receiving side, thereby continuously suppressing the accumulation of timing errors caused by baud rate deviation and clock drift at each slave device level. This prevents errors from spreading to valid data and causing communication anomalies, thus improving the data transmission stability and reliability of chain communication.

[0088] Figure 5 This application provides a schematic diagram of a device receiving and sending target data frames, as shown in the embodiments of the present application. Figure 5 As shown, Figure 5 The upper part describes the receiving side processing flow from the device, and the lower part describes the sending side processing flow from the device. The receiving side first receives the preamble field of the target data frame and forwards it directly to the next-level device along the link direction. After the preamble field, the receiving side sequentially receives each valid data bit in the valid data field (e.g., valid data bit1, valid data bit2, and valid data bit3 as shown in the diagram), and writes the determined valid data bits into the first-in-first-out (FIFO) memory in the order of arrival. Figure 5 (As shown in the "Write" section). After forwarding the preamble field, if there are no valid data bits to be read from the FIFO memory of the slave device, the transmitting side outputs a preset empty bit as a placeholder to the lower-level device; when there are valid data bits in the FIFO memory, the transmitting side reads the valid data bits from the FIFO memory in a first-in-first-out order. Figure 5 (As shown in the "Read" section), and send it sequentially to the next-level device according to the current transmission baud rate, thereby realizing the combined processing of direct forwarding of the preamble and forwarding of valid data bits after FIFO buffering.

[0089] Figure 6 A schematic diagram of the transceiver timing of a slave device is provided for an embodiment of this application, such as... Figure 6 As shown, the receiving signal is the input signal received by the slave device from the upper-level device, and the transmitting signal is the output signal output by the lower-level device. When the slave device receives the target data frame, it first receives the preamble field located at the start of the frame (shown by the dashed box "preamble field" in the figure). Simultaneously, it cascades and forwards the preamble field to enable the lower-level device to obtain a frame start reference. At the same time, the slave device counts the level-flipping edges of the preamble field to obtain the edge interval and determines the first baud rate of the current target data frame. After determining the first baud rate, the slave device enters the receiving and transmitting phase of the valid data field: the slave device continues to receive the encoded signal corresponding to the valid data field sent by the upper-level device and determines the valid data bits, writing the valid data bits into the FIFO memory; when transmitting the valid data field to the lower-level device, the slave device generates a transmission bit period at the first baud rate, reads the valid data bits from the FIFO memory, and transmits them to the lower-level device according to the transmission bit period.

[0090] In one implementation, when the slave device starts receiving valid data fields, the FIFO memory is empty and the slave device has not yet sent any valid data bits. The slave device sends a preset empty bit to the lower-level device as a placeholder until a readable valid data bit appears in the FIFO memory, and then switches to sending valid data bits. This realizes the overall process of direct forwarding of the preamble, determining the baud rate based on the preamble, and forwarding valid data bits according to the baud rate.

[0091] In the above embodiments, the slave device needs to receive valid data bits sent by the superior device. The specific process of the slave device receiving valid data bits sent by the superior device will be described in detail below.

[0092] In one possible embodiment, the effective data bits are encoded and transmitted using Biphase Mark Code (BMC).

[0093] The upstream device outputs the BMC encoded signal corresponding to the valid data field on the physical link, and the downstream device receives the encoded signal corresponding to the valid data field through the receiving interface.

[0094] It should be noted that BMC encoding uses the level change characteristics per unit time to identify valid data bits.

[0095] Figure 7 A schematic diagram of a BMC waveform provided for an embodiment of this application, such as... Figure 7 As shown, a level flip within a preset unit of time (e.g., one bit period or its sub-interval) can be used to represent the bit value "1", and a level flip without a level flip within the unit of time can be used to represent the bit value "0".

[0096] In one implementation, the slave device can detect level switching characteristics in the first half of a bit cycle to obtain the decision information corresponding to the current bit, so as to generate valid data bits based on the decision information and perform buffering and forwarding in subsequent steps.

[0097] The method steps shown in S403 can be implemented by Sa1 and Sa3, which are described in detail below.

[0098] Sa1: Receives the encoded signal corresponding to the valid data field sent by the superior device from the device.

[0099] It should be noted that the encoded signal is the signal waveform transmitted on the communication link, which can be characterized by high and low levels and level transition edges. The encoded signal is used to carry and represent multiple valid data bits in the valid data field. What the receiving device directly obtains at the receiving end is the encoded signal, not the determined bit values.

[0100] Sa2. The slave device determines the bit period used to make decisions on the encoded signal based on the first baud rate.

[0101] The encoded signal is divided into multiple encoded signal segments according to the bit period in time.

[0102] It should be noted that the first baud rate is used to characterize the communication rate parameter of the target data frame. The slave device can determine the time length corresponding to a single bit, i.e., the bit period, based on the first baud rate. The bit period is used to limit the time window for decision-making on the encoded signal and to provide a time reference for subsequent decision-making based on features within the bit period.

[0103] The encoded signal is divided into multiple encoded signal segments according to the bit period in time. Each encoded signal segment corresponds to the encoded signal part within one bit period and is used to carry and represent one valid data bit.

[0104] In this embodiment, the slave device can segment the encoded signal based on the start and end times of the bit period. For example, using the start position of the detected valid data field as the initial segmentation reference point, multiple encoded signal segments are obtained by sequentially dividing the signal according to consecutive bit periods.

[0105] In one implementation, the slave device can generate a decision timing signal corresponding to the bit period based on a local timer or counter. For example, a counting threshold value corresponding to the bit period is obtained according to a first baud rate, and a segmentation boundary is generated when the count reaches the threshold value, thereby realizing the continuous division of the coded signal segment; during the division process, the slave device can record the sequence number, start and end timestamps, or corresponding sampling point range of the current coded signal segment so as to make a decision on the coded signal segment in subsequent Sa3.

[0106] Sa3. Based on the level switching characteristics in the first half of the bit period, the device makes a decision on the coded signal segment corresponding to the bit period to obtain the valid data bits corresponding to the coded signal segment.

[0107] It should be noted that the first half of the bit period refers to the first half of the bit period's time window. During this first half of the bit period's time window, the device detects changes in the level of the encoded signal segment and determines the bit value of the valid data bit according to the preset BMC decision rules.

[0108] For example, when a level flip (rising edge or falling edge) is detected in the first half of the cycle, the valid data bit corresponding to the decision coded signal segment is logic "1"; when no level flip is detected in the first half of the cycle, the valid data bit corresponding to the decision coded signal segment is logic "0".

[0109] This embodiment of the application, under the premise of using BMC transmission for the valid data field, enables the slave device to first receive the encoded signal corresponding to the valid data field, and establish a bit period for decision-making based on a first baud rate, thereby dividing the continuous encoded signal into encoded signal segments corresponding to each valid data bit in time. Subsequently, the slave device only needs to detect the level flipping feature of the encoded signal segment in the first half of each bit period to complete the decision of the current bit and obtain the corresponding valid data bit value. Since the decision time is moved to the first half of the bit period, the slave device can obtain the valid data bit earlier and enter the buffering and forwarding process, thereby reducing the timing lag caused by decision waiting in the chain-like step-by-step forwarding scenario, and to a certain extent reducing the risk of decision out-of-bounds due to the deviation of the transmit and receive rates, thereby improving the timing stability and reliability of valid data decision-making and forwarding.

[0110] In the above embodiments, the slave device needs to compensate the first baud rate based on the deviation indication to obtain the target baud rate. Next, the specific process by which the slave device compensates the first baud rate based on the deviation indication to obtain the target baud rate will be described in detail.

[0111] In one possible embodiment, the method steps shown in S407 can be implemented by Sc1 and Sc2, which are described in detail below.

[0112] Sc1. When the deviation indicator is used to indicate that the write rate is greater than the read rate, the slave device detects the remaining depth of the FIFO memory and increases the first baud rate based on the remaining depth to obtain the second baud rate, which is the target baud rate.

[0113] The remaining depth of the FIFO memory is used to characterize the size of the available cache space of the FIFO memory. The remaining depth of the FIFO memory can be determined by the total depth of the FIFO and the current occupancy, or it can be directly read from the hardware FIFO status register. This embodiment does not limit this.

[0114] In one implementation, the device reads the remaining depth of the FIFO memory in real time and compares it with a preset interval to determine the triggering and compensation magnitude of the amplification process. For example, the smaller the remaining depth, the larger the corresponding amplification magnitude. After completing the amplification process of the first baud rate, the device obtains a second baud rate and uses the second baud rate to configure the transmission rate of subsequent valid data bits.

[0115] Figure 8 This is a flowchart illustrating another chain-based communication method provided in an embodiment of this application. Figure 8 As shown, in one possible embodiment, Sc1 can be implemented by Sc11 to Sc19, which will be described in detail below.

[0116] Sc11, Detect the remaining depth of the FIFO memory from the device.

[0117] Sc12. Determine from the device whether the remaining depth is less than the first threshold.

[0118] The first threshold is a pre-set FIFO memory remaining depth threshold, which is used to classify and determine the occupancy status of the FIFO memory.

[0119] When the remaining depth is less than the first threshold, the FIFO memory is considered to have entered the first level of congestion risk range, thereby triggering the subsequent first level of baud rate compensation operation.

[0120] In this embodiment, the value of the first threshold can be determined based on parameters such as the total FIFO depth, the expected link jitter range, and the statistical window length. This embodiment does not limit the specific value of the first threshold.

[0121] Furthermore, both the second and third thresholds are smaller than the first threshold, and are used to form higher-level hierarchical triggering conditions.

[0122] Sc13. When the remaining depth is less than the first threshold, the slave device reduces the baud rate count corresponding to the first baud rate by the target number to obtain the fourth baud rate.

[0123] It should be noted that for any baud rate, the baud rate count corresponding to that baud rate is inversely proportional to that baud rate; that is, a decrease in the baud rate count corresponds to an increase in the baud rate.

[0124] The target quantity is a preset step size, which can be 1 or other integer steps. This embodiment does not limit the specific value of the target quantity.

[0125] In one implementation, when the remaining depth is less than a first threshold, the FIFO memory enters the first congestion risk zone, triggering the slave device to perform a first-level baud rate increase operation. The slave device performs a subtraction step operation on the register storing the baud rate count corresponding to the first baud rate to obtain the updated baud rate count, and calculates the fourth baud rate based on the updated baud rate count.

[0126] In one possible embodiment, when the remaining depth is greater than or equal to a first threshold, the method steps shown in Sc11 are repeatedly executed from the device.

[0127] It should be noted that when the remaining depth is greater than or equal to the first threshold, it indicates that the FIFO memory has not entered the first level of congestion risk range, and the slave device continues to repeatedly execute Sc11 to update the remaining depth.

[0128] Sc14. If the remaining depth is less than the first threshold, the device determines whether the remaining depth is less than the second threshold, and the second threshold is less than the first threshold.

[0129] After the first baud rate increase operation has been triggered, the device further determines whether the remaining depth is less than the second threshold.

[0130] It should be noted that the second threshold corresponds to a higher level of congestion determination condition, which is used to indicate the state where the remaining space of the FIFO memory is further reduced.

[0131] Sc15. When the remaining depth is less than the second threshold, the slave device reduces the baud rate count corresponding to the fourth baud rate by the target number to obtain the fifth baud rate.

[0132] It should be noted that when the remaining depth is less than the second threshold, the FIFO memory enters the second level of congestion risk range, triggering the slave device to perform the second level of baud rate increase operation. On the basis of the first level of baud rate increase operation, a subtraction step compensation is performed again to further reduce the baud rate count, thereby obtaining the fifth baud rate.

[0133] Sc16. When the remaining depth is greater than or equal to the second threshold, the slave device determines the fourth baud rate as the second baud rate.

[0134] When the remaining depth is greater than or equal to the second threshold, it indicates that the second baud rate increase operation has not been triggered, and the slave device will determine the fourth baud rate as the second baud rate.

[0135] It should be noted that the second baud rate is used as the result of this increase processing based on the remaining depth (i.e., one implementation of the target baud rate). Therefore, when a higher level of compensation is not triggered, the fourth baud rate obtained by the slave device from the first baud rate increase operation is used as the final output second baud rate and is used for subsequent baud rate configuration updates on the transmitting side.

[0136] Sc17. If the remaining depth is less than the second threshold, the device determines whether the remaining depth is less than the third threshold, and the third threshold is less than the second threshold.

[0137] After the second baud rate increase operation has been triggered, the device further determines whether the remaining depth is less than the third threshold.

[0138] It should be noted that the third threshold corresponds to the highest level of congestion determination condition, which is used to indicate the state where the remaining space of the FIFO memory is further reduced.

[0139] The value of the third threshold, together with the first and second thresholds, forms a hierarchical interval. This embodiment does not impose specific limitations on this.

[0140] Sc18. When the remaining depth is less than the third threshold, the slave device reduces the baud rate count corresponding to the fifth baud rate by the target number to obtain the sixth baud rate, and determines the sixth baud rate as the second baud rate.

[0141] It should be noted that when the remaining depth is less than the third threshold, the FIFO memory enters the third level of congestion risk range, triggering the slave device to perform the third level of baud rate increase operation. On the basis of the second level of baud rate increase operation, a subtraction step compensation is performed again to further reduce the baud rate count, thereby obtaining the sixth baud rate.

[0142] When the third baud rate increase operation is triggered, the slave device uses the sixth baud rate obtained from the third baud rate increase operation as the final output second baud rate, which is used for subsequent baud rate configuration updates on the transmitting side.

[0143] Sc19. When the remaining depth is greater than or equal to the third threshold, the slave device determines the fifth baud rate as the second baud rate.

[0144] When the remaining depth is greater than or equal to the third threshold, it indicates that the third baud rate increase operation has not been triggered, and the slave device determines the fifth baud rate as the second baud rate.

[0145] It should be noted that if the triggering conditions for the second baud rate increase operation have been met and the fifth baud rate has been obtained, but the triggering conditions for the third baud rate increase operation are no longer met, the slave device will use the fifth baud rate obtained from the second baud rate increase operation as the final output second baud rate, and use it for subsequent baud rate configuration updates on the transmitting side.

[0146] In this embodiment, when the write rate is greater than the read rate, a graded threshold determination mechanism based on the remaining FIFO depth is introduced. This mechanism maps the FIFO congestion level to graded compensation levels for the first baud rate. When the remaining depth is successively lower than the first, second, and third thresholds, the baud rate count corresponding to the first baud rate is updated in decreasing steps once, twice, and three times, respectively. Based on this, different levels of compensation baud rates are obtained, and the corresponding compensation results are then determined as the second baud rate for updating the sending-side rate configuration. Since the baud rate count is inversely proportional to the baud rate, the gradual decrease in the baud rate count corresponds to the gradual increase in the sending-side baud rate. This allows the slave device to adaptively adjust the sending rate according to changes in the remaining FIFO space. The compensation level is increased when data accumulation intensifies, and a smaller compensation level is maintained when a higher level threshold is not reached. This suppresses the continuous filling of the FIFO and the subsequent expansion of timing deviations caused by the receiving rate being faster than the sending rate during chain forwarding, thereby improving the timing matching stability and data transmission reliability of the cascade forwarding process.

[0147] Sc2. When the deviation indicator is used to indicate that the read rate is greater than the write rate, the slave device determines the transmit lead time and reduces the first baud rate based on the transmit lead time to obtain the third baud rate, which is the target baud rate.

[0148] The send lead time is the amount of time that the read rate leads the write rate.

[0149] It should be noted that the transmission lead time is used to characterize the extent to which the transmitting side leads the receiving side on the time axis.

[0150] In one implementation, the slave device can determine the transmission lead time using a timing method. For example, the time difference between the time when the transmitting side prepares to transmit the next valid data bit and the time when the receiving side writes the corresponding valid data bit into the FIFO memory can be calculated as the transmission lead time.

[0151] Figure 9 This is a flowchart illustrating another chain communication method provided in an embodiment of this application. Figure 9 As shown, in one possible embodiment, Sc2 can be implemented by Sc21 to Sc29, which will be described in detail below.

[0152] Sc21. Determine the transmission lead time from the device.

[0153] It should be noted that the transmission lead time is used to characterize the degree of time lead of the transmitting side relative to the receiving side. For example, it can characterize the time difference between the time when the transmitting side reads and prepares to send the next valid data and the time when the receiving side writes the corresponding valid data. When the transmission lead time increases, it indicates that the degree of lead of the transmitting side relative to the receiving side increases.

[0154] Sc22. Determine from the device whether the transmission lead time is greater than the fourth threshold.

[0155] In this embodiment, the fourth threshold is a preset time threshold used to trigger the first baud rate reduction operation.

[0156] In one possible embodiment, when the transmission lead time is less than or equal to a first threshold, the slave device repeatedly executes the method steps shown in Sc21.

[0157] Sc23. When the transmission lead time is greater than the fourth threshold, the slave device increases the baud rate count corresponding to the first baud rate by the target number to obtain the seventh baud rate.

[0158] Specifically, when the transmission lead time is greater than the fourth threshold, the transmission baud rate (first baud rate) can be reduced by increasing the baud rate count corresponding to the first baud rate by a preset step (target number).

[0159] In one implementation, the slave device performs an addition step operation on the register storing the baud rate count corresponding to the first baud rate, and calculates the seventh baud rate based on the updated baud rate count.

[0160] Sc24. If the transmission lead time is greater than the fourth threshold, the slave device determines whether the transmission lead time is greater than the fifth threshold, and the fifth threshold is greater than the fourth threshold.

[0161] It should be noted that the fifth threshold corresponds to a higher level of triggering conditions, used to indicate a state where the transmission lead time has further increased; when the transmission lead time is greater than the fifth threshold, the second level of baud rate reduction operation can be triggered.

[0162] Sc25. When the transmission lead time is greater than the fifth threshold, the slave device increases the baud rate count corresponding to the seventh baud rate by the target number to obtain the eighth baud rate.

[0163] When the transmission lead time is greater than the fifth threshold, it indicates that the trigger condition for the second baud rate reduction operation is met. The slave device increases the baud rate count corresponding to the seventh baud rate by the target number to obtain the eighth baud rate. This is equivalent to continuing to perform an addition step on the basis of the first addition step, so that the baud rate count is further increased, thereby obtaining the transmission side baud rate configuration corresponding to the eighth baud rate.

[0164] Sc26. When the transmission lead time is less than or equal to the fifth threshold, the slave device determines the seventh baud rate as the third baud rate.

[0165] When the transmission lead time is less than or equal to the fifth threshold, it indicates that the trigger condition for the second baud rate reduction process has not been met, and the slave device determines the seventh baud rate as the third baud rate.

[0166] It should be noted that the third baud rate is used as the result of this baud rate reduction operation based on the transmission lead time. Therefore, if a higher level of addition step is not triggered, the slave device uses the seventh baud rate obtained from the first baud rate reduction operation as the final output third baud rate, and uses it for subsequent baud rate configuration updates on the transmitting side.

[0167] Sc27. If the transmission lead time is greater than the fifth threshold, the slave device determines whether the transmission lead time is greater than the sixth threshold, and the sixth threshold is greater than the fifth threshold.

[0168] It should be noted that the sixth threshold corresponds to the highest level of triggering conditions, indicating a further increase in the lead time on the transmitting side. When the transmission lead time exceeds the sixth threshold, a third-level baud rate reduction operation can be triggered.

[0169] In this embodiment, the sixth threshold is configured together with the fourth and fifth thresholds to form a hierarchical interval, and the specific values ​​of the fourth, fifth and sixth thresholds are not limited.

[0170] Sc28. When the transmission lead time is greater than the sixth threshold, the slave device increases the baud rate count corresponding to the eighth baud rate by the target number to obtain the ninth baud rate, and determines the ninth baud rate as the third baud rate.

[0171] It should be noted that the third baud rate reduction operation is equivalent to performing another addition step on the basis of the first two addition steps, which further increases the baud rate count, thereby obtaining the transmitting side baud rate configuration corresponding to the ninth baud rate.

[0172] When the trigger condition for the third baud rate reduction processing is met, the slave device uses the ninth baud rate as the final output third baud rate for subsequent baud rate configuration updates on the transmitting side.

[0173] Sc29. When the transmission lead time is less than or equal to the sixth threshold, the slave device determines the eighth baud rate as the third baud rate.

[0174] When the transmission lead time is less than or equal to the sixth threshold, it indicates that the triggering condition for the third baud rate reduction operation has not been met. If the triggering condition for the second baud rate reduction operation has been met and the eighth baud rate has been obtained, and the triggering condition for the third baud rate reduction operation is no longer met, the slave device will use the eighth baud rate obtained from the second baud rate reduction operation as the final output third baud rate, and use it for subsequent baud rate configuration updates on the transmitting side.

[0175] In this embodiment, when the deviation indicator indicates that the read rate is greater than the write rate, i.e., the sending side has a time lead relative to the receiving side, a graded threshold determination mechanism based on the transmission lead time is introduced. The degree of transmission lead is mapped to the graded reduction of the first baud rate: when the transmission lead time is successively greater than the fourth threshold, the fifth threshold, and the sixth threshold, the baud rate count corresponding to the first baud rate is updated by one, two, and three increments, respectively, and different levels of compensation baud rates are obtained accordingly. The corresponding compensation result is then determined as the third baud rate to update the sending side rate configuration. Since the baud rate count is inversely proportional to the baud rate, the gradual increase of the baud rate count corresponds to the gradual decrease of the sending side baud rate. This allows the slave device to adaptively adjust the transmission rate according to the change of the transmission lead time. When the lead is aggravated, the reduction processing intensity is increased, and when a higher level threshold is not reached, the reduction processing intensity is kept small. This suppresses the FIFO emptying caused by the transmission being faster than the reception and the expansion of the sending side lead, reduces the risk of the spread of timing deviation in chain cascading, and improves the timing matching stability and data transmission reliability of the step-by-step forwarding process.

[0176] In one possible embodiment, the fourth threshold is one-eighth, the fifth threshold is one-quarter, and the sixth threshold is three-eighths.

[0177] This application sets the classification threshold based on transmission lead time to a normalized time threshold proportional to the bit period, where the fourth, fifth, and sixth thresholds are one-eighth, one-quarter, and three-eighths of the bit period, respectively. This makes the judgment of transmission lead degree no longer dependent on absolute time, but consistent with the bit time scale corresponding to the current baud rate. Therefore, regardless of the range of the first baud rate, the slave device can classify the lead degree under a unified relative time reference and trigger the corresponding baud rate reduction process, thereby improving the portability and consistency of threshold judgment and compensation triggering, avoiding threshold criterion mismatch due to baud rate changes, and thus enhancing the stability and reliability of the transmission side rate adjustment during chain forwarding.

[0178] In one possible embodiment, the method further includes S501 to S503, which are described in detail below.

[0179] S501. If the valid data bits in the FIFO memory are empty and the slave device has sent valid data bits, the slave device will bypass the valid data bits and send them to the next-level device, and control the valid data bits not to be written into the FIFO memory.

[0180] When the deviation indicator is used to indicate that the read rate is greater than the write rate, it means that the sending side is reading from and sending data from the FIFO memory faster than the receiving side is writing data to the FIFO memory, which may result in the FIFO being about to be empty or already empty. If the valid data bits in the FIFO memory are empty, the slave device will bypass and send the currently valid data bits to the next lower-level device and control the valid data bits not to be written to the FIFO memory.

[0181] It should be noted that bypass transmission refers to the slave device directly outputting the valid data bits obtained from the decision to the next-level device without forwarding them through the FIFO memory buffer. Not writing to the FIFO memory is to avoid the same valid data bit being output through the bypass path and then repeatedly buffered through the FIFO path at the same time, which would lead to repeated transmission or disordered transmission order.

[0182] In one implementation, after receiving the encoded signal corresponding to the valid data field sent by the superior device and completing the bit decision, the slave device generates the current valid data bit. When the deviation indicator indicates that the read rate is greater than the write rate and the valid data bit in the FIFO memory is empty, the slave device sends the current valid data bit directly into the transmission logic through the bypass path and outputs it to the lower-level device according to the transmission timing corresponding to the current transmission baud rate. At the same time, the FIFO write enable is gated to prevent the current valid data bit from being written to the FIFO memory.

[0183] In another alternative implementation, if the slave device has written the currently valid data bits into the FIFO memory before the bypass trigger time, the slave device can suppress the read control of the FIFO memory or discard the read data to prevent the currently valid data bits from being read and retransmitted via the FIFO path later.

[0184] In one possible embodiment, the slave device detects the state of the FIFO memory during the valid data forwarding process of the target data frame and sets a preset timeout. When the slave device's FIFO memory is empty and the slave device does not receive any valid data bits from the upstream device within the preset timeout, the slave device considers that the reception and transmission process of the target data frame has been completed and ends the current communication process.

[0185] Figure 10 This is a schematic diagram of the structure of a slave device provided in an embodiment of this application. Figure 10 As shown, the slave device 1000 provided in this embodiment can exist independently and is used to implement the operations corresponding to the slave device in the above method embodiment.

[0186] The slave device 1000 may include a transceiver module 1001 and a processing module 1002. The processing module 1002 is used for data processing, and the transceiver module 1001 can implement corresponding communication functions. The transceiver module 1001 may also be referred to as a communication interface or a communication unit.

[0187] Optionally, the slave device 1000 may further include a storage unit, which can be used to store instructions and / or data. The processing module 1002 can read the instructions and / or data in the storage unit so that the slave device 1000 can implement the steps implemented by the slave device in the foregoing method embodiments.

[0188] The transceiver module 1001 is used to perform the receiving-related operations of the slave device in the method embodiment above, and the processing module 1002 is used to perform the processing-related operations of the slave device in the method embodiment above.

[0189] Optionally, the transceiver module 1001 may include a sending module and a receiving module. The sending module is used to perform the sending operation in the above method embodiments. The receiving module is used to perform the receiving operation in the above method embodiments.

[0190] It should be noted that the slave device 1000 may include a transmitting module but not a receiving module. Alternatively, the slave device 1000 may include a receiving module but not a transmitting module. This depends on whether the above-described scheme executed by the slave device 1000 includes both transmitting and receiving actions.

[0191] As an example, device 1000 is used to perform the aforementioned... Figure 4 The actions performed by the device in the illustrated embodiment.

[0192] The device 1000 may include a transceiver module 1001 and a processing module 1002.

[0193] The transceiver module 1001 is used to receive the preamble field sent by the upstream device.

[0194] The transceiver module 1001 is used to send a preamble field to a lower-level device and determine the first baud rate of the target data frame based on the edge spacing of the preamble field.

[0195] The transceiver module 1001 is used to receive valid data bits sent by the upper-level device and write the valid data bits into the corresponding first-in-first-out FIFO memory of the slave device.

[0196] The transceiver module 1001 is used to send a preset empty bit to the lower-level device when the valid data bits in the FIFO memory are empty and the slave device has not sent any valid data bits.

[0197] The transceiver module 1001 is used to read valid data bits from the FIFO memory when valid data bits exist in the FIFO memory, and to send the valid data bits to the lower-level device based on a first baud rate.

[0198] The processing module 1002 is used to determine the deviation indicator based on the write rate and read rate of the valid data bits in the FIFO memory during the transmission of valid data bits. The deviation indicator is used to indicate the magnitude relationship and degree of deviation between the write rate and the read rate.

[0199] The processing module 1002 is used to compensate the first baud rate based on the deviation indication to obtain the target baud rate, and to treat the target baud rate as the first baud rate, and to repeatedly execute the step of receiving valid data bits sent by the upper-level device from the slave device.

[0200] It should be understood that the corresponding processes performed by each module have been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0201] The processing module 1002 in the preceding embodiments can be implemented by at least one processor or processor-related circuitry. The transceiver module 1001 can be implemented by a transceiver or transceiver-related circuitry. The transceiver module 1001 can also be referred to as a communication unit or communication interface. The storage unit can be implemented by at least one memory.

[0202] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 11 As shown, the electronic device 1100 provided in this embodiment includes a memory 1101 and a processor 1102.

[0203] The memory 1101 can be a separate physical unit, connected to the processor 1102 via a bus 1103. Alternatively, the memory 1101 and processor 1102 can be integrated and implemented in hardware. The memory 1101 stores program instructions, which the processor 1102 calls to execute operations performed by the slave device in any of the above method embodiments.

[0204] Optionally, when some or all of the methods in the above embodiments are implemented by software, the electronic device 1100 may also include only the processor 1102. The memory 1101 for storing programs is located outside the electronic device 1100, and the processor 1102 is connected to the memory via circuits / wires to read and execute the programs stored in the memory. The processor 1102 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. The processor 1102 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0205] The memory 1101 may include volatile memory, such as random-access memory (RAM); the memory may also include non-volatile memory, such as flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory may also include a combination of the above types of memory.

[0206] For example, this application provides a chip including: an interface circuit and a logic circuit. The interface circuit is used to receive signals from other chips outside the chip and transmit them to the logic circuit, or to send signals from the logic circuit to other chips outside the chip. The logic circuit is used to perform operations performed by the device in the above method embodiments.

[0207] For example, this application provides a computer-readable storage medium having computer program instructions stored thereon, which are executed by a processor of an electronic device to cause the electronic device to perform the operations performed by the device in the above method embodiments.

[0208] For example, this application provides a computer program product that, when run on an electronic device, causes the electronic device to perform the operations performed by the device in the above method embodiments.

[0209] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chained communication method applied to a chained communication system, the chained communication system comprising a master device and multiple slave devices; the multiple slave devices are cascaded in series, the first slave device in the cascaded series is connected to the output terminal of the master device, and the last slave device in the cascaded series is connected to the input terminal of the master device, the slave devices are used to receive target data frames from upper-level devices and forward the target data frames to lower-level devices, the target data frame comprising a preamble field and a valid data field, the valid data field comprising multiple valid data bits, characterized in that, The method includes: The device receives the preamble field sent by the superior device; The slave device sends the preamble field to the lower-level device and determines the first baud rate of the target data frame based on the edge spacing of the preamble field; The slave device receives the valid data bits sent by the upper-level device and writes the valid data bits into the first-in-first-out (FIFO) memory corresponding to the slave device. When the slave device has the valid data bits in the FIFO memory, it reads the valid data bits from the FIFO memory and sends the valid data bits to the lower-level device based on the first baud rate. During the transmission of the valid data bits, the slave device determines a deviation indicator based on the write rate and read rate of the valid data bits in the FIFO memory. The deviation indicator is used to indicate the magnitude relationship and degree of deviation between the write rate and the read rate. The slave device compensates for the first baud rate based on the deviation indication to obtain a target baud rate, and treats the target baud rate as the first baud rate, and cyclically executes the step of the slave device receiving the valid data bits sent by the upper-level device.

2. The method according to claim 1, characterized in that, The method further includes: If the slave device has no valid data bits in the FIFO memory and has not sent any valid data bits, it sends a preset empty bit to the lower-level device.

3. The method according to claim 1, characterized in that, The effective data bits are encoded and transmitted using Biphase Marker (BMC) encoding. The process of receiving the valid data bits sent by the superior device from the slave device includes: The device receives the encoded signal corresponding to the valid data field sent by the superior device; The slave device determines the bit period for making a decision on the encoded signal based on the first baud rate; wherein the encoded signal is divided into multiple encoded signal segments in time according to the bit period; The slave device makes a decision on the encoded signal segment corresponding to the bit period based on the level switching characteristics in the first half of the bit period, and obtains the effective data bits corresponding to the encoded signal segment.

4. The method according to claim 1, characterized in that, The slave device compensates for the first baud rate based on the deviation indication to obtain the target baud rate, including: When the deviation indicator is used to indicate that the write rate is greater than the read rate, the slave device detects the remaining depth of the FIFO memory and increases the first baud rate based on the remaining depth to obtain a second baud rate, where the second baud rate is the target baud rate. When the deviation indicator is used to indicate that the read rate is greater than the write rate, the slave device determines the transmit lead time and reduces the first baud rate based on the transmit lead time to obtain a third baud rate, wherein the third baud rate is the target baud rate; wherein the transmit lead time is the time lead of the read rate relative to the write rate.

5. The method according to claim 4, characterized in that, The slave device increases the first baud rate based on the remaining depth of the FIFO memory to obtain the second baud rate, including: The device detects the remaining depth of the FIFO memory; The slave device determines whether the remaining depth is less than a first threshold. When the remaining depth is less than the first threshold, the slave device reduces the baud rate count corresponding to the first baud rate by a target number to obtain a fourth baud rate; The slave device determines whether the remaining depth is less than a second threshold, where the second threshold is less than the first threshold. When the remaining depth is less than the second threshold, the slave device reduces the baud rate count corresponding to the fourth baud rate by the target number to obtain the fifth baud rate; When the remaining depth is greater than or equal to the second threshold, the slave device determines the fourth baud rate as the second baud rate; The slave device determines whether the remaining depth is less than a third threshold, wherein the third threshold is less than the second threshold; When the remaining depth is less than the third threshold, the slave device reduces the baud rate count corresponding to the fifth baud rate by the target number to obtain a sixth baud rate, and determines the sixth baud rate as the second baud rate; When the remaining depth is greater than or equal to the third threshold, the slave device determines the fifth baud rate as the second baud rate.

6. The method according to claim 4, characterized in that, The slave device reduces the first baud rate based on the transmission lead time to obtain the third baud rate, including: The device determines the transmission lead time; The slave device determines whether the transmission lead time is greater than a fourth threshold. When the transmission lead time is greater than the fourth threshold, the slave device increases the baud rate count corresponding to the first baud rate by a target number to obtain the seventh baud rate; The slave device determines whether the transmission lead time is greater than a fifth threshold, wherein the fifth threshold is greater than the fourth threshold; When the transmission lead time is greater than the fifth threshold, the slave device increases the baud rate count corresponding to the seventh baud rate by the target number to obtain the eighth baud rate; When the transmission lead time is less than or equal to the fifth threshold, the slave device determines the seventh baud rate as the third baud rate; The slave device determines whether the transmission lead time is greater than a sixth threshold, wherein the sixth threshold is greater than the fifth threshold; When the transmission lead time is greater than the sixth threshold, the slave device increases the baud rate count corresponding to the eighth baud rate by the target number to obtain the ninth baud rate, and determines the ninth baud rate as the third baud rate; When the transmission lead time is less than or equal to the sixth threshold, the slave device determines the eighth baud rate as the third baud rate.

7. The method according to claim 6, characterized in that, The fourth threshold is one-eighth, the fifth threshold is one-quarter, and the sixth threshold is three-eighths.

8. The method according to claim 5 or 6, characterized in that, The target quantity is 1; The baud rate count of the target baud rate is used to determine the target baud rate, and the baud rate count of the target baud rate is inversely proportional to the target baud rate.

9. The method according to claim 1, characterized in that, When the deviation indicator is used to indicate that the read rate is greater than the write rate, the method further includes: When the valid data bits in the FIFO memory are empty, the slave device bypasses the valid data bits and sends them to the lower-level device, and controls the valid data bits not to be written into the FIFO memory.

10. A chain-type communication system, characterized in that, The system includes a master device and multiple slave devices; The plurality of slave devices are cascaded in series, with the first slave device in the cascade connected to the output terminal of the master device, and the last slave device in the cascade connected to the input terminal of the master device. The slave device is used to implement the method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when executed, implement the method as described in any one of claims 1 to 9.

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