A track allocation method based on pseudo boolean optimization local search in wiring

Abstract

The application discloses a track allocation method based on pseudo Boolean optimization local search in wiring, and steps of the method comprise: generating a topological model containing hierarchical track, wire net and obstacle information according to topological information of hierarchical panel data structure of a large-scale integrated circuit to be analyzed; generating a multi-dimensional overlapping cost quantization model based on an overlapping area calculation rule and the topological model; constructing a decision variable matrix, and converting the decision variable matrix into a pseudo Boolean optimization constraint matrix by setting a constraint condition; generating a global approximate optimal solution sequence based on an initial solution of the pseudo Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; and generating a track layout scheme of the large-scale integrated circuit to be analyzed according to an optimal solution in the global approximate optimal solution sequence to perform track layout. The optimization process of the application can dynamically respond to design rule requirements of different process nodes, and effectively reduces the rule violation risk in the manufacturing stage.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation technology and relates to a track allocation method based on pseudo-Boolean optimization local search in wiring. Background Technology

[0002] Electronic Design Automation (EDA) is a core technology supporting modern integrated circuit design. It primarily involves the development of a complete toolchain from system-level design to physical implementation, covering key stages such as logic synthesis, placement and routing, timing analysis, and power optimization. This field addresses the complexity challenges of designing circuits with hundreds of millions of transistors at the nanometer scale through algorithmic innovation and computational architecture optimization. Particularly in the physical design stage, it addresses core issues such as routing congestion, signal integrity, and manufacturing process constraints. Among these, the pseudo-Boolean optimization-based local search track allocation method in routing refers to a technical solution that transforms the routing resource allocation problem into a pseudo-Boolean optimization model and uses a heuristic local search algorithm for efficient solution in the track allocation stage of integrated circuit physical design.

[0003] In handling large-scale integrated circuit routing, existing technologies often face a trade-off between solution space search efficiency and constraint satisfaction in the track allocation process. Traditional local search algorithms, employing fixed neighborhood radii and static weight settings, are prone to getting trapped in local optima when dealing with multi-layered routing structures. For example, in 16nm process node testing, the standard algorithm exhibited a suboptimal solution probability of 12.3% for allocating over 5000 tracks. Evaluation models based on a single cost dimension fail to accurately reflect the multi-objective conflicts in actual manufacturing, resulting in an average of 3.2 design iterations required to correct the routing scheme during the timing convergence phase. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a track allocation method based on pseudo-Boolean optimization local search in wiring. This method solves the contradiction between solution space search efficiency and constraint satisfaction that often exists in existing technologies when dealing with large-scale integrated circuit wiring. Traditional local search algorithms use fixed neighborhood radii and static weight settings, which are prone to getting trapped in local optima when dealing with multi-layer wiring structures. For example, in 16-nanometer process node testing, the standard algorithm has a suboptimal solution probability of 12.3% for the task of allocating more than 5,000 tracks.

[0005] The technical solution of this invention is as follows: A track allocation method based on pseudo-Boolean optimization local search in wiring, comprising the following steps: Based on the topology information of the layered panel data structure of the large-scale integrated circuit wiring to be analyzed, a topology model containing layered track, net and obstacle information is generated. Based on the overlap area calculation rule and the aforementioned topological model, a multi-dimensional overlap cost quantification model is generated. Construct a decision variable matrix, and then convert the decision variable matrix into a pseudo-Boolean optimization constraint matrix by setting constraints; A global approximate optimal solution sequence is generated based on the initial solution of the pseudo-Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; Based on the optimal solution in the global approximate optimal solution sequence, a track layout scheme for the wiring of the large-scale integrated circuit to be analyzed is generated for track layout.

[0006] Preferably, the multi-dimensional overlap cost includes line segment overlap cost, pin conflict cost, and obstacle avoidance cost.

[0007] Preferably, a feasible solution space reference vector is generated based on the pseudo-Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; a local optimal solution candidate pool is generated based on the feasible solution space reference vector; the current optimal solution is iteratively updated to generate a global approximate optimal solution sequence.

[0008] Preferably, an initial solution satisfying the pseudo-Boolean optimization constraint matrix is ​​generated by Monte Carlo random sampling; the initial cost is calculated based on the initial solution and the multi-dimensional overlapping cost quantization model, and the initial cost is used as the reference vector of the feasible solution space.

[0009] Preferably, the method for generating the local optimal solution candidate pool is as follows: using a variable neighborhood search strategy, starting from the current optimal solution in the feasible solution space reference vector, performing a single bit flip operation to generate a set of candidate solutions in the surrounding neighborhood of the current solution, adding candidate solutions with a number of tabu operations within a threshold into the candidate pool, and selecting candidate solutions from them to generate the local optimal solution candidate pool.

[0010] Preferably, the method for generating the topology model is as follows: generating the track and the network segment to be wired for each layer of the layered panel data structure, mapping the inaccessible area in the layer of the panel to an obstacle; creating an axial priority search tree and an R* tree index structure according to the preferred direction of each layer of the panel, and generating a cross-panel connection relationship matrix to form the topology model.

[0011] Preferably, the constraints include single-track constraints and obstacle constraints.

[0012] A track assignment system based on pseudo-Boolean optimization local search in cabling, characterized in that it includes: The topology model generation module generates a topology model containing layered track, net, and obstacle information based on the topology information of the layered panel data structure of the large-scale integrated circuit wiring to be analyzed. The multi-dimensional overlap cost quantification model generation module generates a multi-dimensional overlap cost quantification model based on the overlap area calculation rule and the topological model. The pseudo-Boolean optimization constraint matrix generation module constructs a decision variable matrix and converts the decision variable matrix into a pseudo-Boolean optimization constraint matrix by setting constraints. The global approximate optimal solution sequence generation module generates a global approximate optimal solution sequence based on the initial solution of the pseudo-Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; The track layout scheme generation module generates a track layout scheme for the large-scale integrated circuit wiring to be analyzed based on the optimal solution in the global approximate optimal solution sequence, and then performs track layout.

[0013] A computer device includes a memory and a processor, the memory storing a computer program configured to be executed by the processor, the computer program including instructions for performing the methods described above.

[0014] A computer-readable storage medium having a computer program stored thereon, characterized in that the computer program implements the above-described method when executed by a processor.

[0015] The present invention has the following beneficial effects: This invention integrates tracks, nets, obstacles, and soft constraints into a unified topology model through the application of a hierarchical panel data structure. Through coordinate normalization and hierarchical spatial indexing, it achieves collaborative analysis of multi-dimensional design elements. A three-dimensional cost function integrates multi-objective quantitative evaluation of track overlap, pin conflicts, and obstacle avoidance. A process-sensitive conflict intensity distribution model is established using the Manhattan projection method and a dynamic weight fusion mechanism. A constraint matrix generation method based on pseudo-Boolean optimization, combined with 0-1 integer programming and obstacle masking technology, forms a scalable constraint expression system. The collaborative application of Monte Carlo random initialization and variable neighborhood search strategies, through tabu-guided local search and dynamic radius adjustment, achieves a balance between efficiency and quality in solution space exploration. An adaptive adjustment mechanism for hard constraint weights, combined with an elite retention strategy, enables the optimization process to dynamically respond to design rule requirements at different process nodes. The application of bilinear interpolation compensation and iterative repair mechanisms ensures high-fidelity conversion from mathematical optimization results to physical layout, effectively reducing the risk of rule violations during the manufacturing stage. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method of the present invention.

[0017] Figure 2 This is a schematic diagram of the main process of an embodiment of the present invention.

[0018] Figure 3 This is a detailed schematic diagram of step S1 of the present invention.

[0019] Figure 4 This is a detailed schematic diagram of step S2 of the present invention.

[0020] Figure 5 This is a detailed schematic diagram of step S3 of the present invention.

[0021] Figure 6 This is a detailed schematic diagram of step S4 of the present invention.

[0022] Figure 7 This is a detailed schematic diagram of step S5 of the present invention.

[0023] Figure 8 This is a detailed schematic diagram of step S6 of the present invention.

[0024] Figure 9 This is a detailed schematic diagram of step S7 of the present invention.

[0025] Figure 10 This is a system block diagram of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The process of the track allocation method based on pseudo-Boolean optimization local search in the wiring of this invention is as follows: Figure 1 As shown, the steps include: Based on the topology information of the layered panel data structure of the large-scale integrated circuit wiring to be analyzed, a topology model containing layered track, net and obstacle information is generated. Based on the overlap area calculation rule and the aforementioned topological model, a multi-dimensional overlap cost quantification model is generated. Construct a decision variable matrix, and then convert the decision variable matrix into a pseudo-Boolean optimization constraint matrix by setting constraints; A global approximate optimal solution sequence is generated based on the initial solution of the pseudo-Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; Based on the optimal solution in the global approximate optimal solution sequence, a track layout scheme for the wiring of the large-scale integrated circuit to be analyzed is generated for track layout.

[0028] like Figure 2 As shown, an optional embodiment of the present invention provides a track allocation method based on pseudo-Boolean optimization local search in wiring, including the following steps: S1: Based on the layered panel data structure of the large-scale integrated circuit wiring to be analyzed, the topology information is extracted using a track feature parsing algorithm, and obtained through a multi-list parsing module: track set T={t1,t2,...,t...} m The set of line segments to be assigned is S = {s1, s2, ..., s...} n};The set of hard obstacles B={b1,b2,...,b p};The set of soft constraints F={f1,f2,...,f q}, generate a hierarchical track-net-obstacle quadruple topology model with a hierarchical panel data structure; where t m For the m-th orbit, s n For the nth line segment to be assigned, b p Let f be the p-th hard obstacle and fq be the q-th soft constraint; S2: Based on the overlap area calculation rule, a three-dimensional cost function is established using the Manhattan distance metric; line segment overlap cost C o =Σ(overlap(s i ,s j )|track); Pin conflict cost C p =Σ(overlap(s i ,p j (|layer); Obstacle avoidance cost C β =Σ(overlap(s i ,bk)|region), generate a multi-dimensional overlapping cost quantification model C=αCo+βCp+γCb; α:β:γ=3:2:1; S3: Construct the decision variable matrix X=[x] using the 0-1 integer programming method. ij ] n × m , where x ij ∈{0,1} represents line segment s i Assigned to orbit t j The state is determined by constraints; single-track constraint: Σ j x ij =1 (∀i∈[1,n]), that is, each line segment s i Must be assigned to one and only one track; obstacle constraint: x ij ·overlap(s i ,b k )=0 (∀i,j,k), generating a pseudo-Boolean optimization constraint matrix; S4: Generate the initial solution X using the Monte Carlo random initialization algorithm. 0 The initial cost C is calculated through the cost function evaluation module. 0 =αC o +βCp +γC β , where α, β, γ are process weight coefficients, generating a baseline vector for the feasible solution space; S5: Based on the variable neighborhood search strategy (VNS), a candidate solution set {X'} is generated through a single bit flipping operation. A tabu list management mechanism is used to avoid circular search. The search radius r=⌈log2(n)⌉ is dynamically updated to generate a local optimal solution candidate pool. S6: Implement a dynamic weight scoring mechanism. Through adaptive adjustment of hard constraint weights and comprehensive calculation of the scoring function, adopt a tabu-guided local search strategy to iteratively update the current optimal solution X* and generate a global approximate optimal solution sequence. S7: The final solution in the global near-optimal solution sequence is converted into physical layout instructions through the decoding mapping engine. The DRC verification module is used to check for design rule violations and outputs a track allocation scheme in GDSII format to generate a track layout scheme for the routing of the large-scale integrated circuit to be analyzed.

[0029] like Figure 3 As shown, in a preferred embodiment, generating a hierarchical track-net-obstacle quadruple topology model based on S1 includes the following steps: S101: Parse the panel layer structure and perform the following for each panel: Track generation: Generate parallel track coordinates based on the [axis] direction of tracklist, in the range from [start] to [end] with [step_length] as the interval; Segment extraction: Parse the rectangular coordinates corresponding to each net_id from wire_list to generate the network segments to be wired; Obstacle mapping: Convert the rectangles in hard_shape_list into impassable areas; S102: Construct a hierarchical spatial index: Create an axis-first search tree based on the panel's [prefer_direction]; establish an R* tree index structure for panels with the same layer_id; generate a cross-panel connection matrix; S103: Coordinate normalization: Using [Ib_x][Ilb_y] of the panel as the reference point; discretizing is performed using the process grid λ: x' = (rt_x - Ib_x) / λ; generating a normalized orbital coordinate sequence {t'1, t'2, ..., t' m}

[0030] like Figure 4 As shown, in a preferred embodiment, generating a multi-dimensional overlapping cost quantification model based on S2 includes the following steps: S201: The Manhattan projection method is applied to calculate the minimum interval between line segments, and a scanning window algorithm is used to detect horizontal / vertical overlapping areas, generating a line segment overlap cost feature vector. The purpose is to transform the spatial overlap relationship between line segments from a geometric determination into a quantifiable cost feature, which is used to characterize the degree and distribution of conflicts between different line segments. This feature vector serves as an important input to the total wiring cost function, used for quantitative evaluation of candidate solutions, and in subsequent neighborhood search and multi-objective optimization processes to guide the dynamic adjustment of path adjustment direction and cost weights. S202: Perform track translation conflict analysis, calculate the pin access conflict amount ΔL = original overlap amount - minimum reversible overlap amount, and generate a conflict intensity distribution map. The purpose is to present the spatial distribution of track translation conflicts in a graphical form, intuitively showing the conflict intensity of each region. This map provides a visual basis for decision-making during the optimization process, guiding the algorithm to prioritize adjusting areas with greater conflicts to improve routing performance. By dynamically adjusting weights and path optimization, the efficiency and effectiveness of the algorithm are enhanced. S203: Integrate the multi-objective weighted function, merge the results of steps 2.1-2.2 in a ratio of α:β:γ=3:2:1, and establish the cost function C=3C. o +2C p +1C β Generate a multi-dimensional overlapping cost quantification model.

[0031] Step S201 is used to extract the geometric cost features of spatial overlap between line segments. Step S202 analyzes the degree of conflict resolution under track translation conditions based on the geometric overlap features. Step S203 further weights and fuses the geometric conflict cost and the resolvable conflict cost to construct a unified multi-objective cost function for subsequent routing optimization decisions.

[0032] like Figure 5 As shown, in a preferred embodiment, generating the pseudo-Boolean optimization constraint matrix based on S3 includes the following steps: S301: Define the 0-1 decision variable space X∈{0,1} nxm , where n is the number of line segments and m is the track capacity, generating a Boolean decision variable matrix X; S302: Applying full-difference constraint coding, the single-track allocation conditions are transformed into ∑ j x ij A linear constraint set with =1 is used to generate a single-track allocation constraint equation set. S303: Using obstacle masking technology, bit masking operation is performed on the decision variable matrix X to eliminate illegal allocation combinations and generate a pseudo-Boolean optimization constraint matrix.

[0033] Preferably, generating the feasible solution space baseline vector based on S4 includes the following steps: S401: Perform Monte Carlo random sampling to generate samples that satisfy ∑ j x ij The initial solution X = 1 0 Set the sampling rate θ=0.3 to generate the baseline vector of the feasible solution space; S402: Runs the cost evaluation engine, calling the cost model in S203 to calculate C(X). 0 This process records the Pareto front and generates an initial solution quality assessment report. It provides an iterative starting point and benchmark for subsequent variable neighborhood search (S5). like Figure 6 As shown, in a preferred embodiment, generating a local optimum candidate pool based on S5 includes the following steps: S501: Initiate the variable neighborhood search strategy, define the flip radius r∈[1,⌈log2n⌉], generate the candidate solution set {X'}, and generate the neighborhood solution state transition graph; S502: Apply tabu list management, use FIFO queue to store recent operations, tabu length τ=√n, and generate a list of valid candidate solutions for filtering. S503: Execute the elite retention strategy, select the top-k solutions from the candidate pool, k=min(5,0.1n), and generate a local optimum candidate pool.

[0034] like Figure 7 As shown, in a preferred embodiment, generating a sequence of globally approximate optimal solutions based on S6 includes the following steps: S601: Initialize hard constraint weight w(c)=1, target weight w(o)=0, calculate smoothness coefficient smooth(c)=average of process coefficients of the same type of constraint; S602: Construct the scoring function score(x)=Σ[smooth(c)×w(c)×Δviol(c)] + smooth(o)×w(o)×Δobj; S603: When the local optimum is reached, w(c) + 1 for unsatisfied constraints, and w(o) + 1 when all constraints are satisfied; S604: Select the optimal solution using tabu-guided variable neighborhood search.

[0035] like Figure 8 As shown, in a preferred embodiment, generating a manufacturable track layout scheme based on S7 includes the following steps: S701: Executes the decoding mapping engine to convert X* into physical coordinates, applies bilinear interpolation to compensate for quantization errors, and generates the original orbital layout draft; S702: Run the DRC verification process, check design rules such as minimum spacing and width, mark violation areas, and generate a heat map of design rule violations; S703: Implement an iterative repair mechanism, feed back violation information to the cost model of S203, output GDSII, and generate a manufacturable track layout scheme.

[0036] In one optional embodiment, a three-dimensional cost function is established using the Manhattan distance metric based on the overlap area calculation rule; the line segment overlap cost C o =Σ(overlap(s i ,s j )|track); Pin conflict cost C p =Σ(overlap(s i ,p j (|layer); Obstacle avoidance cost C β =Σ(overlap(s i ,b j )|region), generate a multi-dimensional overlapping cost quantification model C=αCo+βCp+γCb (α:β:γ=3:2:1); Among them, overlap(s) i ,s j ) represents line segment s i With s j The projection overlap length along the same orbital direction is calculated using Manhattan geometry: overlap(s) i ,s j )=max(0,min(s i.end ,s j.end )-max(s i.start ,s j.start Track refers to detecting only line segments along the same axis as the track to prevent short circuits in the conductors (Design Rule Check).

[0037] overlap(s i ,p j ) represents line segment s i With pin p j Overlapping area in the same metal layer; Calculation method: rectangular intersection area (pins are usually modeled as rectangles) area=(x max -x min )×(y max -y min ); layer refers to the connection of pins across layers through a cross-panel connection matrix.

[0038] overlap(s i ,b k ) represents line segment s i With hard obstacles b kOverlapping area in the wiring region; Calculation method: intersection of rectangles that conflict with the pins; region refers to the local area where the obstacle is located.

[0039] In an optional embodiment, a 0-1 integer programming method is used to construct the decision variable matrix X=[x ij ] n × m , where x ij ∈{0,1} represents line segment s i Assigned to orbit t j The state is determined by constraints; single-track constraint: Σ j x ij =1 (∀i∈[1,n]); Obstacle constraint: x ij ·overlap(s i ,b k )=0 (∀i,j,k), generating a pseudo-Boolean optimization constraint matrix; In an optional embodiment, the Monte Carlo random initialization algorithm is used to generate the initial solution X. 0 The initial cost C is calculated through the cost function evaluation module. 0 =αC o +βC p +γC β , where α, β, γ are process weight coefficients, generating a baseline vector for the feasible solution space; In an optional embodiment, generating a hierarchical track-net-obstacle quadruple topology model based on S1 includes the following steps: S101: Parse the panel layer structure and perform the following for each panel: Track generation: Generate parallel track coordinates based on the [axis] direction of the tracklist, with intervals of [step_length] from [start] to [end]; Segment extraction: Parse the rectangular coordinates corresponding to each net_id from the wire_list to generate the network segments to be wired; Obstacle mapping: Convert the rectangles in the hard_shape_list into impassable regions; When parsing the panel layer structure, a track generation operation is performed for each panel instance. When the axis parameter in tracklist is horizontal, the start parameter value is used as the starting coordinate, the end parameter value as the ending coordinate, and parallel tracks are generated at intervals according to the step_length parameter value. For example, when start=0μm, end=100μm, and step_length=2μm, 51 horizontal track coordinate sequences are generated. In the line segment extraction stage, the rectangle coordinate data corresponding to each net_id in wire_list is traversed, and the coordinates of the rectangle's diagonal points are converted into line segment endpoint coordinates. When a certain n When the rectangular coordinates corresponding to et_id are lb_x=10μm, lb_y=20μm, rt_x=30μm, and rt_y=40μm, the horizontal line segment endpoint (10,30) and the vertical line segment endpoint (20,40) are generated. During the obstacle mapping process, the four boundary coordinates of each rectangular region in hard_shape_list are expanded by λ / 2 to form an impassable region. When the process grid λ=0.5μm, the original rectangle (50,60,70,80) will be expanded into an obstacle region of (49.75,59.75,70.25,80.25), thus completing the establishment of the spatial relationship between the track, line segment, and obstacle.

[0040] S102: Construct a hierarchical spatial index: Create an axis-first search tree based on the panel's [prefer_direction]; establish an R* tree index structure for panels with the same layer_id; generate a cross-panel connection matrix; When constructing the hierarchical spatial index, the axial priority dimension is selected according to the value of the panel parameter prefer_direction. When prefer_direction is marked as vertical, a B+ tree structure with the Y-axis as the primary index key is constructed. The node splitting threshold stores 100 coordinate points for each tree node. For multiple panels with the same layer_id, when using the R* tree index structure, the minimum boundary rectangle overlap rate is set to 15%, and the node capacity is 50 objects. The cross-panel connection relationship matrix is ​​generated by traversing the track endpoint coordinates of adjacent panels. When the difference between the Ib_x coordinates of two panels is 200μm and the process grid λ=0.5μm, an offset mapping relationship of normalized coordinate 400λ is established. The matrix element values ​​are determined by calculating the ratio of track spacing to the minimum process linewidth. When the adjacent track spacing is 2λ, the connection strength is marked as 0.8.

[0041] S103: Coordinate Normalization Processing: Using [Ib_x][Ilb_y] of the panel as the reference point; discretizing is performed using the process grid λ: x' = (rt_x - Ib_x) / λ; generating a normalized orbital coordinate sequence {t'1, t'2, ..., t' m}

[0042] In the coordinate normalization stage, using panel parameters Ib_x=50μm and Ilb_y=30μm as reference points, the physical coordinate rt_x=78.3μm is discretized. When the process grid λ=0.2μm, x'=(78.3-50) / 0.2=141.5 is calculated, which is rounded to x'=142λ. The orbital coordinate sequence is sorted and deduplicated. When the original coordinate sequence contains 142λ, 142λ, and 143λ, a normalized sequence {t'1=142, t'2=143} is generated. The discretization error is verified to not exceed λ / 2. When rt_x=50.1μm, x'=(50.1-50) / 0.2=0.5λ is calculated, which is rounded to 1λ to ensure that all coordinates are aligned with the process grid. Finally, the integerized orbital coordinate sequence is output.

[0043] In an optional embodiment, generating a multi-dimensional overlapping cost quantization model based on S2 includes the following steps: S201: The Manhattan projection method is applied to calculate the minimum interval between line segments, and the horizontal / vertical overlapping areas are detected by the scanning window algorithm to generate a feature vector of line segment overlap cost. When applying the Manhattan projection method, the coordinates of the endpoints of the line segments are decomposed into X / Y axis components. The Y-axis coordinates of the horizontal line segments are taken as the projection reference, and the X-axis coordinates of the vertical line segments are taken as the projection reference. When processing the horizontal line segment from the starting point (10,20) to the ending point (30,20), it is projected onto the axis of Y=20 to form the interval [10,30]. The scanning window algorithm sets the window width to 1.2 times the minimum process spacing λ. When λ=0.5μm, the window width is 0.6μm. The overlapping is detected by sliding along the projection axis with a step size of 0.1λ. If another line segment is detected with a projection interval of [25,35], the length of the overlapping area is calculated to be 5μm and recorded as the overlapping cost item. The feature vector elements are sorted by the track index. When processing the 5th track, the sum of the overlapping lengths of all line segments on the track is accumulated as the value of the 5th dimension of the vector. For example, if there are 3 overlapping points on track 5 with lengths of 2μm, 1.5μm and 3μm respectively, the corresponding feature vector value is 6.5μm.

[0044] In an optional embodiment, S202: Perform track translation conflict analysis, calculate the pin access conflict amount ΔL = original overlap amount - minimum reversible overlap amount, and generate a conflict intensity distribution map; During the track translation conflict analysis phase, for pin p jOrbit t k The original overlap L0 is calculated as the line segment s. i The overlap length between the pin metal region and the layer direction, when s i With the coordinates of metal layer M2 at (50, 60, 70, 80), pin p j In M2, the coordinates are (60, 55, 80, 75). The X-axis overlap is 20 μm, and the Y-axis overlap is 20 μm. The smaller value of 20 μm is taken as L0. The minimum eliminateable overlap L_min is set to λ×3 according to the process rules. When λ=0.5 μm, L_min=1.5 μm. The conflict amount ΔL=20-1.5=18.5 μm. The conflict intensity is classified according to the ratio of ΔL / L_min. When ΔL≥5L_min, it is high conflict (red). When 3L_min≤ΔL<5L_min, it is medium conflict (yellow). When ΔL<3L_min, it is low conflict (green). The distribution map is rendered using a thermal layer. The color intensity of each orbital unit is proportional to the ΔL value.

[0045] In an optional embodiment, S203: Integrate a multi-objective weighting function, and fuse the results of steps 2.1-2.2 in a ratio of α:β:γ=3:2:1 to establish a cost function C=3C. o +2C p +1C β Generate a multi-dimensional overlapping cost quantification model.

[0046] When performing multi-objective weighted fusion, the line segment overlap cost C is set. o Pin conflict cost C p Obstacle avoidance cost C β The baseline weighting ratio is 3:2:1, and the weighting coefficients are dynamically adjusted according to the importance of the process layer. When processing metal layer M3, due to the high wiring density of this layer, C... o The weighting was increased to 3.5, C β With the weight reduced to 0.8, in the cost function calculation example, the C of a certain solution... o =120μm, C p =80μm, C β =40μm, the weighted sum is 3×120+2×80+1×40=560μm. The weight ratio refers to the metal layer priority table in the design rule manual. For the top signal layer, the pin conflict weight β increases by 0.1 per 100μm of wiring length. When the wiring length reaches 500μm, β=2.1. The fusion process adopts a track-by-track calculation method. The final cost value of each track is the linear sum of the cost of each item multiplied by the corresponding weight.

[0047] In an optional embodiment, generating the pseudo-Boolean optimization constraint matrix based on S3 includes the following steps: S301: Define the 0-1 decision variable space X∈{0,1} nxm , where n is the number of line segments and m is the track capacity, generating a Boolean decision variable tensor; When defining the decision variable space, based on the scale of n=500 line segments and m=20 tracks in the wiring task, a 500×20 two-dimensional matrix X is created, where each element x... ij This represents the state of line segment i assigned to track j. When processing line segment i=150, all tracks j=1 to 20 are traversed, and x is set during initialization. 150 ,5=1 indicates that the orbital is tentatively assigned to orbital 5, and the remaining x 150 , j =0. During the Boolean tensor generation process, the capacity limit is checked for each track j. When track j has been allocated k=15 line segments and the capacity limit m=20, the remaining available capacity of the track is marked as 5. The variable space is optimized through bit plane storage. Each variable occupies 1 bit of storage space. A 500×20 matrix requires a total of 10000 bits, or 1250 bytes of memory space. In the example, the track-based block storage method is used, and every 32 variables are packaged into a 32-bit integer data unit.

[0048] S302: Applying full-difference constraint coding, the single-track allocation conditions are transformed into ∑ j x ij A linear constraint set with =1 is used to generate a single-track allocation constraint equation set. In the full difference constraint coding stage, constraint equations are generated for each line segment i. When processing line segment i=200, equation x is constructed. 200 ,1+x 200 ,2+...+x 200 , 20 =1, the corresponding position in row 200 of the coefficient matrix is ​​set to 1, and the rest are set to 0. The constraint equation system adopts a sparse matrix storage format. For the case of n=500 line segments and m=20 tracks, a coefficient matrix of 500 rows × 20 columns is generated, with a total of 500 × 20 = 10,000 non-zero elements. During storage, only the column index and value of the non-zero elements are recorded. For example, row 200 is stored as [1:1, 2:1, ..., 20:1]. A single constraint occupies 20 × (4 + 1) = 100 bytes of memory, and the total amount of constraint data is 500 × 100 = 50,000 bytes. When solving the equation system, slack variables are introduced to handle boundary conditions. When a line segment can only choose from 3 tracks due to obstacles, the corresponding equation becomes x i ,3+x i 7+x i , 15 =1.

[0049] S303: Using obstacle masking technology, bit masking operation is performed on X to eliminate illegal allocation combinations and generate a pseudo-Boolean optimization constraint matrix.

[0050] When implementing obstacle masking technology, a track-obstacle conflict bitmap is pre-generated. When track j=8 overlaps with obstacle b3 in the coordinate interval [50μm, 80μm], the corresponding bit in the 8th column of the mask matrix M is set to 0. A bitwise AND operation is performed on the decision matrix X, for example, the original allocation scheme x. 123 ,8=1, becomes x after the masking operation of M8=0. 123 ,8=0, During the illegal combination elimination process, all line segment i and track j combinations are traversed. When the length of line segment i=45 is 15μm and the distance between obstacles in track j=12 is less than 5μm, x is set. 45 , 12 =0, the mask update adopts an incremental method, and the corresponding bit is updated every time a conflict allocation is detected. In the example, when processing 500×20=10,000 variables, an average of 25 mask operations are required per track, and the density of non-zero elements in the final constraint matrix decreases from the initial 100% to 72.3%.

[0051] In an optional embodiment, generating a feasible solution space baseline vector based on S4 includes the following steps: S401: Perform Monte Carlo random sampling to generate samples that satisfy ∑ j x ij The initial solution X = 1 0 Set the sampling rate θ=0.3 to generate the baseline vector of the feasible solution space; When implementing Monte Carlo sampling, setting the sampling rate θ=0.3 means randomly selecting 30% of the total possible solution space as initial samples. When the wiring problem contains n=500 line segments and m=20 tracks, the theoretical solution space size is 20^500, and the actual number of samples is 0.3×500=150 initial solutions, each with a solution vector X. 0 The generation is achieved by randomly selecting a unique track j for each line segment i. For example, for line segment i=75, a uniformly distributed random number generator is used to round down the interval [1,20]. When the random value is 13, x is set. 75 , 13 =1, other x 75 , j =0, collision detection is implemented during sampling. When the randomly assigned track j=8 overlaps with an obstacle, the line segment allocation is regenerated until the constraint is met. The number of valid samplings is recorded. If the allocation fails 5 times consecutively, the backup track selection strategy is activated. The reference vector storage uses sparse encoding, only recording the positions of non-zero elements, such as the solution vector X. 0The 150th solution is stored as a set of key-value pairs {(1,5),(2,17),...,(500,9)}, with each solution vector occupying an average of 2.5KB of storage space.

[0052] S402: Runs the cost evaluation engine, calling the cost model in S203 to calculate C(X). 0 Record the Pareto frontier and generate an initial solution quality assessment report.

[0053] During the cost evaluation, the cost model of S203 is invoked for each initial solution X. 0 When performing calculations, for the initial solution k=45, C is calculated by traversing all line segments. o C p C β Components, such as line segment i=200 assigned to track j=10, are found to overlap with adjacent line segments in 3 places on track 10, accumulating C. o Increasing by 3×λ (λ=0.5μm) yields 1.5μm. In pin collision detection, this line segment overlaps with 5 pins in the layer direction. Each collision deducts β=2 points, resulting in C. p =10, obstacle avoidance check found 2 spacing violations, deduct γ=1 point for each, resulting in C. β =2, total cost C=3×1.5+2×10+1×2=26.5. Pareto front maintenance adopts ε-dominance strategy. When the cost vector of the new solution (26.5,10,2) is compared with the existing front solution, if C o C p C β If a solution is not inferior to any existing solution in all three dimensions, it is added to the frontier set. The evaluation report calculates the percentage of frontier solutions among the 150 solutions. When there are 15 non-dominated solutions, their cost value distribution interval is recorded as C. o [15.2,24.8]、C p [8,15]、C β [1,3] The generated CSV quality report includes the three-dimensional cost coordinates and orbital utilization index for each solution.

[0054] In an optional embodiment, generating a local optimum candidate pool based on S5 includes the following steps: S501: Initiate the variable neighborhood search strategy, define the flip radius r∈[1,⌈log2n⌉]. The variable neighborhood search strategy starts with the current best solution in the baseline vector of the feasible solution space, and performs a single-bit flip operation through the flip radius r, thereby generating a set of candidate solutions {X'} in the neighborhood of the current solution, and constructing a state transition graph describing the search path based on this.

[0055] When initiating the variable neighborhood search strategy, the value of the flip radius r is determined based on the orbital assignment state of the current solution X. When the total number of line segments n=500, the upper bound of r is calculated as ⌈log2500⌉=9, and the initial radius r=3. During the candidate solution generation stage, r line segments are randomly selected for orbital redistribution. For example, line segments i=45, 189, and 302 are selected, and their current orbital assignment states are flipped. If the original assignments were orbits 5, 8, and 12, they are changed to orbits 7, 3, and 9 respectively in the new solution X'. The state transition diagram records the neighborhood transition path of each solution. When processing the t=15th iteration, the current solution X... 15 X is generated by flipping the radius r=5. 15 ', Add a slave node X to the graph structure 15 To X 15 The directed edges are set with edge weights set to the cost change ΔC = 120 μm caused by the flip operation. The neighborhood solution set is stored in layers according to radius. The solution with radius r = 1 is stored in the first layer, the solution with r = 2 is stored in the second layer, and so on up to the ninth layer with r = 9.

[0056] S502: Apply tabu list management, use FIFO queue to store recent operations, tabu length τ=√n, and generate a list of valid candidate solutions for filtering. During the tabu search phase, a tabu list is introduced to manage recent flip operations. The tabu list uses a first-in, first-out queue structure, with a queue length set to... Used to store the flip operations corresponding to the most recent accepted solutions.

[0057] The flipping operation refers to the track reallocation operation performed on a single line segment, denoted as a triplet. Represents line segment From the original orbit Reassigned to orbit When a candidate solution When a solution is selected as the update solution in the current iteration, its set of flip operations relative to the current solution is added to the tabu list; if the queue is full, the oldest tabu entry is removed.

[0058] Each taboo item has a taboo period set to "the iteration number at the time of inclusion + 22". For example, the taboo item (45,5,7) means that during the taboo period, line segment 45 is prohibited from retreating from track 7 to track 5 to avoid short-period oscillations during the search process.

[0059] In the In each iteration, for each generated candidate solution The system checks whether all the flip operations contained in a candidate solution match taboo items in the taboo list. If the number of matching taboo operations exceeds a threshold of 2, the candidate solution is marked as invalid and filtered out. For example, if a candidate solution contains 3 taboo flip operations, the solution will be directly eliminated.

[0060] Through the above filtering mechanism, the retention rate of effective candidate solutions is controlled within the range of 70%–80%. When the initial number of candidate solutions is 100, about 75 effective candidate solutions are retained after filtering and are uniformly placed into the candidate pool for subsequent evaluation and selection strategies.

[0061] S503: Execute the elite retention strategy, select the top-k solutions from the candidate pool, k=min(5,0.1n), and generate a local optimum candidate pool.

[0062] When implementing the elite retention strategy, the solutions in the current candidate pool are sorted according to their cost function values. When n=500, k=min(5,0.1×500)=5 is calculated, and the 5 solutions with the lowest cost are selected into the elite pool. The selection criterion for elite solutions is C(X)≤Cost of the current best solution×1.05. When the cost of the best solution is 1200μm, all solutions with a cost ≤1260μm are selected. For solutions tied for 5th place, a random selection mechanism is used. For example, when the cost of the 5th and 6th place solutions is the same as 1255μm, one of them is randomly selected. The elite pool is maintained using a sliding window mechanism. In each iteration, the elite solutions of the most recent 10 iterations are retained. When processing the t=100th iteration, the elite pool contains the 5 best solutions generated during iterations 90-100. The local candidate pool merges the elite solutions of the current iteration with the newly generated valid candidate solutions to form a solution set of size 80 for subsequent selection.

[0063] In an optional embodiment, generating a sequence of globally approximate optimal solutions based on S6 includes the following steps: S601: Initialize hard constraint weight w(c)=1, target weight w(o)=0, calculate smoothness coefficient smooth(c)=average of process coefficients of the same type of constraint; When initializing the weight parameters, initial weights w(c1)=1, w(c2)=1, and w(c3)=1 are assigned to the three types of hard constraints (single track constraint, obstacle constraint, and process spacing constraint) in the routing task. When calculating the smoothing coefficient, the spacing coefficients of metal layers M2 (0.8), M3 (0.7), and M4 (0.9) in the current process file are collected, and the average value is taken as smooth(c)=(0.8+0.7+0.9) / 3=0.8. The target weight w(o) is initially set to 0. When handling hybrid process node designs, smooth(c) is adjusted according to the priority of the metal layers. For example, if the process factor of the top metal M6 is 1.2, then smooth(c) is updated to (0.8+0.7+0.9+1.2) / 4=0.9. The weight parameters are stored as a three-dimensional vector [w(c1),w(c2),w(c3)]=[1,1,1]. Under the 45nm process conditions, the process factor table specifies that the smoothing coefficient benchmark value of the spacing constraint is 0.8±0.05.

[0064] S602: Construct the scoring function score(x)=Σ[smooth(c)×w(c)×Δviol(c)] + smooth(o)×w(o)×Δobj; When constructing the scoring function, the constraint violation amount Δviol(c) is calculated for each candidate solution X'. When there are 2 single-track constraint violations, 3 obstacle constraint violations, and 1 process spacing violation, Δviol(c1)=2, Δviol(c2)=3, and Δviol(c3)=1. The target improvement amount Δobj=50μm, which is the difference between the current solution cost of 1200μm and the new solution cost of 1150μm. Substituting into the formula, the score is calculated as 0.8×1×2 + 0.8×1×3 + 0.8×1×1 + 1.0×0×50=6.4. When processing metal layer M3, since the process coefficient is adjusted to 0.7, the corresponding term becomes 0.7×1×3=2.1. During the scoring process, each candidate solution is calculated independently. When there are 100 candidate solutions, a 100-dimensional scoring vector is generated. The top 10% are selected as the preferred solutions in descending order.

[0065] S603: When the local optimum is reached, w(c) + 1 for unsatisfied constraints, and w(o) + 1 when all constraints are satisfied; In the adaptive weight adjustment phase, when a local optimum is detected, all constraint violations are iterated. The weight w(c2) of the unsatisfied constraint c2 (obstacle constraint) is increased by 1, changing it from 1 to 2. If all hard constraints are satisfied, the target weight w(o) is increased from 0 to 1. The adjustment process sets the maximum weight limit to 5. When w(c2) = 5, it stops increasing. In the example, in a certain iteration, the violation amount Δviol(c1) = 1, c2 = 0, and c3 = 0 is found. Since there is an unsatisfied constraint c1, the w(c1) + 1 operation is performed, and the weight vector is updated to [2, 1, 1]. When all constraints are satisfied in 3 consecutive iterations, w(o) increases to 3. However, according to the rule limit, the actual w(o) = min(3, 5) = 3.

[0066] S604: Select the optimal solution using tabu-guided variable neighborhood search.

[0067] When implementing the tabu-guided search strategy, in conjunction with the current weight vector [w(c), w(o)]=[2,1,1,3], the search prioritizes tracks related to high-weight constraints in the variable neighborhood search. For example, for a single track constraint corresponding to w(c1)=2, the operation with a flip radius r=4 is forced to include at least two line segments related to single track constraints. The tabu list specifically prohibits reverse operations on constraints with weights ≥2. When a flip attempts to move line segment i=78 from the compliant track back to the original violating track, the operation is blocked by the tabu list because w(c1)=2. The search process records the weight adjustment history of each solution. When a solution's score increases by 15% under the weight vector [2,1,1,3], it is marked as a potential optimal solution and added to the candidate sequence.

[0068] In an optional embodiment, generating a manufacturable track layout based on S7 includes the following steps: S701: Executes the decoding mapping engine to convert X* into physical coordinates, applies bilinear interpolation to compensate for quantization errors, and generates the original orbital layout draft; When executing the interpretation mapping engine, the normalized coordinates in the optimization variable X* are converted into physical coordinates. When the process grid λ=0.2μm and the reference point Ib_x=50μm, the track with normalized coordinate t'=142 is subjected to inverse discretization calculation, and the physical coordinate rt_x=50+142×0.2=78.4μm. During bilinear interpolation compensation, the actual physical coordinates of adjacent tracks t'=141 and t'=143 are detected as 78.2μm and 78.6μm, respectively. When line segment s iWhen the theoretical position should be 78.35μm, calculate its weight distribution among the three orbitals. The weight coefficients are distributed inversely proportional to the distance. For t'=141, the weight is (78.35-78.2) / (78.6-78.2)=0.375; for t'=142, the weight is 0.25; for t'=143, the weight is 0.375. The final position is adjusted to 78.2×0.375+78.4×0.25+78.6×0.375=78.4μm, compensating for a quantization error of 0.05μm. When generating the orbital layout draft, coordinate correction is performed on 500 orbitals. The average adjustment range per orbital is 0.03λ, and the maximum adjustment of 0.12λ occurs in the edge panel area.

[0069] S702: Run the DRC verification process, check design rules such as minimum spacing and width, mark violation areas, and generate a heat map of design rule violations; When running the DRC verification process, the minimum spacing inspection threshold is set to 1.1 times the process rule value. When the process requires a minimum spacing of 0.5 μm for metal layer M2, the actual inspection threshold is 0.55 μm. A scan line algorithm is used to detect the spacing between adjacent line segments along the track direction. When line segment s is detected... 150 (75.0-75.5μm) and s 238 When the Y-axis projection overlaps (75.6-76.1μm), the X-axis spacing is calculated to be 75.5-75.6=-0.1μm (violation). This area is marked as a spacing violation. The heatmap uses eight levels of color to represent the severity of the violation. When the spacing violation amount Δ=0.1μm corresponds to the fourth level orange, when the cumulative violation length of a single track exceeds 20% of the track length, the entire track is marked in red. In the example, when processing 500 tracks, 32 tracks were found to have spacing violations, with the maximum single track violation length accounting for 35%.

[0070] S703: Implement an iterative repair mechanism, feed back violation information to the cost model of S203, output GDSII, and generate a manufacturable track layout scheme.

[0071] When implementing the iterative repair mechanism, DRC violation information is converted into incremental parameters of the cost model. When there are 3 spacing violations on track j=45, each violation is 2μm long, and the total violation length is 6μm, the conflict cost coefficient α_j = original value × 1.5 and the obstacle avoidance cost γ_j = original value × 2.0 are added to the S203 cost model. When the optimization process is rerun, the priority of the line segment allocation of this track is reduced. After three iterations, the violation length of track j=45 is reduced to 0.8μm. In the GDSII file generation stage, the coordinates of each track are checked for λ / 100 precision. When the coordinate value of 78.399μm is rounded to 78.4μm, the bounding box coordinates written in GDSII format are (78400,0) to (78400,10000). The final solution passes the full-chip DRC check, and the number of violation hotspots is reduced from the initial 128 to 7, with the remaining violation area accounting for 0.15%.

[0072] like Figure 10 As shown, an optional embodiment of the present invention also provides a track allocation system based on pseudo-Boolean optimization local search in cabling, comprising: The topology model generation module generates a topology model containing layered track, net, and obstacle information based on the topology information of the layered panel data structure of the large-scale integrated circuit wiring to be analyzed. The multi-dimensional overlap cost quantification model generation module generates a multi-dimensional overlap cost quantification model based on the overlap area calculation rule and the topological model. The pseudo-Boolean optimization constraint matrix generation module constructs a decision variable matrix and converts the decision variable matrix into a pseudo-Boolean optimization constraint matrix by setting constraints. The global approximate optimal solution sequence generation module generates a global approximate optimal solution sequence based on the initial solution of the pseudo-Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; The track layout scheme generation module generates a track layout scheme for the large-scale integrated circuit wiring to be analyzed based on the optimal solution in the global approximate optimal solution sequence, and then performs track layout.

[0073] A computer device includes a memory and a processor, the memory storing a computer program configured to be executed by the processor, the computer program including instructions for performing the methods described above.

[0074] A computer-readable storage medium having a computer program stored thereon, characterized in that the computer program implements the above-described method when executed by a processor.

[0075] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A track allocation method based on pseudo-Boolean optimization local search in wiring, comprising the following steps: Based on the topology information of the layered panel data structure of the large-scale integrated circuit wiring to be analyzed, a topology model containing layered track, net and obstacle information is generated. Based on the overlap area calculation rule and the aforementioned topological model, a multi-dimensional overlap cost quantification model is generated. Construct a decision variable matrix, and then convert the decision variable matrix into a pseudo-Boolean optimization constraint matrix by setting constraints; A global approximate optimal solution sequence is generated based on the initial solution of the pseudo-Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; Based on the optimal solution in the global approximate optimal solution sequence, a track layout scheme for the wiring of the large-scale integrated circuit to be analyzed is generated for track layout.

2. The method according to claim 1, characterized in that, The multi-dimensional overlap cost includes line segment overlap cost, pin conflict cost, and obstacle avoidance cost.

3. The method according to claim 1, characterized in that, A feasible solution space baseline vector is generated based on the pseudo-Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; a local optimal solution candidate pool is generated based on the feasible solution space baseline vector; the current optimal solution is iteratively updated to generate a global approximate optimal solution sequence.

4. The method according to claim 3, characterized in that, An initial solution satisfying the pseudo-Boolean optimization constraint matrix is ​​generated by Monte Carlo random sampling; the initial cost is calculated based on the initial solution and the multi-dimensional overlapping cost quantization model, and the initial cost is used as the reference vector of the feasible solution space.

5. The method according to claim 3 or 4, characterized in that, The method for generating the local optimal solution candidate pool is as follows: using a variable neighborhood search strategy, starting from the current optimal solution in the feasible solution space reference vector, a single bit flip operation is performed to generate a set of candidate solutions in the surrounding neighborhood of the current solution. Candidate solutions with a number of taboo operations within a threshold are added to the candidate pool, and candidate solutions are selected from them to generate the local optimal solution candidate pool.

6. The method according to claim 1, characterized in that, The method for generating the topology model is as follows: generate the track and the network segment to be wired for each layer of the panel in the layered panel data structure, and map the inaccessible area in the layer of the panel as an obstacle; Based on the preferred orientation of each panel, an axial priority search tree and an R* tree index structure are created, and a cross-panel connection matrix is ​​generated to form the topology model.

7. The method according to claim 1, characterized in that, The constraints include single-track constraints and obstacle constraints.

8. A track assignment system based on pseudo-Boolean optimization local search in cabling, characterized in that, include: The topology model generation module generates a topology model containing layered track, net, and obstacle information based on the topology information of the layered panel data structure of the large-scale integrated circuit wiring to be analyzed. The multi-dimensional overlap cost quantification model generation module generates a multi-dimensional overlap cost quantification model based on the overlap area calculation rule and the topological model. The pseudo-Boolean optimization constraint matrix generation module constructs a decision variable matrix and converts the decision variable matrix into a pseudo-Boolean optimization constraint matrix by setting constraints. The global approximate optimal solution sequence generation module generates a global approximate optimal solution sequence based on the initial solution of the pseudo-Boolean optimization constraint matrix and the multi-dimensional overlapping cost quantization model; The track layout scheme generation module generates a track layout scheme for the large-scale integrated circuit wiring to be analyzed based on the optimal solution in the global approximate optimal solution sequence, and then performs track layout.

9. A computer device comprising a memory and a processor, the memory storing a computer program configured to be executed by the processor, the computer program including instructions for performing the method of any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 7.

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