A polar code fscl decoding method and system based on pc check

Abstract

This invention provides a Polar code FSCL decoding method and system based on PC-check. The method includes: during FSCL decoding, determining whether the current decoding node is an R0 node, R1 node, REP node, or SPC node, and generating candidate codeword sequences based on soft information to construct an extended decoding path set; copying the extended decoding paths generated by splitting and independently maintaining the state of the circular shift buffer, operating the generator matrix matching the candidate codeword sequence and the node code length in the GF(2) domain to recover the original bit sequence, and updating the state of the circular shift buffer accordingly; performing PC-check on the PC-check bits involved in the current node based on the updated state of the circular shift buffer, prioritizing the elimination of extended decoding paths that fail PC-check and filtering the set of decoding paths with the maximum number of paths L by combining path metrics; performing supplementary PC-check on the uncovered PC-check bits and setting a fallback output strategy before the decoding ends.

Description

Technical Field

[0001] This invention relates to the field of communication channel coding and decoding technology, and in particular to a Polar code FSCL decoding method and system based on PC check. Background Technology

[0002] Polar codes are a class of channel coding schemes that can be proven to reach the channel capacity limit. Due to their good theoretical performance and feasibility, they have been selected as the main coding method for the control channel in the 3GPP New Radio (NR) communication system. In the actual decoding process of Polar codes, in order to balance decoding performance and implementation complexity, successive elimination-type decoding algorithms and their improved forms are usually used. Among them, the Fast Successive Cancellation List (FSCL) decoding algorithm divides the nodes in the decoding tree into R0 nodes, R1 nodes, REP nodes, and SPC nodes, and directly outputs the corresponding codeword results for different node types, thereby significantly reducing the decoding computation and improving the decoding throughput. It has become a commonly used high-speed Polar code decoding scheme in engineering implementation.

[0003] However, in the FSCL decoding algorithm, since R0, R1, REP, and SPC nodes all directly decode codewords to accelerate the decoding process, traditional implementations often only rely on path metrics for path selection, failing to fully utilize the check constraint information carried by the PC bits during the node-level fast processing stage. While this approach can maintain a high decoding speed, it can easily lead to erroneous decoding paths being retained due to temporary path metric dominance when there are many path extensions or poor channel conditions, resulting in a decrease in overall decoding performance.

[0004] Therefore, we propose a Polar code FSCL decoding method and system based on PC-verified data. The information disclosed above in the background section is only for enhancing the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing a Polar code FSCL decoding method and system based on PC verification, thereby resolving the technical problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A Polar code FSCL decoding method based on PC check includes the following steps: S1. Obtain the soft information of the Polar code to be decoded and set the maximum number of retained paths to L; establish an initial decoding path set, initialize the state of the cyclic shift buffer of each decoding path to all zeros, and initialize the PC check status flag to incomplete. S2. During the decoding process, the node type is determined based on the distribution of information bits and frozen bits within the current decoding node. Candidate codeword sequences are generated according to the fast decoding rules of the corresponding type to construct an extended decoding path set, and PC status maintenance flags are set for candidate codeword sequences involving PC check bits. S3. For each extended decoding path, recover the original bit sequence based on the candidate codeword sequence, and update the state of the circular shift register accordingly. The update rule is: perform a circular left shift operation on the state of the circular shift register, and perform an XOR operation between the input bits in the original bit sequence and the state of the first bit register after shifting to obtain the updated state of the circular shift register. S4. Perform PC verification and path filtering based on the updated circular shift register state: directly obtain the first register value of the circular shift register state as the expected verification value, compare it with the actual PC verification bit value to update the PC verification state flag; prioritize discarding extended decoding paths that fail PC verification, and then select and retain L extended decoding paths from the remaining paths according to the path metric.

[0007] S5. Perform a consistency check on the retained decoding path set: perform PC check on the uncovered PC check bits and remove paths that fail the check. In the remaining paths, combine the Cyclic Redundancy Check (CRC) result with the path metric to select the optimal decoding path and output its corresponding decoding result.

[0008] S1 specifically involves: acquiring the soft information of the Polar code to be decoded, which is a log-likelihood ratio sequence arranged in the order of the Polar code bits; establishing a generator matrix identifier for recovering the original bit sequence, making its order match the code length of the subsequent decoding nodes; initializing the path metric of each decoding path to a preset minimum metric value, and initializing the state of the circular shift buffer to all zeros.

[0009] S2 specifically refers to: during the decoding process, obtaining the frozen bit or information bit attribute of each bit position in the current decoding node; if all bits in the node are frozen bits, it is determined to be an R0 node; if all bits are information bits, it is determined to be an R1 node; if only the last bit is an information bit, it is determined to be a REP node; if only the first bit is a frozen bit, it is determined to be an SPC node.

[0010] The specific steps for generating candidate codeword sequences are as follows: hard-determine the soft information to obtain a baseline candidate codeword sequence; generate an all-zero candidate codeword sequence for R0 nodes; generate a candidate codeword sequence for REP nodes based on the last bit information constraint; perform splitting on the baseline candidate codeword sequence for R1 nodes or SPC nodes to generate multiple candidate codeword sequences; if the generated candidate codeword sequence involves PC check bits, set a PC state maintenance flag to trigger subsequent recovery of the original bit sequence.

[0011] The recovery of the original bit sequence in S3 is as follows: For node R0, the original bit sequence is determined to be an all-zero sequence; For node R1, SPC or REP, when the state update of the cyclic shift register is required, the candidate codeword sequence and the generator matrix corresponding to the current node code length are subjected to matrix operation in the binary field GF(2) to recover the original bit sequence used to drive the register update.

[0012] In S4, path selection is as follows: when the number of extended decoding paths is greater than L, pre-screening is performed, prioritizing the removal of extended decoding paths marked as failing the PC check. If the number of remaining paths after pre-screening is less than L, paths are selected from the removed paths in descending order of path metric until L is reached. If the number of remaining paths after pre-screening is still greater than L, only the L extended decoding paths with the best path metric are retained. When the path metrics are the same, a deterministic selection is performed using preset rules.

[0013] S5 specifically involves: before outputting, performing a consistency check on the reserved decoding path set, performing supplementary checks on uncovered PC check bit positions, and removing paths that fail the check; in the remaining set of decoded paths that pass the check, prioritizing the search for paths that pass the Cyclic Redundancy Check (CRC); if a path that passes the CRC exists, selecting the path with the best path metric as the output; if no path that passes the CRC exists, selecting the path with the best path metric among all paths that pass the PC check as the output.

[0014] A Polar code FSCL decoding system based on PC verification includes: a decoding initialization module, an FSCL subcode node processing module, an original bit sequence recovery and cyclic shift buffer update module, a PC verification and path filtering module, and a complete verification and decoding output module.

[0015] The beneficial effects of this invention are as follows: This invention introduces PC check constraints during FSCL decoding, combining PC check results with path metrics for path filtering. This allows erroneous decoding paths to be effectively eliminated early in the decoding process. Without disrupting the fast processing mechanisms of R0, R1, REP, and SPC nodes, it increases the probability of retaining correct decoding paths, thus significantly improving overall decoding accuracy. PC checking is performed not only at the end of decoding but also at various sub-code node processing stages, with the check bits used for dynamic path filtering. This forms a closed-loop PC check mechanism covering the entire decoding process, effectively avoiding performance loss caused by performing a one-time check only at the end of decoding.

[0016] This invention improves the stability and engineering feasibility of the decoding process by copying and independently maintaining the state of the circular shift register during decoding path splitting, while allowing efficient reuse of register states in inherited paths. This ensures the accuracy of the PC check state between different decoding paths and avoids unnecessary storage and computational overhead. A fallback strategy is implemented in the path selection and final output stages. When the PC check fails, resulting in insufficient or empty candidate paths, the optimal decoding path can still be output based on path metrics, preventing decoding process interruption and significantly enhancing the robustness of the decoding system under complex channel conditions.

[0017] This invention employs a modular and streamlined design for node determination, candidate codeword generation, original bit sequence recovery, cyclic shift buffer update, PC verification, and path selection. The terminology and rules are consistent throughout, facilitating implementation on different platforms such as DSP, ASIC, or FPGA, and ensuring compatibility with existing 3GPP NR Polar coding schemes. By introducing only necessary PC verification and state maintenance operations within the FSCL decoding framework, without significantly increasing decoding complexity or hardware resource consumption, a substantial improvement in error rate performance can be achieved. This makes it suitable for high-speed wireless communication systems with high requirements for both decoding performance and throughput. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a Polar code FSCL decoding method based on PC verification according to the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example 1: As Figure 1As shown, this embodiment provides a Polar code FSCL decoding method based on PC verification, including the following steps: S1. Obtain the soft information of the Polar code to be decoded and set the maximum number of retained paths to L; establish an initial decoding path set, initialize the state of the cyclic shift buffer of each decoding path to all zeros, and initialize the PC check status flag to incomplete. S2. During the decoding process, the node type is determined based on the distribution of information bits and frozen bits within the current decoding node. Candidate codeword sequences are generated according to the fast decoding rules of the corresponding type to construct an extended decoding path set, and PC status maintenance flags are set for candidate codeword sequences involving PC check bits. S3. For each extended decoding path, recover the original bit sequence based on the candidate codeword sequence, and update the state of the circular shift register accordingly. The update rule is: perform a circular left shift operation on the state of the circular shift register, and perform an XOR operation between the input bits in the original bit sequence and the state of the first bit register after shifting to obtain the updated state of the circular shift register. S4. Perform PC verification and path filtering based on the updated circular shift register state: directly obtain the first register value of the circular shift register state as the expected verification value, compare it with the actual PC verification bit value to update the PC verification state flag; prioritize discarding extended decoding paths that fail PC verification, and then select and retain L extended decoding paths from the remaining paths according to the path metric.

[0021] S5. Perform a consistency check on the retained decoding path set: perform PC check on the uncovered PC check bits and remove paths that fail the check. In the remaining paths, combine the Cyclic Redundancy Check (CRC) result with the path metric to select the optimal decoding path and output its corresponding decoding result.

[0022] S1 specifically includes the following sub-steps: S110. Input Acquisition and Parameter Setting: Acquire the soft information of the Polar code to be decoded, which is a log-likelihood ratio (LLR) sequence arranged in Polar code bit order; set the maximum number of retained paths to L. Simultaneously, establish a generator matrix identifier for subsequent "candidate codeword sequence → original bit sequence" recovery, ensuring the generator matrix identifier is consistent with the code length of the current decoding node; wherein, the generator matrix satisfies: in, for Generating matrix of order, For the fundamental matrix of Polar codes, This represents the Kronecker exponentiation operation. The codeword length corresponding to the current decoding node. This is the order parameter corresponding to the codeword length.

[0023] S120. Decoding Path Set Establishment: Establish an initial decoding path set, which must contain at least one initial decoding path. Configure and bind the following path attributes for each decoding path: path metric, circular shift register state, and PC check state flag. Initialize the path metric of the initial decoding path to a preset minimum metric value, so that subsequent selection based on the path metric has a definite initial benchmark. Initialize the circular shift register state of the initial decoding path to an all-zero state, so that the subsequent PC check register evolution has a definite starting state.

[0024] S130, State Consistency Initialization: Initialize the PC verification status flag of each decoding path to "PC verification incomplete", and stipulate that the PC verification status flag is used at least to indicate whether the corresponding decoding path has completed PC verification, so as to be consistently called by subsequent PC verification execution, path filtering and supplementary verification processes; wherein, when the subsequent steps complete the PC verification of a certain decoding path, the PC verification status flag of the decoding path is updated to "PC verification passed" or "PC verification failed", so as to form a state closed loop that can be directly referenced by the path filtering rules.

[0025] S2 specifically includes the following sub-steps: S210, Node Type Determination: During the decoding process, for the current decoding node, determine the node code length of the current decoding node as follows: And obtain the frozen bit / information bit attribute corresponding to each bit position in the current decoding node; wherein, the node code length satisfies: in, This is the order parameter corresponding to the current decoding node. Based on the frozen bit / information bit attributes, the node type of the current decoding node is determined according to the following rules: when all bits in the current decoding node are frozen bits, it is determined to be an R0 node; when all bits in the current decoding node are information bits, it is determined to be an R1 node; when only the last bit in the current decoding node is an information bit and the rest are frozen bits, it is determined to be a REP node; when only the first bit in the current decoding node is a frozen bit and the rest are information bits, it is determined to be an SPC node.

[0026] S220. Candidate Codeword Sequence Generation: For each decoding path in the decoding path set, based on the node type and the soft information corresponding to the current decoding node, at least one candidate codeword sequence associated with the decoding path is generated. Specifically, this includes: performing hard judgment on the soft information to obtain a baseline candidate codeword sequence; when the node type is R0, limiting the baseline candidate codeword sequence to an all-zero candidate codeword sequence; when the node type is REP, generating a candidate codeword sequence based on the constraint that the last bit is an information bit, and setting a PC state maintenance flag for the candidate codeword sequence when the last bit is a PC check bit; when the node type is R1 or SPC, performing splitting based on the baseline candidate codeword sequence to generate multiple candidate codeword sequences. In particular, if the Polar code block to be decoded contains a PC check bit, a "PC state maintenance flag" is set for each generated candidate codeword sequence; if the current decoding node contains a PC check bit, the specific position of the PC check bit within the node is additionally recorded. The PC state maintenance flag is used to indicate that subsequent steps require original bit sequence recovery and cyclic shift buffer state update for the corresponding candidate codeword sequence.

[0027] S230. Construction of Extended Decoding Path Set: Each decoding path is associated with each candidate codeword sequence it generates to construct an extended decoding path set. Each extended decoding path in the set includes at least: a parent decoding path identifier, a candidate codeword sequence, a path metric, a circular shift register (CFR) state, a PC check state flag, and a PC state maintenance flag. For each extended decoding path, the path metric of its parent decoding path is inherited, and the CFR state and PC check state flag of its parent decoding path are used as the input states for that extended decoding path. Simultaneously, it is stipulated that when an extended decoding path is generated by a split, that extended decoding path should have an independently maintained CFR state, so that subsequent steps will perform CFR state updates and PC check processing separately for different extended decoding paths.

[0028] S3 specifically includes the following sub-steps: S310. Circular Shift Buffer State Copying and Binding: For each extended decoding path in the extended decoding path set, its parent decoding path is determined based on its parent decoding path identifier. When an extended decoding path is generated by splitting, the circular shift buffer state of the parent decoding path is copied as an independent instance, and the independent instance is bound to the extended decoding path to ensure that the circular shift buffer states corresponding to different extended decoding paths are independent of each other. When an extended decoding path is generated by inheritance, the circular shift buffer state of the parent decoding path can be referenced as an input state using pointer indexing, and the updated circular shift buffer state is written back to the circular shift buffer state corresponding to the extended decoding path during subsequent updates.

[0029] S320. Original Bit Sequence Recovery and Determination (GF(2) Definition): For each extended decoding path in the extended decoding path set, based on the candidate codeword sequence of the extended decoding path and the node code length of the current decoding node... Determine the original bit sequence of the extended decoding path, specifically including: When the current decoding node is node R0, the original bit sequence is determined to be the same as the node code length. A consistent sequence of all-zero raw bits; when the current decoding node is an R1 node or an SPC node and the PC state maintenance flag of the extended decoding path indicates "PC parity bit exists", or when the current decoding node does not contain a PC parity bit but contains information bits and needs to maintain the continuous evolution of the cyclic shift buffer state, the candidate codeword sequence of the extended decoding path is recorded as a binary vector. (length is) ), will be with The generating matrix of the matching is denoted as The following operations are performed within the GF(2) domain to obtain the original bit sequence. : in," " represents matrix multiplication, " " indicates a bitwise modulo-2 operation, the output is For length A binary vector whose bit order is consistent with the bit position order of the current decoding node; When the current decoding node is a REP node, the original bit sequence is determined to be the original bit sequence that satisfies "only the last bit is an information bit"; and when the last bit is a PC check bit, the original bit sequence is kept for subsequent cyclic shift buffer state updates and PC check calculations.

[0030] S330. Based on the original bit sequence of each extended decoding path, update the state of its circular shift buffer to obtain the updated state of the circular shift buffer and write it back to the extended decoding path. Specifically, this includes: representing the state of the circular shift buffer as a 5-bit vector. Extract the input bit subsequence from the original bit sequence in the order of the bit positions of the current decoding node to drive the state update of the circular shift buffer. The input bit subsequence contains at least the information bits from the original bit sequence but excludes the frozen bits; for each input bit... Perform the update sequentially, with the following update rules: First, perform a circular left shift operation on the circular shift register state, that is, temporarily store the first and second state, and then... Then the input bits The bit is XORed with the shifted first bit register state for updating, i.e. The states of the remaining registers remain unchanged after the shift.

[0031] When the PC status maintenance flag of the extended decoding path indicates "PC check bit exists", the updated circular shift buffer state is used as the input state for subsequent PC checks to ensure that the PC check calculation is consistent with the state used for path filtering.

[0032] S4 specifically includes the following sub-steps: S410, PC Check Execution and Status Flag Update: Based on the updated circular shift register state, perform PC check on each extended decoding path in the extended decoding path set and update the PC check status flag of that extended decoding path. Specifically, this includes: Read the updated circular shift register state of the extended decoding path. And the actual values ​​of the corresponding PC check bits in its candidate codeword sequence; determine the set of PC check bit positions that need to be checked in the current decoding node as P, where P is determined by the PC state maintenance flag and PC check bit position identifier of the extended decoding path, and only includes PC check bit positions that fall in the current decoding node.

[0033] For any PC check bit position Directly obtain the value of the first register of the current circular shift register state. As expected PC check value And compare it with the actual PC check bit value in the candidate codeword sequence. Perform a comparison to obtain the verification result for that location: in, This is an indicator function that takes the value 1 when the equation within the parentheses is true, and 0 otherwise.

[0034] The overall PC check result of the extended decoding path within set P is defined as: in, This represents a logical AND operation, indicating that the overall verification result is true only if the verification result at all positions in set P is 1. When PASS is true, the PC verification status flag of the extended decoding path is updated to "PC verification passed"; when PASS is false, the PC verification status flag of the extended decoding path is updated to "PC verification failed". If P is an empty set, the PC verification status flag of the extended decoding path remains unchanged.

[0035] S420, Over-limit Pre-screening and Fallback Rules: When the number of extended decoding paths in the extended decoding path set is greater than the maximum number of retained paths L, pre-screening is performed based on the PC verification status flag: extended decoding paths marked with "PC verification failed" are discarded as elimination objects, resulting in a pre-screened extended decoding path set; if the number of extended decoding paths marked with "PC verification passed" after pre-screening is less than L, extended decoding paths marked with "PC verification failed" are allowed to be supplemented from the extended decoding paths marked with "PC verification failed" in order of path metric from best to worst so that the number of extended decoding paths after pre-screening reaches L, and the PC verification status of the supplemented extended decoding paths is kept marked with "PC verification failed" for subsequent steps to continue processing; if the number of extended decoding paths marked with "PC verification passed" after pre-screening is 0, extended decoding paths are not discarded due to PC verification, and selection based on path metric is adopted to ensure that the decoding process is not interrupted.

[0036] S430. Metric Selection and Deterministic Parallel Processing: When the number of extended decoding paths in the pre-selected extended decoding path set is still greater than the maximum number of retained paths L, the L extended decoding paths with the best path metrics are selected from the pre-selected extended decoding path set as a new decoding path set. When path metrics are tied among candidate extended decoding paths, a preset deterministic rule is used to break the tie to ensure the selection result is reproducible. The preset deterministic rule includes at least one of the following: Prioritize extended decoding paths with a PC verification status marked as "PC verification passed"; if the PC verification status marks are the same, select according to the preset order of the parent decoding path identifiers; if the parent decoding path identifiers are still the same, select according to the preset order of the candidate codeword sequences. After selection, the new decoding path set is output and processed by the next decoding node.

[0037] S5 specifically includes the following sub-steps: S510, Supplementary PC Check for Uncovered PC Parity Bits (Coverage Closed Loop): Before decoding ends or before output, perform PC parity coverage checks and supplementary PC checks on each decoding path in the decoding path set. Specifically, this includes maintaining a set of checked PC parity bit positions for each decoding path. And determine the set of unchecked PC check bits corresponding to the decoding path. for: in, This is the set of global PC parity bit positions determined by the Polar coding scheme. This represents the set difference operation. For any decoding path, when... When not empty, the updated circular shift register state based on the decoding path. The same verification rule as step S410 is used (i.e., directly obtain the value of the first register of the circular shift register state). As the expected verification value), for Each PC check bit position in the array is checked sequentially using PC verification; after completing the supplementary PC verification, the corresponding position is added. Based on the supplementary PC verification results, the PC verification status of the decoding path is updated to "PC verification passed" or "PC verification failed".

[0038] S520. Removal of Failed Decoding Paths and Determination of the Last Set: Based on the PC verification status flag, the decoding path set is filtered out, and decoding paths with the PC verification status flag "PC verification failed" are removed, resulting in a set of verified decoding paths. When the set of verified decoding paths is empty, the last set of decoding paths is determined as the set of decoding paths after supplementing PC verification to ensure that the decoding output is not interrupted. When the set of verified decoding paths is not empty, the candidate output set is determined as the set of verified decoding paths.

[0039] S530. Optimal Decoding Path Selection and Decoding Result Output: The optimal decoding path is selected from the candidate output set, and Cyclic Redundancy Check (CRC) is introduced as a joint decision criterion. The specific selection strategy is as follows: CRC Priority Screening: First, perform a CRC check on each decoding path in the candidate output set. If at least one decoding path in the candidate output set passes the CRC check, then these paths that pass the CRC check constitute the CRC Pass Set. .

[0040] Measured selection: If If not empty, then in The optimal decoding path is selected based on the path metric. ;like If the result is empty (i.e., all paths fail the CRC check), then a fallback strategy is activated, directly adding the candidate output from the original set. The optimal decoding path is the one with the best path metric. .

[0041] The selection of the optimal decoding path satisfies the following optimization objective: in, The filter set determined based on the CRC check result (i.e. or ), Indicates the decoding path Path metrics This represents the variable value that minimizes the objective function.

[0042] Finally, output the optimal decoding path. The corresponding decoding result is the information bit sequence extracted from the original bit sequence of the optimal decoding path according to the information bit position set.

[0043] Example 2: This example provides a Polar code FSCL decoding system based on PC verification, including: The decoding initialization module is used to: acquire the soft information of the Polar code to be decoded, which is a log-likelihood ratio (LLR) sequence arranged in the order of the Polar code bits; set the maximum number of retained paths to L; establish a generator matrix identifier that matches the code length of the current decoding node; establish an initial set of decoding paths, and configure a path metric, a circular shift buffer state, and a PC check status flag for each decoding path, wherein the path metric of the initial decoding path is initialized to a preset minimum metric value, the circular shift buffer state is initialized to an all-zero state, and the PC check status flag is initialized to an incomplete PC check; The FSCL subcode node processing module is used for: determining the node code length and obtaining the frozen bit / information bit attributes for the current decoding node; determining whether the current decoding node is an R0 node, R1 node, REP node, or SPC node based on the frozen bit / information bit attributes; for each decoding path in the decoding path set, performing hard judgment based on the soft information corresponding to the current decoding node to obtain a baseline candidate codeword sequence, and generating at least one candidate codeword sequence according to the node type, wherein when the current decoding node is an R0 node, an all-zero candidate codeword sequence is generated, and when the current decoding node is a REP node, an all-zero candidate codeword sequence is generated. Candidate codeword sequences are generated based on the constraint that the last bit is an information bit. When the current decoding node is an R1 node or an SPC node, splitting is performed on the baseline candidate codeword sequence to generate multiple candidate codeword sequences. A PC status maintenance flag is set for the candidate codeword sequences containing PC check bits, and each decoding path is associated with each candidate codeword sequence it generates to construct an extended decoding path set. Each extended decoding path includes at least the parent decoding path identifier, candidate codeword sequence, path metric, cyclic shift buffer status, PC check status flag, and PC status maintenance flag. The original bit sequence recovery and cyclic shift buffer update module is used for: determining the parent decoding path for each extended decoding path in the extended decoding path set based on the parent decoding path identifier; when the extended decoding path is generated by splitting, copying the cyclic shift buffer state of the parent decoding path as an independent instance and binding it to the extended decoding path; determining the original bit sequence of the extended decoding path, wherein when the current decoding node is an R0 node, the original bit sequence is an all-zero original bit sequence; when the current decoding node is an R1 node or an SPC node and the PC state maintenance flag indicates the presence of a PC check bit; or when the current decoding node does not contain a PC check bit but contains information bits and needs to maintain the continuous evolution of the cyclic shift buffer state, operating the generator matrix based on the candidate codeword sequence and the node code length in the GF(2) domain to obtain the original bit sequence; extracting the input bits for updating according to the bit position order based on the original bit sequence and performing bit-by-bit update on the cyclic shift buffer state to obtain the updated cyclic shift buffer state and writing it back to the extended decoding path; The PC verification and path filtering module is used to: determine the set of PC verification bit positions that need to be verified within the current decoding node for each extended decoding path in the extended decoding path set, and perform PC verification on the set of PC verification bit positions based on the updated circular shift buffer state to obtain the overall PC verification result and update the PC verification status to PC verification passed or PC verification failed; when the number of extended decoding paths is greater than L, the extended decoding paths that fail PC verification are discarded as elimination objects to obtain a pre-filtered extended decoding path set; when the number of extended decoding paths that pass PC verification after pre-filtering is less than L, the extended decoding paths that fail PC verification are supplemented by selecting from the extended decoding paths that fail PC verification in descending order of path metric to make the number of extended decoding paths after pre-filtering reach L; when the number of extended decoding paths after pre-filtering is still greater than L, the L extended decoding paths with the best path metric are selected as a new decoding path set according to the path metric, and the selection is completed according to the preset deterministic rules when the path metrics are in sync. The complete verification and decoding output module is used for: maintaining a set of verified PC check bit positions for each decoding path in the decoding path set, and determining a set of unverified PC check bit positions; when the set of unverified PC check bit positions is not empty, performing supplementary PC verification on the set of unverified PC check bit positions based on the updated cyclic shift buffer state of the decoding path and updating the set of verified PC check bit positions and the PC verification status flag; removing decoding paths that fail PC verification to obtain a set of verified decoding paths; when the set of verified decoding paths is empty, using the set of decoding paths after supplementary PC verification as the fallback decoding path set; selecting the decoding path with the optimal path metric from the set of verified decoding paths or the fallback decoding path set as the optimal decoding path, and outputting the information bit sequence extracted from the original bit sequence of the optimal decoding path according to the information bit position set as the decoding result.

[0044] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters and thresholds in the formulas are set by those skilled in the art according to the actual situation.

[0045] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions according to the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. Semiconductor media can be solid-state drives.

[0046] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0047] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0048] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0049] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0050] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0051] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0052] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0053] In conclusion, the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A Polar code FSCL decoding method based on PC check, characterized in that, Includes the following steps: S1. Obtain the soft information of the Polar code to be decoded and set the maximum number of retained paths to L; establish an initial decoding path set, initialize the state of the cyclic shift buffer of each decoding path to all zeros, and initialize the PC check status flag to incomplete. S2. During the decoding process, the node type is determined based on the distribution of information bits and frozen bits within the current decoding node. Candidate codeword sequences are generated according to the fast decoding rules of the corresponding type to construct an extended decoding path set, and PC status maintenance flags are set for candidate codeword sequences involving PC check bits. S3. For each extended decoding path, recover the original bit sequence based on the candidate codeword sequence, and update the state of the circular shift register accordingly. The update rule is: perform a circular left shift operation on the state of the circular shift register, and perform an XOR operation between the input bits in the original bit sequence and the state of the first bit register after shifting to obtain the updated state of the circular shift register. S4. Perform PC verification and path filtering based on the updated circular shift register state: directly obtain the first register value of the circular shift register state as the expected verification value, and compare it with the actual PC verification bit value to update the PC verification state flag. Prioritize discarding extended decoding paths that fail PC verification, and then select and retain L extended decoding paths from the remaining paths based on path metrics.

2. The Polar code FSCL decoding method based on PC verification according to claim 1, characterized in that, Also includes: S5. Perform a consistency check on the retained decoding path set: perform PC check on the uncovered PC check bits and remove paths that fail the check. In the remaining paths, combine the Cyclic Redundancy Check (CRC) result with the path metric to select the optimal decoding path and output its corresponding decoding result.

3. The Polar code FSCL decoding method based on PC verification according to claim 1, characterized in that, S1 specifically refers to: Obtain the soft information of the Polar code to be decoded, which is a log-likelihood ratio sequence arranged in the order of the Polar code bits; establish a generator matrix identifier for recovering the original bit sequence, and match its order with the code length of the subsequent decoding nodes; initialize the path metric of each decoding path to a preset minimum metric value, and initialize the state of the circular shift buffer to all zeros.

4. The Polar code FSCL decoding method based on PC verification according to claim 1, characterized in that, S2 specifically refers to: During the decoding process, the frozen bit or information bit attribute of each bit position in the current decoding node is obtained; if all bits in the node are frozen bits, it is determined to be an R0 node; if all bits are information bits, it is determined to be an R1 node; if only the last bit is an information bit, it is determined to be a REP node; if only the first bit is a frozen bit, it is determined to be an SPC node.

5. The Polar code FSCL decoding method based on PC verification according to claim 4, characterized in that, The specific steps for generating candidate codeword sequences are as follows: hard-determine the soft information to obtain a baseline candidate codeword sequence; generate an all-zero candidate codeword sequence for R0 nodes; generate a candidate codeword sequence for REP nodes based on the last bit information constraint; perform splitting on the baseline candidate codeword sequence for R1 nodes or SPC nodes to generate multiple candidate codeword sequences; if the generated candidate codeword sequence involves PC check bits, set a PC state maintenance flag to trigger subsequent recovery of the original bit sequence.

6. The Polar code FSCL decoding method based on PC verification according to claim 1, characterized in that, The recovery of the original bit sequence in S3 is specifically as follows: For node R0, the original bit sequence is determined to be an all-zero sequence; for node R1, SPC or REP, when the state of the cyclic shift register needs to be updated, the candidate codeword sequence and the generator matrix corresponding to the current node code length are subjected to matrix operation in the binary field GF(2) to recover the original bit sequence used to drive the register update.

7. The Polar code FSCL decoding method based on PC verification according to claim 1, characterized in that, The specific path filtering in S4 is as follows: When the number of extended decoding paths is greater than L, pre-screening is performed, prioritizing the removal of extended decoding paths marked as failing the PC check. If the number of remaining paths after pre-screening is less than L, paths are selected from the removed paths in descending order of path metric until L is reached. If the number of remaining paths after pre-screening is still greater than L, then only the L extended decoding paths with the best path metrics will be retained; when the path metrics are the same, a deterministic selection will be made using preset rules.

8. The Polar code FSCL decoding method based on PC check as described in claim 2, characterized in that, S5 specifically refers to: Before output, a consistency check is performed on the reserved set of decoding paths, supplementary checks are performed on the uncovered PC check bits, and paths that fail the check are removed. In the remaining set of decoded paths that pass the check, paths that pass the Cyclic Redundancy Check (CRC) are searched first. If a path that passes the CRC exists, the path with the best path metric is selected as the output. If no path that passes the CRC exists, the path with the best path metric is selected as the output among all paths that pass the PC check.

9. A Polar code FSCL decoding system based on PC-checking, employing the Polar code FSCL decoding method based on PC-checking as described in any one of claims 1-8, characterized in that, include: The module includes a decoding initialization module, an FSCL subcode node processing module, a raw bit sequence recovery and cyclic shift buffer update module, a PC check and path filtering module, and a complete check and decoding output module.

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