Optoelectronic package structure and method of packaging the same

Abstract

The application discloses an optoelectronic packaging structure and a packaging method thereof. The optoelectronic packaging structure comprises a support substrate, an optical chip, at least one electric chip and at least one passive connection chip. The support substrate comprises a substrate body and at least one opening, and the opening penetrates through the substrate body. The optical chip and the passive connection chip are arranged in the opening. The electric chip is arranged on one side of the support substrate and is electrically connected with the optical chip and the passive connection chip respectively. The overlapping area between the electric chip and the optical chip is S1, the area of a device surface in the optical chip is S2, and S1 / S2<50%. The technical scheme of the application solves the problem of large planar size of the optoelectronic packaging structure caused by side-by-side arrangement, realizes miniaturized optoelectronic packaging structure, and realizes electric connection between the electric chip and the optical chip while reducing the influence of the electric chip with large heat generation on the optical chip by laminating the optical chip and the electric chip and reducing the overlapping area.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and more particularly to optoelectronic packaging structures and packaging methods. Background Technology

[0002] Optoelectronic co-packaging structure is a structure that integrates an optical engine and an electrical chip into the same package through packaging technology.

[0003] The existing optoelectronic co-packaging structure has the following problems:

[0004] (1) Mounting optical chips and electrical chips side by side on a circuit board results in an excessively large product size;

[0005] (2) When the electrical chip is directly mounted on the optical chip, the heat generated by the electrical chip during operation will affect the performance of the optical chip and the heat dissipation will be poor. Summary of the Invention

[0006] This invention provides an optoelectronic packaging structure and its packaging to solve the problems of large size and poor heat dissipation in existing optoelectronic co-packaging technologies.

[0007] According to one aspect of the present invention, an optoelectronic packaging structure is provided, including a support substrate, an optical chip, at least one electrical chip, and at least one passive connection chip;

[0008] The support substrate includes a substrate body and at least one opening, the opening penetrating the substrate body; the optical chip and the passive connection chip are disposed within the opening;

[0009] The electrical chip is disposed on one side of the support substrate and is electrically connected to the optical chip and the passive connection chip, respectively.

[0010] Along the stacking direction of the electrical chip and the supporting substrate, the overlap area between the electrical chip and the optical chip is S1, and the area of ​​the device surface in the optical chip is S2, where S1 / S2 < 50%.

[0011] Optionally, the electrical chip includes a first electrical chip and a second electrical chip, both of which are electrically connected to the optical chip;

[0012] The device surface includes a first side, a second side, and a third side connecting the first side and the second side, which are disposed opposite to each other.

[0013] Along the stacking direction of the electrical chip and the supporting substrate, the first electrical chip overlaps with the first side, and the second electrical chip overlaps with the second side; the optical port of the optical chip is located at the third side.

[0014] Optionally, the passive connection chip is electrically connected to at least one electrical chip.

[0015] Optionally, the optical chip and the passive connection chip are housed in the same opening;

[0016] Alternatively, the support substrate may include multiple openings, with the optical chip and passive connection chip disposed in different openings.

[0017] Optionally, the optoelectronic packaging structure may also include a first connection structure, a second connection structure, and a welding connection structure;

[0018] The first connection structure is located on the first surface of the supporting substrate. The first connection structure includes at least one first dielectric layer and a first wiring structure located in the first dielectric layer. The first wiring structure electrically connects the passive connection chip and the electrical chip, and electrically connects the optical chip and the electrical chip.

[0019] The second connection structure is located on the second surface of the supporting substrate, and the second surface is disposed opposite to the first surface. The second connection structure includes at least one second dielectric layer and a second wiring structure located in the second dielectric layer. The second wiring structure electrically connects the passive connection chip and the welding connection structure, and electrically connects the optical chip and the welding connection structure.

[0020] Optionally, passive interconnect chips include glass via interconnect chips or silicon via interconnect chips.

[0021] According to another aspect of the present invention, a packaging method for an optoelectronic packaging structure is provided, comprising:

[0022] A support substrate is provided, the support substrate including a substrate body and at least one opening, the opening penetrating the substrate body;

[0023] The opening is filled with at least one set of optical chips and at least one passive connection chip; the optical chips include a first optical chip and a second optical chip and a dicing channel located between the first optical chip and the second optical chip; the optical ports of the first optical chip and the second optical chip are located on both sides of the dicing channel, respectively.

[0024] An electrical chip is disposed on one side of a support substrate, and is electrically connected to an optical chip assembly and to a passive connection chip; along the stacking direction of the electrical chip and the support substrate, the overlap area between the electrical chip and the optical chip assembly is S1, and the area of ​​the device surface in the optical chip assembly is S2, wherein S1 / S2 < 50%;

[0025] The optical chip assembly and the supporting substrate are cut along the cutting path to prepare the optoelectronic packaging structure.

[0026] Optionally, the electrical chip includes a first electrical chip and a second electrical chip;

[0027] The device surface includes a first side and a second side that are arranged opposite to each other;

[0028] An electrical chip is disposed on one side of a support substrate and electrically connected to an optical chip assembly, including:

[0029] A first electrical chip is disposed on one side of the first optical chip and electrically connected to the first optical chip; a second electrical chip is disposed on one side of the second optical chip and electrically connected to the first optical chip.

[0030] A first electrical chip is disposed on one side of the second optical chip and electrically connected to the second optical chip. A second electrical chip is disposed on one side of the second optical chip and electrically connected to the second optical chip.

[0031] Optionally, the optical chip assembly and supporting substrate are cut along the dicing path, including:

[0032] The optical chip assembly and supporting substrate are cut along the cutting path using a hidden cutting process.

[0033] Optionally, the opening is filled with at least one set of optical chipsets and at least one passive interconnect chip, including:

[0034] A first temporary carrier is attached to one side of the supporting substrate;

[0035] At least one set of optical chipsets and at least one passive connection chip are filled on one side of the first temporary carrier and inside the opening;

[0036] An electrical chip is disposed on one side of the support substrate, and before the electrical chip is electrically connected to the optical chip assembly and the electrical chip is electrically connected to the passive connection chip, the following is also included:

[0037] At least one first dielectric layer is prepared on the first surface of a supporting substrate, and a first wiring structure is prepared in the first dielectric layer to obtain a first connection structure; the first wiring structure is electrically connected to a passive connection chip and an optical chip assembly, respectively.

[0038] A second temporary carrier is prepared on one side of the first connecting structure, and the first temporary carrier is removed;

[0039] At least one second dielectric layer is prepared on the second surface of the supporting substrate, and a second wiring structure is prepared in the second dielectric layer to obtain a second connection structure; the second wiring structure is electrically connected to the passive connection chip and the optical chip assembly, respectively.

[0040] A welding connection structure is prepared on the side of the second connection structure away from the supporting substrate, and the welding connection structure is electrically connected to the second wiring structure.

[0041] Remove the second temporary carrier;

[0042] An electrical chip is disposed on one side of a support substrate, and the electrical chip is electrically connected to an optical chip assembly and electrically connected to a passive connection chip, including:

[0043] An electrical chip is disposed on the side of the first connection structure away from the support substrate, and the electrical chip is electrically connected to the first wiring structure.

[0044] The technical solution of this invention places the electrical chip on one side of the support substrate, allowing the electrical chip and the optical chip to be stacked together, which solves the problem of large planar size of optoelectronic packaging structure caused by side-by-side placement. At the same time, the overlap area S1 between the electrical chip and the optical chip and the area S2 of the device surface in the optical chip are set to satisfy S1 / S2<50%, so that the electrical chip and the optical chip have a small overlap area, which ensures the connection between the electrical chip and the optical chip, reduces the impact of the high-heat electrical chip on the optical chip, and improves heat dissipation performance.

[0045] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of a first optoelectronic packaging structure provided according to an embodiment of the present invention;

[0048] Figure 2 yes Figure 1 A schematic diagram of the cross-section along AA';

[0049] Figure 3 This is a schematic diagram of the fabrication process of an optoelectronic packaging structure according to an embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram of a second optoelectronic packaging structure provided according to an embodiment of the present invention;

[0051] Figure 5 This is a schematic diagram of a third optoelectronic packaging structure provided according to an embodiment of the present invention;

[0052] Figure 6 yes Figure 5 A schematic diagram of the cross-section along BB';

[0053] Figure 7 This is a cross-sectional schematic diagram of an optoelectronic packaging structure provided according to an embodiment of the present invention;

[0054] Figure 8This is a flowchart of a packaging method for a first optoelectronic packaging structure provided by an embodiment of the present invention;

[0055] Figure 9 This is a structural diagram corresponding to a packaging method for an optoelectronic packaging structure provided in an embodiment of the present invention;

[0056] Figure 10 This is a flowchart of a packaging method for a second optoelectronic packaging structure provided by an embodiment of the present invention;

[0057] Figure 11 This is a flowchart of a packaging method for a third optoelectronic packaging structure provided in an embodiment of the present invention;

[0058] Figure 12 This is a flowchart of a packaging method for a fourth optoelectronic packaging structure provided in an embodiment of the present invention;

[0059] Figure 13 This is a partial structural diagram corresponding to a packaging method for another optoelectronic packaging structure provided by an embodiment of the present invention;

[0060] Figure 14 This is another part of the structural diagram corresponding to the packaging method of another optoelectronic packaging structure provided in the embodiment of the present invention. Detailed Implementation

[0061] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0063] Figure 1 This is a schematic diagram of a first optoelectronic packaging structure provided according to an embodiment of the present invention. Figure 2 yes Figure 1 A schematic cross-sectional view along AA'. (Combined with...) Figure 1 and Figure 2 As shown, the optoelectronic packaging structure includes:

[0064] Supporting substrate 1, optical chip 2, at least one electrical chip 3, and at least one passive connection chip 4;

[0065] The support substrate 1 includes a substrate body 11 and at least one opening 12, the opening 12 penetrating the substrate body 11; the optical chip 2 and the passive connection chip 4 are disposed in the opening 12.

[0066] The electrical chip 3 is disposed on one side of the support substrate 1 and is electrically connected to the optical chip 2 and the passive connection chip 4 respectively.

[0067] Along the stacking direction y of the electrical chip 3 and the supporting substrate 1, the overlap area between the electrical chip 3 and the optical chip 2 is S1, and the area of ​​the device surface in the optical chip 2 is S2, where S1 / S2 < 50%.

[0068] The supporting substrate 1 can be a substrate in an optoelectronic packaging structure, serving to support the structure and ensure its stability. In some embodiments, the supporting substrate 1 can be a silicon-based supporting substrate. The supporting substrate 1 includes a substrate body 11 and at least one opening 12 penetrating the substrate body 11, which can be formed by etching the supporting substrate 1.

[0069] The optical chip 2 can be a chip that performs photoelectric conversion and can be used for optical signal processing; for example, it is a silicon photonic chip 2. The optical chip 2 is disposed in the opening 12 of the supporting substrate 1, and the position of the opening 12 in the supporting substrate 1 can limit the optical chip 2. The opening 12 serves to fix and position the optical chip 2, and since the opening 12 penetrates the substrate body 11, the optical chip 2 disposed in the opening 12 can be electrically connected to both sides of the supporting substrate 1. The device surface of the optical chip 2 can be a functional surface, that is, the side of the optical chip 2 that integrates optical devices, electrical devices, waveguides, and electrodes. In the optoelectronic packaging structure, the device surface of the optical chip 2 must face the electrical chip 3 for connection.

[0070] In this structure, the electrical chip 3 can be a chip with electrical functions in the optoelectronic packaging structure, such as a driver chip or a transimpedance amplifier. The driver chip can amplify electrical signals, and the transimpedance amplifier can convert the current signal from light conversion into a voltage signal and amplify it. The electrical chip 3 is disposed on one side of the support substrate 1 and electrically connected to the optical chip 2. It is not arranged horizontally with the optical chip 2, but rather stacked on the support substrate 1. This ensures that the electrical chip 3 is connected to the optical chip 2 while reducing the horizontal dimensions of the optoelectronic packaging structure. Along the stacking direction y of the electrical chip 3 and the support substrate 1, the overlap area S1 between the electrical chip 3 and the optical chip 2 and the area S2 of the device surface in the optical chip 2 satisfy S1 / S2 < 50%. This means that the electrical chip 3 and the optical chip 2 have a small overlap area, reducing the contact area between the heat-generating electrical chip 3 and the optical chip 2, thus reducing the impact of the electrical chip 3 on the performance of the optical chip 2 and optimizing the heat dissipation of the optoelectronic packaging structure.

[0071] It should be noted that S1 / S2 < 50%, where S1 / S2 can be any value or any range of values ​​less than 50%, for example, 1% < S1 / S2 < 50%, or 5% < S1 / S2 < 50%, or 10% < S1 / S2 < 50%, or 20% < S1 / S2 < 50%, or 1% < S1 / S2 < 45%, or 5% < S1 / S2 < 45%, or 10% < S1 / S2 < 45%, or 15% < S1 / S2 < 45%, or 1% < S1 / S2 < 40%, or 1% < S1 / S2 < 35%, or 1% < S1 / S2 < 30%, or 1% < S1 / S2 < 25%, or 1% < S1 / S2 < 20%, or 1% < S1 / S2 < 15%. Alternatively, S1 / S2 can be 1%, 2%, 3%, 5%, 8%, 10%, 12%, 15%, 17%, 20%, 23%, 25%, 28%, 30%, 31%, 33%, 36%, 38%, 40%, 42%, 44%, 45%, 47%, 49%, etc. The embodiments of this application do not limit the specific numerical range or specific value of S1 / S2.

[0072] The passive connection chip 4 is used to realize electrical connections in the optoelectronic packaging structure. The passive connection chip 4 can be a glass through-hole connection chip, a silicon through-hole connection chip, a resistor, an inductor, or a capacitor, etc., depending on the requirements, but it must be a qualified unpackaged bare chip. The passive connection chip 4 is also disposed in the opening 12 of the support substrate 1. The opening 12 corresponding to the passive connection chip 4 and the opening 12 of the optical chip 2 can be the same opening 12 or different openings 12, depending on the requirements. The electrical chip 3 is disposed on one side of the support substrate 1 and is electrically connected to the passive connection chip 4. The electrical chip 3 can have its pins brought out through the passive connection chip 4, facilitating connection with other electrical components. The technical solution of this embodiment of the invention, by placing the passive connection chip 4 in the opening 12 of the support substrate 1, can improve the overall packaging yield of the optoelectronic packaging structure and also help reduce costs.

[0073] The technical solution of this invention places the electrical chip on one side of the support substrate, allowing the electrical chip and the optical chip to be stacked together, which solves the problem of large planar size of the optoelectronic packaging structure caused by side-by-side placement. At the same time, the overlap area S1 between the electrical chip and the optical chip and the area S2 of the device surface in the optical chip are set to satisfy S1 / S2<50%, so that the electrical chip and the optical chip have a small overlap area, which ensures the connection between the electrical chip and the optical chip, reduces the impact of the heat-generating electrical chip on the optical chip, and improves the heat dissipation performance of the optoelectronic packaging structure.

[0074] Optionally, in some embodiments, the passive connection chip 4 includes a glass through-hole connection chip or a silicon through-hole connection chip. The glass through-hole connection chip has advantages such as low loss, low crosstalk, low stress, low warpage, and high light transmittance. Replacing the adapter board in the prior art with a glass through-hole connection chip can improve the packaging yield of optoelectronic co-packaging and help reduce costs. The silicon through-hole connection chip has advantages such as high heat dissipation efficiency and structural stability. Using a silicon through-hole connection chip can improve the stability and heat dissipation capacity of the optoelectronic packaging structure.

[0075] Optional, continue to refer to Figure 1 and Figure 2 As shown, the electrical chip 3 includes a first electrical chip 31 and a second electrical chip 32, both of which are electrically connected to the optical chip 2.

[0076] The device surface includes a first side 201, a second side 202 disposed opposite to each other, and a third side 203 connecting the first side 201 and the second side 202;

[0077] Along the stacking direction y of the electrical chip 3 and the supporting substrate 1, the first electrical chip 31 overlaps with the first side 201, and the second electrical chip 32 overlaps with the second side 202; the optical port 200 of the optical chip 2 is disposed at the third side 203.

[0078] In this embodiment, the first electrical chip 31 and the second electrical chip 32 can be understood as electrical chips 3 overlapping different sides of the device surface of the optical chip 2, or as electrical chips 3 disposed on different sides of the device surface of the optical chip 2. This application does not limit the specific types of the first electrical chip 31 and the second electrical chip 32; the first electrical chip 31 and the second electrical chip 32 can be the same type of electrical chip, or they can be different types of electrical chips. For example, the first electrical chip 31 and the second electrical chip 32 can both be driver chips; or the first electrical chip 31 and the second electrical chip 32 can both be transimpedance amplifiers; or the first electrical chip 31 can be a driver chip, and the second electrical chip 32 can be a transimpedance amplifier.

[0079] In this design, the optical port 200 of the optical chip 2 serves as both an input and output port for optical signals. The first electrical chip 31 overlaps with the first side 201, and the second electrical chip 32 overlaps with the second side 202. The optical port 200 for the optical signal is positioned at the third side 203. This arrangement ensures the connection between the electrical chip 3 and the optical chip 2 while preventing obstruction of the optical port 200 of the optical chip 2, thus guaranteeing the normal operation of the optoelectronic packaging structure. Furthermore, this configuration of the optical port 200 and electrical chip 3 allows for the simultaneous fabrication of two optoelectronic packaging structures. Figure 3 This is a schematic diagram of the fabrication process of an optoelectronic packaging structure according to an embodiment of the present invention, as shown below. Figure 3 As shown, two optoelectronic packaging structures are designed back-to-back in the opening 12 of the same support substrate 1 with the optical ports 200 in the optical chip 2 facing each other. After the two optoelectronic packaging structures are prepared, they are cut to obtain two independent optoelectronic packaging structures.

[0080] For example, in combination Figure 1 , Figure 2 and Figure 3 As shown, the support substrate 1 includes an opening 12, within which an optical chip group containing two optical chips 2 is disposed. The third side 203 of one optical chip 2 faces the third side 203 of the other optical chip 2. The first side 201 of one optical chip 2 and the second side 202 of the other optical chip 2 are on the same side of the optical chip group, meaning the two optical chips 2 are arranged back-to-back. Simultaneously, a first electrical chip 31 overlaps with the first side 201 of the optical chip 2, and a second electrical chip 32 overlaps with the second side 202 of the optical chip 2. After fabricating the above structure, the two back-to-back optoelectronic packaging structures are cut along a cutting channel 6 between the two third sides 203, thereby forming two independent optoelectronic packaging structures.

[0081] It is understandable that, due to the overlap of the first electrical chip 31 with the first side 201, the overlap of the second electrical chip 32 with the second side 202, and the optical port 200 of the optical chip 2 being located on the third side 203, the optoelectronic packaging structure can be fabricated in a back-to-back manner. After processing, the two optoelectronic packaging structures can be separated, which improves the fabrication efficiency of the optoelectronic packaging structure and effectively solves the impact of foreign matter and dirt on the optical port 200 of the optical chip 2 during the processing of the optoelectronic packaging structure, ensuring that the optical port 200 can efficiently transmit optical signals.

[0082] Optional, Figure 4 This is a schematic diagram of a second optoelectronic packaging structure provided according to an embodiment of the present invention, combined with... Figure 1 and Figure 4 As shown, the passive connection chip 4 is electrically connected to at least one electrical chip 3.

[0083] One passive connection chip 4 can connect to only one electrical chip 3, or one passive connection chip 4 can connect to multiple electrical chips 3.

[0084] For example, such as Figure 1 As shown, a passive connection chip 4 is electrically connected to an electrical chip 3, and the passive connection chip 4 overlaps only with the electrical chip 3. Figure 4 As shown, a passive connection chip 4 is electrically connected to two electrical chips 3, and the passive connection chip 4 overlaps with the two electrical chips 3.

[0085] It is understandable that the number of passive connection chips 4 connected to electrical chips 3 can be determined by combining the overall package size and stress balance of the optoelectronic packaging structure. For example, one passive connection chip 4 can also be electrically connected to four electrical chips 3.

[0086] The technical solution of this invention provides that a passive connection chip is electrically connected to at least one electrical chip, which ensures the normal operation of the optoelectronic packaging structure and allows for flexible configuration of the correspondence between the electrical chip and the passive connection chip according to requirements. This improves the flexibility of the optical packaging structure design and effectively mitigates the warping phenomenon caused by packaging stress.

[0087] Optional, continue to refer to Figure 1 and Figure 2 As shown, the optical chip 2 and the passive connection chip 4 are disposed in the same opening 12;

[0088] or, Figure 5 This is a schematic diagram of a third optoelectronic packaging structure provided according to an embodiment of the present invention. Figure 6 yes Figure 5 A cross-sectional view along BB', combined with... Figure 5 and Figure 6As shown, the support substrate 1 includes multiple openings 12, and the optical chip 2 and the passive connection chip 4 are disposed in different openings 12.

[0089] The optical chip 2 and the passive connection chip 4 can be set in the same opening 12 or in different openings 12.

[0090] For example, such as Figure 1 and Figure 2 As shown, the support substrate 1 includes only one opening 12. Both the optical chip 2 and the passive connection chip 4 are disposed within this opening 12, with the passive connection chip 4 positioned on opposite sides of the optical chip 2. The optical chip 2 and the passive connection chip 4 are bonded together using adhesive 8. Distributing the optical chip 2 and the passive connection chip 4 within the same opening 12 reduces the horizontal dimension of the optoelectronic packaging structure, facilitating miniaturized and compact optoelectronic packaging design.

[0091] For example, such as Figure 5 and Figure 6 As shown, the support substrate 1 includes multiple openings 12, with the optical chip 2 and the passive connection chip 4 each disposed in different openings 12. The passive connection chip 4 is disposed in two openings 12 opposite to the optical chip 2. Disposing the optical chip 2 and the passive connection chip 4 in different openings 12 provides a substrate body 11 that isolates them, thus mitigating the warping problem caused by packaging stress in the optoelectronic packaging structure.

[0092] Optional, Figure 7 This is a cross-sectional schematic diagram of an optoelectronic packaging structure provided according to an embodiment of the present invention, as shown below. Figure 7 As shown, the optoelectronic packaging structure also includes a first connection structure 51, a second connection structure 52, and a welding connection structure 53;

[0093] The first connection structure 51 is located on the first surface 01 of the support substrate 1. The first connection structure 51 includes at least one first dielectric layer 511 and a first wiring structure 512 located in the first dielectric layer 511. The first wiring structure 512 electrically connects the passive connection chip 4 and the electrical chip 3, and electrically connects the optical chip 2 and the electrical chip 3.

[0094] The second connection structure 52 is located on the second surface 02 of the support substrate 1, and the second surface 02 is disposed opposite to the first surface 01. The second connection structure 52 includes at least one second dielectric layer 521 and a second wiring structure 522 located in the second dielectric layer 521. The second wiring structure 522 electrically connects the passive connection chip 4 and the welding connection structure 53, and electrically connects the optical chip 2 and the welding connection structure 53.

[0095] The first surface 01 of the supporting substrate 1 can be the surface facing the electrical chip 3, which corresponds to the device surface of the optical chip 2. The first connection structure 51 serves as an electrical connection, specifically, the first connection structure 51 electrically connects the passive connection chip 4 and the electrical chip 3, and electrically connects the optical chip 2 and the electrical chip 3. Further, the first connection structure 51 includes at least one first dielectric layer 511 and a first wiring structure 512 located in the first dielectric layer 511. The first dielectric layer 511 serves as an insulating protection layer, and the number of layers of the first dielectric layer 511 can be set according to requirements. The first wiring structure 512 may include a redistribution layer and a metallization layer under the bump, serving as an electrical connection, specifically, the first wiring structure 512 realizes the electrical connection between the passive connection chip 4 and the electrical chip 3, and the electrical connection between the optical chip 2 and the electrical chip 3. Placing the first wiring structure 512 in the first dielectric layer 511 can prevent crosstalk between electrical signals.

[0096] The second surface 02 can be the surface opposite to the first surface 01 of the supporting substrate 1, corresponding to the non-device surface of the optical chip 2. The second connection structure 52 serves as an electrical connection, specifically, the second connection structure 52 electrically connects the passive connection chip 4 and the solder connection structure 53, and electrically connects the optical chip 2 and the solder connection structure 53. Further, the second connection structure 52 includes at least one second dielectric layer 521 and a second wiring structure 522 located in the second dielectric layer 521. The second dielectric layer 521 serves as an insulating protection layer, and the number of layers of the second dielectric layer 521 can be set according to requirements. The second wiring structure 522 may include a redistribution layer and a bump under-metallization layer, serving as an electrical connection, specifically, the second wiring structure 522 electrically connects the passive connection chip 4 and the solder connection structure 53, and electrically connects the optical chip 2 and the solder connection structure 53. Placing the second wiring structure 522 in the second dielectric layer 521 prevents crosstalk between electrical signals. The welding connection structure 53 can be a solder ball array (BGA) or a pad array (LGA) located on the second surface 02 of the support substrate 1.

[0097] The technical solution of this invention, by setting a first connection structure, a second connection structure, and a welding connection structure, realizes the electrical connection between the electrical chip and the optical chip, the electrical chip and the passive connection chip, the electrical chip and the welding connection structure, and the optical chip and the welding connection structure, thereby ensuring the normal operation of the optoelectronic packaging structure.

[0098] Based on the same inventive concept, this application also provides a packaging method for an optoelectronic packaging structure, specifically... Figure 8 This is a flowchart of a packaging method for a first optoelectronic packaging structure provided by an embodiment of the present invention. Figure 9This is a structural diagram corresponding to a packaging method for an optoelectronic packaging structure provided by an embodiment of the present invention, combined with... Figure 8 and Figure 9 As shown, the packaging method for the optoelectronic packaging structure provided in this embodiment of the invention includes:

[0099] S10. A support substrate is provided, the support substrate including a substrate body and at least one opening, the opening penetrating the substrate body.

[0100] like Figure 9 As shown in step (a), a support substrate 1 with opening 12 can be fabricated using photolithography and deep silicon etching techniques. The position of opening 12 can be obtained through patterning design in conjunction with the positions of the optical chip group 20 and the passive interconnect chip 4.

[0101] S11. Fill the opening with at least one set of optical chipsets and at least one passive connection chip.

[0102] like Figure 9 As shown in step (b), the optical chip group 20 includes a first optical chip 21 and a second optical chip 22, and a cleaving channel 6 located between the first optical chip 21 and the second optical chip 22; the optical port 200 of the first optical chip 21 and the optical port 200 of the second optical chip 22 are located on both sides of the cleaving channel 6.

[0103] The optical chipset 20 includes two optical chips 2, namely a first optical chip 21 and a second optical chip 22. The optical ports 200 of the optical chips can serve as ports for optical signal input and output. The dicing channel 6 is used for positioning in subsequent cutting and separation processes. The optical ports 200 of the first optical chip 21 and the second optical chip 22 are located on both sides of the dicing channel 6, so that the two optical ports 200 of the first optical chip 21 and the second optical chip 22 face each other and are designed back-to-back in the opening 12 of the same supporting substrate 1.

[0104] Among them, the passive connection chip 4 can be a qualified unpackaged bare chip that has been tested and screened.

[0105] When both the optical chip group 20 and the passive connection chip 4 are located in one opening 12, an adhesive 8 can be placed between the optical chip group 20 and the passive connection chip 4 to connect the optical chip group 20 and the passive connection chip 4 into a whole carrier wafer; when the optical chip group 20 and the passive connection chip 4 are in different openings 12, the optical chip group 20 and the passive connection chip 4 are placed in the corresponding openings 12 respectively during filling.

[0106] S12. An electrical chip is disposed on one side of the support substrate, and the electrical chip is electrically connected to the optical chip group and electrically connected to the passive connection chip.

[0107] Combination Figure 9 Step (c) and Figure 2As shown, the electrical chip 3 is soldered to one side of the support substrate 1 using a soldering process and is electrically connected to the optical chip group 20 and the passive connection chip 4, respectively. The first optical chip 21 and the second optical chip 22 can each correspond to different electrical chips 3, and the specific configuration can be set according to requirements. After the electrical chip 3 is installed, along the stacking direction y of the electrical chip 3 and the support substrate 1, the overlap area S1 between the electrical chip 3 and the optical chip group 20 and the area S2 of the device surface in the optical chip group 20 satisfy S1 / S2 < 50%, that is, the electrical chip 3 and the optical chip group 20 are set to have a small overlap area, which reduces the contact area between the electrical chip 3, which generates a lot of heat, and the optical chip group 20, increases the overlap area between the electrical chip 3 and the support substrate 1, reduces the impact of the optoelectronic packaging structure on the performance of the optical chip group 20, and optimizes the heat dissipation of the optoelectronic packaging structure.

[0108] It should be noted that S1 / S2 < 50%, where S1 / S2 can be any value or any range of values ​​less than 50%, for example, 1% < S1 / S2 < 50%, or 5% < S1 / S2 < 50%, or 10% < S1 / S2 < 50%, or 20% < S1 / S2 < 50%, or 1% < S1 / S2 < 45%, or 5% < S1 / S2 < 45%, or 10% < S1 / S2 < 45%, or 15% < S1 / S2 < 45%, or 1% < S1 / S2 < 40%, or 1% < S1 / S2 < 35%, or 1% < S1 / S2 < 30%, or 1% < S1 / S2 < 25%, or 1% < S1 / S2 < 20%, or 1% < S1 / S2 < 15%. Alternatively, S1 / S2 can be 1%, 2%, 3%, 5%, 8%, 10%, 12%, 15%, 17%, 20%, 23%, 25%, 28%, 30%, 31%, 33%, 36%, 38%, 40%, 42%, 44%, 45%, 47%, 49%, etc. The embodiments of this application do not limit the specific numerical range or specific value of S1 / S2.

[0109] S13. Cut the optical chip assembly and the support substrate along the cutting path to prepare the optoelectronic packaging structure.

[0110] Combination Figure 9 As shown in step (d), after the electrical chip 3 is installed, the optical chip group 20 and the support substrate 1 are cut along the cutting path 6, so that the first optical chip 21 and the second optical chip 22 are separated, thereby forming two independent optoelectronic packaging structures.

[0111] It is understandable that the optical ports 200 of the first optical chip 21 and the second optical chip 22 are located on both sides of the cutting channel 6. After the electrical chip 3 is processed, the optical chip group 20 and the support substrate 1 are cut along the cutting channel 6 to separate the first optical chip 21 and the second optical chip 22. This arrangement effectively avoids the influence of foreign matter and dirt on the optical port 200 of the optical chip 2 during the preparation of the optoelectronic packaging structure.

[0112] Furthermore, for the two optoelectronic packaging structures obtained by cutting, in each optoelectronic packaging structure, the overlap area S1 between the electrical chip 3 and the optical chip 2 and the area S2 of the device surface in the optical chip 2 satisfy S1 / S2<50%, that is, the optical chip 2 and the electrical chip 3 are stacked and the overlap area is small. In this way, the electrical chip 3 and the optical chip 2 are electrically connected, while the impact of the electrical chip 3 with high heat generation on the optical chip 2 is reduced.

[0113] It should be noted that S1 can be understood as the overlap area between the electrical chip 3 and the optical chip 2, or as the overlap area between the electrical chip 3 and the optical chip group 20. S2 can be understood as the area of ​​the device surface of the optical chip 2, or as the area of ​​the device surface of the optical chip group 20. Since the number of electrical chips 3 corresponding to the optical chip group 20 is twice the number of electrical chips 3 corresponding to a single optical chip 2, the value of S1 / S2 remains unchanged regardless of whether the packaging structure is before or after cutting.

[0114] In the embodiments of the present invention Figure 9 The image shown is a top view of the optoelectronic packaging process. Figure 2 This is a cross-sectional schematic diagram, combined with Figure 9 and Figure 2 As shown. Specifically, firstly, unpackaged passive connection chip 4, electrical chip 3, and a support substrate 1 with an etched opening 12 are provided after testing and screening to ensure they pass. An optical chip assembly 20 containing a first optical chip 21 and a second optical chip 22, and the passive connection chip 4 are placed in the opening 12, with the optical ports 200 of the two optical chips 2 in the optical chip assembly 20 located on both sides of the dicing channel 6. Electrical chips 3 are soldered to one side of the support substrate 1, with the device surface of the optical chip assembly 20 facing the electrical chip 3, ensuring that the overlap area S1 between the electrical chip 3 and the optical chip 2 and the area S2 of the device surface in the optical chip assembly 20 satisfy S1 / S2 < 50%. Then, the optical chip assembly 20 and the support substrate 1 are cut along the dicing channel 6 to form two independent optoelectronic packaging structures.

[0115] The technical solution of this invention places the electrical chip on one side of the support substrate, stacking the electrical chip and the optical chip together. This solves the problem of large planar dimensions in the optoelectronic packaging structure caused by side-by-side placement. Simultaneously, the overlap area S1 between the electrical chip and the optical chip and the area S2 of the device surface in the optical chip group are set to satisfy S1 / S2 < 50%, resulting in a small overlap area between the electrical chip and the optical chip group. This ensures connection between the electrical chip and the optical chip group while reducing the impact of the heat-generating electrical chip on the optical chip group, thus improving the heat dissipation performance of the optoelectronic packaging structure. Furthermore, designing the two optical chips of the optical chip group back-to-back and cutting them into two independent optoelectronic packaging structures after the electrical chip is fabricated improves the fabrication efficiency of the optoelectronic packaging structure and solves the problem of foreign matter and contaminants affecting the optical port of the optical chip during the optoelectronic packaging structure processing.

[0116] Based on the above embodiments, Figure 10 This is a flowchart of a packaging method for a second optoelectronic packaging structure provided by an embodiment of the present invention, combined with... Figure 9 and Figure 10 As shown, the electrical chip 3 includes a first electrical chip 31 and a second electrical chip 32; the device surface includes a first side 201 and a second side 202 disposed opposite to each other. The packaging method includes:

[0117] S20. A support substrate is provided, the support substrate including a substrate body and at least one opening, the opening penetrating the substrate body.

[0118] like Figure 9 As shown in step (a).

[0119] S21. Fill the opening with at least one set of optical chipsets and at least one passive connection chip.

[0120] like Figure 9 As shown in step (b).

[0121] S22. A first electrical chip is disposed on one side of the first optical chip and electrically connected to the first optical chip, and a second electrical chip is disposed on one side of the second optical chip and electrically connected to the first optical chip.

[0122] Combination Figure 9 As shown in step (c), the first electrical chip 31 is located on the first side 201 of the first optical chip 21, and the second electrical chip 32 is located on the second side 202 of the first optical chip 21. The optical port 200 of the first optical chip 21 can also be located on the third side 203. This ensures the connection between the first electrical chip 31 and the second electrical chip 32 and the first optical chip 21, while avoiding the obstruction of the optical port 200 of the first optical chip 21, thus ensuring the normal operation of the optoelectronic packaging structure.

[0123] S23. A first electrical chip is disposed on one side of the first optical chip and electrically connected to the second optical chip, and a second electrical chip is disposed on one side of the second optical chip and electrically connected to the second optical chip.

[0124] Combination Figure 9 As shown in step (c), the first electrical chip 31 is located on the first side 201 of the second optical chip 22, and the second electrical chip 32 is located on the second side 202 of the second optical chip 22. The optical port 200 of the second optical chip 22 can also be located on the third side 203. This arrangement makes the first side 201 of the first optical chip 21 and the second side 202 of the second optical chip 22 on the same side, and the second side 202 of the first optical chip 21 and the first side 201 of the second optical chip 22 on the same side, ensuring the back-to-back design of the first optical chip 21 and the second optical chip 22, realizing the simultaneous fabrication of two optoelectronic packaging structures, and ensuring the normal operation of the optoelectronic packaging structure.

[0125] It is understood that the first electrical chip 31 and the second electrical chip 32 can be understood as electrical chips 3 overlapping different sides of the device surface of the optical chip 2, or as electrical chips 3 disposed on different sides of the device surface of the optical chip 2. This application embodiment does not limit the specific type of the first electrical chip 31 and the second electrical chip 32; the first electrical chip 31 and the second electrical chip 32 can be the same type of electrical chip, or they can be different types of electrical chips. For example, the first electrical chip 31 and the second electrical chip 32 can both be driver chips; or, the first electrical chip 31 and the second electrical chip 32 can both be transimpedance amplifiers; or the first electrical chip 31 can be a driver chip, and the second electrical chip 32 can be a transimpedance amplifier.

[0126] S24. Cut the optical chip assembly and the supporting substrate along the cutting path to prepare the optoelectronic packaging structure.

[0127] Combination Figure 9 As shown in step (d).

[0128] The technical solution of this invention adopts a back-to-back method in the preparation of optoelectronic packaging structures, and then separates the two optoelectronic packaging structures after processing. This improves the preparation efficiency of optoelectronic packaging structures and can effectively solve the influence of foreign matter and dirt on the optical chip optical port during the processing of optoelectronic packaging structures.

[0129] Based on the above embodiments, Figure 11 This is a flowchart of a packaging method for a third optoelectronic packaging structure according to an embodiment of the present invention, combined with... Figure 9 and Figure 11 As shown, the encapsulation method includes:

[0130] S30. A support substrate is provided, the support substrate including a substrate body and at least one opening, the opening penetrating the substrate body.

[0131] like Figure 9 As shown in step (a).

[0132] S31. Fill the opening with at least one set of optical chipsets and at least one passive connection chip.

[0133] like Figure 9 As shown in step (b).

[0134] S32. An electrical chip is disposed on one side of the support substrate, and the electrical chip is electrically connected to the optical chip group and electrically connected to the passive connection chip.

[0135] Combination Figure 9 As shown in step (c).

[0136] S33. The optical chip assembly and support substrate are cut along the cutting path using a hidden cutting process.

[0137] Combination Figure 9 As shown in step (d).

[0138] The hidden cutting process can be a process in which a laser is focused on the optical chip group 20 and the support substrate 1 to form a continuous modified damage layer in the optical chip group 20 and the support substrate 1, and then separated along the cutting path 6 by external force stretching.

[0139] The technical solution of this invention employs a hidden cutting process to cut the optical chip group and the supporting substrate, resulting in high precision of the cutting surface and reducing the likelihood of edge chipping, contamination, and other problems. This further reduces contamination of the optical port in the optical chip group and improves the yield of the optoelectronic packaging structure.

[0140] Based on the above embodiments, Figure 12 This is a flowchart of a packaging method for a fourth optoelectronic packaging structure provided by an embodiment of the present invention. Figure 13 This is a partial structural diagram corresponding to a packaging method for another optoelectronic packaging structure provided by an embodiment of the present invention. Figure 14 This is another part of the structural diagram corresponding to the packaging method of another optoelectronic packaging structure provided by the embodiment of the present invention, combined with Figure 12 , Figure 13 and Figure 14 As shown, the encapsulation method includes:

[0141] S40. A support substrate is provided, the support substrate including a substrate body and at least one opening, the opening penetrating the substrate body.

[0142] like Figure 13 As shown in step (e).

[0143] S41. Attach a first temporary carrier to one side of the support substrate.

[0144] like Figure 13 As shown in step (f), the first temporary carrier 71 can serve as a temporary support and enhance the processing strength. The first temporary carrier 71 can be attached to one side of the support substrate 1 using a temporary adhesive film 70.

[0145] S42. Fill at least one set of optical chipsets and at least one passive connection chip into one side of the first temporary carrier and into the opening.

[0146] like Figure 13 As shown in step (g), at least one set of optical chipset 20 and at least one passive connection chip 4 are filled in the opening 12, and both the optical chipset 20 and the passive connection chip 4 are located on the side of the first temporary carrier 71 near the support substrate 1.

[0147] S43. At least one first dielectric layer is prepared on the first surface of the supporting substrate, and a first wiring structure is prepared in the first dielectric layer to obtain a first connection structure. The first wiring structure 512 is electrically connected to the passive connection chip 4 and the optical chip group 20, respectively.

[0148] like Figure 13 As shown in step (h), the first surface 01 can be the surface away from the first temporary carrier 71, that is, the side corresponding to the device surface of the optical chip 2.

[0149] The first dielectric layer 511 serves as an insulating layer. A first wiring structure 512 is patterned and fabricated within the first dielectric layer 511. The first wiring structure 512 may include a redistribution layer and a metallization layer under the bumps, serving as an electrical connection. Placing the first wiring structure 512 within the first dielectric layer 511 prevents crosstalk between electrical signals, thereby ensuring that the first wiring structure 512 enables electrical connections between the passive connection chip 4 and the electrical chip 3, as well as between the optical chip 2 and the electrical chip 3.

[0150] S44. Prepare a second temporary carrier on one side of the first connecting structure and remove the first temporary carrier.

[0151] like Figure 13 As shown in step (i), since the first surface 01 has been prepared, the first temporary carrier 71 is removed so that the second connection structure can be prepared on the side of the second surface 02 opposite to the first surface 01.

[0152] Furthermore, to avoid damage to the first connecting structure 51 during the subsequent fabrication of the second connecting structure, a second temporary carrier 72 can be fabricated on one side of the first connecting structure 51. This second temporary carrier 72 serves as temporary support, enhances processing strength, and protects the first connecting structure 51. The second temporary carrier 72 can be attached to one side of the first connecting structure 51 using a temporary adhesive film.

[0153] S45. At least one second dielectric layer is prepared on the second surface of the supporting substrate, and a second wiring structure is prepared in the second dielectric layer to obtain a second connection structure.

[0154] like Figure 14 As shown in step (j), the second wiring structure 522 is electrically connected to the passive connection chip 4 and the optical chip group 20, respectively.

[0155] The second surface 02 can be the surface opposite to the first surface 01 of the supporting substrate 1, which corresponds to the non-device surface of the optical chip 2. The second connection structure 52 serves as an electrical connection. The second dielectric layer 521 in the second connection structure 52 serves as an insulating protection layer, and the number of layers of the second dielectric layer 521 can be set according to requirements. The second wiring structure 522 may include a redistribution layer and a metallization layer under the bump, serving as an electrical connection. Placing the second wiring structure 522 in the second dielectric layer 521 prevents crosstalk between electrical signals. The second wiring structure 522 can be used to realize the electrical connection between the passive connection chip 4 and the solder connection structure 53, and the electrical connection between the optical chip 2 and the solder connection structure 53.

[0156] S46. A welding connection structure is prepared on the side of the second connection structure away from the support substrate, and the welding connection structure is electrically connected to the second wiring structure.

[0157] like Figure 14 As shown in step (k), the solder connection structure 53 can be a solder ball array (BGA) or a pad array (LGA) located on the second surface O2 of the support substrate 1. Fabricating the solder connection structure 53 on the side of the second connection structure 52 away from the support substrate 1 can be used to achieve electrical connection between the optoelectronic packaging structure and external electronic components.

[0158] S47. Remove the second temporary carrier.

[0159] like Figure 14 As shown in step (l), after the second surface 02 is prepared, the second temporary carrier 72 is removed so that the electrical chip 3 can continue to be processed on the first connection structure 51.

[0160] S48. An electrical chip is disposed on the side of the first connection structure away from the support substrate, and the electrical chip is electrically connected to the first wiring structure.

[0161] like Figure 14 As shown in step (m), before mounting the electrical chip 3, solder bumps can be pre-fabricated on the electrical chip 3 using wafer-level packaging technology. After the electrical chip 3 is prepared, the electrical chip 3 is soldered onto the metallization layer under the bumps on the side of the first connection structure 51 away from the support substrate 1 via the solder bumps.

[0162] In some embodiments, to ensure the packaging effect, resin glue can be used to fill the gaps between the electrical chip 3 and the supporting substrate 1, and between the electrical chip 3 and the optical chip 2.

[0163] S49. Cut the optical chip assembly and the supporting substrate along the cutting path to prepare the optoelectronic packaging structure.

[0164] In summary, the technical solution of the embodiments of the present invention has the following advantages:

[0165] Using passive interconnect chips embedded in the support substrate to replace the adapter board can improve the overall packaging yield of co-package and effectively reduce costs.

[0166] The support substrate adopts a back-to-back design with a two-in-one graphic opening design. During the processing, the two modules are treated as one large module and are separated only after processing is completed, which effectively solves the impact of foreign matter and dirt on the optical port of silicon photonics chip during processing.

[0167] The placement of the electrical chip has been optimized. The chip with high heat generation is no longer placed on the temperature-sensitive optical chip, but above the passive connection chip, or even on the support substrate, thus solving the problem of heat dissipation affecting the silicon photonic chip.

[0168] Placing the electrical chip and the optical chip vertically upwards can solve the problem of large planar size caused by placing them side by side;

[0169] Passive interconnect chips can be single, two-in-one, or four-in-one multi-functional devices. This approach can effectively improve the warping phenomenon caused by packaging stress.

[0170] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0171] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A photoelectric packaging structure, characterized in that, It includes a support substrate, an optical chip, at least one electrical chip, and at least one passive connection chip; The supporting substrate includes a substrate body and at least one opening, the opening penetrating the substrate body; the optical chip and the passive connection chip are disposed within the opening; The electrical chip is disposed on one side of the support substrate and is electrically connected to the optical chip and the passive connection chip, respectively. Along the stacking direction of the electrical chip and the supporting substrate, the overlap area between the electrical chip and the optical chip is S1, and the area of ​​the device surface in the optical chip is S2, wherein S1 / S2 < 50%.

2. The optoelectronic packaging structure according to claim 1, characterized in that, The electrical chip includes a first electrical chip and a second electrical chip, both of which are electrically connected to the optical chip. The device surface includes a first side, a second side, and a third side connecting the first side and the second side, which are disposed opposite to each other. Along the stacking direction of the electrical chip and the supporting substrate, the first electrical chip overlaps with the first side, and the second electrical chip overlaps with the second side; the optical port of the optical chip is disposed at the third side.

3. The optoelectronic packaging structure according to claim 1, characterized in that, The passive connection chip is electrically connected to at least one of the electrical chips.

4. The optoelectronic packaging structure according to claim 1, characterized in that, The optical chip and the passive connection chip are disposed in the same opening; Alternatively, the support substrate may include a plurality of openings, with the optical chip and the passive connection chip disposed in different openings.

5. The optoelectronic packaging structure according to claim 1, characterized in that, The optoelectronic packaging structure further includes a first connection structure, a second connection structure, and a welding connection structure; The first connection structure is located on the first surface of the supporting substrate. The first connection structure includes at least one first dielectric layer and a first wiring structure located in the first dielectric layer. The first wiring structure electrically connects the passive connection chip and the electrical chip, and electrically connects the optical chip and the electrical chip. The second connection structure is located on the second surface of the supporting substrate, and the second surface is disposed opposite to the first surface; the second connection structure includes at least one second dielectric layer and a second wiring structure located in the second dielectric layer, the second wiring structure electrically connecting the passive connection chip and the welding connection structure and electrically connecting the optical chip and the welding connection structure.

6. The optoelectronic packaging structure according to claim 1, characterized in that, The passive interconnect chip includes a glass through-hole interconnect chip or a silicon through-hole interconnect chip.

7. A packaging method for an optoelectronic packaging structure, characterized in that, include: A support substrate is provided, the support substrate including a substrate body and at least one opening, the opening penetrating the substrate body; The opening is filled with at least one set of optical chips and at least one passive connection chip; the optical chip set includes a first optical chip and a second optical chip and a dicing channel located between the first optical chip and the second optical chip; the optical ports of the first optical chip and the second optical chip are respectively located on both sides of the dicing channel; An electrical chip is disposed on one side of the supporting substrate, and is electrically connected to the optical chip group and electrically connected to the passive connection chip; along the stacking direction of the electrical chip and the supporting substrate, the overlap area between the electrical chip and the optical chip group is S1, and the area of ​​the device surface in the optical chip group is S2, wherein S1 / S2 < 50%; The optical chip assembly and the supporting substrate are cut along the cutting path to prepare an optoelectronic packaging structure.

8. The packaging method according to claim 7, characterized in that, The electrical chip includes a first electrical chip and a second electrical chip; The device surface includes a first side and a second side disposed opposite to each other; An electrical chip is disposed on one side of the support substrate, and the electrical chip is electrically connected to the optical chip group, comprising: The first electrical chip is disposed on one side of the first optical chip and electrically connected to the first optical chip; the second electrical chip is disposed on one side of the second optical chip and electrically connected to the first optical chip. The first electrical chip is disposed on one side of the first side of the second optical chip and electrically connected to the second optical chip, and the second electrical chip is disposed on one side of the second optical chip and electrically connected to the second optical chip.

9. The packaging method according to claim 7, characterized in that, Cutting the optical chip assembly and the supporting substrate along the cutting path includes: The optical chip assembly and the supporting substrate are cut along the cutting path using a hidden cutting process.

10. The packaging method according to claim 7, characterized in that, The opening is filled with at least one set of optical chipsets and at least one passive connection chip, including: A first temporary carrier is attached to one side of the support substrate; At least one set of optical chipsets and at least one passive connection chip are filled on one side of the first temporary carrier and in the opening. Before the electrical chip is disposed on one side of the support substrate, and before the electrical chip is electrically connected to the optical chip group and the passive connection chip electrically connected to the electrical chip, the method further includes: At least one first dielectric layer is formed on the first surface of the supporting substrate, and a first wiring structure is formed in the first dielectric layer to obtain a first connection structure; the first wiring structure is electrically connected to the passive connection chip and the optical chip assembly, respectively. A second temporary carrier is prepared on one side of the first connecting structure, and the first temporary carrier is removed; At least one second dielectric layer is formed on the second surface of the supporting substrate, and a second wiring structure is formed in the second dielectric layer to obtain a second connection structure; the second wiring structure is electrically connected to the passive connection chip and the optical chip assembly, respectively. A welding connection structure is prepared on the side of the second connection structure away from the supporting substrate, and the welding connection structure is electrically connected to the second wiring structure; Remove the second temporary carrier; An electrical chip is disposed on one side of the support substrate, and the electrical chip is electrically connected to the optical chip group and the passive connection chip is electrically connected to the electrical chip, comprising: An electrical chip is disposed on the side of the first connection structure away from the supporting substrate, and the electrical chip is electrically connected to the first wiring structure.

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