Storage device, method of operating a storage device, and storage system comprising the same

Abstract

A storage device includes a nonvolatile storage device and a storage controller configured to control the nonvolatile storage device. The storage controller includes a receiver configured to receive a reception signal from an external device through a first signal line, a temperature sensor configured to sense a temperature of the storage device and output temperature information, and a receiver control logic configured to adjust a setting value of the receiver based on the temperature information.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0182745, filed on December 10, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Some example embodiments relate to semiconductor memories, and more specifically, to a storage device, a method of operating the storage device, and / or a storage system including the storage device. Background Technology

[0003] Semiconductor memories are classified as volatile memories, meaning the data stored in them is lost when the power is turned off, such as static random access memory (SRAM) or dynamic random access memory (DRAM). Semiconductor memories can also be classified as non-volatile memories, meaning the data stored in them is retained even when the power is off, such as flash memory, phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), or ferroelectric random access memory (FRAM).

[0004] Flash memory is widely used as a high-capacity storage medium. Storage devices that include flash memory operate under the control of a host. The storage device and the host communicate with each other through various interfaces. As an example, the storage device and the host can communicate based on NVMe (Fast Non-Volatile Memory), which is based on PCIe (Fast Peripheral Component Interconnect). PCIe provides high-speed serial communication. The storage device and the host communicate with each other based on the specifications defined in the PCIe or NVMe standards. The operating temperature of a storage device can increase depending on its various operating environments. In such cases, the communication quality between the storage device and the host may degrade. Summary of the Invention

[0005] Some example embodiments can provide storage devices with improved reliability and / or improved performance by adjusting the settings of the receivers included in the storage device according to the temperature of the storage device, the operating method of the storage device, and / or the storage system including the storage device.

[0006] According to some example embodiments, a storage device includes: a non-volatile storage device; and a storage controller configured to control the non-volatile storage device. The storage controller includes: a receiver configured to receive a received signal from an external device via a first signal line; a temperature sensor configured to sense the temperature of the storage device and output temperature information; and receiver control logic configured to adjust a setpoint received by the receiver to an adjusted setpoint based on the temperature information.

[0007] Alternatively or additionally, a method of operating a storage device includes: setting a receiver to receive a received signal from an external device via a first signal line using default settings; monitoring the temperature of the storage device; and adjusting the receiver settings in response to the temperature of the storage device being greater than or equal to a reference value.

[0008] Alternatively or additionally, according to some example embodiments, a storage device includes: a non-volatile storage device; and a storage controller configured to control the non-volatile storage device. The storage controller is configured to configure a receiver using default settings upon initialization with an external device, the receiver being configured to receive a received signal from the external device. In response to the storage device's temperature exceeding a reference temperature, the storage controller is configured to reconfigure the receiver based on a first setpoint corresponding to the storage device's temperature.

[0009] Alternatively or additionally, according to some example embodiments, a storage system includes: a host device; a first storage device including a first receiver configured to receive a first transmitted signal from the host device via a first signal line; and a second storage device including a second receiver configured to receive a second transmitted signal from the host device via a second signal line. In response to a first temperature of the first storage device exceeding a reference temperature, the host device is configured to perform a first link retraining on the first storage device, the first link retraining adjusting a first setpoint of the first receiver. In response to a second temperature of the second storage device exceeding a reference temperature, the host device is configured to perform a second link retraining on the second storage device, the second link retraining adjusting a second setpoint of the second receiver. Attached Figure Description

[0010] The above and other objects and features of the present invention will become clearer by referring to the accompanying drawings and describing in detail some exemplary embodiments of the present invention.

[0011] Figure 1 This is a block diagram illustrating a system according to some example embodiments.

[0012] Figure 2 It is used to describe Figure 1 The diagram of the zeroth and first physical layers in the diagram.

[0013] Figure 3 It is used to describe Figure 2 The curve of the first receiver in the image based on the characteristics of temperature change.

[0014] Figure 4 It shows Figure 1 A flowchart of the operation of the storage device in the process.

[0015] Figure 5 It specifically shows Figure 2 A block diagram of the first receiver in the system.

[0016] Figure 6 It is used to describe Figure 5 A diagram illustrating the operation of the receiver control logic.

[0017] Figure 7 It shows Figure 1 A flowchart of the operation of the storage device in the process.

[0018] Figure 8 It is used to describe Figure 7 The diagram shows operation S230.

[0019] Figure 9 It shows Figure 1 A flowchart of the operation of the storage device in the process.

[0020] Figure 10 It shows Figure 1 A flowchart of the operation of the storage device in the process.

[0021] Figure 11 and Figure 12 It is used to describe Figure 2 A diagram illustrating the operation of the receiver control logic.

[0022] Figure 13 This is a block diagram illustrating a system according to some example embodiments.

[0023] Figure 14 It shows Figure 13 The flowchart of the host's operation.

[0024] Figure 15 It shows Figure 13 A diagram showing the hierarchical structure of host and storage devices.

[0025] Figure 16 It shows Figure 13 The flowchart shows the link retraining operation between the host and storage devices.

[0026] Figure 17 It is used to describe Figure 16 A diagram of the operations in stage 2.

[0027] Figure 18 This is a block diagram illustrating a system according to some example embodiments.

[0028] Figure 19 This is a block diagram illustrating a system according to some example embodiments.

[0029] Figure 20This is a block diagram illustrating a host-storage system according to some example embodiments.

[0030] Figure 21 This is a diagram illustrating a data center with application storage devices according to some example embodiments.

[0031] Figure 22 This is a block diagram illustrating an electronic system according to some example embodiments. Detailed Implementation

[0032] Below, some exemplary embodiments will be described in detail and clearly to enable those skilled in the art to readily implement this disclosure.

[0033] Figure 1 This is a block diagram illustrating a system according to some example embodiments. (Refer to...) Figure 1 System 100 may include host 110 and storage device 120. In some example embodiments, system 100 may include at least one of various information processing devices, such as personal computers, laptops, servers, workstations, smartphones, and tablets. Alternatively or additionally, system 100 may be or may include one or more systems included in automotive equipment, such as navigation systems, black boxes (e.g., black box flight recorders, such as flight data recorders and / or cockpit voice recorders), or automotive electronics, and / or include high-capacity storage media included in automotive equipment. Alternatively or additionally, system 1000 may be or may include, or may be included in, a data center or a storage server or application server included in a data center configured to store and manage various data.

[0034] Host 110 can be configured to control storage device 120. For example, host 110 can store data in storage device 120 and / or can read data stored in storage device 120.

[0035] Storage device 120 can operate under the control of host 110. For example, storage device 120 may include storage controller 121 and multiple non-volatile memories 122. Storage controller 121 can store data in the multiple non-volatile memories 122 under the control of host 110. Alternatively or additionally, under the control of host 110, storage controller 121 can read data stored in the multiple non-volatile memories 122 and send the read data to host 110.

[0036] In some example embodiments, the storage controller 121 can communicate with or control multiple non-volatile memories 122 via multiple channels CH1 to CHn. In some example embodiments, each of the multiple non-volatile memories 122 may be or may include NAND flash memory, but the example embodiments are not limited thereto.

[0037] In some example embodiments, each of the plurality of nonvolatile memories 122 may have the same electrical and / or physical characteristics, such as, but not limited to, size, operating speed, and storage capacity; however, the example embodiments are not limited thereto. In some example embodiments, at least one of the plurality of nonvolatile memories 122 may have different physical and / or electrical characteristics from at least another nonvolatile memory in the plurality of nonvolatile memories 122.

[0038] In some example embodiments, host 110 and storage device 120 may communicate with each other based on an interface protocol, such as a dynamically determined (or alternative, preset) interface protocol. In some example embodiments, the interface protocol may include an NVMe (Fast Non-Volatile Memory) interface, but the example embodiments are not limited thereto. In some example embodiments, the NVMe interface may provide communication based on a physical layer compliant with the PCIe (Fast Peripheral Component Interconnect) protocol. For example, host 110 may include a zero-layer PHY0, and the storage controller 121 of storage device 120 may include a first-layer PHY1. The zero-layer PHY0 and the first-layer PHY1 may be physically connected to each other via a communication link. Each of the zero-layer PHY0 and the first-layer PHY1 may be configured to provide high-speed serial communication. In some example embodiments, each of the zero-layer PHY0 and the first-layer PHY1 may include a transmitter and a receiver. The transmitter of the zero-layer PHY0 may send signals to the receiver of the first-layer PHY1, and the transmitter of the first-layer PHY1 may send signals to the receiver of the zero-layer PHY0.

[0039] In some example embodiments, the zero-layer PHY0 and the first-layer PHY1 can achieve an improved or optimized communication environment through initialization operations. For example, the zero-layer PHY0 and the first-layer PHY1 can perform link equalization (EQ) and link training as defined in the PCIe standard. Link equalization (EQ) and link training can improve the quality of signals exchanged between the zero-layer PHY0 and the first-layer PHY1.

[0040] In some example embodiments, the link equalization EQ and link training described above are performed on storage device 120 during initialization operations. For example, link equalization EQ and link training are performed at a specific temperature (e.g., room temperature). This may indicate that the zeroth physical layer PHY0 and the first physical layer PHY1 are improved or optimized at a specific temperature (e.g., room temperature). After the initialization of storage device 120, the temperature of storage device 120 may vary depending on various factors (e.g., the operation of storage device 120 and / or temperature variations according to the cooling methods included in system 100). When the temperature of storage device 120 changes, the operating characteristics of the receivers included in the first physical layer PHY1 of storage device 120 may change. In this case, the margin (e.g., data eye) of the signal received by the receivers of the first physical layer PHY1 may decrease. Based on the above description, the signal quality and / or signal reliability of the signal received by storage device 120 may decrease.

[0041] According to some example embodiments, the storage device 120 can control the operating characteristics of the receiver included in the first physical layer PHY1 based on temperature changes of the storage device 120. For example, the storage controller 121 of the storage device 120 may include a temperature sensor 121a and receiver control logic 121b. The temperature sensor 121a may be configured to sense the temperature of the storage device 120 and output temperature information TEMP corresponding to the sensed temperature. For convenience, the example is described using the temperature sensor 121a sensing the temperature of the storage device 120, but the example embodiments are not limited thereto. For example, the temperature sensor 121a may be configured to sense the temperature of at least one of the storage controller 121 and the non-volatile memory 122. For example, the temperature of the storage device 120 may include the temperature of at least one of the storage controller 121 and the non-volatile memory 122.

[0042] Receiver control logic 121b can receive temperature information TEMP from temperature sensor 121a. Receiver control logic 121b can determine whether the temperature of storage device 120 has changed based on the temperature information TEMP. When the temperature of storage device 120 changes and / or when the temperature of storage device 120 exceeds a specific range (e.g., room temperature range), receiver control logic 121b can control the setpoint of the receiver included in the first physical layer PHY1. In some example embodiments, the receiver setpoint may include the amplification gain value of the amplifier included in the receiver. In this case, even if the temperature of storage device 120 changes, the effective margin of the receiver included in the first physical layer PHY1 can be ensured.

[0043] As described above, according to some example embodiments, storage device 120 can ensure, or more likely ensure, the effective margin of the receiver by controlling the settings of the receiver included in the first physical layer PHY1. The configuration and operation of storage device 120 according to some example embodiments will now be described in detail with reference to the accompanying drawings.

[0044] Figure 2 It is used to describe Figure 1 The diagram shows the zeroth physical layer PHY0 and the first physical layer PHY1. For ease of description, components that do not require description of the zeroth physical layer PHY0 and the first physical layer PHY1 are omitted.

[0045] Reference Figure 1 and Figure 2 The host 110 may include a zeroth physical layer PHY0, and the storage controller 121 of the storage device 120 may include a first physical layer PHY1. The zeroth physical layer PHY0 may include a zeroth serializer SER0, a zeroth transmitter TX0, a zeroth receiver RX0, and a zeroth deserializer DES0. The first physical layer PHY1 may include a first receiver RX1, a first deserializer DES1, a first serializer SER1, and a first transmitter TX1.

[0046] Host 110 can send the a-th data DTa to storage device 120. For example, the zeroth serializer SER0 of host 110 can be configured to serialize the a-th data DTa to output the a-th serialized data DTa_SER. The zeroth transmitter TX0 can output the a-th transmit signal SIG_TXa to the first signal line SIGL1 based on the a-th serialized data DTa_SER. The first signal line SIGL1 can be connected to the first receiver RX1. For simplicity of drawing and ease of description, an embodiment with one first signal line SIGL1 is shown, but the example embodiment is not limited thereto. For example, the zeroth transmitter TX0 and the first receiver RX1 can operate based on differential signaling; in this case, the zeroth transmitter TX0 and the first receiver RX1 can be connected to each other via two signal lines.

[0047] The first receiver RX1 can receive the a-th received signal SIG_RXa via the first signal line SIGL1. In some example embodiments, the a-th received signal SIG_RXa may correspond to the sum of the a-th transmitted signal SIG_TXa and the noise caused by the first signal line SIGL1. The first receiver RX1 can sample the a-th received signal SIG_RXa to output the a-th serialized data DTa_SER. The first deserializer DES1 can deserialize the a-th serialized data DTa_SER to output the a-th data Dta. Through the above operations, the host 110 can send the a-th data DTa to the storage device 120.

[0048] Storage device 120 can send the b-th data DTb to host 110. For example, the first serializer SER1 of storage device 120 can be configured to serialize the b-th data DTb to output the b-th serialized data DTb_SER. The first transmitter TX1 can output the b-th transmit signal SIG_TXb to the second signal line SIGL2 based on the b-th serialized data DTb_SER. The second signal line SIGL2 can be connected to the second receiver RX2. For the sake of simplicity and ease of description, an example embodiment with one second signal line SIGL2 is shown, but the example embodiment is not limited thereto. For example, the first transmitter TX1 and the zeroth receiver RX0 can operate based on differential signaling; in this case, the first transmitter TX1 and the zeroth receiver RX0 can be connected to each other via two signal lines.

[0049] The zeroth receiver RX0 can receive the b-th received signal SIG_RXb via the second signal line SIGL2. In some example embodiments, the b-th received signal SIG_RXb may correspond to the sum of the b-th transmitted signal SIG_TXb and the noise caused by the second signal line SIGL2. The zeroth receiver RX0 can sample the b-th received signal SIG_RXb to output the b-th serialized data DTb_SER. The second deserializer DES2 can deserialize the b-th serialized data DTb_SER to output the b-th data DTb. Through the above operations, the storage device 120 can send the b-th data DTb to the host 110.

[0050] In some example embodiments, the zeroth transmitter TX0 and the first transmitter TX1, as well as the zeroth receiver RX0 and the first receiver RX1 included in the zeroth physical layer PHY0 and the first physical layer PHY1, may include equalizers for eliminating or canceling noise caused by the first signal line SIGL1 and the second signal line SIGL2. For example, the zeroth transmitter TX0 may include a feedforward equalizer (FFE), and the first receiver RX1 may include a continuous-time linear equalizer (CTLE) and / or a decision feedback equalizer (DFE). The a-th serialized data DTa_SER can be normally sampled from the a-th received signal SIG_RXa through the feedforward equalizer, the continuous-time linear equalizer, and the decision feedback equalizer of the zeroth transmitter TX0 and the first receiver RX1.

[0051] In some example embodiments, it can be seen by referring to Figure 1The described link equalization (EQ) and link training are used to configure the settings of the feedforward equalizer, continuous-time linear equalizer, and decision feedback equalizer for the zeroth transmitter TX0 and the first receiver RX1. In this case, as described above, when the temperature of the storage device 120 changes, one or more operating characteristics of the first receiver RX1 may change, making it difficult or impossible to properly sample the a-th serialized data DTa_SER from the a-th received signal SIG_RXa.

[0052] Receiver control logic 121b can receive temperature information TEMP from temperature sensor 121a and determine whether the temperature of storage device 120 has changed based on the received temperature information TEMP. When the temperature of storage device 120 changes, receiver control logic 121b can control the setpoint of first receiver RX1. In some examples, receiver control logic 121b can control the amplification gain associated with the continuous-time linear equalizer included in first receiver RX1. Alternatively or additionally, receiver control logic 121b can control the setpoints of the continuous-time linear equalizer and the decision feedback equalizer included in first receiver RX1. In this case, even if the temperature of storage device 120 changes, the effective margin of first receiver RX1 can be ensured.

[0053] Figure 3 It is used to describe Figure 2 A graph showing the characteristics of the first receiver in the circuit based on temperature changes. Figure 3 In the diagram, the horizontal axis represents the temperature of the storage device 120, and the vertical axis represents the height of the data eye of the signal input to the first receiver RX1. In some example embodiments, the height of the data eye may indicate the signal margin or effective margin.

[0054] Figure 3 The graph illustrates the operating characteristics of the first receiver RX1 with default settings. The default settings may indicate the settings configured in the first receiver RX1 during the initialization operation of the storage device 120 via link equalization (EQ) and link training. For example, the default settings may indicate the settings at which the first receiver RX1 operates in good or optimal condition at a specific temperature (e.g., room temperature).

[0055] like Figure 3As shown, as the temperature of the storage device 120 increases, the height of the data eye of the signal received by the first receiver RX1 can decrease. For example, at a first temperature T1, the data eye of the signal received by the first receiver RX1 can have a first height HT1. Conversely, at a second temperature T2, which is higher than the first temperature T1, the data eye of the signal received by the first receiver RX1 can have a second height HT2, which is lower than the first height HT1. This indicates that the operating characteristics of the first receiver RX1 deteriorate as the temperature of the storage device 120 increases. In other words, as the temperature of the storage device 120 increases, the error of the signal or data sampled by the first receiver RX1 may increase.

[0056] Figure 4 It shows Figure 1 A flowchart of the operation of the storage device is provided. For ease of description of embodiments of this disclosure, the operation and components of the first receiver RX1 of the storage device 120 will be described primarily below. However, the exemplary embodiments are not limited thereto.

[0057] Reference Figures 1 to 4 In operation S100, the storage device 120 can be powered on and can perform initialization operations, for example, by executing instructions in the firmware stored on the storage device 120. Through the initialization operation, the storage device 120 can configure the first receiver RX1 based on default settings. For example, during the initialization operation of the storage device 120, link balancing (EQ) and link training of the first physical layer PHY1 can be performed. Through link balancing (EQ) and link training, the storage device 120 can configure the first receiver RX1 based on default settings. For example, the various components of the first receiver RX1 can be set or configured using default settings. Afterwards and / or at least partially simultaneously, the host 110 and the storage device 120 can perform normal operations. For example, the host 110 and the storage device 120 can communicate with each other through the zero physical layer PHY0 and the first physical layer PHY1.

[0058] During operation S110, the storage device 120 can monitor the temperature. For example, a temperature sensor 121a included in the storage controller 121 of the storage device 120 can measure the temperature of the storage device 120.

[0059] In operation S120, storage device 120 can determine whether the measured temperature has changed. For example, receiver control logic 121b included in the storage controller 121 of storage device 120 can receive temperature information TEMP from temperature sensor 121a. Receiver control logic 121b can determine whether the current temperature of storage device 120 has changed based on the temperature information TEMP. In some example embodiments, receiver control logic 121b can determine whether the current temperature of storage device 120 is higher than or equal to a reference temperature. Alternatively or additionally, receiver control logic 121b can determine whether a temperature range including the current temperature has changed.

[0060] When the temperature of the storage device 120 does not change or does not change significantly, the storage device 120 continues to perform operation S110.

[0061] When the temperature of storage device 120 changes or changes significantly, in operation S130, storage device 120 can adjust the amplification gain of the first receiver RX1 based on the current temperature. In some example embodiments, storage device 120 can reconfigure the first receiver RX1 based on a set value corresponding to the current temperature. For example, the first receiver RX1 may include a continuous-time linear equalizer. Receiver control logic 121b can adjust the amplification gain of the continuous-time linear equalizer of the first receiver RX1 based on the current temperature. As the amplification gain of the continuous-time linear equalizer is adjusted, the effective margin or the height of the data eye of the first receiver RX1 can be increased.

[0062] Figure 5 It shows Figure 2 A block diagram of the first receiver in the system. Figure 6 It is used to describe Figure 5 A diagram illustrating the operation of the receiver control logic. In some example embodiments, Figure 5 The first receiver RX1 in the example is provided only as an example, and the example embodiment is not limited thereto.

[0063] Reference Figure 2 , Figure 5 and Figure 6 The first receiver RX1 may include a continuous-time linear equalizer CTLE, a variable gain amplifier VGA, and a decision feedback equalizer DFE.

[0064] The continuous-time linear equalizer (CTLE) can receive the a-th received signal SIG_RXa via the first signal line SIGL1. The CTLE can operate as a high-pass filter associated with the a-th received signal SIG_RXa. The CTLE can be configured to allow high-frequency components of the a-th received signal SIG_RXa to pass through while blocking low-frequency noise caused by the first signal line SIGL1.

[0065] A variable gain amplifier (VGA) can be configured to amplify the output of a continuous-time linear equalizer (CTLE). In some example embodiments, the VGA can amplify the output of the CTLE based on a preset amplification gain.

[0066] A decision feedback equalizer (DFE) can sample the output of a variable gain amplifier (VGA) to output the a-th serialized data, DTa_SER. For example, a DFE can add the levels corresponding to the previous and current signals to output the data for the current signal.

[0067] A decision feedback equalizer (DFE) may include an adder (SUM), a limiter (SL), and multiple delay units (DL1 to DLn). The limiter (SL) samples the output of the variable gain amplifier (VGA) to output the output signal (OUT). For example, the limiter (SL) can compare the output of the VGA with a reference voltage. When the output of the VGA is higher than or exceeds the reference voltage, the limiter (SL) can output a logic high signal as the output signal (OUT); when the output of the VGA is lower than the reference voltage, the limiter (SL) can output a logic low signal as the output signal (OUT).

[0068] Multiple delay units DL1 to DLn can be configured to sequentially delay the output signal OUT. For example, multiple delay units DL1 to DLn can be connected in a cascaded manner. The first delay unit DL1 can delay the output signal OUT for a preset time (e.g., one data cycle). The second delay unit DL2 can delay the output of the first delay unit DL1 for a preset time. The nth delay unit DLn can delay the output of the delay units preceding the nth delay unit DLn for a preset time.

[0069] Multiple weights α1 to αn can be applied to the outputs of multiple delay units DL1 to DLn. For example, a first weight α1 can be applied to the output of a first delay unit DL1. A second weight α2 can be applied to the output of a second delay unit DL2. An nth weight αn can be applied to the output of an nth delay unit DLn. Each of the multiple weights α1 to αn can be a real number; however, the example embodiment is not limited thereto. Each of the multiple weights α1 to αn can be the same as each other, or at least one weight can be different from the other weights. Each of the multiple weights α1 to αn can be positive; however, the example embodiment is not limited thereto.

[0070] The adder SUM adds signals weighted from α1 to αn. The output of the adder SUM is provided to the limiter SL. The limiter SL compares the input signal with a reference voltage to output the output signal OUT.

[0071] As described above, a decision feedback equalizer (DFE) can generate an output signal OUT by applying information corresponding to previous data values ​​of the input signal to the current data value. In this case, inter-symbol interference (ISI) of the input signal can be eliminated.

[0072] In some example embodiments, the decision feedback equalizer (DFE) may be or may include an n-tap decision feedback equalizer. However, the example embodiments are not limited thereto. For example, the number of taps in the decision feedback equalizer (DFE) can be varied or modified, and therefore, the number of delay units can also vary.

[0073] The output signal OUT of the decision feedback equalizer DFE can be provided to the first deserializer DES1 as the a-th serialized data DTa_SER. The first deserializer DES1 can deserialize the a-th serialized data DTa_SER to output the a-th data Dta.

[0074] In some exemplary embodiments, the amplification gain G_amp of the variable gain amplifier VGA can be set to a set value, such as, but not limited to, a preset set value and / or a good value (such as, but not limited to, an optimal value), at a link equalization EQ or link training time point through the link equalization EQ and link training of the storage device 120. In this case, the operating characteristics of the components of the first receiver RX1 may change when the temperature of the storage device 120 changes and / or when the temperature of the storage device 120 increases. For example, the signal quality (e.g., the height of the data eye) of the signal output from the variable gain amplifier VGA may degrade.

[0075] In this scenario, receiver control logic 121b can adjust the amplification gain G_amp of the variable gain amplifier VGA based on the current temperature of the storage device 120. As an example, such as... Figure 6 As shown, when the current temperature of storage device 120 is within the first temperature range TEMP_RG1, receiver control logic 121b can adjust the variable gain amplifier VGA to the first amplification gain G_amp1. Alternatively, when the current temperature of storage device 120 is within the second temperature range TEMP_RG2 (which may or may not overlap with the first temperature range TEMP_RG1), receiver control logic 121b can adjust the variable gain amplifier VGA to the second amplification gain G_amp2. Alternatively, when the current temperature of storage device 120 is within the m-th temperature range TEMP_RGm, receiver control logic 121b can adjust the variable gain amplifier VGA to the m-th amplification gain G_ampm. In some example embodiments, the second temperature range TEMP_RG2 may be higher than the first temperature range TEMP_RG1 (e.g., the lower end of the second temperature range TEMP_RG2 may be greater than or equal to the higher end of the first temperature range TEMP_RG1), and the second amplification gain G_amp2 may be greater than the first amplification gain G_amp1. For example, as the temperature of storage device 120 increases, receiver control logic 121b can increase the amplification gain G_amp of the variable gain amplifier VGA included in the first receiver RX1.

[0076] In some example embodiments, the good or optimal amplification gain of the variable gain amplifier VGA can vary depending on the temperature of the storage device 120 or the temperature of the first receiver RX1. For example, at room temperature, the first amplification gain G_amp1 may be the optimal amplification gain of the variable gain amplifier VGA. At a first temperature above room temperature, a second amplification gain G_amp2 higher than the first amplification gain G_amp1 may be the optimal amplification gain of the variable gain amplifier VGA. At room temperature, when the variable gain amplifier VGA is set to have the second amplification gain G_amp2, the output signal of the variable gain amplifier VGA can swing over a relatively wide range. In this case, when the output signal of the variable gain amplifier VGA transitions from a high level to a low level or from a low level to a high level, the output signal may not swing normally. In this case, even if the amplification gain increases, the eye level of the data may become relatively low.

[0077] For example, the good or optimal amplification gain of the variable gain amplifier VGA may vary depending on the temperature of the storage device 120, and the receiver control logic 121b can control the amplification gain of the variable gain amplifier VGA based on the temperature of the storage device 120.

[0078] In some example embodiments, the continuous-time linear equalizer (CTLE) and variable-gain amplifier (VGA) of the first receiver RX1 can constitute the analog front-end (AFE) of the first receiver RX1, and the decision feedback equalizer (DFE) of the first receiver RX1 can be the digital circuitry of the first receiver RX1. The receiver control logic 121b can control the analog front-end (AFE) of the first receiver RX1 based on the temperature of the storage device 120.

[0079] exist Figure 5 and Figure 6 In some of the example embodiments shown, receiver control logic 121b is described as selecting amplification gain based on a temperature range, including the temperature of storage device 120, but the example embodiments are not limited thereto. For example, receiver control logic 121b may set the amplification gain G_amp to be linearly proportional to the temperature of storage device 120.

[0080] Figure 7 It shows Figure 1 A flowchart of the operation of the storage device in the process. Figure 8 It is used to describe Figure 7 The diagram illustrates operation S230. For ease of description, additional descriptions associated with the aforementioned components will be omitted to avoid redundancy. See also... Figure 1 , Figure 2 , Figure 7 and Figure 8 The storage device 120 can execute operations S200, S210, and S220. Operations S200, S210, and S220 are related to... Figure 4 Operations S100, S110, and S120 are similar, and therefore, additional descriptions will be omitted to avoid redundancy.

[0081] When the temperature of the storage device 120 changes, in operation S230, the storage device 120 can search for a good or optimal amplification gain of the first receiver RX1. For example, operation S230 may include operations S231 to S236.

[0082] In operation S231, the variable "k" is set to 1. In some example embodiments, the variable "k" is used to describe the iterative operation, for example, as a dummy counter used to search for a good or optimal amplification gain of the storage device 120, and should not be interpreted as having any other technical meaning.

[0083] In operation S232, the storage device 120 can adjust the first receiver RX1 based on the k-th amplification gain. For example, as... Figure 8As shown, the first receiver RX1 may include a continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), and a decision feedback equalizer (DFE). The configuration and operation of the CTLE, VGA, and DFE have been described in reference to... Figure 5 The description has been provided, and therefore, additional descriptions will be omitted to avoid redundancy. Receiver control logic 121b-1 can control the amplification gain G_amp of the variable gain amplifier VGA. In this case, receiver control logic 121b-1 can adjust the variable gain amplifier VGA based on the k-th amplification gain.

[0084] In operation S233, storage device 120 can check the signal margin based on the output signal of the first receiver RX1. For example, receiver control logic 121b-1 can receive the output signal SIG_vga of a variable gain amplifier VGA set to the k-th amplification gain. Receiver control logic 121b-1 can check the signal margin of the output signal SIG_vga. In some example embodiments, the signal margin can indicate the eye level or amplitude of the output signal SIG_vga.

[0085] In operation S234, storage device 120 can determine whether variable "k" is at its maximum value. For example, receiver control logic 121b-1 can determine whether all configurable amplification gains are applied to the variable gain amplifier VGA.

[0086] When the variable "k" is not at its maximum value, in operation S235, the variable "k" is incremented by "1". Afterwards, storage device 120 iteratively executes operations S231 to S234.

[0087] When the variable "k" is at its maximum value (i.e., when all amplification gains are applied), in operation S236, the storage device 120 can determine a good or optimal amplification gain based on the checked margin. For example, the receiver control logic 121b-1 can select the amplification gain corresponding to the good or optimal margin from the checked margin as the good or optimal amplification gain.

[0088] In operation S240, storage device 120 can adjust the first receiver RX1 based on optimal amplification gain. For example, receiver control logic 121b-1 can apply good or optimal amplification gain to the variable gain amplifier VGA.

[0089] As described above, receiver control logic 121b-1 can apply multiple amplification gains to the variable gain amplifier VGA and can check the margins corresponding to the amplification gains respectively. Receiver control logic 121b-1 can select the optimal amplification gain corresponding to the optimal margin.

[0090] Figure 9 It shows Figure 1 A flowchart illustrating the operation of storage devices. (Refer to...) Figure 1 and Figure 9 In operation S300, the storage device 120 may adjust the setpoint (e.g., amplification gain) of the first receiver RX1 based on the temperature of the storage device 120. In some example embodiments, operation S300 may include adjusting the setpoint (e.g., amplification gain) based on a reference. Figures 1 to 8 The described operation involves adjusting the amplification gain of the first receiver RX1 based on the temperature of the storage device 120.

[0091] In operation S310, the storage device 120 can check for errors in the first receiver RX1. For example, as... Figure 8 As shown, receiver control logic 121b-1 can adjust the amplification gain of the variable gain amplifier VGA and can check the output signal SIG_vga of the variable gain amplifier VGA. Receiver control logic 121b-1 can detect errors in the output signal SIG_vga (e.g., lack of effective margin).

[0092] When an error is detected in the first receiver RX1, in operation S320, the storage device 120 can change the setting value of the first receiver RX1. For example, when an error is detected in the first receiver RX1, the receiver control logic 121b-1 can control the setting values ​​of the various components included in the first receiver RX1. For example, the receiver control logic 121b can adjust the setting value of the continuous-time linear equalizer CTLE of the first receiver RX1. Alternatively or additionally, the receiver control logic 121b-1 can adjust the setting value of the decision feedback equalizer DFE.

[0093] As described above, after fully adjusting the amplification gain of the variable gain amplifier VGA by operating S300, the effective margin of the first receiver RX1 may not be guaranteed. In this case, the receiver control logic 121b-1 can recover the first receiver RX1 from its error by changing the setting value of the first receiver RX1.

[0094] Figure 10 It shows Figure 1 A flowchart illustrating the operation of storage devices. (Refer to...) Figure 1 , Figure 2 and Figure 10 In operation S400, storage device 120 can initiate a reset operation (or restart operation). For example, storage device 120 can initiate a reset operation under the control of host 110.

[0095] In operation S410, storage device 120 can determine the reset type. For example, storage device 120 can perform a hot reset or a cold reset. A hot reset can indicate a reset operation performed in response to an explicit reset request received from host 110 via a communication link. A cold reset can indicate a reset operation performed when system 100 is powered on again after a power outage and / or when a sudden power outage event occurs.

[0096] When the reset type corresponds to a warm reset, in operation S421, the storage device 120 can store information about the current amplification gain G_amp in the non-volatile memory 122. When the reset type corresponds to a cold reset, in operation S422, the storage device 120 can clear the information about the current amplification gain G_amp.

[0097] In operation S430, storage device 120 can perform a reset operation and then be powered on.

[0098] In the case of a hot reset, during operation S441, the storage device 120 can configure the first receiver RX1 based on the amplification gain G_amp stored in the non-volatile memory 122. In the case of a cold reset, during operation S442, the storage device 120 can configure the first receiver RX1 based on the default settings.

[0099] In some example embodiments, in the case of a hot reset, the storage device 120 is more likely to maintain its temperature because the reset operation is performed within a short period of time. Accordingly, the reliability of the first receiver RX1 can be improved by setting it based on a preset amplification gain G_amp. Conversely, in the case of a cold reset, the storage device 120 is more likely to experience a temperature drop because the timing of the reset operation is not specified. Accordingly, the reliability of the first receiver RX1 can be improved by setting it based on a default setting.

[0100] Figure 11 and Figure 12 It is used to describe Figure 2 A diagram illustrating the operation of the receiver control logic is provided. For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy. See also... Figure 2 , Figure 11 and Figure 12 The first receiver RX1 may include a continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), and a decision feedback equalizer (DFE). The operation of the CTLE, VGA, and DFE has been described in detail below. Figure 5 A description has been provided, and therefore, additional descriptions will be omitted to avoid redundancy.

[0101] In some example embodiments, each of receiver control logic 121b and receiver control logic 121b-1 controls the analog front-end (AFE) of the first receiver RX1, such as the amplification gain G_amp of the variable gain amplifier VGA, based on the temperature of the storage device 120. However, the example embodiments are not limited thereto.

[0102] In some example embodiments, Figure 11 The receiver control logic 121b-2 can control the amplification gain G_amp of the variable gain amplifier VGA, and can also control the setting value SV_CTLE of the continuous-time linear equalizer CTLE (hereinafter referred to as "CTLE setting value") and the setting value SV_DFE of the decision feedback equalizer DFE (hereinafter referred to as "DFE setting value").

[0103] In some example embodiments, such as Figure 12 As shown, when the temperature of the storage device 120 is within the first temperature range TEMP_RG1, the receiver control logic 121b can control the variable gain amplifier VGA based on the first amplification gain G_amp1, control the continuous-time linear equalizer CTLE based on the first CTLE setting value SV_CTLE1, and control the decision feedback equalizer DFE based on the first DFE setting value SV_DFE1. When the temperature of the storage device 120 is within the second temperature range TEMP_RG2, the receiver control logic 121b-2 can control the variable gain amplifier VGA based on the second amplification gain G_amp2, control the continuous-time linear equalizer CTLE based on the second CTLE setting value SV_CTLE2, and control the decision feedback equalizer DFE based on the second DFE setting value SV_DFE2. When the temperature of the storage device 120 is within the m-th temperature range TEMP_RGm, the receiver control logic 121b-2 can control the variable gain amplifier VGA based on the m-th amplification gain G_ampm, control the continuous-time linear equalizer CTLE based on the m-th CTLE setting value SV_CTLEm, and control the decision feedback equalizer DFE based on the m-th DFE setting value SV_DFEm.

[0104] The size of each temperature range in TEMP_RG1 to TEMP_RGm may be the same as the others; however, the example embodiment is not limited thereto. The relationship between the temperature ranges TEMP_RG1 to TEMP_RGm and each of the amplification gains G_amp1 to G_ampm, the setpoints SV_CTLE1 to SV_CTLEm, and the setpoints SV_DFE1 to SV_DFEm may be linear; however, the example embodiment is not limited thereto, and the relationship may be non-linear, such as polynomial and / or exponential and / or piecewise linear.

[0105] In some example embodiments, the multiple amplification gains G_amp1 to G_ampm may be different from each other, or at least some of the multiple amplification gains G_amp1 to G_ampm may be the same as each other. The multiple CTLE settings SV_CTLE1 to SV_CTLEm may be different from each other, or at least some of the multiple CTLE settings SV_CTLE1 to SV_CTLEm may be the same as each other. The multiple DFE settings SV_DFE1 to SV_DFEm may be different from each other, or at least some of the multiple DFE settings SV_DFE1 to SV_DFEm may be the same as each other. Alternatively or additionally, this relationship can be derived by performing iterative experiments or testing procedures on various storage devices.

[0106] In some example embodiments, the continuous-time linear equalizer (CTLE) can operate as a high-pass filter associated with the input signal. In this case, the CTLE setting SV_CTLE can be a value corresponding to the DC or AC gain of the CTLE. The operating characteristics or output signal of the CTLE can be controlled by controlling the CTLE setting SV_CTLE.

[0107] A decision feedback equalizer (DFE) can be configured to add the signal corresponding to previous data to the current signal and output data corresponding to the current signal. In this case, the DFE setting SV_CTLE can indicate the number of coefficients to be applied to the signal corresponding to the previous data. For example, by controlling the DFE setting SV_DFE, the application ratio of the signal corresponding to the previous data can be changed, and therefore, the output signal of the decision feedback equalizer (DFE) can be controlled.

[0108] As described above, the receiver control logic 121b-2 can control the amplification gain and / or setpoints of the various components included in the first receiver RX1 based on the temperature of the storage device 120. According to the above description, even if the temperature of the storage device 120 increases, the effective margin of the first receiver RX1 can be guaranteed, or is more likely to be guaranteed.

[0109] Figure 13 This is a block diagram illustrating a system according to some example embodiments. (Refer to...) Figure 13 System 200 may include a host 210 and a storage device 220. Storage device 220 may include a storage controller 221 and multiple non-volatile memories 222. Storage controller 221 may include a temperature sensor 221a. The operation of host 210 and storage device 220 has been described in accordance with... Figure 1A description has been provided, and therefore, additional descriptions will be omitted to avoid redundancy.

[0110] In some example embodiments, host 210 may perform link retraining based on the temperature of storage device 220. For example, host 210 may include temperature monitoring logic 211 and link retraining logic 212. Temperature monitoring logic 211 may receive temperature information TEMP about the temperature of storage device 220 from temperature sensor 221a included in storage device 220. For example, host 210 may periodically or randomly receive temperature information TEMP from temperature sensor 221a. For example, host 210 may periodically or randomly check SMART information, including temperature information TEMP, from storage device 220.

[0111] Temperature monitoring logic 211 can determine whether the temperature of storage device 220 has changed based on temperature information TEMP. For example, temperature monitoring logic 211 can determine whether the temperature of storage device 220 is higher than a reference temperature based on temperature information TEMP. Alternatively or additionally, temperature monitoring logic 211 can determine whether the temperature range, including the temperature of storage device 220, has changed based on temperature information TEMP. When the temperature of storage device 220 changes, temperature monitoring logic 211 can provide a notification signal to link retraining logic 212.

[0112] Link retraining logic 212 can perform link retraining operations on the zero physical layer PHY0 and the first physical layer PHY1 in response to the notification signal. For example, the zero physical layer PHY0 and the first physical layer PHY1 can perform link retraining operations defined by the PCIe standard under the control of link retraining logic 212. In this case, the effective margin of the first receiver RX1 included in the first physical layer PHY1 of the storage device 220 can be improved or optimized.

[0113] As described above, when the temperature of storage device 220 changes, the effective margin of the receivers included in the first physical layer PHY1 of storage device 220 may decrease. In this case, host 210 can perform link retraining operations based on the temperature of storage device 220. According to the above description, the effective margin of the receivers included in the first physical layer PHY1 can be ensured again.

[0114] Figure 14 It shows Figure 13 The flowchart shows the operations of the host machine. (Refer to...) Figure 13 and Figure 14 During operation S500, the host 210 can be powered on and can perform initialization operations. For example, the host 210 can perform initialization operations with the storage device 220.

[0115] In operation S510, host 210 can monitor the temperature of storage device 220. For example, storage device 220 may include a temperature sensor 221a. Host 210 may periodically or randomly receive temperature information TEMP about the temperature of storage device 220 from temperature sensor 221a of storage device 220. In some example embodiments, host 210 may periodically or randomly receive SMART information including temperature information TEMP from storage device 220.

[0116] In operation S520, host 210 can determine whether the temperature of storage device 220 has changed. For example, host 210's temperature monitoring logic 211 can determine whether the temperature of storage device 220 has changed based on temperature information TEMP. Alternatively or additionally, host 210's temperature monitoring logic 211 can determine whether the temperature of storage device 220 exceeds a reference temperature based on temperature information TEMP. Alternatively, host 210's temperature monitoring logic 211 can determine whether the temperature range, including the temperature of storage device 220, has changed based on temperature information TEMP.

[0117] When the temperature of storage device 220 changes, in operation S530, host 210 can perform link retraining to adjust the settings of the first receiver RX1 of storage device 220. For example, the link retraining logic 212 of host 210 can perform link retraining on the zero physical layer PHY0 and the first physical layer PHY1. In this case, the settings of the transmitters and receivers included in the zero physical layer PHY0 and the first physical layer PHY1 can be improved or optimized. For example, the effective margin of the transmitters and receivers included in the zero physical layer PHY0 and the first physical layer PHY1 can be ensured.

[0118] Figure 15 It shows Figure 13 A diagram showing the hierarchical structure of host and storage devices. (Refer to...) Figure 13 and Figure 15 Host 210 may include a transaction layer, a data link layer, and a physical layer. The transaction layer can be configured to assemble and disassemble transaction layer data packets (TLPs). Transaction layer data packets can be used to communicate read, write, or specific types of events. The transaction layer can be configured to control the flow of transaction layer data packets (TLPs).

[0119] The data link layer can serve as an intermediary layer between the transaction layer and the physical layer. It can be configured to perform data integrity and link management, including error detection and correction.

[0120] The physical layer may include circuitry for interface operation. The physical layer may include logic sub-blocks and electrical sub-blocks. Logic sub-blocks may be configured to perform functions associated with interface initialization and management. Electrical sub-blocks may include circuit components (e.g., a transmitter TX and a receiver RX) configured to send signals to or receive signals from the storage device 220.

[0121] Storage device 220 may include a transaction layer, a data link layer, and a physical layer. The functions and configurations of the transaction layer, data link layer, and physical layer of storage device 220 are similar to those of host 210, and therefore, additional descriptions will be omitted to avoid redundancy.

[0122] In some example embodiments, a logical sub-block of the physical layer in each of host 210 and storage device 220 may include a Link Training and State Machine (LTSSM). The LTSSM may be configured to control link retraining. In some example embodiments, link retraining logic 212 may be an LTSSM included in a logical sub-block of the physical layer. Alternatively or additionally, link retraining logic 212 may be, may include, or be included in a functional block and / or hardware of an LTSSM configured to control a logical sub-block of the physical layer.

[0123] Figure 16 It shows Figure 13 The flowchart illustrates the link retraining operation between the host and storage devices. (Refer to...) Figure 13 , Figure 15 and Figure 16 Host 210 and storage device 220 can perform link retraining through operations S10 to S30. In some example embodiments, operations S10 to S30 may correspond to the link equalization (EQ) process included in the link retraining.

[0124] For ease of description, the following text will refer to the above reference. Figure 2 As described in the given description, it is assumed that the zeroth physical layer PHY0 of host 210 includes a zeroth transmitter TX0 and a zeroth receiver RX0, and the first physical layer PHY1 of storage device 220 includes a first transmitter TX1 and a first receiver RX1.

[0125] In operation S10, the host 210 and storage device 220 can perform the operations of phase 0. As an example, in the operations of phase 0, storage device 220 can transmit the training sequence to the host 210. For instance, storage device 220 can send the transmitter preset value and transmitter preset cue to the host 210 using 8b / 10b encoding. In some example embodiments, the transmitter preset value and transmitter preset cue can be sent using an ordered set of EQ TS2 (training sequence 2).

[0126] In operation S20, host 210 and storage device 220 can perform the operations of phase 1. For example, in the operations of phase 1, host 210 and storage device 220 can exchange training sequences with each other. For example, host 210 and storage device 220 can exchange ordered sets of TS1 to complete fine-tuning of one transmitter and multiple transmitters in subsequent operations.

[0127] In operation S30, the host 210 and storage device 220 can perform the operation of phase 2. For example, in the operation of phase 2, storage device 220 can adjust the setting value of the zeroth transmitter TX0 of host 210 and the setting value of the first receiver RX1 of storage device 220. For example, storage device 220 requests a preset value or coefficient of the zeroth transmitter TX0 of host 210. Host 210 sends a signal to storage device 220 corresponding to the preset value or coefficient requested from storage device 220. Storage device 220 receives the signal from host 210 and requests another preset value and another coefficient from host 210. As the above operations are performed iteratively, the zeroth transmitter TX0 of host 210 and the first receiver RX1 of storage device 220 can be improved or optimized.

[0128] In operation S40, the host 210 and storage device 220 can perform the operation of phase 3. For example, in the operation of phase 3, the host 210 can adjust the setting value of the first transmitter TX1 of the storage device 220 and the setting value of the zeroth receiver RX0 of the host 210. In some example embodiments, except for the interchange of the main components in phases 2 and 3, the manner in which the operation of phase 3 is performed is similar to the manner in which the operation of phase 2 is performed, and therefore, additional descriptions will be omitted to avoid redundancy.

[0129] In some example embodiments, host 210 may be a downstream port and storage device 220 may be an upstream port. In this case, the downstream channel between host 210 and storage device 220 can be improved or optimized through the operation of stage 2, and the upstream channel between host 210 and storage device 220 can be improved or optimized through the operation of stage 3.

[0130] According to some example embodiments, host 210 can sense temperature changes in storage device 220 and perform link retraining based on these temperature changes. In this case, even if the temperature of storage device 220 increases, the first receiver RX1 of storage device 220 can ensure, or is more likely to ensure, effective margin through link retraining.

[0131] Figure 17 It is used to describe Figure 16A diagram illustrating the operations in stage 2. For ease of description, components whose operations in stage 2 do not require description have been omitted. See also... Figure 13 and Figure 17 The host 210 and storage device 220 can optimize the zeroth transmitter TX0 and the first receiver RX1. For example, the storage device 220 can request a preset value or coefficient for the zeroth transmitter TX0 from the host 210 (operation [1]). In response to this request, the host 210 can send a signal corresponding to the value (such as a preset value or coefficient) to the storage device 220 via the first signal line SIGL1 (operation [2]). For example, the zeroth transmitter TX0 of the host 210 can be an equalized transmitter including a feedforward equalizer (FFE). The host 210 can control the EQ settings of the zeroth transmitter TX0 based on the preset value or coefficient.

[0132] Storage device 220 can receive the signal from zero transmitter TX0 via the first signal line SIGL1 and the first receiver RX1, and can perform an evaluation (e.g., quality factor (FOM)). Storage device 220 can control the setting value of the continuous-time linear equalizer CTLE of the first receiver RX1 based on the evaluation results. Subsequently, storage device 220 can request other values ​​from host 210, such as other preset values ​​and other coefficients for zero transmitter TX0 (e.g., iteration of operation [1]). With iterative operation of the above, zero transmitter TX0 and the first receiver RX1 can be improved or optimized.

[0133] In some example embodiments, as the temperature of storage device 220 increases, host 210 can perform link retraining. In this case, host 210 and storage device 220 can perform reference... Figure 16 The described link retraining operations (e.g., operations from phases 0 to 3) are described. However, the example embodiments are not limited thereto. For example, when the temperature of storage device 220 increases, host 210 may only perform the operations of phase 2 to ensure the effective margin of the first receiver RX1 of storage device 220. For example, when the temperature of storage device 220 increases, host 210 and storage device 220 may optimize downstream channels under the control of host 210 or upon request from host 210.

[0134] Figure 18 This is a block diagram illustrating a system according to some example embodiments. (Refer to...) Figure 18 The system 1000 may include a host 1100 and multiple storage devices 1210 to 1230. Figure 18 Three storage devices 1210 to 1230 are shown, but the example embodiment is not limited thereto. For example, host 1100 may communicate with more storage devices.

[0135] Host 1100 can independently control multiple storage devices 1210 to 1230. The temperatures of the multiple storage devices 1210 to 1230 can vary from one another, for example, depending on the operating environment. For instance, host 1100 and the multiple storage devices 1210 to 1230 can be installed in a single server rack. In this case, the temperatures of the multiple storage devices 1210 to 1230 can vary depending on the location of the multiple storage devices 1210 to 1230. Alternatively or additionally, the temperatures of the multiple storage devices 1210 to 1230 can vary depending on the workload.

[0136] The first storage device 1210 may have a first temperature, the second storage device 1220 may have a second temperature higher than the first temperature, and the third storage device 1230 may have a third temperature higher than the second temperature. In this case, as described above, the receivers RX of the multiple storage devices 1210 to 1230 can be set to different set values. For example, the first storage device 1210 may include a first temperature sensor TS1, a first receiver control logic RXCL1, and a first non-volatile memory NVM1. The first temperature sensor TS1 can monitor the temperature of the first storage device 1210. The first receiver control logic RXCL1 can adjust the receivers included in the first storage device 1210 based on a first set value SV1 corresponding to the temperature of the first storage device 1210. The second storage device 1220 may include a second temperature sensor TS2, a second receiver control logic RXCL2, and a second non-volatile memory NVM2. The second temperature sensor TS2 can monitor the temperature of the second storage device 1220. The second receiver control logic RXCL2 can adjust the receivers included in the second storage device 1220 based on a second set value SV2 corresponding to the temperature of the second storage device 1220. The third storage device 1230 may include a third temperature sensor TS3, a third receiver control logic RXCL3, and a third non-volatile memory NVM3. The third temperature sensor TS3 can monitor the temperature of the third storage device 1230. The third receiver control logic RXCL3 can adjust the receiver included in the third storage device 1230 based on a third setpoint SV3 corresponding to the temperature of the third storage device 1230.

[0137] In some example embodiments, each of the first receiver control logic RXCL1 to the third receiver control logic RXCL3 may be or may include a reference. Figures 1 to 12 The described receiver control logic 121b, 121b-1, or 121b-2, and / or may be based on references Figures 1 to 12 The described method is used to perform the operation.

[0138] As described above, the host 1100 can communicate with multiple storage devices 1210 to 1230. In this case, the operating temperatures of the multiple storage devices 1210 to 1230 can be different from each other. In this case, each of the multiple storage devices 1210 to 1230 can set the receiver included therein based on a set value corresponding to its operating temperature. Accordingly, even if the operating temperatures of the multiple storage devices 1210 to 1230 are different from each other, the receiver can be controlled individually, and therefore, the effective margin of each receiver can be ensured.

[0139] Figure 19 This is a block diagram illustrating a system according to some example embodiments. (Refer to...) Figure 19 System 2000 may include host 2100 and multiple storage devices 2210 to 2230. Host 2100 can communicate with the multiple storage devices 2210 to 2230. (See reference...) Figure 18 The multiple storage devices 2210 to 2230 can have different temperatures.

[0140] Multiple storage devices 2210 to 2230 may each include temperature sensors TS1 to TS3. Host 2100 may collect temperature information TEMP1 to TEMP3 from the temperature sensors TS1 to TS3 of the multiple storage devices 2210 to 2230. For example, the temperature monitoring logic of host 2100 may collect the temperature information TEMP1 to TEMP3 from the multiple storage devices 2210 to 2230.

[0141] The link equalization (EQ) / retraining logic of host 2100 can perform link retraining on each of the multiple storage devices 2210 to 2230 based on temperature information TEMP1 to TEMP3. For example, host 2100 can determine that the temperature of the first storage device 2210 has changed or exceeded a reference temperature based on the first temperature information TEMP1. In this case, host 2100 can then determine the temperature of the first storage device 2210 based on the reference temperature information TEMP1. Figures 13 to 17 The described operation method performs link retraining on the physical layer of the first storage device 2210. Accordingly, even if the temperature of the first storage device 2210 changes or increases, the effective margin of the receivers included in the physical layer of the first storage device 2210 can be ensured. In some example embodiments, the host 2100 may perform link retraining on each of the plurality of storage devices 2210 to 2230. Accordingly, the optimization of the receivers respectively included in the plurality of storage devices 2210 to 2230 can be maintained based on the temperature of the plurality of storage devices 2210 to 2230.

[0142] Figure 20 This is a block diagram of a host storage system 3000 according to an example embodiment.

[0143] The host storage system 3000 may include a host 3001 and a storage device 3100. Furthermore, the storage device 3100 may include a storage controller 3110 and an NVM 3120. According to some example embodiments, the host 3001 may include a host controller 3002 and host memory 3003. The host memory 3003 may be used as a buffer memory configured to temporarily store data to be sent to or received from the storage device 3100.

[0144] Storage device 3100 may include a storage medium configured to store data in response to a request from host 3001. For example, storage device 3100 may include at least one of an SSD, embedded memory, and removable external memory. When storage device 3100 is or includes an SSD, it may be, may include, or may be included in a device compliant with the NVMe standard. When storage device 3100 is or includes embedded memory or external memory, it may be, may include, or may be included in a device compliant with the UFS standard or the eMMC standard. Each of host 3001 and storage device 3100 may generate and transmit data packets according to the adopted standard protocol.

[0145] When the NVM 3120 of storage device 3100 includes flash memory, the flash memory may include a 31D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. Alternatively or additionally, storage device 3100 may include various other types of NVM. For example, storage device 3100 may include magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FRAM), PRAM, RRAM, and various other types of memory.

[0146] According to some example embodiments, the host controller 3002 and the host memory 3003 can be implemented as separate semiconductor chips. Alternatively, in some example embodiments, the host controller 3002 and the host memory 3003 can be integrated on the same semiconductor chip. For example, the host controller 3002 can be any of a plurality of modules included in an application processor (AP). The AP can be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 3003 can be embedded memory included in the AP, or an NVM or memory module located outside the AP.

[0147] The host controller 3002 can manage operations that store data (e.g., write data) in the buffer area of ​​the host memory 3003 in the NVM 3120, or operations that store data (e.g., read data) in the buffer area of ​​the NVM 3120.

[0148] Storage controller 3110 may include host interface 3111, memory interface 3112, and CPU 3113. Additionally, storage controller 3110 may include flash translation layer (FTL) 3114, data packet manager 3115, buffer memory 3116, error correction code (ECC) engine 3117, and Advanced Encryption Standard (AES) engine 3118. Storage controller 3110 may also include working memory (not shown) that loads FTL 3114. CPU 3113 can execute FTL 3114 to control data write and read operations on NVM 3120.

[0149] Host interface 3111 can send data packets to host 3001 and receive data packets from host 3001. Data packets sent from host 3001 to host interface 3111 may include commands or data to be written to NVM 3120. Data packets sent from host interface 3111 to host 3001 may include responses to those commands and / or data read from NVM 3120. Memory interface 3112 can send data to be written to NVM 3120 or receive data read from NVM 3120. Memory interface 3112 can be configured to conform to standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0150] The FTL 3114 can perform one or more of the following functions: address mapping, wear leveling, and garbage collection. Address mapping can be the process of translating a logical address received from the host 3001 into a physical address used to actually store data in the NVM 3120. Wear leveling is a technique that prevents excessive corruption of specific blocks by allowing blocks in the NVM 3120 to be used uniformly. As an example, wear leveling can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection can be a technique that ensures available capacity in the NVM 3120 by erasing existing blocks after copying valid data from them to new blocks.

[0151] Data packet manager 3115 can generate data packets according to the interface protocol of licensed host 3001, or parse various types of information from data packets received from host 3001. Furthermore, buffer memory 3116 can temporarily store data to be written to or read from NVM 3120. Although buffer memory 3116 may be a component included in storage controller 3110, buffer memory 3116 may be located external to storage controller 3110.

[0152] The ECC engine 3117 can perform error detection and correction operations on the read data read from the NVM 3120. More specifically, the ECC engine 3117 can generate parity bits for the write data to be written to the NVM 3120 and store the generated parity bits together with the write data in the NVM 3120. During data reading from the NVM 3120, the ECC engine 3117 can correct errors in the read data by using the parity bits read from the NVM 3120 and the read data, and output the error-corrected read data.

[0153] The AES engine 3118 can perform at least one of encryption and decryption operations on the data input to the storage controller 3110 using a symmetric key algorithm.

[0154] In some example embodiments, Figure 20 The host 3001 can be Figures 1 to 19 One of the hosts 110, 210, 1100, and 2100, and Figure 20 The storage device 3100 can be one of storage devices 120, 220, 1210 to 1230, and 2210 to 2230. For example, the host 3001 can perform link retraining between the host 3001 and the storage device 3100 in response to the operating temperature of the storage device 3100 or a change in operating temperature. Alternatively or additionally, the storage device 3100 can adjust the settings of the receiver included in the host interface circuitry 3111 in response to the operating temperature of the storage device 3100 or a change in operating temperature.

[0155] Figure 21 This is a diagram of a data center 4000 for application storage devices according to some example embodiments.

[0156] Reference Figure 21Data center 4000 can be a facility that collects various types of data and provides services, and can be referred to as a data storage center. Data center 4000 can be a system for operating search engines and databases, and can be a computing system used by companies such as banks or government agencies. Data center 4000 can include application servers 4100 to 4100n and storage servers 4200 to 4200m. The number of application servers 4100 to 4100n and the number of storage servers 4200 to 4200m can be selected differently depending on the embodiment. The number of application servers 4100 to 4100n can differ from the number of storage servers 4200 to 4200m.

[0157] Application server 4100 or storage server 4200 may include at least one of processors 4110 and 4210 and memories 4120 and 4220. Storage server 4200 will now be described as an example. Processor 4210 may control all operations of storage server 4200, access memory 4220, and execute instructions and / or data loaded in memory 4220. Memory 4220 may be, may include, or may be included in one or more of Double Data Rate Synchronous DRAM (DDRSDRAM), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), Dual In-line Memory Module (DIMM), Optane DIMM, and / or Non-Volatile DIMM (NVMDIMM). In some example embodiments, the number of processors 4210 and memory 4220 included in storage server 4200 may be selected differently. In some example embodiments, processors 4210 and memory 4220 may provide processor-memory pairs. In some example embodiments, the number of processors 4210 may differ from the number of memories 4220. Processor 4210 may include a single-core processor or a multi-core processor. The above description of storage server 4200 can be similarly applied to application server 4100. In some example embodiments, application server 4100 may not include storage device 4150. Storage server 4200 may include at least one storage device 4250. The number of storage devices 4250 included in storage server 4200 may be selected differently depending on the embodiment.

[0158] Application servers 4100 to 4100n can communicate with storage servers 4200 to 4200m via network 4300. Network 4300 can be implemented using Fibre Channel (FC) and / or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission and uses an optical switch with high performance and high availability. Storage servers 4200 to 4200m can be provided as one or more of file storage, block storage, or object storage, depending on the access method of network 4300.

[0159] In some example embodiments, network 4300 may be, may include, or may be included in a storage-specific network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN may be, may include, or may be included in an Internet Protocol (IP)-SAN that uses a Transmission Control Protocol (TCP) / IP network and is implemented according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In some example embodiments, network 4300 may be, may include, or may be included in a general-purpose network, such as a TCP / IP network. For example, network 4300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and Architecture-based NVMe (NVMe-oF).

[0160] The following text will primarily describe application server 4100 and storage server 4200. The description of application server 4100 can be applied to another application server 4100n, and the description of storage server 4200 can be applied to another storage server 4200m.

[0161] Application server 4100 can store data requested by users or clients in one of storage servers 4200 to 4200m via network 4300. Furthermore, application server 4100 can retrieve data requested by users or clients from one of the storage servers 4200 to 4200m via network 4300. For example, application server 4100 can be implemented as a web server and / or a database management system (DBMS).

[0162] Application server 4100 can access memory 4120n or storage device 4150n included in another application server 4100n via network 4300. Alternatively or additionally, application server 4100 can access memory 4220 to 4220m or storage device 4250 to 4250m included in storage servers 4200 to 4200m via network 4300. Therefore, application server 4100 can perform various operations on data stored in application servers 4100 to 4100n and / or storage servers 4200 to 4200m. For example, application server 4100 can execute instructions for moving or copying data between application servers 4100 to 4100n and / or storage servers 4200 to 4200m. In this scenario, data can be moved directly from storage devices 4250 to 4250m of storage servers 4200 to 4200m to storage devices 4120 to 4120n of application servers 4100 to 4100n, or it can be moved via storage devices 4220 to 4220m of storage servers 4200 to 4200m. Data moved over network 4300 can be encrypted for security or privacy purposes.

[0163] Storage server 4200 will now be described as an example. Interface 4254 can provide physical connectivity between processor 4210 and controller 4251, and between network interface card (NIC) 4240 and controller 4251. For example, interface 4254 can be implemented using a direct-attach storage (DAS) scheme, where storage device 4250 is directly connected to a dedicated cable. For example, interface 4254 can be implemented using various interface schemes, such as one or more of ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and / or CF card interface.

[0164] Storage server 4200 may also include switch 4230 and NIC (Network Interconnect) 4240. Switch 4230 can selectively connect processor 4210 to storage device 4250 or selectively connect NIC 4240 to storage device 4250 under the control of processor 4210.

[0165] In some example embodiments, NIC 4240 may include a network interface card and a network adapter. NIC 4240 can be connected to network 4300 via a wired interface, wireless interface, Bluetooth interface, or fiber optic interface. NIC 4240 may include internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to processor 4210 and / or switch 4230 via the host bus interface. The host bus interface may be implemented as one of the above examples of interface 4254. In some example embodiments, NIC 4240 may be integrated with at least one of processor 4210, switch 4230, and storage device 4250.

[0166] In storage servers 4200 to 4200m or application servers 4100 to 4100n, the processor can send commands to storage devices 4150 to 4150n and 4250 to 4250m or memories 4120 to 4120n and 4220 to 4220m, and program or read data. In this case, the data can be data for which errors have been corrected by an ECC engine. The data can be data to which a Data Bus Inversion (DBI) operation and / or Data Masking (DM) operation has been performed, and can include Cyclic Redundancy Check (CRC) information. The data can be encrypted for security and / or privacy.

[0167] Storage devices 4150 to 4150n and 4250 to 4250m can send control signals and command / address signals to NAND flash memory devices 4252 to 4252m in response to read commands received from the processor. Therefore, when reading data from NAND flash memory devices 4252 to 4252m, a read enable (RE) signal can be input as a data output control signal, and thus, data can be output to the DQ bus. The RE signal can be used to generate a data strobe signal DQS. Command and address signals can be latched into the page buffer based on the rising or falling edge of the write enable (WE) signal.

[0168] Controller 4251 can control all operations of storage device 4250. In some example embodiments, controller 4251 may include SRAM. Controller 4251 can write data to NAND flash memory device 4252 in response to a write command, or read data from NAND flash memory device 4252 in response to a read command. For example, write commands and / or read commands may be provided by processor 4210 of storage server 4200, processor 4210m of another storage server 4200m, or processors 4110 and 4110n of application servers 4100 and 4100n. DRAM 4253 can temporarily store (or buffer) data to be written to or read from NAND flash memory device 4252. In addition, DRAM 4253 may also store metadata. Here, metadata may be user data or data generated by controller 4251 to manage NAND flash memory device 4252. Storage device 4250 may include a security element (SE) for security or privacy.

[0169] In some example embodiments, Figure 21 Storage devices 4150 to 4150n and 4250 to 4250m can be referenced. Figures 1 to 20 One or more storage devices described in the reference, or may be based on the reference Figures 1 to 20 The described operation method is used to perform the operation. In some example embodiments, Figure 21 The application servers 4110 to 4110n, storage servers 4200 to 4200m, or processors 4110 to 4110n and 4210 to 4210m included therein may be or may correspond to the reference. Figures 1 to 20 One or more hosts described in the reference, or may be based on the reference Figures 1 to 20 The operation is performed according to the described method. Accordingly, it can be done according to... Figure 21 The temperature of storage devices 4150 to 4150n and 4250 to 4250m is used to ensure the effective margin of the receiver included in each of the storage devices 4150 to 4150n and 4250 to 4250m.

[0170] Figure 22 This is a block diagram illustrating an electronic system according to some example embodiments. (Refer to...) Figure 22Electronic system 5000 may include a first device 5100 and a second device 5200. The first device 5100 and the second device 5200 may be independent devices configured to perform various functions, such as hardware, one or more functional blocks, intellectual property (IP) blocks, etc. Alternatively or additionally, the first device 5100 may be, may include, or may be included in a processor and / or controller configured to control the second device 5200. Alternatively or additionally, the second device 5200 may be, may include, or may be included in a processor and / or controller configured to control the first device 5100.

[0171] In some example embodiments, the first device 5100 may be, may include, or may be included in a Universal Flash Memory (UFS) host, and the second device 5200 may be a UFS device. Alternatively or additionally, the first device 5100 may be a CPU, and the second device 5200 may include at least one of a variety of devices configured to communicate with the CPU, such as one or more of a CPU, modem, main memory, input device, etc.

[0172] The first device 5100 may include a zero-layer PHY0, and the second device 5200 may include a first-layer PHY1. The zero-layer PHY0 and the first-layer PHY1 can be connected to each other via a link for serial communication. In some example embodiments, each of the zero-layer PHY0 and the first-layer PHY1 may support serial communication as defined by the PCIe standard. However, the example embodiments are not limited thereto. For example, the zero-layer PHY0 and the first-layer PHY1 may be configured to support various serial communications, such as MIPI and M-PHY.

[0173] In some example embodiments, the second device 5200 can adjust the settings or amplification gain of the receiver included in the first physical layer PHY1 of the second device 5200 based on temperature changes of the second device 5200. For example, based on a reference... Figures 1 to 12 The described operating method allows the second device 5200 to adjust the settings or amplification gain of the receiver included in the first physical layer PHY1.

[0174] In some example embodiments, the first device 5100 can perform training operations on the zeroth physical layer PHY0 and the first physical layer PHY1 based on the temperature change of the second device 5200. For example, the first device 5100 can perform training operations based on a reference... Figures 13 to 17 The described operation method performs training operations on the zero physical layer PHY0 and the first physical layer PHY1 to optimize the receiver of the second device 5200.

[0175] As described above, according to some example embodiments, the receiver of a storage device can be improved or optimized based on the temperature of the storage device. Accordingly, the possibility and / or impact of a decrease in the effective margin of the receiver due to temperature variations of the storage device can be prevented or reduced. The host can communicate with multiple storage devices and can improve or optimize the receiver of each of the multiple storage devices individually based on the temperature of each of the multiple storage devices. Accordingly, a storage device and storage system with improved performance and improved reliability are provided.

[0176] According to some example embodiments, various settings of the receiver included in the physical layer of the storage device can be adjusted according to the temperature of the storage device. In this case, the receiver can be improved or optimized according to the temperature of the storage device, or the effective margin of the receiver can be ensured according to the temperature of the storage device. Accordingly, a storage device with improved performance, a method of operating the storage device, and a storage system including the storage device are provided.

[0177] The various blocks and / or elements described in the above figures can communicate with other various blocks and / or elements described in the above figures. Communication can be unidirectional, and / or bidirectional, and / or multidirectional (e.g., broadcast). Alternatively or additionally, communication can be carried out via a bus, such as, but not limited to, a wireless bus and / or a wired bus. In some example embodiments, communication may include information, such as, but not limited to, data and / or commands, and communication may be transmitted and / or received digitally and / or analogically. In some cases, communication may be transmitted and / or received serially and / or in parallel; the example embodiments are not limited thereto.

[0178] Any of the elements and / or functional blocks disclosed above may be included or implemented in processing circuitry (such as hardware including logic circuitry; hardware / software combinations such as a processor executing software; or combinations thereof). For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processing circuitry may include electronic components, such as at least one of transistors, resistors, capacitors, etc. Processing circuitry may include electronic components, such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0179] While some exemplary embodiments have been described with reference to embodiments of this disclosure, those skilled in the art will understand that various changes and modifications can be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims. Furthermore, the exemplary embodiments are not necessarily mutually exclusive. For example, some exemplary embodiments may include one or more features described with reference to one or more accompanying drawings, and may also include one or more other features described with reference to one or more other accompanying drawings.

Claims

1. A storage device, comprising: Non-volatile storage devices; as well as A storage controller is configured to control the non-volatile storage device. The storage controller includes: The receiver is configured to receive a received signal from an external device via a first signal line; A temperature sensor is configured to sense the temperature of the storage device and output temperature information; and The receiver control logic is configured to adjust the receiver's setpoint to an adjusted setpoint based on the temperature information.

2. The storage device according to claim 1, wherein, The receiver includes: A continuous-time linear equalizer is configured to receive the received signal via the first signal line and perform a high-pass filtering operation on the received signal; A variable gain amplifier is configured to amplify the output of the continuous-time linear equalizer; and A decision feedback equalizer is configured to perform sampling based on the output of the variable gain amplifier.

3. The storage device according to claim 2, wherein, The receiver also includes: A deserializer is configured to deserialize the output of the decision feedback equalizer.

4. The storage device according to claim 2, wherein, The receiver's settings include an amplification gain value associated with the amplification gain of the variable gain amplifier, and The receiver control logic is configured to adjust the amplification gain of the variable gain amplifier based on the temperature information.

5. The storage device according to claim 4, wherein, As the temperature of the storage device corresponding to the temperature information increases, the amplification gain of the variable gain amplifier increases.

6. The storage device according to claim 4, wherein, In response to the temperature of the storage device corresponding to the temperature information falling within a first temperature range, the receiver control logic is configured to adjust the amplification gain of the variable gain amplifier to a first value, and In response to the storage device having a temperature corresponding to the temperature information that is within a second temperature range different from the first temperature range, the receiver control logic is configured to adjust the amplification gain of the variable gain amplifier to a second value different from the first value.

7. The storage device according to claim 4, wherein, The receiver control logic is configured as follows: The amplification gain of the variable gain amplifier is adjusted to a first value, and a first margin is measured based on the output of the variable gain amplifier. The amplification gain of the variable gain amplifier is adjusted to a second value, and a second margin is measured based on the output of the variable gain amplifier. Based on the first margin and the second margin, one of the first value and the second value is adjusted to achieve a good amplification gain for the variable gain amplifier.

8. The storage device according to claim 2, wherein, The receiver settings include continuous-time linear equalizer settings associated with the continuous-time linear equalizer and decision feedback equalizer settings associated with the decision feedback equalizer.

9. The storage device according to claim 1, wherein, During the initialization operation of the storage device, the receiver is configured to be set based on default settings, and The adjusted setting value is different from the default setting value.

10. The storage device according to claim 9, wherein, In response to a hot reset of the storage device, the receiver control logic is configured to store the adjusted setting value of the receiver in the non-volatile storage device, and In response to a cold reset of the storage device, the receiver control logic is configured to clear the adjusted settings of the receiver.

11. The storage device according to claim 10, wherein, In response to startup after the hot reset, the receiver control logic is configured to set the receiver based on the adjusted settings stored in the non-volatile memory device, and In response to startup after the cold reset, the receiver control logic is configured to set the receiver based on the default settings.

12. The storage device according to claim 1, wherein, The storage controller also includes: The transmitter is configured to output a transmission signal to the external device via a second signal line.

13. A method of operating a storage device, the method comprising: The receiver is configured to receive signals from an external device via a first signal line using default settings. Monitor the temperature of the storage device; and In response to the storage device's temperature being greater than or equal to a reference value, the receiver's setpoint is adjusted to the adjusted setpoint.

14. The operating method according to claim 13, wherein, The receiver includes: A continuous-time linear equalizer is configured to receive the received signal via the first signal line and perform a high-pass filtering operation on the received signal; A variable gain amplifier is configured to amplify the output of the continuous-time linear equalizer; and A decision feedback equalizer is configured to perform sampling based on the output of the variable gain amplifier, and The adjusted setting value of the receiver includes an amplification gain value associated with the amplification gain of the variable gain amplifier.

15. The operating method according to claim 14, wherein, The adjusted settings of the receiver include continuous-time linear equalizer settings associated with the continuous-time linear equalizer and decision feedback equalizer settings associated with the decision feedback equalizer.

16. The operating method according to claim 13, wherein, In response to the storage device's temperature being greater than or equal to the reference value, adjusting the receiver's settings includes: In response to a request from the external device, link retraining is performed.

17. The operating method according to claim 16, wherein, The link retraining includes: Optimize the downstream channel between the receiver of the storage device and the transmitter of the external device.

18. A storage device, comprising: Non-volatile storage devices; as well as A storage controller is configured to control the non-volatile storage device. The storage controller is configured to configure the receiver using default settings during initialization with an external device, and the receiver is configured to receive signals from the external device; and In response to the storage device's temperature exceeding a reference temperature, the storage controller is configured to reconfigure the receiver based on a first set value corresponding to the storage device's temperature.

19. The storage device according to claim 18, wherein, The receiver includes: A continuous-time linear equalizer is configured to receive the received signal via a first signal line and perform a high-pass filtering operation on the received signal; A variable gain amplifier is configured to amplify the output of the continuous-time linear equalizer; and A decision feedback equalizer is configured to perform sampling based on the output of the variable gain amplifier, and The first set value includes an amplification gain value associated with the amplification gain of the variable gain amplifier.

20. The storage device according to claim 19, wherein, The first setting also includes a continuous-time linear equalizer setting associated with the continuous-time linear equalizer and a decision feedback equalizer setting associated with the decision feedback equalizer.

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