Memory controller, method of operating a memory controller, and memory system

Abstract

A memory controller processing a mask write command, an operating method of the memory controller, and a memory system are provided. The operating method of the memory controller includes receiving a mask write request from a host, generating a dummy read command for a target address of the mask write request, converting the mask write request into a normal write command based on processing of the dummy read command, and executing the normal write command.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0185074, filed with the Korean Intellectual Property Office on December 12, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to memory controllers, and more specifically, to memory controllers for processing masked write commands, methods of operation thereof, and memory systems. Background Technology

[0004] Mask write operations can be performed as a read-modify-write (RMW) process. For example, a mask write operation may require a command-to-command latency (tCCDMW) for mask writes. However, the tCCDMW latency can be longer than the command-to-command latency (tCCD) that might be included in a normal write command. For example, the tCCDMW latency can be up to four times the tCCD latency. Therefore, the tCCDMW time penalty caused by mask write operations can lead to an increase in the maximum system-level latency of the relevant memory system, which can be critical in systems composed of real-time intellectual property (IP).

[0005] To potentially address this time penalty, the associated dynamic random access memory (DRAM) scheduler can prioritize mask write commands to potentially prevent DRAM from utilizing a bubble when the last remaining command in the write queue is a mask write command. This could lead to potentially higher efficiency compared to general scheduling. However, when a relatively large number of mask write commands occupy a particular bank, the maximum latency of that bank may increase, which may not be resolved by the associated DRAM scheduler's prioritization.

[0006] Therefore, there is a need for further improvements to memory controller technology, as the requirement to perform mask write operations may be limited by an increase in maximum latency. This paper proposes improvements. These improvements can also be applied to other semiconductor technologies. Summary of the Invention

[0007] One or more exemplary embodiments of this disclosure provide a memory controller, its operation method, and a memory system capable of minimizing the command-to-command latency (tCCDMW) penalty for masked write commands by converting masked write commands into dummy read commands and normal write commands and executing the converted commands.

[0008] According to one aspect of this disclosure, a method of operating a memory controller includes: receiving a mask write request from a host, generating a virtual read command for the target address of the mask write request, converting the mask write request into a normal write command based on processing the virtual read command, and executing the normal write command.

[0009] According to one aspect of this disclosure, a memory controller includes: a buffer memory, one or more processors including processing circuitry, and a memory storing instructions. When executed individually or jointly by the one or more processors, the instructions cause the memory controller to: receive a mask write request from a host, generate a virtual read command for the target address of the mask write request, and convert the mask write request into a normal write command based on processing of the virtual read command.

[0010] According to one aspect of this disclosure, a memory system includes: a host device configured to generate a mask write request, the mask write request including mask write data and mask bits indicating a masked region; and a memory device including a memory controller, the memory controller including one or more dynamic random access memories (DRAM), one or more buffer memories, and a scheduler. The memory controller is configured to receive the mask write request from the host device, generate a virtual read command for a target address of the mask write request, and convert the mask write request into a normal write command based on processing of the virtual read command.

[0011] Additional aspects may be set forth in part in the description below, and in part may be apparent from the description, and / or may be learned by practice of the embodiments presented. Attached Figure Description

[0012] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0013] Figure 1 This is a diagram illustrating a memory system including a memory device performing a mask write operation according to an embodiment;

[0014] Figure 2 This is a block diagram of a memory device according to an embodiment;

[0015] Figure 3A The scheduler is shown based on the comparison example;

[0016] Figure 3B A scheduler according to an embodiment is shown;

[0017] Figure 4 This is a flowchart illustrating an operation method of the scheduler according to an embodiment;

[0018] Figure 5A The changes in the command queue according to the embodiment are shown;

[0019] Figure 5B An example of the buffer state according to an embodiment is shown;

[0020] Figure 6 This is a flowchart illustrating an operation method of the scheduler according to an embodiment;

[0021] Figure 7 The command processing sequence based on the comparison example is shown;

[0022] Figure 8 A command processing sequence according to an embodiment is shown;

[0023] Figure 9 This is a block diagram of a system having an electronic device including a memory device according to an embodiment;

[0024] Figure 10 This is a block diagram of a memory controller according to an embodiment; and

[0025] Figure 11 This is a block diagram of a memory system according to an embodiment. Detailed Implementation

[0026] In the following description, various embodiments are illustrated with reference to the accompanying drawings. Embodiments are provided to describe this disclosure to those skilled in the art. Embodiments may have various modifications and forms, and specific embodiments thereof are shown and described in detail in the drawings. However, the embodiments are not intended to limit this disclosure to a particular mode of practice, but should be understood to include all modifications, equivalents, or substitutions included within the spirit and scope of this disclosure. When describing each drawing, the same reference numerals are used to refer to the same components. In the drawings, the dimensions of structures may be enlarged or reduced from their actual dimensions to ensure clarity of the embodiments.

[0027] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to specify the presence of features, quantities, steps, operations, components, parts or combinations thereof described in this disclosure, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0028] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Terms defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant field, and should not be interpreted in an idealized and / or overly formal sense unless expressly defined in this disclosure.

[0029] When used herein, each of the phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B or C” may include any one or all possible combinations of the items listed together in the corresponding phrase. When used herein, terms such as “first” and “second” or “first” and “second” may be used simply to distinguish corresponding components from another component without otherwise limiting the components (e.g., importance or order). It should be understood that if an element (e.g., a first element) is referred to as “coupled to another element (e.g., a second element),” “coupled to another element,” “connected to another element,” or “connected to another element,” regardless of whether the terms “operably” or “communically” are used, it means that the element may be coupled to the other element directly (e.g., wired), wirelessly, or via a third element.

[0030] Throughout this disclosure, references to "an embodiment," "embodiment," "example embodiment," or similar language can indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the solution. Therefore, throughout this disclosure, the phrases "in one embodiment," "in an embodiment," "in an example embodiment," and similar language can, but do not necessarily, refer to the same embodiment. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and can be implemented in various other forms.

[0031] It should be understood that the specific order or hierarchy of blocks in the disclosed process / flowchart is an illustration of exemplary methods. Based on design preferences, it should be understood that the specific order or hierarchy of blocks in the process / flowchart can be rearranged. Furthermore, some blocks can be combined or omitted. The appended claims present elements of various blocks in an exemplary order and are not intended to limit one to the specific order or hierarchy presented.

[0032] The embodiments described and illustrated herein can be presented in blocks, as shown in the figures, which perform one or more of the described functions. These blocks—which may be referred to herein as cells or modules, or by name as devices, logic, circuits, controllers, counters, comparators, generators, converters, etc.—can be physically implemented by analog and / or digital circuitry, including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0033] In this disclosure, the article “one” (a and an) is intended to include one or more items and can be used interchangeably with “one or more”. The term “a” or similar language is used when referring to only one item. For example, the term “one processor” can refer to a single processor or multiple processors. When a processor is described as performing operations and referred to as performing additional operations, multiple operations can be performed by a single processor or any one or a combination of multiple processors.

[0034] Various embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0035] Figure 1 This is a diagram illustrating a memory system including a memory device that performs a mask write operation according to an embodiment.

[0036] refer to Figure 1 The memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 can control the memory device 200. The memory controller 100 can send control signals to the memory device 200, such as, but not limited to, a clock signal CLK, a command signal CMD, an address signal ADDR, a data strobe signal DQS, a data mask signal DM, and a data signal DQ, and / or can receive the data strobe signal DQS and the data signal DQ from the memory device 200. The memory controller 100 can issue a read command READ, a write command WRITE, and a mask write command MWR, and can send these commands to the memory device 200.

[0037] The memory device 200 may include command (CMD) control logic 202 and error correction code (ECC) engine 204. The command control logic 202 may receive commands (CMD) issued by the memory controller 100, and may generate internal commands (INT_CMD) that can control the operation of the memory device 200 based on the commands (CMD).

[0038] The memory device 200 can perform a read operation in response to a read command (READ), a write operation in response to a write command (WRITE), and a mask write operation in response to a mask write command (MWR). A mask write operation may include masking data during the write operation to prevent it from being written to a portion of a block of memory cells that may constitute a memory cell array.

[0039] Command control logic 202 can generate internal read command INT_RD and internal write command INT_WR based on the read command READ, write command WRITE, or mask write command MWR from memory controller 100. Based on the internal read command INT_RD and internal write command INT_WR, read operations, write operations, and mask write operations of memory device 200 can be executed.

[0040] According to an embodiment, the memory controller 100 may include a scheduler 110. The scheduler 110 may manage read requests and / or write requests as access management of the memory device 200. For example, the scheduler 110 may buffer read requests and / or write requests in a scheduling queue and process the requests sequentially. The scheduler 110 may control the memory device 200 by converting each request into a sequence of dynamic random access memory (DRAM) commands, based on the processing order of the scheduling queue.

[0041] According to an embodiment, scheduler 110 can translate masked write requests. For example, when a masked write request is received, scheduler 110 can translate the masked write request into virtual read commands and normal write commands, instead of generating a masked write command. Since the command-to-command latency (tCCDMW) of a masked write command may be significantly longer (e.g., four times greater) than the command-to-command latency (tCCD) of a normal write command and / or a read command, scheduler 110 can add virtual read commands and normal write commands to the scheduling queue instead of masked write commands to potentially improve (e.g., reduce) the maximum latency of memory system 10.

[0042] In embodiments, scheduler 110 may be physically implemented using analog and / or digital circuitry, including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuitry, passive electronic components, active electronic components, optical components, etc. For example, a field-programmable gate array (FPGA) may be used to implement custom logic that may include the functionality of scheduler 110. As another example, a processor, together with memory, may be used to execute one or more instructions to perform the functionality of scheduler 110. Alternatively or additionally, at least a portion of the functionality of scheduler 110 may be incorporated into memory controller 100 and / or implemented as instructions to be executed by memory controller 100.

[0043] Figure 2 This is a block diagram of a storage device according to an embodiment.

[0044] refer to Figure 2 The memory device 200 can receive a command CMD, an address ADDR, a clock CLK, and input data DATA_IN. For example, the memory device 200 can receive a write operation command CMD, an address ADDR, and input data DATA_IN, and store the input data DATA_IN in the memory cell area corresponding to the address ADDR in the memory cell array 210. As another example, the memory device 200 can receive a read operation command CMD and an address ADDR, read the data stored in the memory cell area corresponding to the address ADDR, and output the read data as output data DATA_OUT.

[0045] In an embodiment, the memory device 200 may include a memory cell array 210, a column decoder 220, a row decoder 230, a write driver / read amplifier 240, an input / output circuit 250, and control logic 260.

[0046] The memory cell array 210 may include a plurality of memory cells MC 211. The plurality of memory cells MC 211 may be placed at the intersection of word lines WL and bit lines BL. The column decoder 220 may select at least one bit line from the plurality of bit lines BL based on the column address CA. The row decoder 230 may activate at least one word line from the plurality of word lines WL based on the row address RA. That is, the row decoder 230 may select at least one word line from the plurality of word lines WL.

[0047] During a write operation, the write driver / read amplifier 240 can send the input data DATA_IN received from the input / output circuit 250 to the column decoder 220. Alternatively or additionally, the write driver / read amplifier 240 can amplify the data received from the column decoder 220 during a read operation and send output data DATA_OUT to the input / output circuit 250. The input / output circuit 250 can transmit the input data DATA_IN to the write driver / read amplifier 240. Alternatively or additionally, the input / output circuit 250 can output the output data DATA_OUT sent from the write driver / read amplifier 240.

[0048] Control logic 260 can receive commands CMD, address ADDR, and clock CLK, and can generate row address RA, column address CA, and control signal CTR. For example, control logic 260 can identify a read command by decoding command CMD and generate row address RA, column address CA, and control signal CTR to read output data DATA_OUT from memory cell array 210. As another example, control logic 260 can identify a read command by decoding command CMD and generate row address RA, column address CA, and control signal CTR to read output data DATA_OUT from memory cell array 210.

[0049] Figure 3A The scheduler is shown based on the comparison example. Figure 3B A scheduler 110 according to an embodiment is shown.

[0050] refer to Figure 3A According to a comparative example, the scheduler can receive masked write requests. For example, a host can request a write operation only for a portion of the data within a DRAM unit. The scheduler can receive a masked write request that requests a write operation while masking the remaining data within the DRAM unit other than the portion for which the request is made. In response to receiving a masked write request, the scheduler can send a command to the memory device (e.g., ...). Figure 1 The memory device 200 sends a mask write command. The mask write command may include write data to be written to a page at a target address and mask data indicating data that will not be written.

[0051] refer to Figure 3BAccording to an embodiment, the scheduler can receive a masked write request. Scheduler 110 can bypass (prevent) the generation of a masked write command in response to the masked write request. Alternatively, scheduler 110 can generate a virtual read command and a normal write command in response to the masked write request. For example, scheduler 110 can add a virtual read command to the scheduling queue. The virtual read command can be and / or can include a command that converts a masked write command into a normal write command. For example, the target address of the virtual read command can be the same as the target address of the masked write request. Scheduler 110 can read the page at the target address of the masked write command using the virtual read command and write only the masked region of the read page into the write buffer. Since the masked write data has already been written into the write buffer, the data stored in the write buffer can match the size of the write data of a general write command by writing the masked region of the read page into the write buffer according to the masked write request. That is, by reading data from the masked region using a virtual read command and writing the read data into the write buffer, the masked write command can be converted into a normal write command. After the bus direction switch is completed and the write phase begins, scheduler 110 can send a normal write command to memory device 200, as shown in the reference. Figure 4 As described.

[0052] Figure 4 This is a flowchart illustrating the operation method of the scheduler 110 according to an embodiment.

[0053] refer to Figure 4 In operation S410, scheduler 110 receives request REQ as command CMD, and can identify the request type in operation S420. For example, request REQ can be any one of a mask write request, a normal write request, or a read request. However, embodiments of this disclosure are not limited thereto, and request REQ can be and / or may include other request types.

[0054] During operation S430, scheduler 110 can update the write command queue. For example, scheduler 110 may have identified the request as a normal write request. In this case, scheduler 110 can update the write command queue by adding a write command to the write command queue in response to the normal write request.

[0055] During operation S440, scheduler 110 can update the write data queue. For example, scheduler 110 can add write data to the write data queue in response to an update of the write command queue.

[0056] During operation S450, scheduler 110 can update the read command queue. For example, scheduler 110 may have identified the request as a read request. In this case, scheduler 110 can update the read command queue by adding a read command to the read command queue in response to the read request.

[0057] During operation S460, scheduler 110 can update the read data queue. For example, in response to an update to the read command queue, scheduler 110 can allocate a region to store data to be read from memory device 200 in the future.

[0058] During operation S470, scheduler 110 can update the write command queue and the read command queue simultaneously. For example, scheduler 110 can identify a request as a masked write request based on mask bits. In this case, scheduler 110 can add a virtual read command to the read command queue in response to the masked write request. The virtual read command can refer to the command used to convert the masked write command into a normal write command.

[0059] In operation S480, scheduler 110 can update the write data queue. When a request is identified as a mask write request, scheduler 110 can allocate a buffer area as if it were a normal write. For example, the DRAM data bandwidth could be 64 bytes, while the mask write data could be 8 bytes. Scheduler 110 can request buffer allocation for write data not only in size corresponding to the mask write data (e.g., 8 bytes) but also in size corresponding to the entire data bandwidth (e.g., 64 bytes). Scheduler 110 can write only the mask write data to the allocated buffer while ensuring the mask area is preserved. Subsequently, scheduler 110 can read the target address page of the mask write command to obtain the data in the mask area. This operation may be intended to achieve access by adding data from the mask area to the mask write data that may have already been written to the buffer, based on a normal write command with data bandwidth.

[0060] In operation S490, scheduler 110 can repeat the operation from operation S410 in the next cycle by incrementing the clock cycle.

[0061] Figure 5A The changes in the command queue according to the embodiment are shown.

[0062] refer to Figure 5A The read command queue (RDQ) and write command queue (WRQ) are shown in chronological order.

[0063] At the first time T1, a read request for memory bank 0 B0 can be received. Scheduler 110 can respond to the read request by adding the read command RD for memory bank 0 B0 to the read command queue RDQ.

[0064] At the second time T2, a mask write request for memory bank 0B0 can be received. Scheduler 110 can add a mask write command MWR to the write command queue WRQ in response to the mask write request.

[0065] Subsequently, according to an embodiment, scheduler 110 can transform masked write commands (MWR) to reduce the tCCDMW penalty of masked write commands. For example, scheduler 110 can generate a virtual read command (dmyRD) for memory bank 0B0 and add the virtual read command (dmyRD) to the read command queue (RDQ). Scheduler 110 can also generate a normal write command (WR) for memory bank 0B0 and add the normal write command (WR) to the write command queue (WRQ).

[0066] Figure 5B An example of a buffer state according to an embodiment is shown.

[0067] refer to Figure 5B State (A) can correspond to the time point at which scheduler 110 receives the mask write request (e.g., Figure 5A (The second time T2). For example, based on a mask write request, scheduler 110 may request the allocation of a buffer region to store the mask write data. Scheduler 110 may request the allocation of a buffer region equal to (or corresponding to) the data bandwidth size, rather than requesting the allocation of a buffer region equal to the mask write data size. Therefore, in state (A), the mask region may correspond to NULL, and the remaining region may be used to write the mask write data MWR DATA.

[0068] State (B) can correspond to the time point at which scheduler 110 completes the virtual read command (e.g., Figure 5A (Second time T2). Scheduler 110 can execute a virtual read command on the target address page of the mask write request. That is, the page to which the mask write data is to be written can be read first and stored in the buffer. Scheduler 110 can write only the data corresponding to the mask region from the read page into the buffer. Therefore, in state (B), the mask region can be filled with the data read by the virtual read command (dmy RD DATA).

[0069] The state (C) can be the point in time when the scheduler 110 transitions from a masked write command to a normal write command (e.g., Figure 5A The third time (T3). That is, the scheduler 110 can treat the virtual read data (dmy RD DATA) of the shielded area and the masked write data (MWR data) of the unshielded area as write data for a general write command. The scheduler 110 can write the write data to the page of the target address according to the converted normal write command.

[0070] Figure 6 This is a flowchart illustrating the operation method of the scheduler 110 according to an embodiment.

[0071] refer to Figure 6 During operation S610, scheduler 110 can identify the current data bus transmission direction. For example, in the case of a read phase, the data bus transmission direction can be from memory device 200 to memory controller 100. As another example, in the case of a write phase, the data bus transmission direction can be from memory controller 100 to memory device 200. In the following text, Figure 6 The stage in S610 can be assumed to be the read stage (READ in operation S610). In operation S610, if the data bus transfer direction is from memory controller 100 to memory device 200 during the write stage, the process can continue to operation S665 (WRITE in operation S610).

[0072] In operation S615, scheduler 110 may search the read command queue RDQ to determine whether a page hit has occurred. A page hit may refer to a situation where the currently open page matches the page at the target address. That is, scheduler 110 may search for a page hit based on page table entries (PTEs). For example, when page 1 of memory bank 0 is open, the valid value of memory bank 0, page 1 in the PTE may be - (1). Scheduler 110 may search for a page hit by comparing whether the target address of the command waiting in the read command queue RDQ is the same as the address with a valid PTE value of - (1). However, embodiments of this disclosure are not limited to this, and the value of the PTE indicating that a page hit has occurred may be a different value than - (1).

[0073] In operation S620, scheduler 110 can determine whether a page hit has occurred. If the target address of a command waiting in the read command queue RDQ does not match a page with a valid PTE value of one (1), scheduler 110 can determine that no page hit has occurred (NO in operation S620). If no page hit has occurred, operation S625 can continue.

[0074] In operation S625, scheduler 110 can determine whether a switch is necessary. A switch can refer to a change in the direction of the data bus. For example, scheduler 110 can determine the necessity of a switch based on various conditions, including but not limited to whether an urgent write command is requested and / or whether the read phase has begun after a threshold time. If a switch is necessary (yes in operation S625), then in operation S627, scheduler 110 can switch the data bus direction and repeat the operation from operation S610 in the next cycle by incrementing the clock cycle in operation S629. According to an embodiment, if a switch is not necessary (no in operation S625), processing can continue to operation S630.

[0075] In operation S630, scheduler 110 can determine whether a page miss has occurred. A page miss can refer to a mismatch between a currently open page and a page at a target address. For example, scheduler 110 can search for a page miss based on the Page Term Expiration (PTE). For example, if page 1 of memory bank 0 is open, the valid value of page 1 in memory bank 0 in the PTE can be - (1). Scheduler 110 can search for a page miss by comparing whether the target address of a command waiting in the read command queue RDQ is different from an address with a valid PTE value of - (1). If there is a mismatch between the target address of a command waiting in the read command queue RDQ and a page with a valid PTE value of - (1), scheduler 110 can determine that a page miss exists. However, embodiments of this disclosure are not limited to this, and the value of the PTE indicating that a page miss has occurred can be a different value than - (1).

[0076] In operation S635, scheduler 110 can activate a new page according to the scheduling policy. That is, since the currently opened page does not match the target address in operation S630, the opened page can be closed, and a new page can be activated and opened. Thereafter, scheduler 110 can repeat operation S610 in the next cycle.

[0077] During operation S640, scheduler 110 can perform data reads according to a scheduling policy. Since a page hit is detected during operation S620, scheduler 110 can execute a read command or a virtual read command according to the scheduling policy. The priority of the virtual read command can be lower than the priority of the (normal) read command. By setting the virtual read command to a lower priority than the read command to handle multiple consecutive masked write requests, this scheduling policy can potentially reduce gaps in the tCCDMW.

[0078] In operation S645, scheduler 110 can determine whether the data being read corresponds to a virtual read command. For example, the data read in operation S640 could be data based on a virtual read command. When reading data via a virtual read command, it may be necessary to determine whether the read data corresponds to the virtual read command because the data mask area may be stored in a buffer. When reading data based on a (normal) read command, the read data queue can be updated by continuing to operation S660. Thereafter, scheduler 110 can repeat operation S610 in the next cycle.

[0079] In operation S650, scheduler 110 can convert masked write commands into normal write commands. For example, when the data read in operation S645 corresponds to a virtual read command, a masked write command waiting in the write command queue can be converted into a normal write command.

[0080] In operation S655, scheduler 110 can update the write data queue. That is, scheduler 110 can update the data corresponding to the masked region of the data read in operation S640 (e.g., Figure 5B The dmy RDDATA in state (B) is written to the buffer. Additionally, when a mask write command is input to the buffer, the mask write data (e.g., Figure 5B The MWR DATA in state (A) may have already been written to the unmasked area. Scheduler 110 may additionally merge the virtual read data dmy RD DATA corresponding to the masked area into the masked write data MWRDATA previously stored in the buffer, and set the merged masked write data as the write data for the normal write command. Thereafter, scheduler 110 may repeat operation S610 in the next cycle. According to various embodiments, when the data bus switches from the read phase to the write phase, scheduler 110 may write the write data of the write data queue to the memory device 200 according to the normal write command, which may have been updated in operation S655. For example, the write data may be the following: the virtual read data dmy RD DATA corresponding to the masked area may be additionally merged into the masked write data MWR DATA that may have been previously stored in the buffer. That is, the masked write command with tCCDMW penalty may not be processed directly, but may be converted into virtual read commands and normal write commands, each with only tCCD delay, so that the same data can be written to the memory device 200.

[0081] In operation S665, scheduler 110 can search the write command queue WRQ for page hits. A page hit can refer to a situation where the currently open page matches the page at the target address. For example, scheduler 110 can search for page hits based on the PTE. For example, if memory bank 0 and page 1 are open, the valid value of memory bank 0 and page 1 in the PTE can be one (1). Scheduler 110 can search for page hits by comparing whether the target address of the command waiting in the write command queue WRQ is the same as the address with a valid PTE value of one (1).

[0082] In operation S670, scheduler 110 can determine whether a page hit has occurred. If the target address of a command waiting in the write command queue WRQ does not match a page with a valid PTE value of one (1), scheduler 110 can determine that no page hit has occurred. When no page hit has occurred, processing can continue to operation S685.

[0083] In operation S685, scheduler 110 can determine whether a switch is needed. A switch can refer to a change in the direction of the data bus. For example, scheduler 110 can determine whether a switch is needed based on various conditions, including but not limited to whether an urgent read command has been requested and / or whether a write phase has begun after a threshold time. If a switch is needed (yes in operation S685), scheduler 110 can switch the data bus direction in operation S627 and repeat the operation from operation S610 in the next cycle by incrementing the clock cycle in operation S629. According to an embodiment, if a switch is not needed (no in operation S685), processing can continue to operation S690.

[0084] In operation S690, scheduler 110 can determine whether a page miss has occurred. A page miss can refer to a mismatch between a currently open page and a page at a target address. For example, scheduler 110 can search for a page miss based on the Page Term Expiration (PTE). For example, if page 1 of memory bank 0 is open, the valid value of memory bank 0 and page 1 in the PTE can be one (1). Scheduler 110 can search for a page miss by comparing whether the target address of a command waiting in the write command queue (WRQ) is different from an address with a valid PTE value of one (1). If there is a mismatch between the target address of a command waiting in the write command queue (WRQ) and a page with a valid PTE value of one (1), scheduler 110 can determine that a page miss exists.

[0085] In operation S695, scheduler 110 can activate a new page according to the scheduling policy. That is, since the currently open page does not match the target address in operation S690, the open page can be closed, and a new page can be activated and opened. Thereafter, scheduler 110 can repeat operation S610 in the next cycle.

[0086] During operation S675, scheduler 110 can execute data writes according to the scheduling policy. Since a page hit is detected in operation S670, scheduler 110 can execute write commands according to the scheduling policy. (Depending on...) Figure 5B In state (B), the write data written to memory device 200 according to the write command may correspond to the write data of the general write command, or the write data may be the write data generated by merging the data dmy RDDATA read by the virtual read command in the previous cycle with the mask write command data MWR DATA.

[0087] During operation of S680, scheduler 110 can update the write data queue. As write data waiting in the write data queue is written to memory device 200, the corresponding buffer area can be deallocated and flushed.

[0088] Figure 7 The command processing sequence based on the comparison example is shown.

[0089] Figure 7 The diagram illustrates the state of eight (8) pending commands in the queue for memory bank 0 B0. For example, at a first time point T1, there may be four (4) read commands RD (4) queued for memory bank B0 (e.g., first read command B0: R1, second read command B0: R2, third read command B0: R3, and fourth read command B0: R4). At a second time point T2, four (4) masked write commands MRW (4) for memory bank 0 B0 (e.g., first masked write command B0: MWR1, second masked write command B0: MWR2, third masked write command B0: MWR3, and fourth masked write command B0: MWR4) may be waiting in the queue.

[0090] According to the comparative example, mask write commands can be processed without converting them into virtual read commands and normal write commands. In this case, four (4) read commands requested first from time a to time b (e.g., first read command B0:R1 to fourth read command B0:R4) can be executed sequentially. At time b, the data bus may be in the read phase. Subsequently, in order to execute the mask write command, scheduler 110 may need to perform a switching TRN to change to the write phase.

[0091] According to the comparative example, four (4) masked write commands (e.g., the first masked write command B0:MWR1 to the fourth masked write command B0:MWR4) can be executed sequentially during time c to time d. However, since the command-to-command delay tCCDMW of the masked write command is significantly longer than the command-to-command delay tCCD of the normal write command (e.g., four (4) times longer), gaps may occur between the masked write commands.

[0092] Figure 8 A command processing sequence according to an embodiment is shown.

[0093] Figure 8 The diagram illustrates a state where eight (8) commands are queued and waiting for memory bank 0 (B0). For example, at a first time point T1, there may be four (4) read commands RD (4) queued for memory bank 0 (B0) (e.g., first read command B0: R1, second read command B0: R2, third read command B0: R3, and fourth read command B0: R4). At a second time point T2, four masked write commands MRW (4) for memory bank 0 (B0) (e.g., first masked write command B0: MWR1, second masked write command B0: MWR2, third masked write command B0: MWR3, and fourth masked write command B0: MWR4) may be waiting in the queue.

[0094] According to the example, a masked write command can be converted into a virtual read command and a normal write command. Therefore, four (4) virtual read commands (e.g., first virtual read command B0: dmyR1, second virtual read command B0: dmyR2, third virtual read command B0: dmyR3 and fourth virtual read command B0: dmyR4) and four (4) normal write commands (e.g., first normal write command B0: W1, second normal write command B0: W2, third normal write command B0: W3 and fourth normal write command B0: W4) can be added to the scheduling queue.

[0095] According to an embodiment, the previously requested first read command B0:R1 to the fourth read command B0:R4 can be executed sequentially from time a to time b. Figure 7Unlike the previous example, since the first virtual read command B0:dmyR1 to the fourth virtual read command B0:dmyR4 should be executed, a switch at time b may not be necessary. Therefore, the first virtual read commands B0:dmyR1 to the fourth virtual read commands B0:dmyR4 added to the scheduling queue can be executed sequentially from time b to time c. The interval between the first virtual read commands B0:dmyR1 to the fourth virtual read commands B0:dmyR4 can be tCCD. When the processing of the first read commands B0:R1 to the fourth read commands B0:R4 and the first virtual read commands B0:dmyR1 to the fourth virtual read commands B0:dmyR4 is completed at time c, a time switch TRN can be executed to change to the write phase so that the first normal write commands B0:W1 to the fourth normal write commands B0:W4 can be executed.

[0096] According to an embodiment, the first normal write command B0:W1 to the fourth normal write command B0:W4 can be executed sequentially during time d to time e. Also refer to... Figure 5B It is likely obvious that the write data written by a normal write command can be obtained by merging the masked areas of the read data corresponding to the first virtual read command B0:dmyR1 to the fourth virtual read command B0:dmyR4 with the first masked write data to the fourth masked write data MWR (4). Figure 7 Compared to the comparison examples in [reference], Figure 8 The described embodiments enable faster processing of mask write commands by translating and processing mask write commands into virtual read commands and normal write commands. For example, when processing mask write commands, the latency tCCDMW may be relatively long (e.g., tCCDMW = 4 × tCCD), depending on the relevant memory controller. However, when as referenced... Figure 7 When processing masked write commands in a descriptive manner, the latency tCCDMW may be relatively short (e.g., tCCDMW = 2 × tCCD), which may be equal to the sum of the processing times of virtual read commands (e.g., one of the first virtual read commands B0:dmyR1 to the fourth virtual read commands B0:dmyR4) and normal write commands (e.g., one of the first normal write commands B0:W1 to the fourth normal write commands B0:W4).

[0097] According to an embodiment, when... Figure 8 The reduction in processing time when repeatedly processing mask write and read requests targeting different regions of the same page can be represented by an equation similar to Equation 1.

[0098] [Equation 1]

[0099] Refer to Equation 1, It can represent the number of read commands, and It can represent the number of mask write commands, and This can represent the command-to-command latency. If the number of requests is large enough, the latency caused by DRAM scheduling, such as but not limited to activation, precharge, refresh time, and bus switching time, can be reduced and / or decreased, and can eventually converge to the rate given by Equation 1.

[0100] refer to Figure 8 According to the embodiment, it can be observed that by converting the first mask write command to the fourth mask write command B0:MWR1 to B0:MWR4 into the first virtual read command B0:R1 to the fourth virtual read command B0:R4 and the first normal write command B0:W1 to the fourth normal write command B0:W4, the processing of eight (8) commands can be completed with the processing of... Figure 7 The time taken for the eight (8) commands is 5 × tCCD faster than that of the previous commands. Figure 7 In contrast, it may be apparent that completing the process can be 9 × tCCD faster (e.g., 3 × (3 × tCCD)) due to the removal of three (3) gaps (e.g., each gap has a duration of 3 × tCCD). However, since executing four (4) additional virtual read commands consumes 4 × tCCD, it may be apparent that the final completion of the process can be 5 × tCCD faster (e.g., 9 × tCCD – 4 × tCCD = 5 × tCCD). However, embodiments of this disclosure are not limited to this example, and as described above with reference to Equation 1, other time savings can be achieved depending on the number of read commands and the number of mask write commands.

[0101] Figure 9 This is a block diagram of a system 2000 having an electronic device including a memory device, according to a root embodiment.

[0102] refer to Figure 9System 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, multiple dynamic random access memories (DRAMs) (e.g., a first DRAM 2500a and a second DRAM 2500b), multiple flash memory devices (e.g., a first flash memory device 2600a and a second flash memory device 2600b), multiple input / output (I / O) devices (e.g., a first I / O device 2700a and a second I / O device 2700b), and an application processor (AP) 2800. System 2000 may be implemented as a laptop computer, mobile phone, smartphone, tablet PC, wearable device, healthcare device, Internet of Things (IoT) device, etc. Additionally or alternatively, system 2000 may be implemented as a server or personal computer. However, embodiments of this disclosure are not limited thereto, and system 2000 may be implemented as other electronic devices. It is worth noting that system 2000 may include components as referenced above. Figures 1 to 8 The memory controller 100 described can be implemented by any electronic device.

[0103] Camera 2100 can capture still and / or moving images under user control and store the captured images or send them to display 2200. Audio processor 2300 can process audio data included in the content of multiple flash memory devices 2600a to 2600b and / or a network. Modem 2400 can perform wired and / or wireless data transmission and / or reception, wherein the transmitting component can modulate and transmit signals, and the receiving component can perform demodulation to recover the original signal from the received signal. Multiple I / O devices 2700a to 2700b may include I / O devices that provide digital input and / or output capabilities, such as, but not limited to, Universal Serial Bus (USB), storage devices, digital cameras, Secure Digital (SD) cards, Digital Universal Optical Disc (DVD), network adapters, touch screens, etc.

[0104] AP 2800 can control the overall operation of system 2000. AP 2800 may include controller block 2810, accelerator block or accelerator chip 2820, and interface block 2830. AP 2800 can control display 2200 so that a portion of the contents stored in multiple flash memory devices 2600a to 2600b can be displayed on display 2200. When user input is received through multiple I / O devices 2700a to 2700b, AP 2800 can perform control operations corresponding to the user input. AP 2800 may include accelerator block 2820, which may be and / or may include dedicated circuitry for artificial intelligence (AI) data processing, and / or may have an accelerator block or accelerator chip 2820 separate from AP 2800. In addition, DRAM 2500b may be mounted on accelerator block or accelerator chip 2820. Accelerator block 2820 may be and / or may include function blocks specifically performing specific functions of AP 2800. For example, accelerator block 2820 may be and / or may include a graphics processing unit (GPU), which may be a processing block dedicated to performing graphics data processing; a neural processing unit (NPU), which may be a processing block dedicated to performing AI computation and inference; a data processing unit (DPU), which may be a processing block dedicated to performing data transmission, and so on.

[0105] System 2000 may include multiple DRAMs 2500a to 2500b. AP 2800 can control the multiple DRAMs 2500a to 2500b using command and / or mode register (MRS) settings conforming to one or more memory module standards, such as, but not limited to, Joint Electronic Devices Engineering Committee (JEDEC) standards. Alternatively or additionally, AP 2800 can communicate with the multiple DRAMs 2500a to 2500b by configuring a DRAM interface protocol to utilize proprietary features such as, but not limited to, low-voltage operation, high-speed processing, enhanced reliability and / or data integrity mechanisms (e.g., Cyclic Redundancy Check (CRC) and ECC). For example, AP 2800 can communicate with a first DRAM 2500a via an interface that may conform to one or more JEDEC standards, such as, but not limited to, Low Power Double Data Rate 4 (LPDDR4) and Low Power Double Data Rate 5 (LPDDR5). As another example, the accelerator block or accelerator chip 2820 can communicate with the first DRAM 2500a by configuring a new DRAM interface specification to control the second DRAM 2500b used by the accelerator block 2820, which can support higher bandwidth (e.g., transfer speed) than the first DRAM 2500a.

[0106] although Figure 9Two DRAMs (e.g., a first DRAM 2500a and a second DRAM 2500b) are shown, but embodiments of this disclosure are not limited thereto, and multiple DRAMs may include additional memory devices. That is, multiple DRAM devices may include any memory type, such as, but not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), or hybrid random access memory (RAM). It is noteworthy that any memory type can be used, provided the memory devices meet the bandwidth, response speed, and / or voltage requirements of the AP 2800 or the accelerator block or accelerator chip 2820. Multiple DRAMs 2500a to 2500b may have relatively lower latency and / or bandwidth compared to multiple I / O devices 2700a to 2700b and / or multiple flash memory devices 2600a to 2600b. When the system 2000 is powered on, multiple DRAMs 2500a to 2500b can be initialized, and operating system and / or application data can be loaded, so that the multiple DRAMs 2500a to 2500b can be used as temporary storage for operating system and / or application data and / or as execution space for various software code.

[0107] Arithmetic operations, such as, but not limited to, addition, subtraction, multiplication, and division, as well as vector operations, address operations, and Fast Fourier Transform (FFT) operations, can be performed in multiple DRAMs 2500a to 2500b. Additionally, functions for performing inference can be executed within the multiple DRAMs 2500a to 2500b. As used herein, inference can be performed using a deep learning algorithm with an artificial neural network. The deep learning algorithm may include: a training step in which a model can be learned from various data; and an inference step in which the learned model can be used to identify data. In an embodiment, an image captured by a user via camera 2100 can be signal-processed and stored in DRAM 2500b, and an accelerator block or accelerator chip 2820 can perform AI data operations to identify data using data stored in a second DRAM 2500b, and a function can be used for inference.

[0108] System 2000 may include multiple storage devices and / or multiple flash memory devices 2600a to 2600b, which may have a larger capacity than multiple DRAMs 2500a to 2500b. Accelerator block or accelerator chip 2820 may use the multiple flash memory devices 2600a to 2600b to perform training steps and AI data operations. In embodiments, each of the multiple flash memory devices 2600a to 2600b may include a memory controller 2610 and a flash memory device 2620, and the training steps and inference AI data operations performed by AP 2800 and / or accelerator block or accelerator chip 2820 may be performed more efficiently by using the computing devices provided in memory controller 2610. The multiple flash memory devices 2600a to 2600b may store images captured by camera 2100 and / or data transmitted via a data network. For example, augmented reality (AR) / virtual reality (VR), high-definition (HD), and / or ultra-high-definition (UHD) content may be stored.

[0109] In System 2000, multiple DRAMs 2500a to 2500b can execute reference... Figures 1 to 8 The described method for processing masked write commands may include the following operations: receiving a masked write request from a host; generating a virtual read command for the target address of the masked write request in response to the masked write request; converting the masked write request into a normal write command in response to processing the virtual read command; and executing the normal write command.

[0110] Figure 10 This is a block diagram of a memory controller 1000 according to an embodiment.

[0111] refer to Figure 10 The memory controller 1000 includes a buffer memory 1010, one or more processors 1020 including processing circuitry, and a memory 1030 storing instructions. According to an embodiment, when executed individually or jointly by one or more processors, the instructions cause the memory controller 1000 to receive a mask write request from a host; generate a virtual read command for the target address of the mask write request; and, based on processing of the virtual read command, convert the mask write request into a normal write command. According to an embodiment, the memory controller 1000 can perform reference... Figures 1 to 8 The method described is for processing mask writing commands.

[0112] Figure 11 This is a block diagram of a memory system 1100 according to an embodiment.

[0113] refer to Figure 11The memory system 1100 includes: a host device 1110 configured to generate a mask write request, the mask write request including mask write data and mask bits indicating a masked area; and a memory device 1120 including a memory controller 1130, the memory controller 1130 including one or more dynamic random access memories (DRAM) 1131, one or more buffer memories 1132, and a scheduler 1133. According to an embodiment, the memory controller 1130 may be configured to: receive a mask write request from the host device 1110; generate a virtual read command for the target address of the mask write request; and, based on processing of the virtual read command, convert the mask write request into a normal write command. According to an embodiment, the memory controller 1130 may perform reference... Figures 1 to 8 The method described is for processing mask writing commands.

[0114] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A method for operating a memory controller, the method comprising: Receive mask write requests from the host; Generate a virtual read command for the target address of the mask write request; Based on the processing of the virtual read command, the mask write request is converted into a normal write command; as well as Execute the normal write command.

2. The operating method according to claim 1 further includes: Based on the receipt of the mask write request, a request is made to allocate a buffer area in the buffer, the buffer area having a size corresponding to the data bandwidth; as well as Write the first data corresponding to the mask write data of the mask write request into the non-mask area of ​​the buffer region.

3. The operating method according to claim 2, wherein, The transformation of the mask write request includes: Determine whether a page hit has occurred at the target address based on page table entries.

4. The operating method according to claim 3, wherein, The transformation of the mask write request further includes: Based on the determination that a page hit has occurred, the read data is obtained by executing the virtual read command on the target address; and Write the second data corresponding to the shielding area of ​​the read data into the shielding area of ​​the buffer area.

5. The operating method according to claim 4, wherein, The execution of the normal write command includes: The first data and the second data stored in the buffer area are written to the target address.

6. The operating method according to claim 5 further includes: The write operation based on the first data and the second data is completed, the buffer is released, and the buffer area is flushed.

7. The operating method according to claim 1, wherein, The priority of the virtual read command is lower than that of the normal read command.

8. A memory controller, comprising: Buffer memory; One or more processors, including processing circuitry; as well as Memory for storing instructions Wherein, when the instructions are executed individually or jointly by the one or more processors, the memory controller: Receive mask write requests from the host; Generate a virtual read command for the target address of the mask write request; and Based on the processing of the virtual read command, the mask write request is converted into a normal write command.

9. The memory controller according to claim 8, wherein, When the instructions are executed individually or jointly by the one or more processors, the memory controller is also caused to: Based on the received mask write request, a request is made to allocate a buffer area in the buffer memory, the buffer area having a size corresponding to the data bandwidth; as well as Write the first data corresponding to the mask write data of the mask write request into the non-mask area of ​​the buffer region.

10. The memory controller according to claim 9, wherein, When the instructions are executed individually or jointly by the one or more processors, the memory controller is also caused to: Determine whether a page hit has occurred at the target address based on page table entries.

11. The memory controller according to claim 10, wherein, When the instructions are executed individually or jointly by the one or more processors, the memory controller is also caused to: Based on the determination that the page hit has occurred, the read data is obtained by executing the virtual read command on the target address; as well as Write the second data corresponding to the read data into the shielded area of ​​the buffer area.

12. The memory controller according to claim 11, wherein, When the instructions are executed individually or jointly by the one or more processors, the memory controller is also caused to: The first data and the second data stored in the buffer area are written to the target address.

13. The memory controller according to claim 12, wherein, When the instructions are executed individually or jointly by the one or more processors, the memory controller is also caused to: The write operation based on the first data and the second data is completed, the buffer is released, and the buffer area is flushed.

14. The memory controller according to claim 8, wherein, The priority of the virtual read command is lower than that of the normal read command.

15. A memory system, comprising: The host device is configured to generate a mask write request, the mask write request including mask write data and mask bits indicating the masking area; as well as A memory device including a memory controller, the memory controller comprising one or more dynamic random access memories (DRAM), one or more buffer memories, and a scheduler. The memory controller is configured as follows: Receive the mask write request from the host device. Generate a virtual read command for the target address of the mask write request; as well as Based on the processing of the virtual read command, the mask write request is converted into a normal write command.

16. The memory system according to claim 15, wherein, The memory controller is also configured to: Based on the received mask write request, a request is made to allocate a buffer region in the one or more buffer memories, the buffer region having a size corresponding to the data bandwidth, and Write first data corresponding to the mask write data of the mask write request into the non-mask area of ​​the buffer region.

17. The memory system according to claim 16, wherein, The scheduler is configured as follows: Determine whether a page hit has occurred at the target address based on page table entries. Based on the determination that a page hit has occurred, the virtual read command is executed on the target address to obtain the read data, and Write the second data corresponding to the read data into the shielding area of ​​the buffer area.

18. The memory system according to claim 17, wherein, The memory controller is also configured to: The first data and the second data stored in the buffer area are written to the target address.

19. The memory system according to claim 18, wherein, The memory controller is also configured to: The write operation based on the first data and the second data is completed, the buffer is released, and the buffer area is flushed.

20. The memory system according to claim 15, wherein, The priority of the virtual read command is lower than that of the normal read command.

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