An edge computing storage module based on an external computing power chip and a data processing method thereof

Abstract

The application discloses an edge computing storage module based on an external computing power chip, and relates to the technical field of computer storage and edge computing.The module comprises a host end, a data stream identification module, an external NPU chip, a hardware bypass switch and a flash memory array.The data stream identification module is used for identifying the type of input data and controlling the data flow direction; when the data is identified as AI computing data, the data is transmitted to the external NPU chip through the host end for computing and processing; when the data is identified as ordinary storage data or the external NPU chip is in a fault state, the hardware bypass switch is automatically turned on, and the data bypasses the NPU chip and is directly transmitted to the flash memory array.The application realizes the fusion of storage function and AI computing function by externally mounting the NPU chip on the basis of the standard storage module and setting the hardware bypass switch, guarantees the reliability of data transmission when the NPU is in a fault state, is compatible with the existing storage interface standard, and reduces the deployment cost and complexity of the edge computing device.

Description

Technical Field

[0001] This invention relates to the fields of computer storage and artificial intelligence hardware technology, specifically to a storage module architecture that connects independent processing units in series in a standard storage interface link, belonging to the fields of edge computing, storage-computing collaboration and embedded hardware design technology. Background Technology

[0002] As artificial intelligence (AI) moves to the edge, various terminal devices (such as surveillance cameras, industrial sensors, and smart wearables) generate massive amounts of data. Current technologies typically rely on external CPUs or cloud servers to process this data, resulting in high bandwidth consumption, large transmission latency, and high risks of privacy breaches. To address these issues, the industry has proposed "in-memory computing" technology. However, existing in-memory computing solutions mainly fall into two categories: Wafer-level in-memory computing (CIM): Integrating computing units inside memory chips or in a 3D stacked structure. While this technology offers superior performance, it requires changes to semiconductor manufacturing processes, incurs extremely high R&D costs, and is difficult to integrate with existing mature production lines.

[0003] Intelligent controller integration: This involves integrating an AI acceleration core within the SSD controller chip. While this approach achieves local processing, the coupling of computing power and storage control functions leads to complex controller chip design, high heat generation, and significant data recovery difficulties should the controller fail. Furthermore, computing power cannot be independently upgraded; if AI algorithms iterate, the entire storage device often needs to be replaced. Therefore, there is an urgent need for a storage module architecture that can achieve local edge computing while maintaining low R&D costs, high compatibility, and support for independent computing power upgrades. Summary of the Invention

[0004] The purpose of this invention is to provide an edge computing storage module based on an external computing chip. By seamlessly embedding independent computing power into the data transmission link without changing the existing storage chips and standard interface protocols, it solves the problems of high cost, high coupling, and difficult upgrades of existing integrated storage and computing solutions. Technical solution

[0005] To achieve the above objectives, the present invention provides the following technical solution: An edge computing storage module based on an external computing chip includes a PCB substrate, a flash memory storage medium array disposed on the PCB substrate, a standard external interface, and a storage control circuit. The module is characterized in that it further includes an independent edge computing processing unit (NPU). The edge computing processing unit (NPU) is configured in a bypass or series manner on the data transmission path of the storage control circuit; The edge computing processing unit (NPU) is equipped with a data flow identification module for monitoring the data packets flowing through it; When a normal read / write command is detected, the edge computing processing unit (NPU) is in pass-through mode, and the data passes through directly; When an AI processing instruction or specific feature data is detected, the edge computing processing unit (NPU) switches to computing mode, intercepts the data, completes inference operations locally, and outputs the results through the standard external interface.

[0006] Furthermore, the edge computing processing unit (NPU) can be detachably mounted on the PCB substrate via a micro-socket, enabling independent replacement and upgrade of the computing hardware without replacing the storage medium.

[0007] Furthermore, the module also includes a hardware bypass switch that automatically closes when the edge computing processing unit (NPU) is in a power-off or faulty state, physically connecting the data path between the storage medium and the standard external interface to ensure the basic availability of the storage function. Beneficial effects

[0008] Compared with the prior art, the present invention has the following significant advantages: Decoupled architecture, extremely low cost: Adopting a board-level external design, it eliminates the need for custom-made expensive in-memory computing wafers. It can be assembled using mature NPU chips and standard NAND Flash, significantly reducing the R&D and manufacturing barriers.

[0009] Flexible upgrades and long lifespan: The computing unit and storage unit are physically separated. When the AI ​​algorithm needs to be upgraded to require stronger computing power, only the NPU submodule needs to be replaced, without discarding the storage medium, which is in line with the concept of green computing.

[0010] Data security with a safety net: The unique hardware bypass design ensures that even if the AI ​​function fails, the device can still be used as a standard storage disk, avoiding the risk of data loss due to a single point of failure.

[0011] Wide compatibility: It maintains consistency with standard interface (such as SATA / PCIe) protocols and can seamlessly replace ordinary hard drives in existing terminals, making it plug-and-play. Attached Figure Description

[0012] Figure 1 A schematic diagram of the edge computing storage module architecture and data flow based on an external computing chip. Detailed Implementation

[0013] The following is in conjunction with the appendix Figure 1 The technical principles and specific implementation methods of the present invention will be described in detail.

[0014] Example 1: Hardware Architecture and Connection Relationships like Figure 1 As shown, this embodiment proposes an edge computing storage module based on an external computing chip. This module is built on a standard PCB circuit board, and its core architecture includes three main parts: Standard external interfaces (such as) Figure 1 (As shown on the left): Used to connect to external hosts (such as computers, servers, or industrial control computers), supporting standard communication protocols such as SATA, PCIe, or USB.

[0015] Non-volatile storage media arrays (such as Figure 1 (As shown on the right): Used for persistent data storage, it is usually composed of multiple NAND Flash memory chips.

[0016] Intelligent data bridging module (such as) Figure 1 (As shown in the middle section): This is the core innovative area of ​​the present invention.

[0017] The intelligent data bridging module is equipped with an independent external NPU chip and a hardware bypass switch.

[0018] The independent external NPU chip is not directly integrated into the storage controller, but is connected in series in the data transmission link as an independent processing node through PCB traces.

[0019] The hardware bypass switch forms a parallel or on / off control relationship with the NPU chip. In normal AI working mode, data flows through the NPU for processing; when the NPU fails, loses power, or the user disables the AI ​​function, the hardware bypass switch closes, "short-circuiting" the NPU from the link, allowing data to pass directly, ensuring that the storage module degenerates into a regular standard hard drive, and guaranteeing that the basic data read and write functions are not lost.

[0020] Example 2: Data Processing Flow (in conjunction with...) Figure 1 (The arrow in the middle flows) Combination Figure 1 The data flow arrows in the diagram indicate the working logic of this module as follows: Data reception and identification: When an external host writes data through a standard external interface, the data first enters the intelligent data bridging module. The controller within the module (or the traffic management unit built into the NPU) monitors the header information or logical block address (LBA) of the data packets in real time.

[0021] Dual-mode switching: Mode 1: Transparent Transmission Mode (Normal Data) like Figure 1As shown in the lower middle path, if the data is identified as a regular file (such as a document or system file), or if the NPU is in a sleep state, the data stream will pass directly through the hardware bypass channel, without performing any AI calculations, and be directly written to the non-volatile storage medium array. This process does not add any additional latency.

[0022] Mode 2: Edge Computing Mode (AI Data) like Figure 1 As shown in the upper middle path, if the data is identified as a specific type of video stream or sensor data (through a preset LBA range or instruction marker), the data stream is directed to a separate external NPU chip.

[0023] Local Inference and Result Writeback After receiving data, the NPU chip calls the built-in lightweight AI models (such as face detection and abnormal sound recognition models) to perform inference.

[0024] Result A: If no anomaly is detected, the NPU instruction storage medium directly stores the original data (or discards it according to the policy).

[0025] Result B: If an anomaly is detected (such as intrusion), the NPU generates a "metadata tag" or "alarm log" and writes it to a specific sector of the storage medium, while selectively storing keyframe images separately.

[0026] Example 3: Physical Implementation and Upgrade In terms of physical implementation, such as Figure 1 The "independent external NPU chip" shown is not directly soldered onto the PCB board, but rather installed via a board-to-board connector or micro-socket. This means that when future AI algorithms are upgraded (for example, from recognizing "faces" to recognizing "human postures"), requiring stronger computing power, users do not need to replace the entire storage module. They can simply remove the old NPU chip and insert the new one, just like replacing RAM, to upgrade the hardware computing power. This design perfectly solves the pain point of traditional embedded devices' inability to iterate computing power.

Claims

1. An edge computing storage module based on an external computing chip, comprising a PCB substrate, a non-volatile storage medium array disposed on the PCB substrate, and a standard external interface, characterized in that: The module also includes a separate edge computing processing unit (NPU). The edge computing processing unit (NPU) is located on the data transmission link between the non-volatile storage medium array and the standard external interface; The edge computing processing unit (NPU) is configured to identify the data flowing through it without changing the standard external interface communication protocol, and to perform data pass-through or local computing operations based on the identification results.

2. The storage module according to claim 1, characterized in that: The edge computing processing unit (NPU) is mounted on the PCB substrate via a detachable connector, which includes a micro socket, a board-to-board connector, or a gold finger slot.

3. The storage module according to claim 1, characterized in that: The module also includes a hardware bypass circuit; the hardware bypass circuit is connected in parallel with the edge computing processing unit (NPU); when the edge computing processing unit (NPU) is not powered on or is in a reset state, the hardware bypass circuit is turned on, physically connecting the non-volatile storage medium array and the standard external interface.

4. The storage module according to claim 1, characterized in that: The edge computing processing unit (NPU) includes a data flow identification module, which is used to monitor the logical block address (LBA) range or specific instruction set of data packets; When LBA is within the preset AI calculation range, a local calculation operation is triggered; When the LBA is located in the normal storage area, a data pass-through operation is triggered.

5. A data processing method based on the storage module according to any one of claims 1-4, characterized in that, Includes the following steps: Step S1: The host sends a data write request through the standard external interface; Step S2: The edge computing processing unit (NPU) intercepts the write request and parses the data packet header information; Step S3: If the parsing result is ordinary data, it is directly passed through to the non-volatile storage medium array for storage; Step S4: If the parsing result is data to be processed, the data is temporarily stored in the NPU on-chip cache, the built-in AI model is called for inference, and the metadata generated by the inference is written to the non-volatile storage medium array, or an interrupt signal is directly returned to the host.

6. The method according to claim 5, characterized in that: In step S4, if an abnormal alarm signal is generated by inference, the NPU sends a high-priority interrupt to the external device through the sideband signal pin. The sideband signal pin reuses a reserved pin or a power management pin in the standard external interface.

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