Method, device and equipment for BMC intelligent generation of BIOS and storage medium

Abstract

The application discloses a BMC intelligent generation BIOS method, device, equipment and storage medium, the method is through compiling the binary efi file of the basic input output system BIOS module of multiple platforms in advance in the substrate management controller BMC side database, each efi file provides an external interface for receiving motherboard configuration information;After the BMC is started, the corresponding target BIOS module is selected according to the motherboard component information, and the motherboard configuration information is dynamically written into the target BIOS module through the external interface;The target BIOS module that writes the motherboard configuration information is packaged to generate BIOS firmware through the BMC, and the BIOS firmware is written into the BIOS Flash chip through the serial peripheral interface SPI channel to complete BIOS deployment;Different hardware configuration servers can be automatically generated to adapt to the BIOS firmware, and the automation degree and efficiency of server firmware deployment are improved.

Description

Technical Field

[0001] This invention relates to the field of server hardware management technology, and in particular to a method, apparatus, device, and storage medium for intelligent BIOS generation via BMC. Background Technology

[0002] With the rapid development and widespread application of new-generation information technologies such as cloud computing, big data, and artificial intelligence, the market demand for server systems has experienced explosive growth, and the product update and iteration cycle is constantly shortening.

[0003] Against this backdrop, the workload of developing and maintaining the Basic Input / Output System (BIOS), which is the core firmware of server systems, has increased significantly, and the demand for BIOS engineers has also risen sharply.

[0004] However, my country is severely lacking in BIOS engineers. According to statistics, there are only about 1,000 BIOS engineers in the country, of which fewer than 200 are technical personnel with core development capabilities.

[0005] BIOS development is a highly specialized field with a very high technical threshold. Engineers typically need at least three years of systematic learning and practice to master the relevant skills.

[0006] At the same time, with the rapid expansion of the domestic chip industry, the demand for BIOS development adapted to different hardware platforms continues to increase. However, the training cycle for BIOS engineers is long and their growth rate is slow, resulting in a huge gap between talent supply and market demand. This talent shortage has become a bottleneck restricting the development of the server industry, seriously affecting the R&D progress and market competitiveness of domestic server products. It is urgent to alleviate the shortage of BIOS engineer resources through technological innovation. Summary of the Invention

[0007] The main objective of this invention is to provide a method, apparatus, device, and storage medium for intelligent BIOS generation by BMC, aiming to solve the technical problems of BIOS engineer shortage and long training cycle in the prior art, and the surge in server demand which requires engineers to manually modify code and recompile for different hardware configurations in traditional BIOS development, resulting in low work efficiency and difficulty in meeting the needs of rapid iteration.

[0008] In a first aspect, the present invention provides a method for intelligently generating a BIOS using a BMC, the method comprising the following steps: The binary EFI files compiled from the multi-platform Basic Input / Output System BIOS module are pre-stored in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information. After the BMC is powered on, it collects motherboard component information, selects the corresponding target BIOS module based on the motherboard component information, and dynamically writes the motherboard configuration information into the target BIOS module through the external interface. The target BIOS module, which contains the motherboard configuration information, is packaged by the BMC to generate BIOS firmware. The BIOS firmware is then flashed into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete the BIOS deployment.

[0009] Optionally, the binary EFI files compiled from the multi-platform Basic Input / Output System (BIOS) module are pre-stored in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information, including: The binary EFI files compiled from the multi-platform Basic Input / Output System (BIOS) module are pre-stored in the Baseboard Management Controller (BMC) side database. The BMC side database pre-stores BIOS module package files for different CPU architectures, and each EFI file provides an external interface for receiving motherboard configuration information.

[0010] Optionally, after the BMC is powered on, collecting motherboard component information, selecting the corresponding target BIOS module based on the motherboard component information, and dynamically writing the motherboard configuration information into the target BIOS module through the external interface includes: After the BMC is powered on, it actively scans and reads the EEPROM of each hardware module through the I2C bus to collect motherboard component information of each key component of the motherboard. The motherboard component information is intelligently matched with the multi-platform BIOS modules pre-stored in the BMC side database to determine the target BIOS module; The collected motherboard configuration information is dynamically written into the corresponding initialization area of ​​the target BIOS module through the external interface.

[0011] Optionally, the step of intelligently matching the motherboard component information with multi-platform BIOS modules pre-stored in the BMC-side database to determine the target BIOS module includes: The motherboard component information is intelligently matched with the multi-platform BIOS modules pre-stored in the BMC side database. The BIOS CRB module of the corresponding platform is determined according to the CPU platform information, the BIOS module version of the corresponding generation is selected according to the CPU generation, the PCIe lane topology scheme is determined according to the Riser information, the memory SPD address information is determined according to the memory topology information, and the GPIO initialization configuration is determined according to the GPIO information. The target BIOS module is determined based on the BIOS CRB module, the BIOS module version, the PCIe lane topology, the memory SPD address information, and the GPIO initialization configuration.

[0012] Optionally, dynamically writing the collected motherboard configuration information into the corresponding initialization area of ​​the target BIOS module through the external interface includes: The CPU platform information from the collected motherboard configuration information is written into the CPU initialization module of the target BIOS module using tool instructions and EFI binary files through the external interface. The memory topology information in the motherboard configuration information is written into the memory initialization module of the target BIOS module using the tool instructions and the EFI binary file through the external interface. The Riser information in the motherboard configuration information is written into the PCIe initialization module of the target BIOS module using the tool instructions and the EFI binary file through the external interface. Using the external interface, the tool instructions and the EFI binary file are used to write the GPIO information in the motherboard configuration information into the GPIO initialization module of the target BIOS module.

[0013] Optionally, the step of packaging the target BIOS module containing the motherboard configuration information into BIOS firmware via the BMC, and then flashing the BIOS firmware into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete BIOS deployment includes: The BMC integrates the dynamically configured BIOS modules according to the preset firmware structure, adds necessary header information, checksums and digital signatures, and generates a complete and executable BIOS firmware image. A communication connection is established with the BIOS Flash chip through a dedicated SPI controller, the chip's programming mode is entered, the target Flash area is erased, the BIOS firmware image is divided into data blocks, and transmitted to the BIOS Flash chip through the SPI four-wire interface. After each data block is transmitted, a comparison and verification is performed. If an error is found, the data is retransmitted. After all firmware data has been flashed, an integrity check is performed. The newly written BIOS firmware is read and compared with the original data to verify the correctness of the flashing operation. The BMC releases the SPI channel and updates the internal status flags, records the information that the BIOS update was successful, and sends a BIOS update completion notification to the host system via the system management bus.

[0014] Optionally, the step of establishing a communication connection with the BIOS Flash chip through a dedicated SPI controller, entering the chip's programming mode, performing an erase operation on the target Flash area, dividing the BIOS firmware image into data blocks, and transmitting them to the BIOS Flash chip via the SPI four-wire interface includes: A stable communication connection with the BIOS Flash chip is established through a dedicated SPI controller, and the SPI clock frequency and data transmission mode are configured. The BMC sends a specific instruction sequence to the BIOS Flash chip, causing the BIOS Flash chip to enter a programmable state. The BMC first performs an erase operation on the target Flash storage area to clear the original BIOS data; The BIOS firmware image is divided into data blocks suitable for SPI transmission by the BMC, and then transmitted sequentially to the BIOS Flash chip through the SPI four-wire interface. The transmission pauses after each data block is transmitted, waiting for chip confirmation.

[0015] Secondly, to achieve the above objectives, the present invention also proposes a BMC intelligent BIOS generation device, the BMC intelligent BIOS generation device comprising: The data pre-storage module is used to pre-store the binary EFI files compiled by the multi-platform Basic Input / Output System BIOS module in the database on the BMC side of the baseboard management controller. Each EFI file provides an external interface for receiving motherboard configuration information. The information writing module is used to collect motherboard component information after the BMC is powered on, select the corresponding target BIOS module according to the motherboard component information, and dynamically write the motherboard configuration information into the target BIOS module through the external interface. The BIOS deployment module is used to package the target BIOS module containing the motherboard configuration information into BIOS firmware via the BMC, and to flash the BIOS firmware into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete the BIOS deployment.

[0016] Thirdly, to achieve the above objectives, the present invention also proposes a BMC intelligent BIOS generation device, the BMC intelligent BIOS generation device comprising: a memory, a processor, and a BMC intelligent BIOS generation program stored in the memory and executable on the processor, the BMC intelligent BIOS generation program being configured to implement the steps of the BMC intelligent BIOS generation method as described above.

[0017] Fourthly, to achieve the above objectives, the present invention also proposes a storage medium storing a BMC intelligent BIOS generation program, wherein when the BMC intelligent BIOS generation program is executed by a processor, it implements the steps of the BMC intelligent BIOS generation method described above.

[0018] The proposed method for intelligent BIOS generation using a Baseboard Management Controller (BMC) involves pre-storing binary EFI files compiled from the Basic Input / Output System (BIOS) modules of multiple platforms in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information. After the BMC powers on, it collects motherboard component information and selects the corresponding target BIOS module based on this information. The motherboard configuration information is then dynamically written to the target BIOS module through the external interface. The BMC packages the target BIOS module containing the motherboard configuration information to generate BIOS firmware, which is then flashed into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete BIOS deployment. This method can automatically and intelligently generate compatible BIOS firmware for servers with different hardware configurations, eliminating the need for BIOS engineers to manually modify code and perform secondary compilation for each project. This significantly reduces manual intervention in BIOS development and deployment, improves the automation and efficiency of server firmware deployment, effectively alleviates the resource constraints faced by BIOS engineers, and ensures precise matching between the BIOS and specific hardware configurations. This enhances system startup stability and compatibility, adapting to the needs of rapid server iteration and diverse configurations in scenarios such as cloud computing and big data. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of the present invention; Figure 2 This is a flowchart illustrating the first embodiment of the BMC intelligent BIOS generation method of the present invention; Figure 3 This is a flowchart illustrating a second embodiment of the BMC intelligent BIOS generation method of the present invention; Figure 4 This is a flowchart illustrating the third embodiment of the BMC intelligent BIOS generation method of the present invention; Figure 5 This is a flowchart illustrating the fourth embodiment of the BMC intelligent BIOS generation method of the present invention; Figure 6 This is a schematic diagram of the multi-layer structure in the BMC intelligent BIOS generation method of the present invention; Figure 7 This is a schematic diagram of the multi-platform BIOS module packaging structure and its interface design in the BMC intelligent BIOS generation method of the present invention; Figure 8 This is a complete schematic diagram of the BMC intelligent BIOS firmware generation method of the present invention; Figure 9 This is a functional block diagram of the first embodiment of the BMC intelligent BIOS generation device of the present invention.

[0020] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0022] The solution of this invention mainly involves: pre-storing the binary EFI files compiled from the multi-platform Basic Input / Output System (BIOS) modules in the database on the Baseboard Management Controller (BMC) side; each EFI file provides an external interface for receiving motherboard configuration information; after the BMC powers on, it collects motherboard component information and selects the corresponding target BIOS module based on the motherboard component information, dynamically writing the motherboard configuration information into the target BIOS module through the external interface; the BMC packages the target BIOS module containing the motherboard configuration information to generate BIOS firmware, and flashes the BIOS firmware into the BIOS through the Serial Peripheral Interface (SPI) channel. BIOS deployment is completed within the Flash chip; it can automatically and intelligently generate adapted BIOS firmware for servers with different hardware configurations, eliminating the need for BIOS engineers to manually modify code and perform secondary compilation for each project. This significantly reduces manual intervention in the BIOS development and deployment process, improves the automation and efficiency of server firmware deployment, effectively alleviates the problem of BIOS engineer resource shortage, and ensures precise matching between the BIOS and specific hardware configurations, improving system startup stability and compatibility. It adapts to the needs of rapid server iteration and diversified configurations in scenarios such as cloud computing and big data, solving the technical problems of BIOS engineer shortage and long training cycle in existing technologies, and the surge in server demand leading to traditional BIOS development requiring engineers to manually modify code and perform secondary compilation for different hardware configurations, resulting in low work efficiency and difficulty in meeting the needs of rapid iteration.

[0023] Reference Figure 1 , Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of the present invention.

[0024] like Figure 1As shown, the device may include: a processor 1001, such as a CPU; a communication bus 1002; a user interface 1003; a network interface 1004; and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0025] Those skilled in the art will understand that Figure 1 The device structure shown does not constitute a limitation on the device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0026] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating device, a network communication module, a user interface module, and a BMC intelligent generation BIOS program.

[0027] The device of this invention calls the BMC intelligent BIOS generation program stored in memory 1005 through processor 1001 and performs the following operations: The binary EFI files compiled from the multi-platform Basic Input / Output System BIOS module are pre-stored in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information. After the BMC is powered on, it collects motherboard component information, selects the corresponding target BIOS module based on the motherboard component information, and dynamically writes the motherboard configuration information into the target BIOS module through the external interface. The target BIOS module, which contains the motherboard configuration information, is packaged by the BMC to generate BIOS firmware. The BIOS firmware is then flashed into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete the BIOS deployment.

[0028] The device of the present invention, through processor 1001 calling the BMC intelligent BIOS generation program stored in memory 1005, also performs the following operations: The binary EFI files compiled from the multi-platform Basic Input / Output System (BIOS) module are pre-stored in the Baseboard Management Controller (BMC) side database. The BMC side database pre-stores BIOS module package files for different CPU architectures, and each EFI file provides an external interface for receiving motherboard configuration information.

[0029] The device of the present invention, through processor 1001 calling the BMC intelligent BIOS generation program stored in memory 1005, also performs the following operations: After the BMC is powered on, it actively scans and reads the EEPROM of each hardware module through the I2C bus to collect motherboard component information of each key component of the motherboard. The motherboard component information is intelligently matched with the multi-platform BIOS modules pre-stored in the BMC side database to determine the target BIOS module; The collected motherboard configuration information is dynamically written into the corresponding initialization area of ​​the target BIOS module through the external interface.

[0030] The device of the present invention, through processor 1001 calling the BMC intelligent BIOS generation program stored in memory 1005, also performs the following operations: The motherboard component information is intelligently matched with the multi-platform BIOS modules pre-stored in the BMC side database. The BIOS CRB module of the corresponding platform is determined according to the CPU platform information, the BIOS module version of the corresponding generation is selected according to the CPU generation, the PCIe lane topology scheme is determined according to the Riser information, the memory SPD address information is determined according to the memory topology information, and the GPIO initialization configuration is determined according to the GPIO information. The target BIOS module is determined based on the BIOS CRB module, the BIOS module version, the PCIe lane topology, the memory SPD address information, and the GPIO initialization configuration.

[0031] The device of the present invention, through processor 1001 calling the BMC intelligent BIOS generation program stored in memory 1005, also performs the following operations: The CPU platform information from the collected motherboard configuration information is written into the CPU initialization module of the target BIOS module using tool instructions and EFI binary files through the external interface. The memory topology information in the motherboard configuration information is written into the memory initialization module of the target BIOS module using the tool instructions and the EFI binary file through the external interface. The Riser information in the motherboard configuration information is written into the PCIe initialization module of the target BIOS module using the tool instructions and the EFI binary file through the external interface. Using the external interface, the tool instructions and the EFI binary file are used to write the GPIO information in the motherboard configuration information into the GPIO initialization module of the target BIOS module.

[0032] The device of the present invention, through processor 1001 calling the BMC intelligent BIOS generation program stored in memory 1005, also performs the following operations: The BMC integrates the dynamically configured BIOS modules according to the preset firmware structure, adds necessary header information, checksums and digital signatures, and generates a complete and executable BIOS firmware image. A communication connection is established with the BIOS Flash chip through a dedicated SPI controller, the chip's programming mode is entered, the target Flash area is erased, the BIOS firmware image is divided into data blocks, and transmitted to the BIOS Flash chip through the SPI four-wire interface. After each data block is transmitted, a comparison and verification is performed. If an error is found, the data is retransmitted. After all firmware data has been flashed, an integrity check is performed. The newly written BIOS firmware is read and compared with the original data to verify the correctness of the flashing operation. The BMC releases the SPI channel and updates the internal status flags, records the information that the BIOS update was successful, and sends a BIOS update completion notification to the host system via the system management bus.

[0033] The device of the present invention, through processor 1001 calling the BMC intelligent BIOS generation program stored in memory 1005, also performs the following operations: A stable communication connection with the BIOS Flash chip is established through a dedicated SPI controller, and the SPI clock frequency and data transmission mode are configured. The BMC sends a specific instruction sequence to the BIOS Flash chip, causing the BIOS Flash chip to enter a programmable state. The BMC first performs an erase operation on the target Flash storage area to clear the original BIOS data; The BIOS firmware image is divided into data blocks suitable for SPI transmission by the BMC, and then transmitted sequentially to the BIOS Flash chip through the SPI four-wire interface. The transmission pauses after each data block is transmitted, waiting for chip confirmation.

[0034] This embodiment utilizes the above-described scheme to pre-store the binary EFI files compiled from the Basic Input / Output System (BIOS) modules of multiple platforms in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information. After the BMC powers on, it collects motherboard component information and selects the corresponding target BIOS module based on this information. The motherboard configuration information is then dynamically written to the target BIOS module through the external interface. The BMC packages the target BIOS module containing the motherboard configuration information to generate BIOS firmware, which is then flashed into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete BIOS deployment. This approach can automatically and intelligently generate compatible BIOS firmware for servers with different hardware configurations, eliminating the need for BIOS engineers to manually modify code and perform secondary compilation for each project. This significantly reduces manual intervention in BIOS development and deployment, improves the automation and efficiency of server firmware deployment, effectively alleviates the resource constraints faced by BIOS engineers, and ensures precise matching between the BIOS and specific hardware configurations. This enhances system startup stability and compatibility, adapting to the needs of rapid server iteration and diverse configurations in scenarios such as cloud computing and big data.

[0035] Based on the above hardware structure, an embodiment of the method for intelligent BIOS generation by BMC of the present invention is proposed.

[0036] Reference Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the BMC intelligent BIOS generation method of the present invention.

[0037] In the first embodiment, the method for intelligently generating BIOS using the BMC includes the following steps: Step S10: The binary EFI file compiled by the multi-platform Basic Input / Output System BIOS module is pre-stored in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information.

[0038] It should be noted that the basic input / output system BIOS function modules developed for different hardware platforms, after being compiled, generate binary EFI executable files, which are pre-stored in the database of the Baseboard Management Controller (BMC). At the same time, it is ensured that each Extensible Firmware Interface (EFI) file is designed with a dedicated interface. These interfaces can receive and process motherboard configuration information from the BMC, providing basic data support for the subsequent dynamic generation of customized BIOS firmware based on the actual hardware configuration.

[0039] Step S20: After the BMC is powered on, collect motherboard component information, select the corresponding target BIOS module according to the motherboard component information, and dynamically write the motherboard configuration information into the target BIOS module through the external interface.

[0040] It should be understood that when the Baseboard Management Controller (BMC) is powered on, it first automatically scans and obtains key information about the hardware components on the server motherboard through communication interfaces such as the I2C bus. Then, the BMC compares and analyzes the collected hardware information with the multi-platform BIOS modules pre-stored in its database, and intelligently identifies the BIOS module that matches the current hardware configuration. Finally, the BMC uses the standardized interface pre-designed in the EFI file of each BIOS module to inject the actually detected motherboard configuration parameters into the selected BIOS module in real time, thereby realizing dynamic customization of the BIOS firmware.

[0041] Step S30: The target BIOS module containing the motherboard configuration information is packaged by the BMC to generate BIOS firmware, and the BIOS firmware is flashed into the BIOS Flash chip through the Serial Peripheral Interface (SPI) channel to complete the BIOS deployment.

[0042] It is understood that the target BIOS module, which contains the motherboard configuration information, is packaged by the BMC to generate BIOS firmware. Subsequently, the BMC uses the Serial Peripheral Interface (SPI) on the server motherboard as a communication channel to transmit the generated BIOS firmware data and write it into a Flash memory chip specifically used to store the BIOS program, thus completing the physical storage process of the firmware.

[0043] This embodiment utilizes the above-described scheme to pre-store the binary EFI files compiled from the Basic Input / Output System (BIOS) modules of multiple platforms in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information. After the BMC powers on, it collects motherboard component information and selects the corresponding target BIOS module based on this information. The motherboard configuration information is then dynamically written to the target BIOS module through the external interface. The BMC packages the target BIOS module containing the motherboard configuration information to generate BIOS firmware, which is then flashed into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete BIOS deployment. This approach can automatically and intelligently generate compatible BIOS firmware for servers with different hardware configurations, eliminating the need for BIOS engineers to manually modify code and perform secondary compilation for each project. This significantly reduces manual intervention in BIOS development and deployment, improves the automation and efficiency of server firmware deployment, effectively alleviates the resource constraints faced by BIOS engineers, and ensures precise matching between the BIOS and specific hardware configurations. This enhances system startup stability and compatibility, adapting to the needs of rapid server iteration and diverse configurations in scenarios such as cloud computing and big data.

[0044] Furthermore, Figure 3 This is a flowchart illustrating a second embodiment of the BMC intelligent BIOS generation method of the present invention, as shown below. Figure 3 As shown, based on the first embodiment, a second embodiment of the method for intelligent BIOS generation by BMC of the present invention is proposed. In this embodiment, step S10 specifically includes the following steps: Step S11: The binary EFI file compiled from the multi-platform Basic Input / Output System (BIOS) module is pre-stored in the Baseboard Management Controller (BMC) side database. The BMC side database pre-stores BIOS module encapsulation files for different CPU architectures, and each EFI file provides an external interface for receiving motherboard configuration information.

[0045] It should be noted that the binary EFI executable files generated after compiling the Basic Input / Output System (BIOS) functional modules developed for different CPU architecture platforms (such as Intel, AMD, Kunpeng, etc.) are pre-stored in the dedicated database of the Server Baseboard Management Controller (BMC). Each of these pre-stored EFI files is designed with a standardized external interface. These interfaces can receive and process the actual motherboard configuration information collected by the BMC, providing basic support for the subsequent dynamic generation of customized BIOS firmware based on the specific hardware environment. This is a prerequisite for realizing the intelligent BIOS generation technology solution.

[0046] This embodiment, through the above-described scheme, pre-stores the binary EFI files compiled from the basic input / output system BIOS modules of multiple platforms in the baseboard management controller (BMC) side database. The BMC side database pre-stores BIOS module packaging files for different CPU architectures. Each EFI file provides an external interface for receiving motherboard configuration information, enabling the pre-compiled storage and dynamic configuration of BIOS modules for multiple CPU platforms. This allows the BMC to automatically select and customize the appropriate BIOS firmware based on the actual hardware environment of the server without relying on BIOS engineers to manually modify the code, significantly improving BIOS deployment efficiency and ensuring precise matching between the firmware and specific hardware configurations.

[0047] Furthermore, Figure 4 This is a flowchart illustrating the third embodiment of the BMC intelligent BIOS generation method of the present invention, as shown below. Figure 4 As shown, based on the first embodiment, a third embodiment of the method for intelligent BIOS generation by BMC of the present invention is proposed. In this embodiment, step S20 specifically includes the following steps: Step S21: After the BMC is powered on, it actively scans and reads the EEPROM of each hardware module through the I2C bus to collect motherboard component information of each key component of the motherboard.

[0048] It should be noted that after power-on, the Baseboard Management Controller (BMC) actively performs a systematic scan of the key hardware components on the server motherboard via the internal Inter-Integrated Circuit (I2C) serial bus protocol. It accesses the electrically erasable programmable read-only memory (EEPROM) integrated on each hardware module, such as the CPU socket, memory modules, and expansion card risers, and reads the hardware identification information and configuration parameters stored therein. This information includes, but is not limited to, key data such as CPU platform type, chipset model, memory specifications, Peripheral Component Interconnect Express (PCIe) topology, and General Purpose Input / Output (GPIO) configuration, avoiding the cumbersome process of manually entering hardware configuration information required in traditional BIOS deployments.

[0049] Step S22: Intelligently match the motherboard component information with the multi-platform BIOS modules pre-stored in the BMC side database to determine the target BIOS module.

[0050] Understandably, intelligent matching of the motherboard component information with multi-platform BIOS modules pre-stored in the BMC side database determines the target BIOS module, laying the foundation for dynamically writing the motherboard configuration information into the module, thereby achieving precise customization of the BIOS firmware and avoiding the tedious process of engineers manually selecting and configuring modules in traditional BIOS development.

[0051] Furthermore, step S22 specifically includes the following steps: The motherboard component information is intelligently matched with the multi-platform BIOS modules pre-stored in the BMC side database. The BIOS CRB module of the corresponding platform is determined according to the CPU platform information, the BIOS module version of the corresponding generation is selected according to the CPU generation, the PCIe lane topology scheme is determined according to the Riser information, the memory SPD address information is determined according to the memory topology information, and the GPIO initialization configuration is determined according to the GPIO information. The target BIOS module is determined based on the BIOS CRB module, the BIOS module version, the PCIe lane topology, the memory SPD address information, and the GPIO initialization configuration.

[0052] It should be noted that, firstly, the BMC determines the applicable basic reference design BIOS Customer Reference Board (BIOS CRB) module type based on the identified CPU platform information (such as Intel, AMD, or Kunpeng); secondly, it selects the corresponding BIOS module version based on the detected CPU generation (such as Intel 10th or 11th generation); simultaneously, the BMC analyzes the riser card configuration information to determine the PCIe lane topology scheme; furthermore, it determines the memory serial presence detection (SPD) address information based on the physical layout and specifications of the memory slots; finally, it determines the corresponding GPIO initialization parameters based on the motherboard GPIO pin configuration. By comprehensively considering these five key dimensions—BIOS CRB module type, BIOS module version, PCIe lane topology scheme, memory SPD address information, and GPIO initialization configuration—the BMC can accurately identify the target BIOS module that perfectly matches the current server hardware environment, achieving automated and precise BIOS configuration. This avoids the tedious process of engineers manually matching hardware and firmware in traditional BIOS deployments, laying the foundation for subsequent dynamic writing of configuration information and generation of customized BIOS firmware.

[0053] Step S23: Dynamically write the collected motherboard configuration information into the corresponding initialization area of ​​the target BIOS module through the external interface.

[0054] It should be understood that by dynamically writing the collected motherboard configuration information into the corresponding initialization area of ​​the target BIOS module through the external interface, BIOS engineers do not need to manually modify the source code and recompile, which greatly simplifies the BIOS deployment process and improves the automation level and accuracy of server firmware configuration.

[0055] Furthermore, step S23 specifically includes the following steps: The CPU platform information from the collected motherboard configuration information is written into the CPU initialization module of the target BIOS module using tool instructions and EFI binary files through the external interface. The memory topology information in the motherboard configuration information is written into the memory initialization module of the target BIOS module using the tool instructions and the EFI binary file through the external interface. The Riser information in the motherboard configuration information is written into the PCIe initialization module of the target BIOS module using the tool instructions and the EFI binary file through the external interface. Using the external interface, the tool instructions and the EFI binary file are used to write the GPIO information in the motherboard configuration information into the GPIO initialization module of the target BIOS module.

[0056] Understandably, the Baseboard Management Controller (BMC) utilizes the standardized external interfaces designed in the pre-stored BIOS module EFI file, combined with dedicated tool instructions and EFI binary file processing technology, to accurately write the actual configuration parameters of the server motherboard collected via the I2C bus into the corresponding functional areas of the target BIOS module. Specifically, the BMC writes the identified CPU platform information (such as Intel, AMD, or Kunpeng architecture) into the BIOS's CPU initialization module to ensure correct processor initialization; it writes the memory slot layout and specification information into the memory initialization module, enabling the BIOS to accurately configure the memory controller; it writes the Riser card configuration information into the PCIe initialization module to determine the topology and bandwidth allocation of the PCIe channels; and it writes the GPIO pin configuration information into the GPIO initialization module to achieve precise configuration of server hardware status monitoring and control functions.

[0057] This embodiment, through the above-described scheme, actively scans and reads the EEPROM of each hardware module via the I2C bus after the BMC powers on, collecting motherboard component information of each key component of the motherboard; intelligently matches the motherboard component information with multi-platform BIOS modules pre-stored in the BMC-side database to determine the target BIOS module; and dynamically writes the collected motherboard configuration information into the corresponding initialization area of ​​the target BIOS module through the external interface. This enables automatic identification of server hardware configuration and intelligent matching of the appropriate BIOS module. Through the fully automated mechanism of the BMC actively collecting key motherboard component information, accurately matching the target BIOS module, and dynamically writing customized configuration parameters, it achieves the generation of fully matching BIOS firmware for different hardware platforms and different generations of CPUs without requiring BIOS engineers to manually modify code and recompile. This significantly improves server firmware deployment efficiency and ensures accurate adaptation of the BIOS to specific hardware environments.

[0058] Furthermore, Figure 5 This is a flowchart illustrating the fourth embodiment of the BMC intelligent BIOS generation method of the present invention, as shown below. Figure 5 As shown, based on the first embodiment, a fourth embodiment of the method for intelligent BIOS generation by BMC of the present invention is proposed. In this embodiment, step S30 specifically includes the following steps: Step S31: The BMC integrates the dynamically configured BIOS modules according to the preset firmware structure, adds necessary header information, checksum and digital signature, and generates a complete and executable BIOS firmware image.

[0059] It should be noted that BMC integrates the various BIOS functional modules (including CPU initialization module, memory initialization module, PCIe initialization module, and GPIO initialization module, etc.) that have already had their motherboard configuration information injected into them, according to the standard organizational structure of BIOS firmware. Specifically, BMC arranges the functional modules in the correct order according to the predefined firmware layout specifications, and adds necessary firmware header information (including version number, build time, applicable hardware platform, and other metadata), integrity check codes (such as CRC32 or SHA-256 hash values), and digital signatures (used to verify the trustworthiness of the firmware source and prevent tampering). Through this integration process, BMC combines the scattered, customized BIOS modules into a complete, standardized, secure, and reliable executable BIOS firmware image. This image meets the standard requirements for server boot firmware, can be correctly recognized and executed by the motherboard chipset, and lays the foundation for subsequent flashing to the BIOS Flash chip via the SPI channel. This achieves automation and standardization of BIOS firmware generation, avoiding the complex process of manual firmware integration and verification required in traditional BIOS development.

[0060] Step S32: Establish a communication connection with the BIOS Flash chip through a dedicated SPI controller, enter the chip's programming mode, perform an erase operation on the target Flash area, divide the BIOS firmware image into data blocks, and transmit them to the BIOS Flash chip through the SPI four-wire interface.

[0061] It is understandable that by establishing a communication connection with the BIOS Flash chip through a dedicated SPI controller, entering the chip's programming mode, performing an erase operation on the target Flash area, dividing the BIOS firmware image into data blocks, and transmitting them to the BIOS Flash chip through the SPI four-wire interface, the reliability of data transmission can be ensured.

[0062] Furthermore, step S32 specifically includes the following steps: A stable communication connection with the BIOS Flash chip is established through a dedicated SPI controller, and the SPI clock frequency and data transmission mode are configured. The BMC sends a specific instruction sequence to the BIOS Flash chip, causing the BIOS Flash chip to enter a programmable state. The BMC first performs an erase operation on the target Flash storage area to clear the original BIOS data; The BIOS firmware image is divided into data blocks suitable for SPI transmission by the BMC, and then transmitted sequentially to the BIOS Flash chip through the SPI four-wire interface. The transmission pauses after each data block is transmitted, waiting for chip confirmation.

[0063] It should be noted that the BMC establishes a stable communication connection with the BIOS Flash chip through a dedicated SPI controller. It configures an appropriate clock frequency (typically within the 10-100MHz range) and data transfer mode (such as mode 0 or mode 3) according to the Flash chip specifications to ensure signal integrity and transmission reliability. Subsequently, the BMC sends a specific sequence of instructions to the Flash chip (usually including a write enable command and an instruction to enter programming mode), switching the chip from read-only to programmable mode, preparing it for data writing. Before writing new firmware, the BMC performs a critical erase operation, resetting all memory cells in the target Flash memory area (usually by sector or block) to a "1" state, because NOR... The physical characteristics of Flash memory dictate that it must be erased before being written. Next, the BMC divides the complete BIOS firmware image into small data blocks (usually 256 bytes or 512 bytes) suitable for SPI transmission. These blocks are then transmitted sequentially to the Flash chip via the four-wire SPI interface (including clock line SCLK, master input / slave output line MOSI, master output / slave output line MISO, and chip select line CS). After each data block is transmitted, the process pauses and waits for the chip to return an acknowledgment signal. This mechanism not only meets the writing timing requirements of the Flash chip but also promptly detects and handles transmission errors, ensuring that each data block is written accurately.

[0064] Step S33: After each data block is transmitted, a comparison and verification is performed. If an error is found, the data is retransmitted.

[0065] It should be understood that during the process of BMC transmitting firmware data to the BIOS Flash chip via the SPI interface, after each data block (usually 256 bytes or 512 bytes) is written, a data integrity verification is immediately performed: BMC rereads the data block just written from the Flash chip and compares it bit by bit with the corresponding data in the original BIOS firmware image; if the comparison results are inconsistent, it indicates that an error occurred during data transmission or writing (which may be caused by signal interference, voltage fluctuations, or Flash storage unit abnormalities, etc.), and BMC will automatically trigger a retransmission mechanism to resend the data block until the verification is successful; this real-time verification and retransmission mechanism effectively ensures the accuracy of BIOS firmware writing, avoids the risk of the entire BIOS firmware being damaged due to a single data block error, and significantly improves the reliability of firmware updates.

[0066] Step S34: After completing the flashing of all firmware data, perform an integrity check, read the newly written BIOS firmware and compare it with the original data to verify the correctness of the flashing operation.

[0067] Understandably, the BMC will completely read the firmware data that was just written from the BIOS Flash chip, and then perform a byte-by-byte comparison with the original BIOS firmware image or perform consistency verification by calculating checksums (such as CRC32, SHA-256, and other hash algorithms). This integrity verification can detect any data errors that may have been missed during the flashing process, including write anomalies caused by SPI communication interference, Flash storage cell failure, or power fluctuations. If the verification result shows that the written data is completely consistent with the original data, the BMC confirms that the BIOS update is successful. If a mismatch is found, the BMC can take corresponding measures according to the preset policy, such as automatically retrying the update process, rolling back to the previous version, or issuing an error alert to the system administrator.

[0068] Step S35: Release the SPI channel through the BMC and update the internal status flag, record the BIOS update success information, and send a BIOS update completion notification to the host system through the system management bus.

[0069] It should be understood that the BMC releases the previously occupied SPI communication channel, including stopping the clock signal, canceling the chip select signal, and disconnecting from the BIOS Flash chip, returning the SPI bus resources to the system, avoiding bus conflicts, and ensuring that other system components can access the Flash memory normally. Secondly, the BMC updates the status flags in its internal non-volatile memory, recording key information such as the success status of the BIOS update operation, the completion timestamp, and the new firmware version number. These records can be used for subsequent system diagnostics, audit trails, and troubleshooting. Finally, the BMC sends a notification message to the host system that the BIOS update is complete through the system management bus (such as SMBus or a dedicated IPMI channel), enabling the host operating system or management software to be aware of the firmware status changes in a timely manner, which may trigger system log recording, status updates, or preparation for subsequent reboot operations. This series of operations completes the final work of the BIOS update process, ensuring the synchronization of the status of all system components, providing complete status assurance for the normal startup or continued operation of the server, and establishing traceable operation records, thereby improving the reliability and maintainability of server management.

[0070] In the specific implementation, see Figure 6 , Figure 6 This is a schematic diagram of the multi-layer structure in the BMC intelligent BIOS generation method of the present invention, as shown below. Figure 6As shown, the Baseboard Management Controller (BMC) first actively acquires key information about the server platform via the I2C bus access link, including Chipset information, memory (Mem) configuration, Riser / PCIe topology, and GPIO pin settings, and collects complete hardware topology information (such as USB device layout). This information is used to intelligently match the corresponding BIOS module from the BMC database, which pre-stores CRB (Customer Reference Module) for different platforms. The BMC (Board of Modules) package files include those for Intel server CRB modules, Whitley server CRB modules, BirchStream server CRB modules, AMD server CRB modules, SP4 CPU server CRB modules, SP5 CPU server CRB modules, and Kunpeng server CRB modules. Each packaged module has been progressively developed with standardized external interfaces, enabling the BMC to dynamically inject collected hardware configuration information into the corresponding modules. Subsequently, the BMC packaging module intelligently arranges and integrates the selected modules based on the structure information defined in the .fdf files within each CRB. After configuration, the BMC intelligently generates customized BIOS firmware and flashes it to the SPI Flash chip via the SPI channel, performing BIOS deployment and flashing operations in a conventional manner, thus achieving automated BIOS deployment without manual intervention.

[0071] The corresponding multi-layered structure is as follows: First layer: CPU platform and Chipset module selection; The second layer: Information collection for each component and data transmission to each encapsulation module; Third layer: BIOS module packaging and intelligent generation of BIOS firmware; Fourth layer: Flash the generated BIOS firmware into the BIOS Flash.

[0072] Figure 6 The corresponding solutions are as follows: 1. The BMC database stores the module EFI package files generated by the BIOS CRB compilation of each platform. Each package module needs to gradually develop external interfaces.

[0073] 2. With BMC as the core, each hardware module is equipped with an I2C channel, and each hardware EEPROM stores its own information.

[0074] BMC reads the component IDs via I2C and matches them with the component driver modules. Then, it adaptively writes the module scheme information into the module initialization encapsulation file through the external interfaces of each module. For example: BMC reads the motherboard CPU platform and chipset information to determine the BIOS CRB module to be used; After reading the Riser information to determine the PCIe lane topology scheme, BMC fills in the corresponding CRB's PCIe initialization module. After the BMC reads the memory topology information to determine the memory SPD address information, it fills it into the memory initialization module of the corresponding CRB. After reading the GPIO information stored in the motherboard's EEPROM, the BMC fills it into the GPIO initialization module of the corresponding CRB. 3. BMC will package the matched BIOS EFI module and intelligently generate BIOS firmware. The generated BIOS firmware will be different for different platforms and hardware configurations.

[0075] 4. The BMC flashes the new firmware into the BIOS Flash via the SPI channel and then proceeds with the normal power-on process.

[0076] In the specific implementation, see Figure 7 , Figure 7 This is a schematic diagram of the multi-platform BIOS module packaging structure and its interface design in the BMC intelligent BIOS generation method of the present invention, as shown below. Figure 7 As shown in the diagram, the organization of BIOS modules for different server platforms is clearly illustrated. This includes BIOS packaging modules for Intel platforms (containing packaging files for various CRB modules of Intel Whitley and Intel BirchStream servers), BIOS packaging modules for AMD platforms (containing packaging files for various CRB modules of AMD SP4 and AMD SP5 CPU servers), and BIOS packaging modules for Kunpeng platforms (containing packaging files for various CRB modules of Kunpeng servers). Each platform's packaging module contains core functional components, such as the SPIFlash chip adapter module (responsible for communication with the BIOS memory chip), the memory initialization module (handling memory configuration), the PCIe initialization module (managing PCIe topology), the EarlyVGA power-on module (implementing early display output), the GPIO module (handling general-purpose input / output signals), and the UART module (providing serial communication functionality), as well as other necessary modules. Crucially, the diagram clearly indicates that each module provides standardized external interfaces. These interfaces enable the BMC to dynamically inject platform-specific parameters based on the actual hardware configuration, achieving intelligent generation of BIOS firmware.

[0077] Figure 7 The BMC database contains a detailed list of the files and their corresponding contents. Figure 6 The first layer involves selecting the platform and Chipset.

[0078] In the specific implementation, see Figure 8 , Figure 8 This is a complete schematic diagram of the BMC intelligent BIOS firmware generation method in the present invention, as shown below. Figure 8 As shown, the Baseboard Management Controller (BMC) collects information on various key hardware components of the server motherboard in parallel through multiple I2C bus channels (I2C1 to I2Cn). Channel I2C1 connects to the CPU component and performs Chipset selection; channel I2C2 reads memory component information to configure the memory initialization module; channel I2C3 obtains PCIe component data for the PCIe initialization module; channel I2C4 collects GPIO component information to configure the GPIO module; channel I2C5 processes UART component data; and the remaining I2Cn channels are responsible for collecting information from other components. The BMC intelligently matches this hardware configuration information with multi-platform BIOS modules pre-stored in the BMC database, selecting modules including the SPI Flash chip adapter module, memory initialization module, PCIe initialization module, and Early... The corresponding functional components, including the VGA lighting module and the UART module, are then used by the BMC to call a dedicated packaging script based on the .fdf file structure information defined in each CRB. This integrates the selected module components in the correct order and format, dynamically generating a customized BIOS firmware that perfectly matches the current hardware configuration. This allows for the intelligent generation of BIOS firmware without requiring BIOS engineers to manually modify the code or perform secondary compilation.

[0079] Figure 8 The process of BMC collecting system component information and generating the BIOS is described in detail. Figure 6 The second and third layers describe the process by which the BMC collects information from various components, fills it into the BIOS packaging template, and generates BIOS firmware.

[0080] In the specific implementation, the specific terms are explained in Table 1 below: Table 1. Examples of Glossary Explanations:

[0081] It should be noted that the current method for generating BIOS files is as follows: At the start of the project, the BIOS engineer obtained CPU platform and Chipset information from the project team; ->The BIOS engineer obtains the BIOS code for the corresponding platform; ->BIOS engineers obtain hardware-related topology information (system topology diagram, i.e., the interconnection relationship and hardware resource allocation relationship of components such as CPU / BMC / BIOS / PCIe components / Memory components, etc.) from hardware engineers. ->BIOS engineers manually fill the hardware topology information into the BIOS code and then compile it; -> Compile to generate intermediate EFI files; The compilation script packages the EFI modules according to the arrangement of the EFI modules in the fdf file within the BIOS code, and finally generates a new BIOS firmware; -> Manually flash the BIOS file into the BIOS Flash chip via BMC web upgrade or other upgrade methods, and then boot the computer.

[0082] In this embodiment, the binary EFI files compiled from BIOS modules of multiple platforms are packaged and stored in the BMC-side database. After booting, the BMC collects motherboard information and intelligently selects the corresponding BIOS module to package and generate BIOS firmware, reducing the need for BIOS engineers to manually modify and recompile code for each project, and alleviating the pressure on BIOS engineers.

[0083] In the actual implementation, the same OpenBmc is used, which contains by default the BIOS module package files for the last two generations of the three platforms (Intel / AMD / Kunpeng).

[0084] Scenario 1: Within the resource pool, Server 1 is an Intel server, Server 2 is an AMD server, and Server 3 is a Kunpeng server—each with a CPU from a different angle.

[0085] At this time Figure 6 At the first level, the BMC within each machine will select different platforms before continuing. Figure 6 The second, third, and fourth floors.

[0086] Scenario 2: Within the resource pool, Server 1 is an Intel Whitley server, and Server 2 is an Intel BirchStream server – representing different CPU generations from different perspectives.

[0087] At this time Figure 6 At the first level, the BMC within each system will select different platforms, then select the CPU generation (which generation of CPU), and then continue. Figure 6 The second, third, and fourth floors.

[0088] Scenario 3: Within the resource pool, Server 1 is an Intel BirchStream server (Topology Scheme 1) + Server 2 is an Intel BirchStream server (Topology Scheme 2) -- different perspectives on component topology schemes.

[0089] At this time Figure 6In the second stage, when collecting PCIe component information and passing it to the PCIe initialization module, the two servers will pass in different PCIe topology information, and the generated BIOS firmware will also be different.

[0090] It should be noted that this embodiment is the first to propose storing the BIOS encapsulated EFI file on the BMC side to form a database; each EFI encapsulated file needs to develop an external interface, and the BMC will use a combination of tools, instructions, and EFI binary to input and modify data in the EFI file; the BIOS will collect information from each component or fill it into the corresponding EFI module file of the BIOS, and finally package it to generate a BIOS undisabled file, which can reduce the problem that BIOS engineers need to manually modify the code and recompile for each project, and alleviate the demand pressure on BIOS engineers.

[0091] This embodiment, through the above-described scheme, integrates the dynamically configured BIOS modules according to a preset firmware structure via the BMC, adds necessary header information, checksums, and digital signatures, and generates a complete, executable BIOS firmware image. A communication connection is established with the BIOS Flash chip via a dedicated SPI controller, entering the chip's programming mode to perform an erase operation on the target Flash area. The BIOS firmware image is divided into data blocks and transmitted to the BIOS via the SPI four-wire interface. Flash chip; after each data block is transmitted, a comparison and verification is performed. If an error is found, the data is retransmitted. After all firmware data has been flashed, an integrity check is performed. The newly written BIOS firmware is read and compared with the original data to verify the correctness of the flashing operation. The SPI channel is released through the BMC and the internal status flag is updated to record the BIOS update success information. A BIOS update completion notification is sent to the host system through the system management bus. It can automatically generate adaptive BIOS firmware for servers with different hardware configurations, eliminating the need for BIOS engineers to manually modify code and perform secondary compilation for each project. This significantly reduces manual intervention in the BIOS development and deployment process, improves the automation and efficiency of server firmware deployment, effectively alleviates the problem of BIOS engineer resource shortage, and ensures precise matching between the BIOS and specific hardware configurations. This improves the stability and compatibility of system startup and adapts to the needs of rapid server iteration and diversified configurations in scenarios such as cloud computing and big data.

[0092] Accordingly, the present invention further provides an apparatus for intelligently generating BIOS using a BMC.

[0093] Reference Figure 9 , Figure 9 This is a functional block diagram of the first embodiment of the BMC intelligent BIOS generation device of the present invention.

[0094] In a first embodiment of the BMC intelligent BIOS generation device of the present invention, the BMC intelligent BIOS generation device includes: The data pre-storage module 10 is used to pre-store the binary EFI files compiled by the multi-platform Basic Input / Output System BIOS module in the database on the BMC side of the baseboard management controller. Each EFI file provides an external interface for receiving motherboard configuration information.

[0095] The information writing module 20 is used to collect motherboard component information after the BMC is powered on, select the corresponding target BIOS module according to the motherboard component information, and dynamically write the motherboard configuration information into the target BIOS module through the external interface.

[0096] The BIOS deployment module 30 is used to package the target BIOS module containing the motherboard configuration information into BIOS firmware through the BMC, and to flash the BIOS firmware into the BIOS Flash chip through the Serial Peripheral Interface (SPI) channel to complete the BIOS deployment.

[0097] The data pre-storage module 10 is also used to pre-store the binary EFI file compiled by the multi-platform Basic Input / Output System BIOS module in the Baseboard Management Controller (BMC) side database. The BMC side database pre-stores BIOS module encapsulation files for different CPU architectures, and each EFI file provides an external interface for receiving motherboard configuration information.

[0098] The information writing module 20 is also used to actively scan and read the EEPROM of each hardware module through the I2C bus after the BMC is powered on, collect motherboard component information of each key component of the motherboard; intelligently match the motherboard component information with the multi-platform BIOS modules pre-stored in the BMC side database to determine the target BIOS module; and dynamically write the collected motherboard configuration information into the corresponding initialization area of ​​the target BIOS module through the external interface.

[0099] The information writing module 20 is further configured to intelligently match the motherboard component information with multi-platform BIOS modules pre-stored in the BMC-side database, determine the corresponding BIOS CRB module based on the CPU platform information, select the corresponding generation BIOS module version based on the CPU generation, determine the PCIe lane topology based on the riser information, determine the memory SPD address information based on the memory topology information, and determine the GPIO initialization configuration based on the GPIO information; and determine the target BIOS module based on the BIOS CRB module, the BIOS module version, the PCIe lane topology, the memory SPD address information, and the GPIO initialization configuration.

[0100] The information writing module 20 is further configured to: write the CPU platform information from the collected motherboard configuration information into the CPU initialization module of the target BIOS module using tool instructions and EFI binary files through the external interface; write the memory topology information from the motherboard configuration information into the memory initialization module of the target BIOS module using the tool instructions and EFI binary files through the external interface; write the Riser information from the motherboard configuration information into the PCIe initialization module of the target BIOS module using the tool instructions and EFI binary files through the external interface; and write the GPIO information from the motherboard configuration information into the GPIO initialization module of the target BIOS module using the tool instructions and EFI binary files through the external interface.

[0101] The BIOS deployment module 30 is further configured to integrate the dynamically configured BIOS modules according to a preset firmware structure via the BMC, add necessary header information, checksums, and digital signatures, and generate a complete and executable BIOS firmware image; establish a communication connection with the BIOS Flash chip via a dedicated SPI controller, enter the chip's programming mode, perform an erase operation on the target Flash area, divide the BIOS firmware image into data blocks, and transmit them to the BIOS Flash chip via the SPI four-wire interface; perform comparison and verification after each data block is transmitted, and retransmit if an error is found; after all firmware data has been flashed, perform an integrity check, read the newly written BIOS firmware and compare it with the original data to verify the correctness of the flashing operation; release the SPI channel and update the internal status flags via the BMC, record the BIOS update success information, and send a BIOS update completion notification to the host system via the system management bus.

[0102] The BIOS deployment module 30 is also used to establish a stable communication connection with the BIOS Flash chip through a dedicated SPI controller, configure the SPI clock frequency and data transmission mode; send a specific instruction sequence to the BIOS Flash chip through the BMC to enable the BIOS Flash chip to enter a programmable state; perform an erase operation on the target Flash storage area through the BMC to clear the original BIOS data; and divide the BIOS firmware image into data blocks suitable for SPI transmission through the BMC, and transmit them sequentially to the BIOS Flash chip through the SPI four-wire interface, pausing and waiting for chip confirmation after each data block is transmitted.

[0103] The steps for implementing each functional module of the BMC intelligent BIOS generation device can be referred to in various embodiments of the BMC intelligent BIOS generation method of the present invention, and will not be repeated here.

[0104] Furthermore, this embodiment of the invention also proposes a storage medium storing a BMC intelligent BIOS generation program, wherein when the BMC intelligent BIOS generation program is executed by a processor, it implements the operations described in the above-described BMC intelligent BIOS generation method embodiment.

[0105] Those skilled in the art will understand that all or part of the steps in the methods described above can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium is a computer-readable storage medium, including: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store program code.

[0106] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0107] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0108] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method for intelligently generating BIOS using a BMC, characterized in that, The method for intelligently generating BIOS using BMC includes: The binary EFI files compiled from the multi-platform Basic Input / Output System BIOS module are pre-stored in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information. After the BMC is powered on, it collects motherboard component information, selects the corresponding target BIOS module based on the motherboard component information, and dynamically writes the motherboard configuration information into the target BIOS module through the external interface. The target BIOS module, which contains the motherboard configuration information, is packaged by the BMC to generate BIOS firmware. The BIOS firmware is then flashed into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete the BIOS deployment.

2. The method for intelligently generating BIOS using BMC as described in claim 1, characterized in that, The binary EFI files compiled from the multi-platform Basic Input / Output System (BIOS) module are pre-stored in the database on the Baseboard Management Controller (BMC) side. Each EFI file provides an external interface for receiving motherboard configuration information, including: The binary EFI files compiled from the multi-platform Basic Input / Output System (BIOS) module are pre-stored in the Baseboard Management Controller (BMC) side database. The BMC side database pre-stores BIOS module package files for different CPU architectures, and each EFI file provides an external interface for receiving motherboard configuration information.

3. The method for intelligently generating BIOS using BMC as described in claim 1, characterized in that, After the BMC is powered on, the process of collecting motherboard component information, selecting the corresponding target BIOS module based on the motherboard component information, and dynamically writing the motherboard configuration information into the target BIOS module through the external interface includes: After the BMC is powered on, it actively scans and reads the EEPROM of each hardware module through the I2C bus to collect motherboard component information of each key component of the motherboard. The motherboard component information is intelligently matched with the multi-platform BIOS modules pre-stored in the BMC side database to determine the target BIOS module; The collected motherboard configuration information is dynamically written into the corresponding initialization area of ​​the target BIOS module through the external interface.

4. The method for intelligently generating BIOS using BMC as described in claim 3, characterized in that, The step of intelligently matching the motherboard component information with multi-platform BIOS modules pre-stored in the BMC-side database to determine the target BIOS module includes: The motherboard component information is intelligently matched with the multi-platform BIOS modules pre-stored in the BMC side database. The BIOS CRB module of the corresponding platform is determined according to the CPU platform information, the BIOS module version of the corresponding generation is selected according to the CPU generation, the PCIe lane topology scheme is determined according to the Riser information, the memory SPD address information is determined according to the memory topology information, and the GPIO initialization configuration is determined according to the GPIO information. The target BIOS module is determined based on the BIOS CRB module, the BIOS module version, the PCIe lane topology, the memory SPD address information, and the GPIO initialization configuration.

5. The method for intelligently generating BIOS using BMC as described in claim 3, characterized in that, The step of dynamically writing the collected motherboard configuration information into the corresponding initialization area of ​​the target BIOS module through the external interface includes: The CPU platform information from the collected motherboard configuration information is written into the CPU initialization module of the target BIOS module using tool instructions and EFI binary files through the external interface. The memory topology information in the motherboard configuration information is written into the memory initialization module of the target BIOS module using the tool instructions and the EFI binary file through the external interface. The Riser information in the motherboard configuration information is written into the PCIe initialization module of the target BIOS module using the tool instructions and the EFI binary file through the external interface. Using the external interface, the tool instructions and the EFI binary file are used to write the GPIO information in the motherboard configuration information into the GPIO initialization module of the target BIOS module.

6. The method for intelligently generating BIOS using BMC as described in claim 1, characterized in that, The process of packaging the target BIOS module containing the motherboard configuration information into BIOS firmware via the BMC, and then flashing the BIOS firmware into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete BIOS deployment includes: The BMC integrates the dynamically configured BIOS modules according to the preset firmware structure, adds necessary header information, checksums and digital signatures, and generates a complete and executable BIOS firmware image. A communication connection is established with the BIOS Flash chip through a dedicated SPI controller, the chip's programming mode is entered, the target Flash area is erased, the BIOS firmware image is divided into data blocks, and transmitted to the BIOS Flash chip through the SPI four-wire interface. After each data block is transmitted, a comparison and verification is performed. If an error is found, the data is retransmitted. After all firmware data has been flashed, an integrity check is performed. The newly written BIOS firmware is read and compared with the original data to verify the correctness of the flashing operation. The BMC releases the SPI channel and updates the internal status flags, records the information that the BIOS update was successful, and sends a BIOS update completion notification to the host system via the system management bus.

7. The method for intelligently generating BIOS using BMC as described in claim 6, characterized in that, The process involves establishing a communication connection with the BIOS Flash chip via a dedicated SPI controller, entering the chip's programming mode, performing an erase operation on the target Flash area, dividing the BIOS firmware image into data blocks, and transmitting them to the BIOS Flash chip via the SPI four-wire interface. A stable communication connection with the BIOS Flash chip is established through a dedicated SPI controller, and the SPI clock frequency and data transmission mode are configured. The BMC sends a specific instruction sequence to the BIOS Flash chip, causing the BIOS Flash chip to enter a programmable state. The BMC first performs an erase operation on the target Flash storage area to clear the original BIOS data; The BIOS firmware image is divided into data blocks suitable for SPI transmission by the BMC, and then transmitted sequentially to the BIOS Flash chip through the SPI four-wire interface. The transmission pauses after each data block is transmitted, waiting for chip confirmation.

8. A device for intelligently generating BIOS using a BMC, characterized in that, The BMC intelligent BIOS generation device includes: The data pre-storage module is used to pre-store the binary EFI files compiled by the multi-platform Basic Input / Output System BIOS module in the database on the BMC side of the baseboard management controller. Each EFI file provides an external interface for receiving motherboard configuration information. The information writing module is used to collect motherboard component information after the BMC is powered on, select the corresponding target BIOS module according to the motherboard component information, and dynamically write the motherboard configuration information into the target BIOS module through the external interface. The BIOS deployment module is used to package the target BIOS module containing the motherboard configuration information into BIOS firmware via the BMC, and to flash the BIOS firmware into the BIOS Flash chip via the Serial Peripheral Interface (SPI) channel to complete the BIOS deployment.

9. A BMC intelligent BIOS generation device, characterized in that, The BMC intelligent BIOS generation device includes: a memory, a processor, and a BMC intelligent BIOS generation program stored in the memory and executable on the processor, the BMC intelligent BIOS generation program being configured to implement the steps of the BMC intelligent BIOS generation method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium stores a BMC intelligent BIOS generation program, which, when executed by a processor, implements the steps of the BMC intelligent BIOS generation method as described in any one of claims 1 to 7.

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