Instruction dependency verification method, electronic device, and storage medium
By allocating status slots and issue timings to chip instructions and combining buffers to simulate hardware pipeline mechanisms, the problems of high resource consumption, insufficient timing accuracy, and poor scalability in chip instruction dependency verification are solved, achieving efficient clock cycle-level accurate verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-03-10
- Publication Date
- 2026-06-12
AI Technical Summary
Existing technologies consume a lot of resources, have insufficient timing accuracy, and poor scalability and real-time performance when verifying chip instruction dependencies, making it difficult to achieve efficient clock cycle-level accurate verification.
By allocating status slots to the target instructions in the design under test, determining the number of slots based on the dependency depth M, and using the status slots and launch timing to determine whether the instructions meet the launch conditions, the dependency relationship is verified by combining the expected and actual launch clock cycles, and a buffer is used to simulate the hardware pipeline mechanism to achieve real-time synchronization.
It reduces system resource requirements, keeps resource consumption constant, does not increase linearly with test time, has good scalability and real-time performance, can detect abnormal behavior in verification in a timely manner, and shortens the debugging cycle.
Smart Images
Figure CN122195798A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip verification technology, and in particular to an instruction dependency verification method, electronic device, and storage medium. Background Technology
[0002] Verification of instruction dependencies is a crucial step in ensuring the correctness of chip functionality, and is mainly achieved through black-box verification methods, white-box verification methods, or static assertion verification methods.
[0003] However, black-box verification methods cannot deeply verify the precise timing of instruction dependencies; white-box verification methods require maintaining an independent state for each instruction, resulting in high resource consumption; and static assertion verification methods are difficult to cover complex dependency scenarios in dynamic execution processes, and may have poor scalability issues when the complexity of dependency relationships increases.
[0004] Therefore, how to achieve accurate clock cycle-level verification of instruction dependencies while reducing resource consumption, and improve its scalability and real-time performance, remains a technical problem that urgently needs to be solved in this field. Summary of the Invention
[0005] This invention provides an instruction dependency verification method, electronic device, and storage medium to address the shortcomings of related technologies in instruction dependency verification, such as high resource consumption, insufficient timing accuracy, and poor scalability and real-time performance.
[0006] This invention provides a method for verifying instruction dependencies, comprising: For the target instruction in the design under test, a state slot under the thread to which the target instruction belongs is assigned, and the number of the state slots is determined based on the dependency depth M. Based on the dependencies and state slots of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, determine whether the target instruction meets the launch conditions; If the target instruction meets the launch conditions, dependency verification is performed based on the expected launch clock cycle of the target instruction and the actual launch clock cycle of the target instruction in the design under test.
[0007] According to the instruction dependency verification method provided by the present invention, the step of determining whether the target instruction meets the issuance conditions based on the dependency relationship and state slot of the target instruction, and the issuance timing of M state slots under the thread to which the target instruction belongs, includes: If the target instruction depends on the Kth instruction preceding it, the launch time of the dependent instruction is determined from the launch time of the M state slots under the thread to which the target instruction belongs, based on the state slot of the target instruction and the value of K. Based on the launch time of the dependent instruction, it is determined whether the target instruction meets the launch conditions; K is less than or equal to M.
[0008] According to the instruction dependency verification method provided by the present invention, the step of determining whether the target instruction meets the launch conditions based on the dependency relationship and state slot of the target instruction, and the launch timing of M state slots under the thread to which the target instruction belongs, further includes: If the target instruction has no dependencies, then the target instruction is determined to meet the launch conditions.
[0009] According to the instruction dependency verification method provided by the present invention, the method further includes, before allocating a state slot under the thread to which the target instruction belongs: If the instruction entry signal of the design under test is detected, and the first buffer set at the instruction entry of the design under test is empty, then the instruction corresponding to the instruction entry signal is taken as the target instruction and the target instruction is stored in the first buffer. If the first buffer set at the instruction entry point of the design under test is not empty, then the design under test is determined to be malfunctioning.
[0010] According to the instruction dependency verification method provided by the present invention, the step of determining whether the target instruction meets the issuance conditions based on the dependency relationship and state slot of the target instruction, and the issuance timing of M state slots under the thread to which the target instruction belongs, includes: If the second buffer set at the instruction emission port of the design under test is empty, the target instruction in the first buffer is stored in the second buffer, and based on the dependency relationship and state slot of the target instruction, as well as the emission timing of the M state slots under the thread to which the target instruction belongs, it is determined whether the target instruction meets the emission conditions.
[0011] According to the instruction dependency verification method provided by the present invention, the dependency verification is performed based on the expected launch clock cycle of the target instruction and the actual launch clock cycle of the target instruction in the design under test, and then further includes: If the expected transmit clock period and the actual transmit clock period are consistent, the target instruction in the second buffer is stored in the third buffer set in the instruction execution port of the design under test; If the command transmission end flag of the design under test is detected, the third buffer is cleared.
[0012] The instruction dependency verification method provided by the present invention further includes: If the command transmission end flag of the design under test is detected, the transmission timer of the status slot of the target command is set to zero.
[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the instruction dependency verification method as described above.
[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the instruction dependency verification method as described above.
[0015] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the instruction dependency verification method as described above.
[0016] The instruction dependency verification method, electronic device, and storage medium provided by this invention maintain only the launch timer for M state slots of dependency depth for each thread, instead of maintaining the state of all instructions indefinitely. This significantly reduces the system resource requirements for dependency verification, and the resource consumption remains constant even when verifying extremely long instruction streams, without increasing linearly with test time. Furthermore, even when expanding the dependency depth, only the number of timers needs to be increased linearly, rather than exponentially increasing the verification complexity, demonstrating good scalability and real-time performance. Additionally, based on the expected and actual launch clock cycles of the target instruction, single-clock-cycle dependency verification is achieved, and the verification logic runs in parallel with the design under test (DUT), enabling timely detection and reporting of abnormal behavior during verification, and significantly shortening the debugging cycle for the DUT. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a flowchart illustrating the instruction dependency verification method provided by the present invention.
[0019] Figure 2 This is a flowchart illustrating the instruction entry checkpoint in the instruction dependency verification method provided by this invention.
[0020] Figure 3 This is a flowchart illustrating the instruction dependency verification method provided by the present invention, specifically the checkpoint for the instruction emission port.
[0021] Figure 4 This is a flowchart illustrating the instruction execution port checkpoint in the instruction dependency verification method provided by the present invention.
[0022] Figure 5 This is a schematic diagram of the instruction dependency verification device provided by the present invention.
[0023] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0025] All actions involving the acquisition of signal information or data in this invention are carried out in compliance with the relevant data protection laws and policies of the country where the device is located, and with the authorization granted by the owner of the device.
[0026] Verification of instruction dependencies is a crucial step in ensuring the correctness of chip functionality, and is mainly achieved through black-box verification methods, white-box verification methods, or static assertion verification methods.
[0027] Black-box verification methods typically treat the Design Under Test (DUT) as a black box, judging the correctness of instruction dependencies solely by applying instruction-related inputs and observing the output behavior. While relatively straightforward, this approach, focusing on the input-output level, often struggles to perform fine-grained verification of when internal dependencies are satisfied. Therefore, black-box verification methods are prone to insufficient verification depth in scenarios requiring dependency verification at the clock cycle level.
[0028] White-box verification methods can also be understood as full-state tracking methods. To accurately grasp the instruction execution process, this method maintains a complete state machine for each instruction and continuously tracks its internal state evolution during verification. As the number of instructions increases, the storage resources and computational overhead required by white-box verification methods rise significantly, resulting in substantial system resource consumption.
[0029] Static assertion verification is a formalized verification method that allows for the constraint and inspection of the design under test by writing assertion rules. However, instruction dependencies often exhibit dynamic and variable characteristics in actual operation. Static assertion verification schemes struggle to cover complex dependency scenarios during dynamic execution, potentially leading to insufficient coverage or limited verification efficiency.
[0030] Therefore, most current methods for verifying instruction dependencies suffer from the following problems: High resource consumption: Traditional white-box verification methods often require maintaining an independent state machine for each instruction, resulting in storage overhead increasing linearly with the number of instructions, and accompanied by high computational overhead.
[0031] Insufficient timing precision: Traditional black-box verification methods are difficult to verify the specific timing of dependency fulfillment at the clock cycle level.
[0032] Poor scalability: As the complexity of dependencies increases, the complexity of verifying dependencies may increase exponentially, making it difficult to extend or maintain the verification method in more complex dependency scenarios.
[0033] Poor real-time performance: Due to the complexity of the verification logic, it is often difficult to detect violations in real time, resulting in a delay in problem discovery and affecting verification efficiency.
[0034] Therefore, in verification scenarios targeting instruction dependencies, how to achieve timing accuracy at the clock cycle level while controlling resource consumption, and effectively improve its scalability and real-time performance, remains a technical problem that urgently needs to be solved in this field.
[0035] To address the aforementioned technical problems, this invention provides a method for verifying instruction dependencies. Figure 1 This is a flowchart illustrating the instruction dependency verification method provided by the present invention, as shown below. Figure 1 As shown, the method includes: Step 110: For the target instruction in the design under test, allocate a state slot under the thread to the target instruction. The number of state slots is determined based on the dependency depth M.
[0036] Here, the design under test (DUT) refers to the RTL (Register Transfer Level) design code that needs to be verified. Specifically, it can be understood as the implementation source code of the hardware implementation that needs to be verified. The hardware implementation here can be a chip, or a computing core or execution unit in the chip, etc. This embodiment of the invention does not make specific limitations on this.
[0037] Within the design under test (DUT), multiple commands can be issued sequentially. During the sequential issuance of multiple commands by the DUT, each command can be treated as a target command, and the dependencies between the target commands can be verified.
[0038] For each instruction in the design under test, each instruction has its own thread identifier, that is, the thread to which each instruction belongs can be determined.
[0039] Furthermore, each instruction has its dependencies, which can be either independent or dependent on the previous K instructions in the same thread. Independent means the instruction can be issued directly without relying on any other instructions; dependent means the instruction depends on the previous K instructions issued before it within the same thread.
[0040] Here, the value of K is less than or equal to the dependency depth M. The dependency depth M refers to the maximum number of dependencies, which is the maximum distance between an instruction and its dependent instructions. For example, assuming the dependency depth M = 2, the value of K can be 0, 1, or 2. K = 0 indicates that the instruction has no dependencies, K = 1 indicates that the instruction depends on the previous instruction in the same thread, and K = 2 indicates that the instruction depends on the instruction two steps ahead in the same thread.
[0041] For a target instruction, a status slot under the thread to which it belongs can be assigned.
[0042] Here, for each thread, M state slots with a dependency depth can be pre-set. Each state slot is used to carry the state of one instruction in the thread. Therefore, compared with the traditional white-box verification method that requires maintaining a complete state machine for all instructions, in this embodiment of the invention, the state of the most recent M instructions is maintained for each thread. This can compress an infinitely long instruction stream into a state space of fixed size M, thereby greatly saving system resources.
[0043] Assign a state slot to the target instruction under its thread. Specifically, the state slot can be assigned to the target instruction based on a circular pointer mechanism. The state slot assigned to the target instruction can be the state slot corresponding to the earliest executed instruction among the M state slots under that thread. In this way, the new target instruction can overwrite the state slot of the old instruction, which can just indicate that the old instruction has been completed and the new instruction has started execution.
[0044] For example, when M is 2, two state slots, 0 and 1, can be set for each thread. In this case, a circular pointer mechanism that alternates between 0 and 1 can be used to allocate state slots for the target instruction. Specifically, in a thread, if the state slot allocated to the first instruction is 0, then the state slot allocated to the second instruction is 1, the state slot allocated to the third instruction is 0, and so on, to achieve sequential allocation of state slots.
[0045] Step 120: Based on the dependency relationship and state slot of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, determine whether the target instruction meets the launch conditions.
[0046] Specifically, in the process of verifying instruction dependencies for the design under test, for each thread, the instruction state under M state slots in that thread can be maintained separately.
[0047] The instruction status here is represented by the launch timer. The launch timer is a timing result starting from the actual launch clock cycle of the instruction. The launch timer increments over time, reflecting not only whether the instruction has been launched, but also the time remaining from the actual launch clock cycle of the instruction. This time can also be used as a criterion for determining whether the instruction has been completed. For example, if the launch timer exceeds a preset duration T, the instruction can be considered to have been completed; if the launch timer is less than or equal to the preset duration T, the instruction can be considered not to have been completed. Therefore, the launch timers of M status slots can represent the instruction status of M instructions preceding the target instruction. Furthermore, since K is less than or equal to M, the launch timers of the M status slots must be able to cover the instruction status of the dependent instructions of the target instruction.
[0048] After allocating status slots to the target instruction, it is possible to determine whether the target instruction meets the launch conditions based on the dependency relationship of the target instruction.
[0049] Specifically, if the target instruction has no dependency, meaning that the issuance of the target instruction does not depend on any other instruction, then there is no need to refer to the issuance timing of any state slot under the thread to which the target instruction belongs, and it can be directly determined that the target instruction meets the issuance conditions.
[0050] If the target instruction depends on the first K instructions of its owning thread, then based on the target instruction's state slots and dependencies, the state slots of its dependent instructions can be determined. This allows us to determine the emission timer of the dependent instruction's state slot from the emission timers of the M state slots in the target instruction's thread. From this, we can determine whether the dependent instruction has completed execution, and consequently, whether the target instruction meets the emission conditions. Here, if the dependent instruction has completed execution, the target instruction meets the emission conditions; if the dependent instruction has not completed execution, the target instruction does not meet the emission conditions.
[0051] Understandably, if the target instruction meets the emission conditions, it means that the target instruction is allowed to be emitted; if the target instruction does not meet the emission conditions, it means that the target instruction cannot be emitted at present, and the target instruction will block subsequent instructions of its owning thread.
[0052] Step 130: If the target instruction meets the launch conditions, perform dependency verification based on the expected launch clock cycle of the target instruction and the actual launch clock cycle of the target instruction in the design under test.
[0053] Specifically, when the target instruction meets the transmission conditions, the expected transmission clock cycle of the target instruction can be determined, which is based on the clock cycle when the target instruction meets the transmission conditions, or it can be understood as the clock cycle when the expected transmission behavior of the target instruction occurs.
[0054] In addition, the design under test can be monitored, and the clock cycle in which the design under test actually transmits the target command can be recorded, that is, the clock cycle in which the target command is actually transmitted. In this embodiment of the invention, this is referred to as the actual transmission clock cycle.
[0055] Based on this, the dependencies of the target instruction can be verified at the clock cycle level, using the expected and actual launch clock cycles. Specifically, if the expected and actual launch clock cycles of the target instruction are the same, the actual launch behavior of the design under test (DUT) for the target instruction is considered correct, and the dependency verification passes. If the expected and actual launch clock cycles are different, the actual launch behavior of the design under test for the target instruction is considered abnormal, and the dependency verification fails.
[0056] In the method provided in this embodiment of the invention, each thread only maintains the launch timer for M state slots with a dependency depth, instead of maintaining the state of all instructions indefinitely. This significantly reduces the system resource requirements for dependency verification, and the resource consumption remains constant when verifying extremely long instruction streams, without increasing linearly with the test time. Furthermore, even when expanding the dependency depth, only the number of timers needs to be increased linearly, rather than exponentially increasing the verification complexity, demonstrating good scalability and real-time performance. Additionally, based on the expected launch clock cycle and the actual launch clock cycle of the target instruction, dependency verification is achieved in a single clock cycle, and the verification logic runs in parallel with the design under test, enabling timely detection and reporting of abnormal behavior during verification, and significantly shortening the debugging cycle for the design under test.
[0057] Based on the above embodiments, step 120, determining whether the target instruction meets the launch conditions based on the dependency relationship and state slots of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, includes: If the target instruction depends on the Kth instruction preceding it, the launch time of the dependent instruction is determined from the launch time of the M state slots under the thread to which the target instruction belongs, based on the state slot of the target instruction and the value of K. Based on the launch time of the dependent instruction, it is determined whether the target instruction meets the launch conditions; K is less than or equal to M.
[0058] Specifically, for the case where the dependency of the target instruction is the Kth instruction preceding the target instruction, that is, the dependent instruction of the target instruction is the Kth instruction counting backwards from the target instruction, the state slot of the dependent instruction of the target instruction can be determined from the state slot of M under the thread to which the target instruction belongs, based on the state slot of the target instruction and the value of K in the dependency relationship of the target instruction.
[0059] Here, we assume the target instruction's status slot is... The state slots of the dependent instructions of the target instruction can be represented as: The % sign represents the modulo operation. This formula allows for the mathematical mapping of dependencies, meaning that the dependent instructions of the target instruction can be mapped to a finite number of M state slots.
[0060] After obtaining the status slots of the dependent instructions of the target instruction, the launch time of the status slots of the dependent instructions can be determined from the launch timers of the M status slots. Therefore, by determining whether the launch timer of this status slot exceeds a preset duration T, it can be determined whether the dependent instruction has been executed completely, and thus whether the target instruction meets the launch conditions.
[0061] It is understandable that if the launch time of the state slot is greater than the preset duration T, it can be determined that the dependency of the target command has been eliminated and the target command meets the launch conditions.
[0062] Based on any of the above embodiments, step 120, which involves determining whether the target instruction meets the launch conditions based on the dependency relationship and state slots of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, further includes: If the target instruction has no dependencies, then the target instruction is determined to meet the launch conditions.
[0063] Specifically, for cases where the target instruction has no dependency, meaning that the issuance of the target instruction does not depend on any other instruction, it is not necessary to refer to the issuance timing of any state slot under the thread to which the target instruction belongs, and it can be directly determined that the target instruction meets the issuance conditions.
[0064] In some embodiments, when the dependency depth M=2, the dependency relationship of each instruction can be represented as dep, where the value of dep can be one of 0, 1, or 2, wherein: dep=0 indicates that the instruction has no dependencies; When dep=1, it means that the instruction depends on the previous instruction in the same thread, that is, it needs to wait for the previous instruction to complete before the instruction is issued; the case of dep=1 can also be understood as the case of K=1.
[0065] When dep=2, it means that the instruction depends on the instruction two instructions above it in the same thread. That is, it needs to wait for the instruction two instructions above it to finish executing before the instruction is issued. The case of dep=2 can also be understood as the case of K=2.
[0066] For the target instruction, if the target instruction's dep=0, then it is directly determined that the target instruction meets the launch conditions; if the target instruction's dep≠0, then it is checked whether cnt[wg_id][ptr_id+dep] is greater than T. If it is greater, then it is determined that the target instruction meets the launch conditions; otherwise, it continues to wait until the target instruction meets the launch conditions.
[0067] Where ptr_id is the state slot of the target instruction, [ptr_id+dep] represents the state slot of the dependent instruction of the target instruction obtained by mapping the state slot of the target instruction to dep, wg_id represents the identifier of the thread to which the target instruction belongs, and cnt[wg_id][ptr_id+dep] represents the emission timer of the state slot of the dependent instruction of the target instruction.
[0068] Based on any of the above embodiments, in step 110, before allocating a status slot under the thread to which the target instruction belongs, the following steps are also included: If the instruction entry signal of the design under test is detected, and the first buffer set at the instruction entry of the design under test is empty, then the instruction corresponding to the instruction entry signal is taken as the target instruction and the target instruction is stored in the first buffer. If the first buffer set at the instruction entry point of the design under test is not empty, then the design under test is determined to be malfunctioning.
[0069] Specifically, to achieve real-time verification of the design under test (DUT), buffers can be established for the lifecycle nodes of instructions within the DUT. In this embodiment of the invention, a buffer, referred to here as the first buffer, can be set at the instruction entry point of the DUT. It can be understood that the instruction entry point here is the interface through which the DUT receives a new instruction, or the node where an instruction enters the DUT. The first buffer, set at the instruction entry point, is used to buffer instructions entering the DUT.
[0070] Based on this, signal monitoring can be performed on the design under test (DUT). Specifically, instruction entry signals can be monitored. If an instruction entry signal of the DUT is detected, it indicates that an instruction is entering the DUT during the current clock cycle.
[0071] To synchronize with the design under test (DUT), when an instruction entry signal is detected and the first buffer is empty, the instruction corresponding to the instruction entry signal can be directly used as the target instruction for synchronization verification and stored in the first buffer. When the first buffer is not empty, the design under test is directly determined to be malfunctioning.
[0072] Understandably, within the design under test (DUT), only one instruction can be issued and executed within the same clock cycle. Given this, if an instruction entry signal is detected and the first buffer is not empty, it indicates that the instruction previously received by the DUT has not yet been issued or executed. The entry of a new instruction violates the rule of issuing only one instruction within the same clock cycle, thus confirming an abnormal operation of the DUT.
[0073] Furthermore, after storing the target instruction in the first buffer, the dependency relationship of the target instruction can be determined, and a state slot under the thread to which the target instruction belongs can be allocated to facilitate the execution of dependency verification for the target instruction.
[0074] In the method provided in the embodiments of the present invention, real-time verification of the design under test is achieved by setting a first buffer at the instruction entry point of the design under test and monitoring the instruction entry signal of the design under test.
[0075] Based on any of the above embodiments, step 120, determining whether the target instruction meets the launch conditions based on the dependency relationship and state slot of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, includes: If the second buffer set at the instruction emission port of the design under test is empty, the target instruction in the first buffer is stored in the second buffer, and based on the dependency relationship and state slot of the target instruction, as well as the emission timing of the M state slots under the thread to which the target instruction belongs, it is determined whether the target instruction meets the emission conditions.
[0076] Specifically, in addition to setting a first buffer at the instruction entry point of the design under test (DUT), a buffer can also be set at the instruction dispatch port of the DUT, referred to here as the second buffer. It can be understood that the instruction dispatch port referred to here is the interface through which the DUT sends instructions from the waiting queue into the execution channel. The second buffer set at the instruction dispatch port is used to buffer instructions waiting to be dispatched.
[0077] After storing the target instruction into the first buffer, it can be determined in the next clock cycle whether the second buffer is empty. If the second buffer is empty, that is, there is no instruction waiting to be issued, the target instruction in the first buffer can be stored into the second buffer, and the first buffer is cleared; if the second buffer is not empty, it enters a waiting state, waiting for the second buffer to become empty before storing the target instruction in the first buffer into the second buffer.
[0078] For a target instruction stored in the second buffer, it can be determined whether the target instruction meets the emission conditions based on the target instruction's dependencies and state slots, as well as the emission timing of the M state slots under the thread to which the target instruction belongs.
[0079] In this embodiment of the invention, by setting a first buffer and a second buffer, and storing the target instruction from the first buffer into the second buffer when the second buffer is empty, the hardware pipeline mechanism of the design under test is simulated, providing conditions for achieving synchronous real-time verification with the design under test.
[0080] Based on any of the above embodiments, after step 130, the instruction dependency verification method further includes: If the expected transmit clock period and the actual transmit clock period are consistent, the target instruction in the second buffer is stored in the third buffer set in the instruction execution port of the design under test; If the command transmission end flag of the design under test is detected, the third buffer is cleared.
[0081] Specifically, in addition to setting a first buffer at the instruction entry point of the design under test (DUT) and a second buffer at the instruction emission port of the DUT, in this embodiment of the invention, a buffer can also be set at the instruction execution port of the DUT, referred to here as a third buffer. It is understood that the instruction execution port referred to here is the interface through which the DUT indicates the end of instruction emission. The third buffer set at the instruction execution port is used to buffer instructions that have been emitted but have not yet been completed.
[0082] If the expected transmit clock cycle matches the actual transmit clock cycle, which means the dependency verification of the target instruction is successful, it can be determined that the target instruction has been correctly transmitted. Therefore, the target instruction in the second buffer is stored in the third buffer.
[0083] After the actual target command is launched and the launch is confirmed to be complete, the design under test will generate a command launch end flag. The command launch end flag is used to indicate that the target command launch is complete.
[0084] After storing the target instruction from the second buffer into the third buffer, the design under test (DUT) can be monitored in real time. If the instruction issuance end flag of the DUT is detected, it indicates that the DUT has completed issuing the target instruction and the target instruction has begun execution. At this point, the third buffer can be cleared, that is, the target instruction can be deleted from the third buffer, thus providing conditions for subsequent instruction issuance.
[0085] Based on any of the above embodiments, the instruction dependency verification method further includes: If the command transmission end flag of the design under test is detected, the transmission timer of the status slot of the target command is set to zero.
[0086] Specifically, if the instruction emission completion flag of the design under test (DUT) is detected, it indicates that the DUT has completed the emission of the target instruction and the target instruction has begun execution. At this time, in addition to clearing the third buffer, the emission timer of the target instruction's status slot can be set to zero. Thus, the status slot of the target instruction starts timing from the start of the DUT's completion of the target instruction emission, which can accurately record the time taken from the completion of the target instruction emission and the start of execution to the current time period, thereby providing a reference for whether subsequent instructions need to wait for the completion of this instruction.
[0087] In this embodiment of the invention, the launch timer can carry the dual semantics of timing and state. Specifically, a launch timer > T indicates that the dependency has been eliminated, and a launch timer set to zero indicates that the instruction has just been launched and has started execution.
[0088] Based on any of the above embodiments, in this embodiment of the invention, three checkpoints can be set for the lifecycle of instructions within the design under test: an instruction entry checkpoint, an instruction dispatch checkpoint, and an instruction execution checkpoint. Furthermore, buffers are set at the instruction entry, instruction dispatch, and instruction execution points, namely a first buffer, a second buffer, and a third buffer, respectively. The setting of these three buffers represents three stages in the instruction lifecycle: instruction ready after instruction processing, waiting to be dispatched, and dispatch completed. Dispatch completed can also be understood as the start of execution.
[0089] Furthermore, assuming a dependency depth M=2, a counter array cnt[wg_id][2] can be constructed to represent the time elapsed between the completion of the first two instructions of each thread wg_id in the design under test, and the waiting time for other instructions. This time elapsed will automatically increment with the clock. In essence, the counter array stores the emission time of each state slot for each thread under the design under test. Each element in the array corresponds to the emission time of a state slot for a thread, representing the time elapsed between the completion of one of the first two instructions of a thread and the waiting time for other instructions.
[0090] Figure 2 This is a flowchart illustrating the instruction entry point checkpoint in the instruction dependency verification method provided by this invention, as shown below. Figure 2 As shown, the instruction entry points of the design under test can be monitored.
[0091] If an instruction entry signal is detected, that is, if a ready instruction is detected to enter the instruction entry, it can be determined whether the first buffer is empty.
[0092] If the first buffer is not empty at this time, it is determined that the design under test is malfunctioning; if the first buffer is empty at this time, the instruction entering the instruction entry point can be used as the target instruction, and the status slot ptr_id under the thread to be assigned to the target instruction in sequence, and the dependency relationship of the target instruction is recorded. When M=2, the status slot ptr_id is 0 or 1.
[0093] In addition, the target instruction can be stored in the first buffer.
[0094] After this, it can be determined whether the second buffer is empty. If the second buffer is empty, the target instruction in the first buffer is stored in the second buffer.
[0095] Figure 3 This is a flowchart illustrating the instruction dependency verification method provided by the present invention, specifically the checkpoint for the instruction emission port. Figure 3 As shown, the command transmission port of the design under test can be monitored.
[0096] In addition, it is possible to determine in real time whether the second buffer is empty. If the second buffer is not empty, the launch time of the target instruction in the second buffer can be obtained from the counter array cnt[wg_id][2] based on the status slot of the target instruction and the dependency relationship of the target instruction. Then, it is determined whether the launch time is greater than or equal to the preset duration T, thereby determining whether the target instruction meets the launch conditions.
[0097] If the launch time is greater than or equal to the preset duration T, it can be determined that the target command meets the launch conditions, and thus the expected launch clock period for the target command can be determined.
[0098] Furthermore, if a transmitted command is detected at the command transmission port, the actual transmission clock cycle of the command can be recorded. Based on this, by comparing the expected transmission clock cycle and the actual transmission clock cycle, it can be determined whether the expected transmission behavior and the actual transmission behavior of the target command occurred simultaneously.
[0099] If both events occur simultaneously, the target instruction in the second buffer is stored in the third buffer. If neither event occurs simultaneously, the design under test is determined to be malfunctioning.
[0100] Figure 4 This is a flowchart illustrating the instruction execution port checkpoint in the instruction dependency verification method provided by this invention, as shown below. Figure 4 As shown, the instruction execution port of the design under test can be monitored.
[0101] Furthermore, during this process, the count of each element in the counter array accumulates automatically as the clock cycle progresses.
[0102] If an instruction issuance end marker is detected at the instruction execution port, the cnt[wg_id][ptr_id] in the counter array can be set to zero. Here, cnt[wg_id][ptr_id] refers to the issuance timer of the status slot of the target instruction under the thread to which the target instruction belongs in the counter array. After detecting the instruction issuance end marker, the issuance timer is set to zero, so that the counter array can start the issuance timer for the target instruction at the clock cycle when the device under test finishes issuing the target instruction and the target instruction begins execution.
[0103] In the method provided in this embodiment of the invention, assuming a dependency depth M=2, only two alternating 0 / 1 state slots are needed to verify instruction dependencies for a single-threaded instruction stream. If the dependency depth M is expanded to a larger value, only M state slots are still needed to verify instruction dependencies for a single-threaded instruction stream.
[0104] In a multi-threaded instruction stream, only an N×M counter is needed to verify dependencies down to the clock cycle level, thus ensuring the correctness of instruction dependency functions. Here, N is the number of threads.
[0105] Furthermore, by using the first, second, and third buffers to implement a three-stage pipeline of entry → wait → execution, it is possible to achieve strict synchronization with the design under test, thereby enabling precise real-time verification at the clock cycle level.
[0106] The instruction dependency verification device provided by the present invention is described below. The instruction dependency verification device described below and the instruction dependency verification method described above can be referred to in correspondence.
[0107] Figure 5 This is a schematic diagram of the instruction dependency verification device provided by the present invention, as shown below. Figure 5 As shown, the device includes: Slot allocation unit 510 is used to allocate a state slot under the thread to a target instruction in the design under test. The number of state slots is determined based on the dependency depth M. The launch judgment unit 520 is used to determine whether the target instruction meets the launch conditions based on the dependency relationship and status slot of the target instruction, as well as the launch timing of the M status slots under the thread to which the target instruction belongs. The launch verification unit 530 is used to perform dependency verification based on the expected launch clock cycle of the target instruction and the actual launch clock cycle of the target instruction in the design under test, provided that the target instruction meets the launch conditions.
[0108] In the apparatus provided in this embodiment of the invention, only the launch timer for M state slots with a dependency depth is maintained for each thread, instead of maintaining the state of all instructions indefinitely. This significantly reduces the system resource requirements for dependency verification, and the resource consumption remains constant when verifying extremely long instruction streams, without increasing linearly with the test time. Furthermore, even when expanding the dependency depth, only the number of timers needs to be increased linearly, rather than exponentially increasing the verification complexity, demonstrating good scalability and real-time performance. Additionally, based on the expected launch clock cycle and the actual launch clock cycle of the target instruction, dependency verification is achieved in a single clock cycle, and the verification logic runs in parallel with the design under test, enabling timely detection and reporting of abnormal behavior during verification, and significantly shortening the debugging cycle for the design under test.
[0109] Based on any of the above embodiments, the transmission determination unit is specifically used for: If the target instruction depends on the Kth instruction preceding it, the launch time of the dependent instruction is determined from the launch time of the M state slots under the thread to which the target instruction belongs, based on the state slot of the target instruction and the value of K. Based on the launch time of the dependent instruction, it is determined whether the target instruction meets the launch conditions; K is less than or equal to M.
[0110] Based on any of the above embodiments, the transmission determination unit is further configured to: If the target instruction has no dependencies, then the target instruction is determined to meet the launch conditions.
[0111] Based on any of the above embodiments, the slot allocation unit is further configured to: If the instruction entry signal of the design under test is detected, and the first buffer set at the instruction entry of the design under test is empty, then the instruction corresponding to the instruction entry signal is taken as the target instruction and the target instruction is stored in the first buffer. If the first buffer set at the instruction entry point of the design under test is not empty, then the design under test is determined to be malfunctioning.
[0112] Based on any of the above embodiments, the transmission determination unit is specifically used for: If the second buffer set at the instruction emission port of the design under test is empty, the target instruction in the first buffer is stored in the second buffer, and based on the dependency relationship and state slot of the target instruction, as well as the emission timing of the M state slots under the thread to which the target instruction belongs, it is determined whether the target instruction meets the emission conditions.
[0113] Based on any of the above embodiments, the launch verification unit is further configured to: If the expected transmit clock period and the actual transmit clock period are consistent, the target instruction in the second buffer is stored in the third buffer set in the instruction execution port of the design under test; If the command transmission end flag of the design under test is detected, the third buffer is cleared.
[0114] Based on any of the above embodiments, the launch verification unit is further configured to: If the command transmission end flag of the design under test is detected, the transmission timer of the status slot of the target command is set to zero.
[0115] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communications interface 620, and the memory 630 communicate with each other via the communication bus 640. The processor 610 can call logical instructions in the memory 630 to execute an instruction dependency verification method, which includes: For the target instruction in the design under test, a state slot under the thread to which the target instruction belongs is assigned, and the number of the state slots is determined based on the dependency depth M. Based on the dependencies and state slots of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, determine whether the target instruction meets the launch conditions; If the target instruction meets the launch conditions, dependency verification is performed based on the expected launch clock cycle of the target instruction and the actual launch clock cycle of the target instruction in the design under test.
[0116] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0117] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program, the computer program being able to be stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer being able to execute the instruction dependency verification method provided by the above methods, the method comprising: For the target instruction in the design under test, a state slot under the thread to which the target instruction belongs is assigned, and the number of the state slots is determined based on the dependency depth M. Based on the dependencies and state slots of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, determine whether the target instruction meets the launch conditions; If the target instruction meets the launch conditions, dependency verification is performed based on the expected launch clock cycle of the target instruction and the actual launch clock cycle of the target instruction in the design under test.
[0118] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the instruction dependency verification method provided by the methods described above, the method comprising: For the target instruction in the design under test, a state slot under the thread to which the target instruction belongs is assigned, and the number of the state slots is determined based on the dependency depth M. Based on the dependencies and state slots of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, determine whether the target instruction meets the launch conditions; If the target instruction meets the launch conditions, dependency verification is performed based on the expected launch clock cycle of the target instruction and the actual launch clock cycle of the target instruction in the design under test.
[0119] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0120] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for verifying instruction dependencies, characterized in that, include: For the target instruction in the design under test, a state slot under the thread to which the target instruction belongs is assigned, and the number of the state slots is determined based on the dependency depth M. Based on the dependencies and state slots of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, determine whether the target instruction meets the launch conditions; If the target instruction meets the launch conditions, dependency verification is performed based on the expected launch clock cycle of the target instruction and the actual launch clock cycle of the target instruction in the design under test.
2. The instruction dependency verification method according to claim 1, characterized in that, The determination of whether the target instruction meets the launch conditions based on the dependency relationship and state slot of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, includes: If the target instruction depends on the Kth instruction preceding it, the launch time of the dependent instruction is determined from the launch time of the M state slots under the thread to which the target instruction belongs, based on the state slot of the target instruction and the value of K. Based on the launch time of the dependent instruction, it is determined whether the target instruction meets the launch conditions; K is less than or equal to M.
3. The instruction dependency verification method according to claim 2, characterized in that, The step of determining whether the target instruction meets the launch conditions based on the dependency relationship and state slots of the target instruction, as well as the launch timing of the M state slots under the thread to which the target instruction belongs, further includes: If the target instruction has no dependencies, then the target instruction is determined to meet the launch conditions.
4. The instruction dependency verification method according to any one of claims 1 to 3, characterized in that, Prior to allocating a status slot under the thread to the target instruction, the process also includes: If the instruction entry signal of the design under test is detected, and the first buffer set at the instruction entry of the design under test is empty, then the instruction corresponding to the instruction entry signal is taken as the target instruction and the target instruction is stored in the first buffer. If the first buffer set at the instruction entry point of the design under test is not empty, then the design under test is determined to be malfunctioning.
5. The instruction dependency verification method according to claim 4, characterized in that, The determination of whether the target instruction meets the launch conditions based on the dependency relationship and state slot of the target instruction, and the launch timing of the M state slots under the thread to which the target instruction belongs, includes: If the second buffer set at the instruction emission port of the design under test is empty, the target instruction in the first buffer is stored in the second buffer, and based on the dependency relationship and state slot of the target instruction, as well as the emission timing of the M state slots under the thread to which the target instruction belongs, it is determined whether the target instruction meets the emission conditions.
6. The instruction dependency verification method according to claim 5, characterized in that, The process involves performing dependency verification based on the expected transmit clock cycle of the target instruction and the actual transmit clock cycle of the target instruction in the design under test, followed by: If the expected transmit clock period and the actual transmit clock period are consistent, the target instruction in the second buffer is stored in the third buffer set in the instruction execution port of the design under test; If the command transmission end flag of the design under test is detected, the third buffer is cleared.
7. The instruction dependency verification method according to claim 6, characterized in that, Also includes: If the command transmission end flag of the design under test is detected, the transmission timer of the status slot of the target command is set to zero.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the instruction dependency verification method as described in any one of claims 1 to 7.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the instruction dependency verification method as described in any one of claims 1 to 7.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the instruction dependency verification method as described in any one of claims 1 to 7.