Chip yield prediction method and prediction system

Abstract

The application relates to the chip yield prediction technical field and discloses a chip yield prediction method and a prediction system. The method comprises the following steps: a process flow graph defining physical flow conversion timing constraints is constructed, and candidate features are coded into agents containing calculation rules and equipment application rules; then, a machine table stability index dynamic adjustment parameter is connected to update a probability, evolution operation is performed on the agent group, and timing logic checking is performed on the offspring feature structure by using the process flow graph to remove invalid structures violating the physical timing; finally, the agents meeting the conditions are converted into explicit mathematical formulas to train a yield prediction model. By introducing the physical timing checking mechanism and the equipment state fusion strategy, the application effectively removes false features violating the cause-effect logic, accurately captures the parallel machine table differences, and improves the convergence efficiency of feature mining, the physical interpretability and the reliability of the yield prediction model.

Description

Technical Field

[0001] This invention relates to the field of chip yield prediction technology, specifically to a chip yield prediction method and prediction system. Background Technology

[0002] Semiconductor integrated circuit manufacturing is an extremely complex systems engineering project, encompassing hundreds or even thousands of precision processes such as photolithography, etching, and thin film deposition. As process nodes continue to shrink, wafer fabs deploy a large number of high-frequency sensors on the production line to collect massive amounts of process data in real time. Fully utilizing this multi-source heterogeneous process data and analyzing the correlation between key process parameters and yield to establish high-precision yield prediction models has become a key means to promptly detect process defects, optimize process windows, and improve production efficiency.

[0003] Existing yield prediction technologies widely employ machine learning or deep learning algorithms, typically utilizing automated feature engineering methods to mathematically transform and combine time-series parameters such as temperature, pressure, and gas flow rate collected by sensors, constructing a high-dimensional feature space. Subsequently, models such as support vector machines, random forests, or neural networks are used to fit the nonlinear mapping relationship between features and yield labels. This data-driven modeling approach reduces reliance on expert experience to some extent, can handle large-scale production line data, and is currently the mainstream application direction in the field of semiconductor intelligent manufacturing.

[0004] However, existing yield prediction technologies, based on statistical correlation-based feature mining, often neglect the physical flow constraints between processes. Algorithms tend to forcibly combine parameters that are numerically correlated but violate causal logic. Semiconductor production lines commonly employ multi-machine parallel operation modes, and existing methods typically mix data from different machines within the same process. This aggregation method masks the individual differences in physical equipment, causing minute drifts in specific machine chambers to be drowned out by overall data noise, making it difficult to accurately capture equipment-level faults. Existing feature search strategies often use globally uniform parameter settings, lacking awareness of process stability, resulting in a significant waste of computational resources on already stable and mature processes. Therefore, this invention provides a chip yield prediction method and system to address the shortcomings of existing technologies. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a chip yield prediction method and system, which solves the problems in existing yield prediction technologies, such as the lack of physical flow time constraints in feature mining leading to the proliferation of false features, the neglect of physical differences between parallel machines making it difficult to capture minor equipment failures, and the lack of targeted feature search strategies resulting in low computational efficiency and a lack of physical interpretability of the model.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A first aspect of the present invention provides a chip yield prediction method, comprising the following steps:

[0008] S1. Obtain semiconductor manufacturing process data to construct a process dataset, and parse the process logic timestamps to construct a process flow diagram that defines physical flow timing constraints;

[0009] S2. Using the sensor parameters in the process dataset, candidate features are encoded into intelligent agents containing calculation rules and equipment applicable rules, and the intelligent agents are divided into corresponding process groups according to the topological structure of the process flow diagram.

[0010] S3. Analyze the mathematical operation formula of the intelligent agent in each process group, calculate the feature output value in combination with the activation state of the applicable rules of the equipment, and quantify the importance score by calculating the correlation between the feature output value and the yield label.

[0011] S4. Select and retain the preferred intelligent agent group based on importance score, and dynamically adjust the parameter update probability of each process group by connecting to the machine stability index;

[0012] S5. Based on the adjusted parameter update probability, perform evolutionary operations on the selected intelligent agent population to generate a progeny population, and use the process flow diagram to perform temporal logic verification on the progeny feature structure to eliminate invalid structures that violate physical timing.

[0013] S6. Transform the agent that meets the termination condition into an explicit mathematical formula, and use the output of the explicit mathematical formula to construct a feature matrix to train the chip yield prediction model.

[0014] Preferably, in step S1, constructing the process flow diagram defining physical flow timing constraints further includes:

[0015] The wafer transfer data in the manufacturing execution system is analyzed to identify all unique process steps. Each process step is defined as an independent node in the graph, and a mapping relationship between sensor parameter indexes and the independent nodes is established.

[0016] Based on the physical path of actual wafer manufacturing, directed edges are established between independent nodes of adjacent process steps and logical timestamps are assigned to construct a directed acyclic graph structure that represents the causal dependencies between processes.

[0017] The physical flow timing constraints are defined using the directed acyclic graph structure, and the reachability matrix between nodes is generated.

[0018] Preferably, in step S2, encoding the candidate features into an agent that includes computational rules and device-applicable rules further includes:

[0019] A linear symbol string consisting of a head and a tail is constructed to define the computational rules of the agent. The length of the tail is strictly constrained based on the length of the head and the number of parameters in the function set, ensuring that any randomly combined symbol string can be decoded into a grammatically closed mathematical expression.

[0020] The physical information of parallel machines under the process steps associated with the candidate features is analyzed, and a binary vector with the same dimension as the number of machines is generated as the applicable rules for the equipment. Each component in the vector represents the active or silent state of the agent on the corresponding physical machine.

[0021] The linear symbol string and the binary vector are combined and associated with the same feature index to complete the encoding of the candidate features, generating an intelligent entity that simultaneously possesses mathematical operation logic and physical device constraints.

[0022] Preferably, in step S3, the step of calculating the feature output value based on the activation state of the device's applicable rules further includes:

[0023] The linear symbol string in the intelligent agent is converted into a mathematical expression tree using a preset decoding strategy. The sensor data of the wafer sample is then input into the mathematical expression tree for calculation to generate initial basic feature values ​​that do not contain machine status information.

[0024] The physical machine index actually used in the corresponding process step is identified based on the wafer sample metadata, and the corresponding activation state component is extracted from the binary vector carried by the agent based on the physical machine index.

[0025] The initial basic feature values ​​are corrected by using the extracted active state components. When the component indicates a silent state, the output is forcibly set to zero to generate the final feature output value filtered by the physical environment.

[0026] Preferably, in step S4, the step of dynamically adjusting the parameter update probability of each process group based on the stability index of the access machine further includes:

[0027] Obtain the machine process capability index of the physical machine set covered by each process group, and calculate the average value as a machine stability index to measure the degree of physical fluctuation in the corresponding process area.

[0028] Construct a negative correlation mapping model between parameter update probability and machine stability index, and calculate the dynamic variation probability value adapted to the current physical state based on the negative correlation mapping model;

[0029] The dynamic mutation probability value is used to drive the adjustment of the evolution strategy. For groups with lower stability index, the mutation probability is increased to enhance exploration, while for groups with higher stability index, the mutation probability is decreased to focus on convergence.

[0030] Preferably, in step S5, the step of using the process flow diagram to perform time-series logic verification on the offspring feature structure to eliminate invalid structures that violate physical timing further includes:

[0031] The algorithm analyzes all sensor parameters referenced in the mathematical structure of the evolved offspring intelligent agent and locates the set of graph nodes corresponding to the sensor parameters in the process flow graph based on the attribution mapping relationship.

[0032] Based on the directed acyclic graph structure, it is retrieved whether there is a directed path that conforms to the physical flow direction between any two nodes in the graph node set;

[0033] A path-based elimination mechanism is implemented. If there is no physically reachable path between nodes in the graph, the child feature structure is determined to violate the physical flow sequence constraints and is eliminated, while only logically valid structures are retained.

[0034] Preferably, in step S4, the step of selecting and retaining the preferred group of agents based on importance scores is as follows:

[0035] Calculate the cosine similarity between the feature output vectors generated by different agents within the same process group to quantify the degree of overlap between features at the data representation level;

[0036] When the cosine similarity between two agents exceeds a preset threshold, a competition mechanism is triggered to compare their importance scores.

[0037] Agents with higher importance scores are retained as preferred members of the agent group, while those with lower importance scores are removed from the group.

[0038] Preferably, in step S6, the step of converting the agent that satisfies the termination condition into an explicit mathematical formula further includes:

[0039] Linear symbol strings are extracted from the preferred intelligent agent group and restored to mathematical expression trees. The mathematical expression trees are then reconstructed into standard infix mathematical expressions using an inorder traversal algorithm.

[0040] Perform a semantic substitution operation to replace the parameter index in the standard infix mathematical expression with the actual process parameter name, and convert the binary vector into a conditional judgment statement about the machine ID;

[0041] The replaced infix mathematical expression is combined with the conditional statement to generate an explicit mathematical formula for physical mechanisms and device dependencies.

[0042] Preferably, in step S6, the step of constructing a feature matrix using the output of an explicit mathematical formula to train a chip yield prediction model further includes:

[0043] The original sample data in the process dataset is sequentially input into the transformed explicit mathematical formula to calculate the high-dimensional feature vector corresponding to each sample.

[0044] The high-dimensional feature vectors of all samples are stacked in order to construct a high-density feature matrix, which serves as the input variable for the prediction model.

[0045] A regression model is constructed using the feature matrix as input and the yield label as the target. The model weights are optimized by minimizing the loss function between the predicted and actual values ​​to generate the final chip yield prediction model.

[0046] A second aspect of the present invention provides a chip yield prediction system, comprising:

[0047] The process data space construction module is used to acquire semiconductor manufacturing process data to construct a process dataset and parse the process logic timestamps to construct a process flow diagram that defines physical flow timing constraints.

[0048] The feature structure encoding module is used to encode candidate features into intelligent agents containing calculation rules and equipment applicable rules using sensor parameters in the process dataset, and to divide the intelligent agents into corresponding process groups according to the topological structure of the process flow diagram.

[0049] The feature fitness evaluation module is used to parse the mathematical formulas generated by the agents in each process group, calculate the feature output value by combining the activation state of the applicable rules of the equipment, and quantify the importance score by calculating the correlation between the feature output value and the yield label.

[0050] The feature optimization and screening module is used to select and retain the preferred intelligent agent group based on importance scores, and to dynamically adjust the parameter update probability of each process group by connecting to the machine stability index.

[0051] The feature iteration generation module is used to perform evolutionary operations on the preferred intelligent agent population based on the adjusted parameter update probability to generate a progeny population, and to use the process flow diagram to perform temporal logic verification on the feature structure of the progeny to eliminate invalid structures that violate physical timing.

[0052] The feature parsing and prediction module is used to convert agents that meet the termination conditions into explicit mathematical formulas, and to use the output of the explicit mathematical formulas to construct a feature matrix to train the chip yield prediction model.

[0053] This invention provides a chip yield prediction method and system. It has the following advantages:

[0054] 1. This invention introduces a timing logic verification mechanism during feature evolution by constructing a process flow diagram that includes physical flow timing constraints. By using a directed acyclic graph structure to perform physical reachability retrieval on the process nodes referenced by the offspring features, invalid structures that violate the process sequence or causal logic can be directly eliminated, ensuring that the final generated features follow the physical flow rules of semiconductor manufacturing, thereby improving the physical interpretability of the features and the causal reliability of the prediction model.

[0055] 2. This invention adopts an intelligent agent coding method that includes applicable equipment rules, and structurally integrates mathematical calculation rules with the physical state of the equipment. By parsing the physical information of parallel equipment to generate binary activation vectors, the feature response is dynamically corrected according to the actual equipment used on the wafer when calculating the feature output value. This effectively distinguishes the different impacts of different equipment on yield, solves the problem that traditional methods are difficult to capture small deviations between parallel equipment or specific chamber faults, and improves the model's perception accuracy of equipment-level process fluctuations.

[0056] 3. This invention utilizes the machine stability index to dynamically adjust the parameter update probability during the evolution process, establishing a data-driven adaptive search strategy. It adjusts the variation amplitude in real time based on the average machine process capability index of process groups, increases the exploration weight for areas with large process fluctuations, and focuses on convergence optimization for areas with stable processes. This avoids wasting computing resources in low-value areas and improves the convergence efficiency and targeting of feature mining algorithms in complex high-dimensional process data spaces. Attached Figure Description

[0057] Figure 1 This is a system architecture diagram of the present invention;

[0058] Figure 2 This is a flowchart of the method steps of the present invention;

[0059] Figure 3 This is a timing logic verification flowchart of the process flow diagram of the present invention;

[0060] Figure 4 This is a graph showing the parameter variation probability adjustment curve of the machine stability index of the present invention. Detailed Implementation

[0061] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] See attached document Figure 1 and attached Figure 2 , Figure 1 This is a system architecture diagram according to an embodiment of the present invention. Figure 2 This is a flowchart of method steps according to an embodiment of the present invention.

[0063] This invention provides a chip yield prediction system, comprising:

[0064] The process data space construction module is used to acquire process data of the entire semiconductor manufacturing process to construct a process dataset, and to parse the time sequence of each process to construct a process flow diagram that defines the physical flow timing constraints.

[0065] The feature structure encoding module is used to define basic computing units based on sensor parameters in the process dataset, represent potential candidate features as virtual intelligent agents containing computing rules and equipment applicable rules, and classify the intelligent agents into corresponding process groups according to the structure of the process flow diagram.

[0066] The feature fitness evaluation module is used to parse the agents in each process group into mathematical operation formulas, calculate feature output values ​​by combining the activation state of the applicable rules of the equipment, and quantify the importance score of the agent by calculating the correlation between the feature output values ​​and the yield label.

[0067] The feature optimization and screening module is used to select the best and worst agents based on importance scores. It eliminates redundant features with high repetition by calculating the similarity between agents, and dynamically adjusts the parameter variation probability of each process group by connecting to the stability index of the real-time machine.

[0068] The feature iteration generation module is used to reorganize and update the retained agents based on the adjusted parameter mutation probability to generate the next generation of the population. During the generation process, the process flow diagram is used to perform temporal logic verification and remove invalid feature structures that violate the physical order.

[0069] The feature parsing and prediction module is used to extract agents with high importance scores and convert them into explicit mathematical formulas after the iterative execution meets the termination condition. The output of these mathematical formulas is then used to build a chip yield prediction model.

[0070] This invention provides a chip yield prediction method, the workflow of which may include the following steps:

[0071] S1, the process data space construction module acquires multi-source heterogeneous process data from the entire semiconductor manufacturing process to construct a high-dimensional process dataset, and parses the logical timestamps of each process to construct a process flow diagram that defines physical flow timing constraints.

[0072] S2, the feature structure encoding module defines the basic computing unit based on the sensor parameters in the process dataset. Using the preset encoding rules, it represents the potential candidate features as an intelligent agent containing the computing rules and the applicable rules of the equipment, and divides the intelligent agent into the corresponding process group according to the topological structure of the process flow diagram.

[0073] S3, the feature fitness evaluation module parses the agents in each process group to generate mathematical operation formulas, calculates feature output values ​​in combination with the activation state of the applicable rules of the equipment, and calculates the correlation between feature output values ​​and yield labels to quantify the importance score of the agents.

[0074] S4, the feature optimization and screening module filters based on the importance score of the agent, calculates the similarity of the output results between agents to remove highly redundant features, and connects to the stability index of the real-time machine to dynamically adjust the parameter update probability of each process group.

[0075] S5, the feature iteration generation module performs recombination and mutation operations on the selected agents based on the adjusted parameter update probability to generate the next generation population, and uses the process flow diagram to perform temporal logic verification to intercept invalid feature structures that violate physical timing.

[0076] S6, after the feature parsing and prediction module iteratively executes until the termination condition is met, extracts the agents with high importance scores and transforms them into explicit mathematical formulas, and reconstructs the output vectors of these formulas into feature matrices to train the chip yield prediction model.

[0077] For step S1, in one specific implementation, a unified process dataset containing input features and target yield is constructed through data acquisition and alignment operations. At least three types of data are acquired from the wafer fab's Computer Integrated Manufacturing (CIM) system: the first type is equipment sensor data generated at each process step during wafer manufacturing, i.e., FDC data; the second type is online measurement data inserted into the process flow, i.e., Metrology data; and the third type is electrical test results generated during the wafer testing phase, specifically wafer yield data for each bin category. For the acquisition of FDC and Metrology data, those skilled in the art can employ standard data extraction and conversion processes based on the actual data storage architecture; these are well-known techniques in the field and will not be elaborated upon here.

[0078] The data alignment process unifies data from different sources into samples based on wafer batches or individual wafers. The system parses metadata such as batch numbers, wafer numbers, and timestamps from each data table to associate all FDC sensor parameters, Metrology measurements, and final CP yield labels belonging to the same batch or wafer. This process forms the initial process dataset. Each of the samples Both contain high-dimensional input feature vectors and target yield value .

[0079] This step performs directed graph topology construction of the process flow diagram, providing physical temporal constraints for subsequent feature generation. The process flow diagram is a directed acyclic graph (DAG), denoted as... The construction process of this map is as follows:

[0080] The system analyzes the wafer transfer history data recorded in the Manufacturing Execution System (MES) to identify all unique process steps. Each unique process step, such as photolithography, etching, or deposition, is defined as a node in the map. For each node Allocate logical timestamps This logical timestamp represents the sequential order of this process step in the standard process flow and is a discrete integer value. If two steps... and If the sequence relationship is satisfied in the process, then its logical timestamp must also satisfy the condition. The system establishes directed edges between nodes representing adjacent process steps based on the physical flow path of the wafer. The existence of directed edges indicates that the wafer has completed the steps. Then, it will proceed to step [number]. Process it.

[0081] The system establishes a mapping relationship between input features and map nodes, for any sensor feature in the process dataset. The system determines the process step to which a product belongs based on its metadata (such as machine ID and recipe ID) and establishes a mapping function. This function indexes the features. Rather than in the process flow diagram The corresponding node Connect them.

[0082] The process flow diagram constructed in the above manner This places unstructured process data into a topology with physical timing logic, providing a basic data structure and judgment basis for timing logic verification in the subsequent step S5.

[0083] In step S2, the computational rule part of the agent is constructed, which determines the mathematical form of the features. An improved Genetic Expression Programming (GEP) strategy is adopted to define candidate features as linear symbol strings consisting of a head and a tail.

[0084] The system has a pre-defined function set. and terminal set function set Includes mathematical operators for feature construction, including but not limited to addition, subtraction, multiplication, division, logarithms, exponentials, trigonometric functions, and custom statistical functions. Terminal set The data consists of all or part of the sensor parameter indexes in the process dataset constructed in step S1. Each terminal symbol represents a physical parameter in a specific process, such as "RF power of etching chamber A" or "average temperature of deposition step".

[0085] To ensure that randomly generated symbol strings can always be parsed into valid mathematical formulas, the agent's computational rules are encoded using a fixed-length bipartite structure. The head primarily contains information from the function set. and terminal set The symbols are used to determine the main structure of the formula; the tail contains only information from the terminal set. The symbol is used to provide necessary parameter supplementation for function nodes during formula construction. Header length The tail length is preset by the user according to the required feature complexity. The following formula is used to determine the syntax closure of the encoding:

[0086] ;

[0087] in, The number of symbols at the end, The number of symbols in the header. Representation function set The maximum number of parameters required by all functions in the expression tree. This length constraint ensures that, regardless of the random combination of the head, the terminal symbol provided by the tail is always sufficient to fill the empty leaf nodes at the bottom of the expression tree, thus avoiding the generation of invalid features.

[0088] To address the data distribution differences caused by parallel operations across multiple machines in semiconductor manufacturing, while defining the computation rules, a device applicability rule is introduced into the agent structure. This rule is specifically represented as a binary vector bound to a specific process step, indicating the validity or activation state of the feature on different physical machines. For any machine referencing a specific process step… The intelligent agent based on the sensor parameters, the system according to the process steps Number of parallel machines included The generation dimension is Applicable vector of equipment :

[0089] ;

[0090] in, Indicates the applicable vector for the device. This represents the total number of physical machines corresponding to this process step, and its components. This indicates that the feature is in the first... The activation status of the machine. When When, it indicates that the calculation logic for this feature applies to the first... Data from machine number 1; when When, it indicates that the feature is in the first... The etching machine is in a silent or inactive state. This mechanism allows the algorithm to automatically learn the unique patterns of a specific machine; for example, a certain feature may only show a strong correlation with yield on a specific etching machine, while being irrelevant on other similar machines. By internalizing the differences in physical equipment as part of the agent, this directly supports the ability to pinpoint the root cause of problems with specific machines in subsequent steps.

[0091] After defining the above coding structure, the system performs population initialization and grouping operations. Based on the process flow diagram constructed in step S1, structured region division is performed. The system identifies key nodes or sub-regions in the process flow diagram and establishes corresponding process groups (i.e., evolutionary niches). For each process group, the system randomly generates a certain number of initial agents. During the generation process, the selection range of terminal symbols for the initial agents is restricted, ensuring that they primarily reference sensor parameters within the physical region corresponding to that process group.

[0092] Specifically, if the process flow diagram defines a photolithography region, an etching region, and a thin film region, the system initializes the photolithography feature group, the etching feature group, and the thin film feature group respectively. This physical topology-based grouping strategy ensures that the initial feature population covers all stages of the manufacturing process, preventing the algorithm from prematurely converging to a local optimum of a specific process.

[0093] In step S3, the system performs a feature structure decoding process, converting the linear encoded string generated in step S2 into executable mathematical logic. For any agent, the system reads the gene encoding from its head and tail, and maps it to a mathematical expression tree according to the breadth-first search inversion rule or a preset syntax tree construction rule. In this expression tree, leaf nodes correspond to sensor parameter inputs in the process dataset, and non-leaf nodes correspond to mathematical operators in the function set. Through this mapping, each agent is instantiated as a specific mathematical function. This function can receive raw sensor data from a wafer sample and output a calculated value.

[0094] After obtaining the mathematical expression tree, the system does not directly use its output as the final feature value. Instead, it needs to perform weighted processing in conjunction with the equipment applicability rules carried by the agent. For each sample in the process dataset... (Representing a wafer or batch), the system identifies the physical machine number actually used for this sample in the process step associated with the current feature. Record the sample. The corresponding machine number index is The system reads the device-applicable vector of the intelligent agent. Extract the component values ​​at the corresponding positions. .

[0095] The final feature output value is determined by the calculation result of the mathematical expression tree and the device's applicable status. The system performs this for each sample. Using the decoded mathematical function Calculate the basic feature values ​​and correlate them with the extracted machine activation states. Multiplying these components yields the final feature output after correction for the physical environment. The calculation process is shown in the following formula:

[0096] ;

[0097] in, Indicates that the agent is in the first... The final feature output value for each sample; For the first Input sensor feature vectors for each sample; It is a mathematical mapping function generated by decoding the agent's gene string; For the sample The index of the machines used in this process; For applicable vectors The binary element (0 or 1) corresponding to the machine index is used in this formula. If the applicable rules for the device corresponding to the agent mark a machine as "silent" (i.e., its corresponding component is 0), then regardless of fluctuations in the sensor data of that machine, its corresponding output value will be forcibly set to zero or an invalid value. This mechanism ensures that the algorithm can distinguish and retain fault mode features that are only valid in a specific subset of machines, avoiding the drowning out of weak signals caused by global averaging.

[0098] After completing the feature output calculation for all samples, the system generates the feature output vector for the agent. ,in This represents the total number of samples. The system uses mutual information as an evaluation metric to quantify the importance score of this feature. Mutual information can capture the feature vector. With yield label vector Arbitrary statistical dependencies, including nonlinear relationships, between them.

[0099] To calculate mutual information, the system first processes the continuous feature output vectors. and yield label vector Probability distribution estimation is then performed. Histogram methods or kernel density estimation are typically used to discretize or approximate the data as a probability distribution. and and joint probability distribution Importance score of the intelligent agent Calculate according to the following formula

[0100] ;

[0101] in, This represents the mutual information value between the feature output and the yield label; and These represent the value spaces of the feature output variable and the yield variable, respectively. Let be the joint probability density function; and These are the marginal probability density functions. The larger the calculated mutual information value, the more information about yield the feature contains, and the stronger its ability to explain yield fluctuations. Therefore, the probability of the agent being retained and proliferating in subsequent evolutionary steps is also higher. For those skilled in the art, in practical engineering implementations, to improve computational efficiency, an entropy estimator based on K-Nearest Neighbors (KNN) can be used to approximate the above mutual information. This is a conventional technique in the field and will not be elaborated upon here.

[0102] See attached document Figure 4 In step S4, the system performs an optimization screening operation for the feature population. This operation includes an internal competition mechanism based on data similarity and an external feedback mechanism based on physical machine status. For agents within each process group, the system first sorts them in descending order according to the mutual information importance score calculated in step S3, retains the agents with the highest scores as the core population, and directly eliminates individuals with scores below a preset benchmark value.

[0103] In the retained core population, to prevent information redundancy caused by feature homogenization, the system further performs a deduplication operation based on vector space similarity. This operation is used to identify and remove features that, although mathematically different, exhibit highly consistent response behaviors to process data. The system calculates the similarity between any two agents within the same process group. and Feature output vector and The cosine similarity between the pairs of pairs. The formula for calculating the cosine similarity is as follows:

[0104] ;

[0105] in, Represents intelligent agents With intelligent agents The similarity coefficient between them ranges from 1 to 10. ; and Representing intelligent agents respectively and In the Feature output values ​​on each sample; The system sets a similarity threshold for the total number of samples. (For example, 0.95). If If the two agents are found to have highly redundant features, the system then compares their importance scores, retains the agent with the higher score, and forcibly removes the agent with the lower score from the population, thereby freeing up niche space to accommodate subsequently generated differentiated features.

[0106] After completing the internal screening, the system introduces an external physical feedback mechanism to dynamically adjust the evolution strategy. The system reads the machine process capability index (Cpk) recorded in the Manufacturing Execution System (MES) or Statistical Process Control (SPC) system via an interface. Cpk is an indicator reflecting the ability of a manufacturing process to meet technical specifications under controlled conditions, directly characterizing the physical stability of that process region. For each process group... The system calculates the average Cpk value of the physical machines covered by this group, denoted as... .

[0107] The system utilizes this physical stability index This dynamically adjusts the parameter variation probability of the process group in the next stage. The basic logic is: for regions with low Cpk values ​​(large process fluctuations), the algorithm should increase the search radius and randomness to capture potential complex failure modes; for regions with high Cpk values ​​(stable process), the algorithm should reduce random perturbations and focus on refined convergence. Based on this logic, the... Parameter variation probability of each process group Dynamic calculations are performed based on the following formula:

[0108] ;

[0109] in, For the first The dynamic parameter variation probability of each process group is used to control the frequency of subsequent gene mutation operations; The basic mutation probability constant preset for the system; This is the gain coefficient, used to control the adjustment range; This is a sensitivity coefficient used to control the rate at which the mutation probability decays with changes in the Cpk value; Represented by natural constant An exponential function with base 0.

[0110] See attached document Figure 3 In step S5, the system performs genetic operations based on the winning agent population output in step S4 to explore new solutions in the feature space. The system determines the parent individuals participating in reproduction using roulette wheel selection or tournament selection based on the importance scores of agents within each process group. The specific implementation logic of the above selection algorithm can be implemented by those skilled in the art with reference to classical evolutionary computation theory; it is a well-known technique in the field and will not be elaborated upon here.

[0111] After determining the parents, the system performs gene recombination. The two selected parent agents exchange portions of their gene coding strings. Due to the use of a head-and-tail separated coding structure, the recombination operation is strictly limited to the head region, or a homologous recombination strategy is used to ensure that the exchanged offspring gene string still conforms to the definition in step S2. Due to the length constraint, the offspring agent not only inherits the computational rule genes of the parent, but also inherits the device-applicable vector of the parent through bitwise logical operations (such as random swapping or logical OR), thereby retaining the excellent computational structure of the parent while continuing its adaptive memory for specific machines.

[0112] The system performs gene mutation operations on the generated offspring, and the dynamic parameter mutation probability is calculated in step S4. Play a key control role. For those in the [position / area]... The system uses probabilistic probabilistic child agents grouped by process. The mutation randomly alters a character in the gene string. If the mutation occurs at the head, the character may change from a function character to a terminal character, and vice versa; if the mutation occurs at the tail, the character only changes within the terminal set. This physically-feedback-controlled mutation mechanism allows the algorithm to automatically increase the diversity of feature search in regions with drastic process fluctuations (low Cpk), while maintaining the convergence of the search in regions with stable process conditions (high Cpk).

[0113] After generating candidate offspring agents, a temporal logic verification step is introduced, using the process flow chart (PFG) constructed in step S1 to perform a physical validity review on the newly generated feature structures. This is to prevent the algorithm from generating invalid features that are mathematically valid but physically temporally reversed or have no causal relationship (e.g., attempting to predict the parameters of a previous process using the parameters of a subsequent process, or associating two processes that are completely isolated in physical topology).

[0114] Specifically, the system parses each newly generated child agent, identifying all referenced terminal symbols (sensor parameters) in its mathematical expression tree. Suppose an agent references a set... In Data for each of the different process steps, where each Corresponding process flow diagram One of the nodes. The system constructs a graph-based reachability matrix. Matrix elements The definition is as follows:

[0115] ;

[0116] Based on this matrix, the system performs a time-series causality check. For any function node in the expression tree that performs a binary operation (such as subtraction, division, or correlation calculation), if its two child nodes involve process steps... and The system checks if it exists. or or If none of the above conditions are met, it means that the two process steps are topologically isolated in terms of physical flow, and there is no direct material or information flow. Forcing a correlation would be a pseudo-correlation.

[0117] To ensure the causal validity of features for yield prediction, the system also needs to verify the temporal constraints between the input features and the target yield measurement points. Let the node corresponding to the yield measurement step in the graph be... Temporal validity criteria for system-defined features :

[0118] ;

[0119] in, It is a Boolean value. The set of all process steps referenced by the intelligent agent. Indicates from the first The formula indicates that the yield measurement step is reachable only if all sensor parameters referenced by the agent originate from upstream processes preceding the yield measurement step (i.e., there is a path to the yield measurement step on the graph). Only when the path is specified is the feature considered "physically legitimate".

[0120] If a candidate offspring agent fails any of the above-mentioned temporal logic checks, the system will directly remove the individual and re-trigger the mutation operation or re-select from the parent population until a valid offspring that meets the physical constraints is generated.

[0121] In step S6, the system determines whether the evolution process meets a preset termination condition. This termination condition is typically set as follows: the number of evolutionary generations has reached a preset maximum number of iterations. Or, the importance score of the best agent in the population in a continuous The growth rate within a generation is less than the preset convergence threshold. If any of the above conditions are met, the system stops the iterative cycle of steps S3 to S5 and enters the result analysis and modeling stage. At this time, based on the mutual information importance score calculated in step S3, the system selects the top-ranked processes from each process group of the final generation. Elite intelligent agents. These elite agents represent the combined features that the algorithm extracts from multi-source heterogeneous data and that have the most significant impact on chip yield.

[0122] The system then performs full-lineage tracing and formula explicitation, converting the genetic codes of these elite agents into physical formulas understandable to engineers. For each selected elite agent, the system reads the encoded strings from its head and tail, reconstructs them into a mathematical expression tree according to the decoding rules of K-expressions, and uses an inorder traversal algorithm to convert the expression tree into a standard infix mathematical expression. During this process, the system performs algebraic simplification of the expressions, merges constant terms, and eliminates redundant operations (e.g., ...). Simplify to , (Simplified to 1). The system replaces the terminal index referenced in the expression with the actual process parameter name (e.g., replacing "Sensor_045" with "etched chamber_RF reflection power"), thereby generating an explicit formula with physical semantics.

[0123] It is important to note that for agents that include applicable rules for the equipment, their explicit formulas will contain conditional terms regarding the machine's state. For example, a feature might be parsed as: "If machine ID=A, then feature value = (temperature - 100)". 2 "If machine ID=B, then the characteristic value=0." This explicit expression directly reveals to engineers the specific physical mechanisms and equipment dependencies that cause yield fluctuations.

[0124] The system utilizes these elite agents to construct a feature matrix for final prediction. Let the selected... The mathematical functions corresponding to each elite intelligent agent are as follows: And the corresponding device applicable vector is The system will use the original samples from the process dataset. By sequentially inputting the above functions, a new high-dimensional feature space is calculated. For the first feature in the dataset... Each wafer sample, its row vector in the feature matrix The structure is as follows:

[0125] ;

[0126] in, The characteristic matrix represents the matrix corresponding to the first... High-dimensional feature row vectors of individual wafer samples; This represents the total number of elite intelligent agents that have been selected and retained. Indicates the first The elite intelligent agent in the first The output value on each sample is determined by the agent's mathematical rules and the applicable device state. Through this operation, the system transforms the original, complex, and low signal-to-noise ratio FDC / Metrology data into a dimensionless format. High-density feature matrix ,in This represents the total number of samples. This new matrix... Each column in the database contains highly condensed physical patterns related to yield.

[0127] The system is based on the reconstructed feature matrix With the target yield vector Train a chip yield prediction model. Due to the feature matrix... Nonlinear feature extraction and denoising have been completed using evolutionary algorithms, and the prediction model has been optimized. Algorithms such as linear regression, support vector regression (SVR), or gradient boosting trees can be used to construct the prediction model. The goal of the prediction model is to minimize the loss function between the predicted yield and the actual yield. :

[0128] ;

[0129] in, For the first The actual yield of each sample; This represents the total number of samples in the process dataset used to train the model; For the model to the first Predicted yield per sample; These are the model weight parameters; The loss function (e.g., mean squared error, MSE); This is a regularization term to prevent overfitting; Represents the regularization coefficient; Indicates about the weight parameters The regularization function term. The specific training process and parameter optimization methods of the above regression algorithm can be implemented using existing machine learning frameworks by those skilled in the art, and are well-known techniques in this field, so they will not be elaborated upon here.

[0130] The trained model can then be used for online prediction. When new wafer data is generated, the system uses the stored elite agent formula to transform it into feature vectors. Then input into the prediction model The predicted yield is obtained. If the predicted yield is lower than the warning threshold, the system not only outputs an alarm signal, but also, based on the feature vector... The components of the median numerical anomaly are traced back to the corresponding explicit physical formulas, thereby directly locating the specific process parameters and equipment that cause the yield decline, enabling interpretable root cause analysis.

[0131] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A chip yield prediction method, characterized in that, Includes the following steps: S1. Obtain semiconductor manufacturing process data to construct a process dataset, and parse the process logic timestamps to construct a process flow diagram that defines physical flow timing constraints; S2. Using the sensor parameters in the process dataset, candidate features are encoded into intelligent agents containing calculation rules and equipment applicable rules, and the intelligent agents are divided into corresponding process groups according to the topological structure of the process flow diagram. S3. Analyze the mathematical operation formula of the intelligent agent in each process group, calculate the feature output value in combination with the activation state of the applicable rules of the equipment, and quantify the importance score by calculating the correlation between the feature output value and the yield label. S4. Select and retain the preferred intelligent agent group based on importance score, and dynamically adjust the parameter update probability of each process group by connecting to the machine stability index; S5. Based on the adjusted parameter update probability, perform evolutionary operations on the selected intelligent agent population to generate a progeny population, and use the process flow diagram to perform temporal logic verification on the progeny feature structure to eliminate invalid structures that violate physical timing. S6. Transform the agent that meets the termination condition into an explicit mathematical formula, and use the output of the explicit mathematical formula to construct a feature matrix to train the chip yield prediction model.

2. The chip yield prediction method according to claim 1, characterized in that, In step S1, the construction of the process flow diagram defining physical flow timing constraints further includes: The wafer transfer data in the manufacturing execution system is analyzed to identify all unique process steps. Each process step is defined as an independent node in the graph, and a mapping relationship between sensor parameter indexes and the independent nodes is established. Based on the physical path of actual wafer manufacturing, directed edges are established between independent nodes of adjacent process steps and logical timestamps are assigned to construct a directed acyclic graph structure that represents the causal dependencies between processes. The physical flow timing constraints are defined using the directed acyclic graph structure, and the reachability matrix between nodes is generated.

3. The chip yield prediction method according to claim 1, characterized in that, In step S2, encoding the candidate features into an agent that includes computation rules and device-applicable rules further includes: A linear symbol string consisting of a head and a tail is constructed to define the computational rules of the agent. The length of the tail is strictly constrained based on the length of the head and the number of parameters in the function set, ensuring that any randomly combined symbol string can be decoded into a grammatically closed mathematical expression. The physical information of parallel machines under the process steps associated with the candidate features is analyzed, and a binary vector with the same dimension as the number of machines is generated as the applicable rules for the equipment. Each component in the vector represents the active or silent state of the agent on the corresponding physical machine. The linear symbol string and the binary vector are combined and associated with the same feature index to complete the encoding of the candidate features, generating an intelligent entity that simultaneously possesses mathematical operation logic and physical device constraints.

4. The chip yield prediction method according to claim 1, characterized in that, In step S3, the step of calculating the feature output value based on the activation state of the device according to the applicable rules further includes: The linear symbol string in the intelligent agent is converted into a mathematical expression tree using a preset decoding strategy. The sensor data of the wafer sample is then input into the mathematical expression tree for calculation to generate initial basic feature values ​​that do not contain machine status information. The physical machine index actually used in the corresponding process step is identified based on the wafer sample metadata, and the corresponding activation state component is extracted from the binary vector carried by the agent based on the physical machine index. The initial basic feature values ​​are corrected by using the extracted active state components. When the component indicates a silent state, the output is forcibly set to zero to generate the final feature output value filtered by the physical environment.

5. The chip yield prediction method according to claim 1, characterized in that, In step S4, the step of dynamically adjusting the parameter update probability of each process group based on the stability index of the access machine further includes: Obtain the machine process capability index of the physical machine set covered by each process group, and calculate the average value as a machine stability index to measure the degree of physical fluctuation in the corresponding process area. Construct a negative correlation mapping model between parameter update probability and machine stability index, and calculate the dynamic variation probability value adapted to the current physical state based on the negative correlation mapping model; The dynamic mutation probability value is used to drive the adjustment of the evolution strategy. For groups with lower stability index, the mutation probability is increased to enhance exploration, while for groups with higher stability index, the mutation probability is decreased to focus on convergence.

6. The chip yield prediction method according to claim 1, characterized in that, In step S5, the step of using the process flow diagram to perform time-series logic verification on the offspring characteristic structure to eliminate invalid structures that violate physical timing further includes: The algorithm analyzes all sensor parameters referenced in the mathematical structure of the evolved offspring intelligent agent and locates the set of graph nodes corresponding to the sensor parameters in the process flow graph based on the attribution mapping relationship. Based on the directed acyclic graph structure, it is retrieved whether there is a directed path that conforms to the physical flow direction between any two nodes in the graph node set; A path-based elimination mechanism is implemented. If there is no physically reachable path between nodes in the graph, the child feature structure is determined to violate the physical flow sequence constraints and is eliminated, while only logically valid structures are retained.

7. The chip yield prediction method according to claim 1, characterized in that, In step S4, the step of selecting and retaining the preferred agent group based on importance scores is as follows: Calculate the cosine similarity between the feature output vectors generated by different agents within the same process group to quantify the degree of overlap between features at the data representation level; When the cosine similarity between two agents exceeds a preset threshold, a competition mechanism is triggered to compare their importance scores. Agents with higher importance scores are retained as preferred members of the agent group, while those with lower importance scores are removed from the group.

8. The chip yield prediction method according to claim 1, characterized in that, In step S6, the step of converting the agent that satisfies the termination condition into an explicit mathematical formula further includes: Linear symbol strings are extracted from the preferred intelligent agent group and restored to mathematical expression trees. The mathematical expression trees are then reconstructed into standard infix mathematical expressions using an inorder traversal algorithm. Perform a semantic substitution operation to replace the parameter index in the standard infix mathematical expression with the actual process parameter name, and convert the binary vector into a conditional judgment statement about the machine ID; The replaced infix mathematical expression is combined with the conditional statement to generate an explicit mathematical formula for physical mechanisms and device dependencies.

9. The chip yield prediction method according to claim 1, characterized in that, In step S6, the step of constructing a feature matrix using the output of an explicit mathematical formula to train a chip yield prediction model further includes: The original sample data in the process dataset is sequentially input into the transformed explicit mathematical formula to calculate the high-dimensional feature vector corresponding to each sample. The high-dimensional feature vectors of all samples are stacked in order to construct a high-density feature matrix, which serves as the input variable for the prediction model. A regression model is constructed using the feature matrix as input and the yield label as the target. The model weights are optimized by minimizing the loss function between the predicted and actual values ​​to generate the final chip yield prediction model.

10. A chip yield prediction system, applied to the chip yield prediction method according to any one of claims 1-9, characterized in that, include: The process data space construction module is used to acquire semiconductor manufacturing process data to construct a process dataset and parse the process logic timestamps to construct a process flow diagram that defines physical flow timing constraints. The feature structure encoding module is used to encode candidate features into intelligent agents containing calculation rules and equipment applicable rules using sensor parameters in the process dataset, and to divide the intelligent agents into corresponding process groups according to the topological structure of the process flow diagram. The feature fitness evaluation module is used to parse the mathematical formulas generated by the agents in each process group, calculate the feature output value by combining the activation state of the applicable rules of the equipment, and quantify the importance score by calculating the correlation between the feature output value and the yield label. The feature optimization and screening module is used to select and retain the preferred intelligent agent group based on importance scores, and to dynamically adjust the parameter update probability of each process group by connecting to the machine stability index. The feature iteration generation module is used to perform evolutionary operations on the preferred intelligent agent population based on the adjusted parameter update probability to generate a progeny population, and to use the process flow diagram to perform temporal logic verification on the feature structure of the progeny to eliminate invalid structures that violate physical timing. The feature parsing and prediction module is used to convert agents that meet the termination conditions into explicit mathematical formulas, and to use the output of the explicit mathematical formulas to construct a feature matrix to train the chip yield prediction model.

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