Display device

Abstract

One or more examples of the display device include: a substrate; a plurality of sub-pixels disposed on a plurality of pixel board patterns and each including circuitry; a plurality of lines disposed on the plurality of pixel board patterns and connected to the circuitry; and a plurality of bypass lines disposed on the plurality of pixel board patterns and a plurality of bypass board patterns. Some lines on some of the pixel board patterns receive signals from corresponding bypass lines on some of the bypass board patterns. Therefore, the plurality of bypass lines and the plurality of bypass board patterns can be used to transmit signals to normal sub-pixels on the pixel board patterns while suppressing signals from being applied to defective sub-pixels of some of the pixel board patterns.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0182621, filed on December 10, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, and more particularly to an extendable and stretchable display device. Background Technology

[0003] As display devices used in computer monitors, televisions, mobile phones, etc., there are organic light-emitting displays (OLEDs) that are configured to emit light independently and liquid crystal displays (LCDs) that require a separate light source.

[0004] The applications of display devices have expanded from computer monitors and televisions to personal mobile devices, and research is underway on display devices with wide display areas as well as reduced size and weight.

[0005] Furthermore, recently, display devices have been manufactured by forming display components, lines, etc., on a flexible substrate made of flexible plastic material. These display devices are manufactured to be stretchable in a specific direction and capable of various shape changes, and have therefore attracted attention as a next-generation display device.

[0006] The description of related technologies should not be construed as prior art simply because they are mentioned or associated with this section. The description of related technologies includes information describing one or more aspects of the subject matter, and the description in this section does not limit the scope of the invention. Summary of the Invention

[0007] One aspect of this disclosure is to provide a stretchable display device that can be transformed into various shapes.

[0008] Another aspect of this disclosure is to provide a stretchable display device that can minimize bright spot defects by blocking signals applied to the path traversed by defective subpixels.

[0009] Another aspect of this disclosure is to provide a stretchable display device that can minimize bright spot defects of defective subpixels by forming separate bypass signal paths that are separate from the defective subpixels.

[0010] Another aspect of this disclosure is to provide a stretchable display device that can transmit signals to the remaining normal sub-pixels by using bypass lines when some connecting lines are removed due to defective sub-pixels.

[0011] Another additional aspect of this disclosure is to provide a stretchable display device that can easily form a bypass signal path using a welding process.

[0012] The aspects of this disclosure are not limited to those described above, and other aspects not mentioned above will be readily understood by those skilled in the art from the following description.

[0013] A display device according to one or more embodiments of the present disclosure includes: a substrate; and a pattern layer disposed on the substrate and including a plurality of pixel plate patterns, a plurality of bypass plate patterns, and a plurality of first line patterns. The pattern includes: a plurality of sub-pixels disposed on the plurality of pixel plate patterns, each of the plurality of sub-pixels including a circuit and a light-emitting element configured to be operated by the circuit; a plurality of lines disposed on the plurality of pixel plate patterns and connected to the plurality of circuits; a plurality of bypass lines disposed on the plurality of pixel plate patterns and the plurality of bypass plate patterns; and a plurality of connecting lines disposed on the plurality of first line patterns, wherein the plurality of first line patterns are disposed between at least some of the pixel plate patterns in the plurality of pixel plate patterns and between the plurality of pixel plate patterns and the plurality of bypass plate patterns, wherein some of the lines located on some of the pixel plate patterns in the plurality of pixel plate patterns receive signals from corresponding lines located on one or more adjacent pixel plate patterns in the plurality of lines, and wherein some of the lines located on some of the remaining pixel plate patterns in the plurality of lines receive signals from corresponding bypass lines located on some of the bypass plate patterns in the plurality of bypass plate patterns, wherein the plurality of pixel plate patterns includes the pixel plate patterns in the plurality of pixel plate patterns and the remaining pixel plate patterns. The remaining pixel board pattern does not include some of the pixel board patterns in the plurality of pixel board patterns. Therefore, multiple bypass lines and multiple bypass board patterns can be used to transmit signals to normal sub-pixels on the pixel board pattern while suppressing signals from being applied to defective sub-pixels on some pixel board patterns.

[0014] A display device according to one or more embodiments of the present disclosure includes: a substrate; a pattern layer disposed on the substrate and including a plurality of pixel board patterns, a plurality of bypass board patterns, and a plurality of first line patterns; a plurality of sub-pixels disposed on the plurality of pixel board patterns, each of the plurality of sub-pixels including circuitry and a light-emitting element configured to be operated by the circuitry; a plurality of lines disposed on the plurality of pixel board patterns and connected to the plurality of circuitry; a plurality of bypass lines disposed on the plurality of pixel board patterns and the plurality of bypass board patterns; and a plurality of connecting lines disposed on the plurality of first line patterns. The plurality of first line patterns may be disposed between the plurality of pixel board patterns and between the plurality of pixel board patterns and the plurality of bypass board patterns. Therefore, by using a plurality of bypass lines, a bypass path capable of applying a signal to a normal sub-pixel while bypassing a defective sub-pixel can be formed.

[0015] Further details of the example embodiments are included in the specific embodiments and the accompanying drawings.

[0016] According to this disclosure, a stretchable display device that can be transformed into various shapes can be provided.

[0017] According to this disclosure, abnormal operation of defective sub-pixels can be suppressed by suppressing the transmission of a suppression signal to the defective sub-pixel.

[0018] According to this disclosure, bright spot defects in defective subpixels can be suppressed by suppressing the transmission of a suppression signal to the defective subpixel.

[0019] According to this disclosure, a separate bypass signal path can be formed, separate from the defective sub-pixels, thereby easily applying signals only to normal sub-pixels other than the defective sub-pixels.

[0020] According to this disclosure, a bypass signal path can be easily formed by a welding process.

[0021] The effects of this disclosure are not limited to those provided above, and many more effects are included in this disclosure. Attached Figure Description

[0022] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic top plan view of a display device according to an embodiment of the present disclosure; Figure 2 This is an enlarged top view of the display area of ​​a display device according to an embodiment of the present disclosure; Figure 3 It is along Figure 2 Cross-sectional views taken from lines A-A' and B-B' in the diagram; Figure 4 This is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure; Figure 5A This is a schematic enlarged top view of the pixel panel pattern of a display device according to an embodiment of the present disclosure; Figure 5B This is an enlarged top view of the display area of ​​a display device according to an embodiment of the present disclosure; Figure 6A This is a schematic enlarged top view of the pixel panel pattern of a display device according to an embodiment of the present disclosure; Figure 6B This is an enlarged top view of the display area of ​​a display device according to an embodiment of the present disclosure; Figure 7 This is an enlarged top plan view of the bypass board pattern of a display device according to an embodiment of the present disclosure; Figures 8A to 9B It is along Figure 7 A cross-sectional view taken by line A-A' in the diagram; Figure 10 yes Figure 2 A schematic cross-sectional view of the third connecting line in regions (1) to (4) of the diagram; Figure 11 This is an enlarged top plan view of the display area of ​​a display device according to an embodiment of the present disclosure; and Figures 12A to 12C This is an enlarged top plan view of a plurality of bypass plate patterns of a display device according to an embodiment of the present disclosure. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0024] In the following description, detailed descriptions of well-known methods, functions, structures, or configurations may have been omitted for brevity where such descriptions might unnecessarily obscure aspects of this disclosure. Furthermore, repeated descriptions may be omitted for the sake of brevity. The described processing steps and / or the progression of operations are non-limiting examples.

[0025] The order of steps and / or operations is not limited to the order set forth herein, and may be changed to occur in a different order than that described herein, except for steps and / or operations that must occur in a specific order. In one or more examples, two consecutive operations may be performed substantially simultaneously, or the two operations may be performed in reverse order or in a different order depending on the functions or operations involved.

[0026] Unless otherwise stated, the same reference numerals may always refer to the same elements, even if they are shown in different figures. Unless otherwise stated, the same reference numerals may be used throughout the specification and figures to refer to the same or substantially the same elements. In one or more aspects, unless otherwise stated, the same elements (or elements with the same name) in different figures may have the same or substantially the same function and characteristics. The names of the corresponding elements used in the following explanation are chosen for convenience only and may therefore differ from those used in actual products.

[0027] The advantages and features of this disclosure and its implementation methods are illustrated by referring to the embodiments described in the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are examples and are provided to make this disclosure thorough and complete, to aid those skilled in the art in understanding the inventive concept, and not to limit the scope of protection of this disclosure.

[0028] The shapes, dimensions (e.g., size, length, width, height, thickness, position, radius, diameter, and area), proportions, ratios, angles, quantities, number of elements, etc., disclosed herein (including those shown in the accompanying drawings) are merely examples, and therefore this disclosure is not limited to the details shown. However, it should be noted that the relative dimensions of the components shown in the accompanying drawings are part of this disclosure.

[0029] When terms such as “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” “composed of,” etc., are used relative to one or more elements (e.g., layers, films, components, electrodes, structures, transistors, segments, members, parts, regions, areas, portions, steps, operations, etc.), one or more additional elements may be added unless terms such as “only” are used. The terminology used in this disclosure is for describing particular exemplary embodiments only and is not intended to limit the scope of this disclosure. Singular terms may include plural forms unless the context clearly indicates otherwise. In one or more examples, unless otherwise stated, an element may be one or more elements; and an element may include multiple elements. In one or more examples, unless otherwise stated, a line may include multiple lines; a signal may include multiple signals; a bypass line may include multiple bypass lines; a connecting line may include multiple connecting lines; and a pattern may include multiple patterns. The word “exemplary” is used to indicate that something is used as an example or illustration. An embodiment is an exemplary embodiment. An aspect is an exemplary aspect. In one or more implementations, “embodiment,” “example,” “aspect,” etc., should not be construed as preferred or advantageous over other implementations. Unless otherwise stated, embodiments, examples, exemplary embodiments, aspects, etc., may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, etc. Furthermore, the term "may" encompasses all meanings of the term "able to".

[0030] In one or more respects, unless otherwise expressly stated, components, features, or corresponding information (e.g., grade, range, size, dimensions, etc.) are interpreted as including a range of errors or tolerances, even if no explicit description of such ranges is provided. Ranges of errors or tolerances may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). When interpreting numerical values, unless otherwise expressly stated, the value is interpreted as including the range of errors.

[0031] When any of the terms used to indicate location or positioning, such as “on top of,” “above,” “top,” “above,” “under,” “above,” “upper,” “on the upper part,” “on the upper side,” “below,” “lower,” “on the lower part,” “below the lower side,” “near,” “close to,” “adjacent to,” “next to,” “next to,” “on one side of,” or “on one side of,” are used to describe the positional relationship between two elements (e.g., layers, films, components, electrodes, structures, transistors, segments, components, parts, regions, areas, sections, etc.), one or more other elements may be located between the two elements, unless more restrictive terms such as “immediately,” “directly,” or “closely” are used. For example, when any of the foregoing terms are used to describe one element and another element, the description should be interpreted to include cases where the elements are in direct contact with each other and cases where one or more additional elements are positioned or inserted between them. Furthermore, spatial relative terms (such as the foregoing terms, and other terms such as “front,” “back,” “back,” “left,” “right,” “top,” “bottom,” “upper,” “lower,” “downward,” “upward,” “above,” “below,” “column,” “row,” “vertical,” “horizontal,” “diagonal,” etc.) refer to any frame of reference. For example, these terms can be used to illustrate the relative relationships between elements, including any correlations as shown in the figures. However, embodiments of this disclosure are not limited to or restricted by this. Spatial relative terms should be understood to include, in addition to the orientations depicted in the figures or described herein, different orientations of elements in use or operation. For example, in the case where a lower element or an element located below another element is flipped, that element can be referred to as an upper element or an element located above another element. Thus, for example, the terms “below” or “under” can, in meaning, encompass the terms “above” or “above.” Example terms such as “below” can include all directions, including directions among “below,” “above,” and diagonal directions. Similarly, example terms such as “above,” “up,” etc., can include all directions, including directions among “above,” “up,” “below,” and diagonal directions.

[0032] When describing temporal relationships, when the temporal order is described as such as "after", "after", "following", "next", "before", "before", "before", etc., it may include discontinuous or non-sequential situations, and therefore one or more other events may occur between them, unless more restrictive terms such as "immediately after", "immediately", or "directly" are used.

[0033] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements (e.g., layer, film, component, electrode, structure, transistor, segment, member, part, region, area, section, step, operation, etc.), these elements should not be limited by these terms, for example, not by any particular order, priority, or number of elements. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may refer to a second element, and similarly, a second element may refer to a first element. Furthermore, without departing from the scope of this disclosure, first elements, second elements, etc., may be named arbitrarily as is convenient for those skilled in the art. For clarity, the function or structure of these elements (e.g., first element, second element, etc.) is not limited by the ordinal number or name preceding the element. Furthermore, a first element may include one or more first elements. Similarly, a second element, etc., may include one or more second elements, etc.

[0034] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify one or more corresponding elements from one or more other elements, and are not used to define the nature, basis, order, or number of elements.

[0035] The expression "joining" of an element (e.g., layer, film, component, electrode, structure, transistor, segment, member, part, region, area, section, etc.) with another element can be understood as meaning that the element can be joined directly or indirectly to the other element. The term "joining" or similar expressions can refer to terms such as "covering," "surrounding," "contacting," "overlapping," "crossing," "intersecting," "connecting," "coupling," "attaching," "adhering," "combining," "linking," "providing," "setting," "interacting," etc. Unless otherwise stated, joining can encompass the placement or insertion of one or more intervening elements between an element and another element. Furthermore, unless otherwise stated, the element can be joined at least partially or wholly (or completely) to the other element. Additionally, the element can be included in at least one of two or more elements joined to each other. Similarly, the other element can be included in at least one of two or more elements joined to each other. When an element joins with another element, at least a portion of the element can be joined with at least a portion of the other element. The term “with another element” or similar expression can be understood as “another element”, or, depending on the context, the term “with another element” or similar expression can be understood as “with another element, to another element, in another element, or on another element.” Similarly, the term “each other” can be understood as “together with each other”, or, depending on the context, the term “each other” can be understood as “each other, mutually, or together with each other.”

[0036] The phrase “through” can be understood as, for example, at least partially through or completely through.

[0037] Terms such as “line” or “direction” should not be interpreted solely based on the geometric relationship in which the corresponding lines or directions are parallel, perpendicular, diagonal, or inclined relative to each other, and the term may also be used to refer to lines or directions with a wider directionality within the range in which the components of this disclosure can be functionally operated.

[0038] The term “at least one” should be understood to include any and all combinations of one or more of the related listed items. For example, each of the phrases “at least one of the first, second, or third items” and “at least one of the first, second, and third items” can mean: (i) a combination of items provided by two or more items of the first, second, and third items, or (ii) only one item of the first, second, or third items. Furthermore, “at least one of a plurality of elements” can mean: (i) one element of a plurality of elements, (ii) some elements of a plurality of elements, or (iii) all elements of a plurality of elements. Additionally, “at least some,” “some,” “at least some parts,” “at least some sections,” “at least a portion,” “at least one or more parts,” “at least a portion,” “at least one or more sections,” “at least some elements,” “one or more,” etc., of a plurality of elements can mean: (i) one element of a plurality of elements, (ii) a portion (or part) of a plurality of elements, (iii) one or more portions (or sections) of a plurality of elements, (iv) one or more elements of a plurality of elements, (v) several elements of a plurality of elements, or (vi) all elements of a plurality of elements, unless the context clearly indicates otherwise. In addition, “at least some,” “some,” “at least some parts,” “at least some sections,” “at least a portion,” “at least one or more parts,” “at least a portion,” “at least one or more sections,” etc., of an element can mean: (i) a part (or section) of an element, (ii) one or more parts (or sections) of an element, (iii) an element, or (iv) all parts of an element, unless the context clearly indicates otherwise.

[0039] The expressions "first element," "second element," and " / or" "third element" should be understood as any one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. A similar interpretation applies to the use of "and / or" in conjunction with two or more elements. For example, A, B, and / or C can refer to: only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); some combination of A, B, and C (e.g., A and B; A and C; or B and C); or all of A, B, and C. Furthermore, the expression "A / B" can be understood as A and / or B. For example, the expression "A / B" can refer to: only A; only B; A or B; or A and B.

[0040] In one or more aspects, unless otherwise stated, the terms "between" and "among" may be used interchangeably for convenience. For example, the expression "between multiple elements" can be understood as "among multiple elements". In another example, the expression "between multiple elements" can be understood as "among multiple elements". In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two. Furthermore, when an element is referred to as being "among" at least two elements, the element may be the only element among at least two elements, or there may be one or more intervening elements.

[0041] In one or more aspects, unless otherwise stated, the phrases “each other” and “mutual” may be used interchangeably for convenience. For example, the expression “different from each other” can be understood as “different from each other”. In another example, the expression “different from each other” can be understood as “different from each other”. In one or more examples, the number of elements involved in the foregoing expression may be two. In one or more examples, the number of elements involved in the foregoing expression may be more than two.

[0042] In one or more respects, unless otherwise stated, the phrases “one or more of” and “among one or more” may be used interchangeably for convenience.

[0043] The term "or" indicates "inclusive or" rather than "exclusive or". That is, unless otherwise stated or clearly evident from the context, the statement "x uses a or b" represents any of the naturally inclusive permutations. For example, "a or b" can mean "a", "b", or "a and b". Similarly, "a, b, or c" can mean "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c".

[0044] The phrases “substantially identical” or “nearly identical” can indicate a degree to which they are considered equivalent to each other, taking into account minor differences caused by errors in the manufacturing process.

[0045] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole; features of the various embodiments of this disclosure may be technically related to each other; and features of the various embodiments of this disclosure may operate, link, or co-drive in various different ways. Embodiments of this disclosure may be implemented or performed independently of each other, or may be implemented or performed together in a mutually dependent or related relationship. In one or more aspects, components of each apparatus and device according to the various embodiments of this disclosure may be operatively coupled and configured.

[0046] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0047] The terms used herein are chosen as general terms in the relevant technical field; however, other terms may exist depending on technological development and / or changes, conventions, preferences of those skilled in the art, etc. Therefore, the terms used herein should not be construed as limiting the technical concept, but rather as examples of terms used to describe exemplary embodiments.

[0048] Furthermore, in certain circumstances, the terminology may be arbitrarily chosen by the applicant, and in such cases, its detailed meaning is described herein. Therefore, the terminology used herein should be understood not only based on its name but also on its meaning and content.

[0049] In the following description, various exemplary embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. Reference numerals for elements in each drawing may denote the same or similar elements in other drawings, and unless otherwise stated, the same reference numerals may refer to the same or similar elements. The same or similar elements may be represented by the same reference numerals even if they are shown in different drawings. For brevity, repeated descriptions of the same or similar elements may be omitted, and unless otherwise stated, the descriptions provided for elements in one or more figures may also apply to elements in other figures using the same or similar reference numerals. Furthermore, for ease of description, the scale, dimensions, size, and thickness of each element shown in the drawings may differ from the actual scale, dimensions, size, and thickness, and therefore, embodiments of the present disclosure are not limited to the scale, dimensions, size, and thickness shown in the drawings.

[0050] When describing signal flow, for example, when a signal is provided (e.g., transmitted or sent) from node A to node B, this can include cases where the signal is provided from node A to node B via one or more nodes, unless phrases such as "provided immediately" or "provided directly" are used.

[0051] Figure 1 This is a top plan view of a display device according to an embodiment of the present disclosure. Figure 2 This is an enlarged top view of the display area of ​​a display device according to an embodiment of the present disclosure. Figure 3 It is along Figure 2 The cross-sectional view taken by lines A-A' and B-B' in the diagram. Figure 4 This is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0052] First, the display device 100 according to the embodiments of this disclosure is a display device 100 that can display images even when bent or stretched. The display device 100 may also be referred to as a stretchable display device, a flexible display device, an extendable display device, etc. Compared to general display devices in the related art, the display device 100 can not only have high flexibility but also stretchability. Therefore, the user can bend or stretch the display device 100, and the shape of the display device 100 can be freely changed according to the user's manipulation. For example, when the user holds and pulls one end of the display device 100, the display device 100 can be stretched in the direction the user pulls. Alternatively, when the user places the display device 100 on a non-flat outer surface, the display device 100 can be configured to bend along the shape of the outer surface of the wall surface. Furthermore, when the force applied by the user is removed, the display device 100 can return to its original shape.

[0053] refer to Figures 1 to 3The lower substrate 111 can support several components of the display device 100, and the upper substrate 112 can cover several components of the display device 100.

[0054] Both the lower substrate 111 and the upper substrate 112 can be flexible substrates made of a bendable or stretchable insulating material. For example, both the lower substrate 111 and the upper substrate 112 can be made of silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE), and thus possess flexibility. Furthermore, the lower substrate 111 and the upper substrate 112 can be made of the same material. However, this disclosure is not limited thereto. The lower substrate 111 and the upper substrate 112 can undergo various modifications.

[0055] The display device 100 or the lower substrate 111 may have, define or indicate a display area AA for displaying an image and a non-display area NA other than the display area AA.

[0056] The display area AA is the area of ​​the display device 100 where the image is displayed. Multiple pixels PX, each including display elements and circuit elements, can be disposed in the display area AA, and a gate driver GD and a power supply PS configured to operate the multiple pixels PX disposed in the display area AA can be disposed in the non-display area NA.

[0057] A pattern layer 120 is disposed on a lower substrate 111 and includes a plurality of first plate patterns 121 and a plurality of first line patterns 122 disposed in a display area AA, and a plurality of second plate patterns 123 and a plurality of second line patterns 124 disposed in a non-display area NA. For example, the plurality of first plate patterns 121 and the plurality of second plate patterns 123 may be disposed in an island-like arrangement spaced apart from each other. The plurality of first line patterns 122 may connect adjacent first plate patterns 121, and the plurality of second line patterns 124 may connect adjacent first plate patterns 121 and second plate patterns 123 or connect adjacent second plate patterns 123.

[0058] Multiple pixels PX can be formed on multiple first board patterns 121, and gate driver GD and power supply PS can be formed on multiple second board patterns 123.

[0059] at the same time, Figure 1 The diagram shows multiple first plate patterns 121 and multiple second plate patterns 123, all having quadrilateral shapes. However, this disclosure is not limited thereto.

[0060] The plurality of first line patterns 122 and the plurality of second line patterns 124 may all have curved shapes, such as sinusoidal shapes. However, this disclosure is not limited thereto. The plurality of first line patterns 122 and the plurality of second line patterns 124 may all have various shapes, such as shapes extending in a zigzag manner, or shapes in which a plurality of rhomboid-shaped substrates are connected and extend at their vertices.

[0061] The plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 are all rigid patterns. For example, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be more rigid than the lower substrate 111 and the upper substrate 112. For example, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can all be made of a plastic material having lower flexibility than the lower substrate 111 and the upper substrate 112. Therefore, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can all have a higher elastic modulus and hardness than the lower substrate 111.

[0062] A gate driver GD can be mounted on multiple second board patterns 123. The gate driver GD is a component configured to provide gate voltages to multiple pixels PX disposed in a display area AA. For example, the gate driver GD includes multiple stages formed on each of the multiple second board patterns 123. Each stage of the gate driver GD can be electrically connected to each other via multiple gate connection lines. Therefore, a gate voltage output from any stage can be transferred to another stage. Furthermore, each stage can sequentially provide gate voltages to the multiple pixels PX respectively connected to that stage.

[0063] A power supply PS can be mounted on multiple second board patterns 123. The power supply PS can be electrically connected to the gate driver GD and multiple pixels PX. For example, the power supply PS can provide gate drive voltage and gate clock voltage to the gate driver GD. Furthermore, the power supply PS can be connected to multiple pixels PX and provide pixel drive voltage to the multiple pixels PX.

[0064] A printed circuit board (PCB) includes controllers (such as IC chips and circuit components), memory, processors, etc., and is configured to transmit signals and voltages from the controllers to display elements for operating the display elements. A PCB may include stretchable and non-stretchable areas to ensure stretchability. For example, IC chips, circuit components, memory, processors, etc., can be mounted in non-stretchable areas. Wires electrically connected to IC chips, circuit components, memory, and processors can be located in stretchable areas.

[0065] A data driver DD is a component configured to provide a data voltage Vdata to multiple pixels PX located in a display area AA. The data driver DD can be configured as an IC chip and is therefore referred to as a data integrated circuit (D-IC).

[0066] refer to Figure 2 and Figure 3 Multiple first board patterns 121 are disposed on the lower substrate 111 in the display area AA. The multiple first board patterns 121 include multiple pixel board patterns 121A and multiple bypass board patterns 121B.

[0067] The multiple pixel board pattern 121A is a substrate on which pixels PX, including multiple sub-pixels SPX, are formed. The multiple pixel board pattern 121A can be arranged in a matrix shape, and simultaneously arranged in multiple rows and multiple columns. The multiple pixel board pattern 121A can be arranged in a first direction X and a second direction Y.

[0068] The plurality of sub-pixels SPX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, any one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be a red sub-pixel SPX, another sub-pixel may be a green sub-pixel SPX, and the remaining sub-pixels may be blue sub-pixels SPX. However, this disclosure is not limited thereto.

[0069] Each of the multiple sub-pixels SPX may include a light-emitting element 170 and a driving transistor 160 configured to operate the light-emitting element 170. The light-emitting element 170 may be any of a light-emitting diode (LED) or a micro-LED. However, an organic light-emitting diode (OLED) may be used as the light-emitting element 170. However, this disclosure is not limited thereto.

[0070] Multiple bypass board patterns 121B are arranged in the area between multiple pixel board patterns 121A. The multiple bypass board patterns 121B and the multiple pixel board patterns 121A can be arranged in different rows and different columns.

[0071] Multiple bypass lines are provided on multiple bypass board patterns 121B. When a pixel board pattern 121A with a defective sub-pixel (XSPX) is detected, all first line patterns 122, first connecting lines 181, and second connecting lines 182 connected to that pixel board pattern 121A can be removed, thereby suppressing bright spot defects. For example, such patterns 122 (or portions thereof) and lines 181 and 182 (or portions thereof) can be separated, removed, or cut off from the pixel board pattern 121A using, for example, a laser beam. For example, defective sub-pixels XSPX may be caused by various types of foreign matter, transfer defects of the light-emitting element 170, defects of the light-emitting element 170, defects in the circuitry of the sub-pixel SPX, etc. In this case, signals to be transmitted to the defective sub-pixel XSPX can be blocked, thereby minimizing bright spot defects that may occur in the defective sub-pixel XSPX. That is, the path through which signals are applied to the defective sub-pixel XSPX can be removed, thereby reducing bright spot defects caused by continuous emission from the defective sub-pixel XSPX. In this case, multiple bypass lines can be used to normally apply signals to the pixel board pattern 121A, which is located in the same row and column as the pixel board pattern 121A with the defective sub-pixel XSPX. Reference will be made below. Figures 5A to 12C A more detailed description of the repair method using multiple bypass routes.

[0072] Meanwhile, the size of the bypass board pattern 121B can be smaller than the size of the pixel board pattern 121A. Only multiple bypass lines are disposed on the bypass board pattern 121B, while multiple transistors, multiple capacitors, multiple light-emitting elements 170, etc., constituting multiple sub-pixels SPX, are disposed on the pixel board pattern 121A. Therefore, the size of the pixel board pattern 121A can be larger than the size of the bypass board pattern 121B.

[0073] A plurality of first line patterns 122 are disposed between a plurality of first plate patterns 121. The plurality of first line patterns 122 may be disposed between a plurality of pixel plate patterns 121A and between a plurality of pixel plate patterns 121A and a plurality of bypass plate patterns 121B. For example, some of the plurality of first line patterns 122 may be disposed between the plurality of pixel plate patterns 121A and extend in a first direction X and a second direction Y. The remaining first line patterns 122 may be disposed between the plurality of pixel plate patterns 121A and the plurality of bypass plate patterns 121B and extend in a direction different from the first direction X and the second direction Y.

[0074] Multiple connecting lines 180 are disposed on multiple first line patterns 122. The multiple connecting lines 180 include multiple first connecting lines 181, multiple second connecting lines 182, and multiple third connecting lines 183.

[0075] Multiple first connecting lines 181 can be lines disposed between multiple pixel board patterns 121A and extending in a first direction X, and multiple second connecting lines 182 can be disposed between multiple pixel board patterns 121A and extending in a second direction Y. Therefore, multiple first connecting lines 181 and multiple second connecting lines 182 can connect multiple lines on the pixel board pattern 121A. For example, multiple first connecting lines 181 extending in the first direction X can connect the reference line RL, the first data line DL1, the second data line DL2, and the third data line DL3 on the pixel board pattern 121A. For example, multiple second connecting lines 182 extending in the second direction Y can connect the low-potential power line VSSL, the scan line SL, the light emission control line EML, and the high-potential power line VDDL on the pixel board pattern 121A.

[0076] In this case, the first data line DL1, the second data line DL2, and the third data line DL3 can be data lines DL that are respectively connected to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0077] Next, multiple third connecting lines 183 can be disposed between multiple pixel board patterns 121A and multiple bypass board patterns 121B, and extend in a direction different from the first direction X and the second direction Y. For example, the multiple third connecting lines 183 can extend in a direction inclined to both the first direction and the second direction. For example, the third connecting lines 183 can extend to a corner of the bypass board pattern 121B adjacent to one of the four corners of the pixel board pattern 121A. The multiple third connecting lines 183 can connect multiple bypass lines on the pixel board pattern 121A to multiple bypass lines on the bypass board pattern 121B.

[0078] In the following text, reference will be made to Figure 3 Describe the cross-sectional structure on pixel plate pattern 121A.

[0079] A multi-buffer layer 141 is disposed on the pixel board pattern 121A, and an active buffer layer 142 is disposed on the multi-buffer layer 141. The multi-buffer layer 141 and the active buffer layer 142 can reduce the penetration of moisture or impurities from the outside into the lower substrate 111 and the pixel board pattern 121A, thereby protecting the various components of the display device 100. For example, the multi-buffer layer 141 and the active buffer layer 142 can both be configured as a single layer or multiple layers made of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). However, this disclosure is not limited thereto.

[0080] A light-blocking layer BSM is disposed between the multi-buffer layer 141 and the active buffer layer 142. The light-blocking layer BSM can block light from entering the active layer 161 of the driving transistor 160, which will be described below, from the underside of the substrate, thereby minimizing leakage current from the driving transistor 160.

[0081] The driving transistor 160 is disposed on the active buffer layer 142. The driving transistor 160 includes an active layer 161, a gate electrode 162, a source electrode 163, and a drain electrode 164.

[0082] An active layer 161 is disposed on the active buffer layer 142. The active layer 161 may be made of a semiconductor material such as oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, this disclosure is not limited thereto.

[0083] A gate insulating layer 143 is disposed on the active layer 161. The gate insulating layer 143 is an insulating layer used to insulate the active layer 161 from the gate electrode 162. The gate insulating layer 143 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0084] Gate electrode 162 is disposed on gate insulating layer 143. Gate electrode 162 may be configured as a single-layer or multi-layer structure made of conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), gold (Au), chromium (Cr), or alloys thereof). However, this disclosure is not limited thereto.

[0085] A first interlayer insulating layer 144 is disposed on the gate electrode 162, and a second interlayer insulating layer 145 is disposed on the first interlayer insulating layer 144. The first interlayer insulating layer 144 and the second interlayer insulating layer 145 are insulating layers for protecting components disposed beneath them. Both the first interlayer insulating layer 144 and the second interlayer insulating layer 145 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0086] Source electrode 163 and drain electrode 164 are disposed on the second interlayer insulating layer 145. Source electrode 163 and drain electrode 164 can be electrically connected to the active layer 161 through contact holes formed in the second interlayer insulating layer 145, the first interlayer insulating layer 144, and the gate insulating layer 143. Source electrode 163 and drain electrode 164 can both be made of conductive material. However, this disclosure is not limited thereto.

[0087] Next, an intermediate metal layer IM is formed on the first interlayer insulating layer 144. The intermediate metal layer IM and the gate electrode 162 of the driving transistor 160 can overlap each other and form a storage capacitor.

[0088] A third interlayer insulating layer 146 is disposed on the driving transistor 160, and a passivation layer 147 is disposed on the third interlayer insulating layer 146. The third interlayer insulating layer 146 and the passivation layer 147 are insulating layers used to protect components disposed beneath them. The third interlayer insulating layer 146 and the passivation layer 147 may both be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0089] A planarization layer 148 is disposed on the passivation layer 147. The planarization layer 148 can planarize the upper part of the pixel board pattern 121A, on which multiple conductive layers, driving transistors 160 and multiple lines are disposed. The planarization layer 148 can be configured as a single layer or multiple layers made of organic materials. For example, the planarization layer 148 can be made of photoresist or acrylic-based organic materials. However, this disclosure is not limited thereto.

[0090] Meanwhile, at least one of the multiple buffer layer 141, active buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146, and passivation layer 147 can be made of an inorganic insulating material among insulating materials. For this reason, the display device 100 may be prone to breakage and damage during the stretching process. Therefore, the multiple buffer layer 141, active buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146, and passivation layer 147 can be patterned in the form of multiple first plate patterns 121 and formed only above the multiple first plate patterns 121, and not in the area between the multiple first plate patterns 121.

[0091] The planarization layer 148 can be configured to cover the top and side surfaces of the multi-buffer layer 141, active buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146, and passivation layer 147 on a plurality of first board patterns 121. Therefore, the planarization layer 148 can compensate for horizontal differences between the side surfaces of the multi-buffer layer 141, active buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146, and passivation layer 147. Furthermore, the planarization layer 148 can increase the bonding strength with the plurality of interconnect lines 180 disposed on the side surface of the planarization layer 148.

[0092] First connection pad CNT1 and second connection pad CNT2 are disposed on planarization layer 148. First connection pad CNT1 and second connection pad CNT2 are electrodes used to electrically connect the light-emitting element 170 to the driving transistor 160 and the power supply line. For example, first connection pad CNT1 can electrically connect the p electrode 175 of the light-emitting element 170 to the driving transistor 160, and second connection pad CNT2 can electrically connect the n electrode 174 of the light-emitting element 170 to the power supply line.

[0093] A bonding layer AD is disposed on the first connection pad CNT1 and the second connection pad CNT2. The light-emitting element 170 can be bonded to the first connection pad CNT1 and the second connection pad CNT2 through the bonding layer AD.

[0094] The bonding layer AD can be a conductive bonding pattern made by dispersing conductive balls into an insulating base component. Therefore, when heat or pressure is applied to the bonding layer AD, the conductive balls become electrically connected in the areas where heat or pressure is applied, giving the bonding layer AD conductive properties. Areas not pressed can have insulating properties.

[0095] A light-emitting element 170 is disposed on a bonding layer AD. The light-emitting element 170 includes an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175. The light-emitting element 170 of the display device 100 according to an embodiment of the present disclosure has a flip-chip structure having an n-electrode 174 and a p-electrode 175 formed on one surface thereon.

[0096] The n-type layer 171 can also be disposed on a separate base substrate made of a light-transmitting material. An active layer 172 is disposed on the n-type layer 171. The active layer 172 can be a light-emitting layer disposed in the light-emitting element 170 and configured to emit light. A p-type layer 173 can be disposed on the active layer 172.

[0097] The light-emitting element 170 of the display device 100 according to an embodiment of the present disclosure is manufactured by sequentially stacking an n-type layer 171, an active layer 172 and a p-type layer 173, etching a predetermined portion, and then forming an n-electrode 174 and a p-electrode 175.

[0098] The n-electrode 174 can be disposed in the etched region as described above. The n-electrode 174 can be made of a conductive material. Furthermore, the p-electrode 175 can be disposed in the non-etched region. The p-electrode 175 can also be made of a conductive material. For example, the n-electrode 174 is disposed on the n-type layer 171 exposed by the etching process, and the p-electrode 175 is disposed on the p-type layer 173. The p-electrode 175 can be made of the same material as the n-electrode 174.

[0099] A dam 149 is disposed on the planarization layer 148. The dam 149 is a component that separates adjacent sub-pixels SPX. The dam 149 can be disposed between multiple light-emitting elements 170 and suppress color mixing.

[0100] Simultaneously, various conductive layers can be further disposed on the pixel board pattern 121A. For example, a first conductive layer 151 can be disposed on the gate insulating layer 143, and a second conductive layer 152 can be disposed on the first interlayer insulating layer 144. Furthermore, a third conductive layer 153 can be disposed on the second interlayer insulating layer 145, and a fourth conductive layer 154 can be disposed on the planarization layer 148. Multiple conductive layers can be included in any of multiple lines, multiple transistors, and multiple capacitors.

[0101] A filler layer 190 is disposed between the lower substrate 111 and the upper substrate 112. The filler layer 190 may be disposed on the entire surface of the lower substrate 111, and the space between the constituent elements disposed on the upper substrate 112 and the lower substrate 111 may be filled with the filler layer 190. The filler layer 190 may be made of a curable adhesive.

[0102] Next, multiple connection lines 180 can extend from the first line pattern 122 to the pixel board pattern 121A and connect to multiple lines on the pixel board pattern 121A. For example, the first connection line 181 and the second connection line 182 can extend from the first line pattern 122 to the planarization layer 148 of the pixel board pattern 121A. The first connection line 181 can be connected to the reference line RL and multiple data lines DL, and the second connection line 182 can be connected to the low-potential power line VSSL, the scan line SL, the light emission control line EML, and the high-potential power line VDDL.

[0103] The third connecting line 183 includes a third upper connecting line 183b and a third lower connecting line 183a. The third connecting line 183 may have a bilinear structure including the third upper connecting line 183b and the third lower connecting line 183a. A third interlayer insulating layer 146 is disposed on the third lower connecting line 183a, and the third upper connecting line 183b is disposed on the third interlayer insulating layer 146. The third lower connecting line 183a can extend from the first line pattern 122 to the second interlayer insulating layer 145 of the pixel board pattern 121A. The third upper connecting line 183b can extend from the first line pattern 122 to the third interlayer insulating layer 146 of the pixel board pattern 121A. The third connecting line 183 can extend from the first line pattern 122 to the pixel board pattern 121A and connect to any one of the multiple lines on the pixel board pattern 121A, or be spaced apart from the multiple lines. Reference will be made below. Figure 5A and Figure 5B The third connecting line 183 is described in more detail.

[0104] In this configuration, the accompanying drawings show a third upper connecting line 183b extending to the third interlayer insulating layer 146 of the pixel board pattern 121A, and a third lower connecting line 183a extending to the second interlayer insulating layer 145 of the pixel board pattern 121A. However, these lines may extend to other insulating layers among the plurality of insulating layers on the pixel board pattern 121A. However, this disclosure is not limited thereto. Furthermore, the accompanying drawings show a third interlayer insulating layer 146 extending from the pixel board pattern 121A disposed between the third upper connecting line 183b and the third lower connecting line 183a. However, another insulating layer may be disposed between the third upper connecting line 183b and the third lower connecting line 183a. However, this disclosure is not limited thereto.

[0105] Meanwhile, in the case of a typical display device, various lines, such as multiple scan lines and multiple data lines, are arranged between multiple sub-pixels and extend in a straight line. Multiple sub-pixels are connected to a single signal line. Therefore, in the case of a typical display device, various lines, such as scan lines, data lines, power lines, and reference lines, extend in a direction from one side to the other without interruption on the substrate.

[0106] Conversely, in the case of the display device 100 according to an embodiment of the present disclosure, various lines (e.g., scan lines SL, data lines DL, power lines, and reference lines RL) that can be considered as straight lines for a general display device are only provided on the plurality of first board patterns 121 and the plurality of second board patterns 123. That is, in the display device 100 according to an embodiment of the present disclosure, straight lines are only provided on the plurality of first board patterns 121 and the plurality of second board patterns 123. Furthermore, in the display device 100 according to an embodiment of the present disclosure, lines on two adjacent first board patterns 121 can be connected by a plurality of connecting lines 180. Therefore, the plurality of connecting lines 180 electrically connect the lines on two adjacent first board patterns 121.

[0107] Meanwhile, the circuitry of the sub-pixel SPX configured to operate the light-emitting element 170 can be configured in various ways. For example, in addition to the driving transistor 160, the circuitry of the sub-pixel SPX can also include various transistors and capacitors. The configuration of multiple lines can vary depending on the configuration of the sub-pixel SPX circuitry.

[0108] For example, such as Figure 4 As shown, when the circuit of the sub-pixel SPX includes a light-emitting element 170, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a driving transistor 160, and a capacitor Cst, the sub-pixel SPX can be connected to the scan line SL, the data line DL, the light-emitting control line EML, the reference line RL, the high-potential power line VDDL, and the low-potential power line VSSL.

[0109] First, a first transistor T1 is positioned between the data line DL and the first node N1. The first transistor T1 can be turned on by the scan signal SCAN of the scan line SL, and transmit the voltage of the data line DL to the first node N1.

[0110] The second transistor T2 is disposed between the second node N2 and the third node N3. The second transistor T2 can be turned on by the scan signal SCAN of the scan line SL and connects the second node N2 and the third node N3.

[0111] The third transistor T3 is positioned between the first node N1 and the reference line RL. The third transistor T3 can be turned on by the light emission control signal EM of the light emission control line EML, and transmit the reference voltage Vref to the first node N1.

[0112] The fourth transistor T4 is located between the third node N3 and the fourth node N4. The fourth transistor T4 can be turned on by the light emission control signal EM of the light emission control line EML and is connected to the third node N3 and the fourth node N4.

[0113] The fifth transistor T5 is positioned between the reference line RL and the fourth node N4. The fifth transistor T5 can be turned on by the scan signal SCAN of the scan line SL, and transmits the reference voltage Vref to the fourth node N4.

[0114] The driving transistor 160 is disposed between the high-potential power line VDDL and the third node N3. The driving transistor 160 can control the driving current flowing through the third node N3 and the fourth node N4 to the light-emitting element 170. In addition, the gate electrode 162 and the drain electrode 164 of the driving transistor 160 can be connected to the second node N2 and the third node N3 respectively, and the driving transistor 160 can be switched to a diode connection state when the second transistor T2 is turned on.

[0115] A capacitor Cst is positioned between the first node N1 and the second node N2. When the light-emitting element 170 emits light, the capacitor Cst can maintain a constant voltage on the gate electrode 162 of the driving transistor 160.

[0116] The light-emitting element 170 is disposed between the fourth node N4 and the low-potential power line VSSL. The light-emitting element 170 can emit light by using the drive current from the drive transistor 160.

[0117] In the following description, it will be assumed that multiple sub-pixels SPX are connected to scan line SL, data line DL, light emission control line EML, reference line RL, high-potential power line VDDL, and low-potential power line VSSL.

[0118] Figure 5AThis is a schematic enlarged top view of the pixel panel pattern of a display device according to an embodiment of the present disclosure. Figure 5B This is an enlarged top view of the display area of ​​a display device according to an embodiment of the present disclosure. Figure 6A This is a schematic enlarged top view of the pixel panel pattern of a display device according to an embodiment of the present disclosure. Figure 6B This is an enlarged top view of the display area of ​​a display device according to an embodiment of the present disclosure. Figure 7 This is an enlarged top plan view of the bypass board pattern of a display device according to an embodiment of the present disclosure. Figures 8A to 9B It is along Figure 7 The cross-sectional view taken by line A-A' in the diagram. Figure 10 yes Figure 2 A schematic cross-sectional view of the third connecting line in regions (1) to (4) of the diagram.

[0119] Specifically, Figure 5A and Figure 5B It is a view used to explain lines extending in the first direction X and their adjacent routes. Figure 6A and Figure 6B It is a view used to explain lines extending in the second direction Y and their adjacent routes. Figure 8A and Figure 8B This is a view used to explain one embodiment of the welded portion WD, and Figure 9A and Figure 9B This is a view used to explain another embodiment of the welded portion WD. For ease of description, in... Figures 5A to 6B In the diagram, multiple lines are shown as thick solid lines, the first type of bypass route is shown as dashed lines, and the second type of bypass route is shown as a single-dot dashed line. Furthermore, Figure 10 The bypass line connected by the third connecting line 183 and its corresponding reference numerals are shown.

[0120] refer to Figures 5A to 6B Multiple bypass lines are disposed on pixel board pattern 121A and bypass board pattern 121B, with multiple lines disposed on pixel board pattern 121A. These multiple lines can be lines used to directly apply signals to multiple sub-pixels SPX. When a defective sub-pixel XSPX occurs, the multiple bypass lines can be lines that receive signals from the multiple lines and transmit the signals to adjacent pixel board pattern 121A and lines that transmit normal sub-pixels SPX.

[0121] Multiple bypass lines can include first-type bypass lines and second-type bypass lines. First-type bypass lines can be directly connected to multiple lines and receive signals. Signals transmitted from another bypass line to the first-type bypass line can be transmitted to a line connected to the first-type bypass line, enabling the circuitry of the sub-pixel SPX connected to that line to operate. Second-type bypass lines connected to the first-type bypass lines can be separate from the circuitry of the multiple lines and the sub-pixel SPX, and are only connected to the first-type bypass line. Second-type bypass lines can receive signals from the first-type bypass line and transmit signals to another first-type or second-type bypass line. Second-type bypass lines can suppress the application of signals to defective sub-pixels XSPX. If signals are applied to defective sub-pixels XSPX, bright spot defects such as continuous emission from the defective sub-pixel XSPX may occur. Therefore, second-type bypass lines can suppress signal transmission to defective sub-pixels XSPX.

[0122] In this scenario, for each of the multiple lines, either only a first-type bypass path can be formed, or both a first-type bypass path and a second-type bypass path can be formed. For example, only a first-type bypass path can be used to form signal bypass paths for the high-potential power line VDDL, the low-potential power line VSSL, and the reference line RL, which apply a common voltage to the sub-pixel SPX. Alternatively, both first-type and second-type bypass paths can be used to form signal bypass paths for the scan line SL and the light emission control line EML, which control the operating timing of the sub-pixel SPX, or to form signal bypass paths for the first data line DL1, the second data line DL2, and the third data line DL3, which apply different voltages to the sub-pixel SPX. Therefore, a second-type bypass path can be used to form signal bypass paths for at least some of the multiple lines, thereby suppressing bright spot defects by suppressing signals from being applied to some defective sub-pixels XSPX.

[0123] refer to Figure 5A and Figure 5B Reference line RL, first data line DL1, second data line DL2, and third data line DL3 extend along a first direction X on pixel board pattern 121A. The two opposite ends of each of reference line RL, first data line DL1, second data line DL2, and third data line DL3 can be connected to multiple first connection lines 181.

[0124] Bypass reference line RLa, first-first bypass data line DL1a, first-second bypass data line DL1b, second-first bypass data line DL2a, second-second bypass data line DL2b, third-first bypass data line DL3a, and third-second bypass data line DL3b are disposed on pixel board pattern 121A. The two opposite ends of each of the multiple bypass lines can be connected to multiple third connection lines 183. In this case, bypass reference line RLa, first-first bypass data line DL1a, second-first bypass data line DL2a, and third-first bypass data line DL3a can be first-type bypass lines directly connected to existing lines and configured to receive signals, and first-second bypass data line DL1b, second-second bypass data line DL2b, and third-second bypass data line DL3b can be second-type bypass lines configured to receive signals from the first-type bypass lines.

[0125] The bypass reference line RLa can be electrically connected to the reference line RL. For example, the bypass reference line RLa can be connected to the reference line RL and receive the reference voltage Vref. One end of the bypass reference line RLa can extend to the upper left corner of the pixel board pattern 121A, and the other end of the bypass reference line RLa can extend to the lower left corner of the pixel board pattern 121A and connect to the third connection line 183.

[0126] The first-first bypass data line DL1a can be electrically connected to the first data line DL1, and the first-second bypass data line DL1b can be configured to be separate from the first data line DL1 and the first-first bypass data line DL1a. The first-first bypass data line DL1a can be directly connected to the first data line DL1 and receive the first data voltage. The first-second bypass data line DL1b can be configured to be spaced apart from the first data line DL1 and separate from the circuitry of the first sub-pixel SPX1 on the same pixel board pattern 121A. That is, the signal from the first-second bypass data line DL1b can be excluded from the circuitry of the first sub-pixel SPX1 on the same pixel board pattern 121A. One end of each of the first-first bypass data line DL1a and the first-second bypass data line DL1b can extend to the upper left corner of the pixel board pattern 121A, and the other end of each of the first-first bypass data line DL1a and the first-second bypass data line DL1b can extend to the lower left corner of the pixel board pattern 121A and connect to the third connection line 183.

[0127] The second-first bypass data line DL2a can be electrically connected to the second data line DL2, and the second-second bypass data line DL2b can be configured to be separate from the second data line DL2 and the second-first bypass data line DL2a. The second-first bypass data line DL2a can be connected to the second data line DL2 and receive the second data voltage, and the second-second bypass data line DL2b can be configured to be spaced apart from the second data line DL2 and separate from the circuitry of the second sub-pixel SPX2. The signal from the second-second bypass data line DL2b can be not directly applied to the circuitry of the second sub-pixel SPX2 on the same pixel board pattern 121A. One end of each of the second-first bypass data line DL2a and the second-second bypass data line DL2b can extend to the upper right corner of the pixel board pattern 121A, and the other end of each of the second-first bypass data line DL2a and the second-second bypass data line DL2b can extend to the lower right corner of the pixel board pattern 121A and connect to the third connecting line 183.

[0128] The third-first bypass data line DL3a can be electrically connected to the third data line DL3, and the third-second bypass data line DL3b can be configured to be separate from the third data line DL3 and the third-first bypass data line DL3a. The third-first bypass data line DL3a can be connected to the third data line DL3 and receive the third data voltage, and the third-second bypass data line DL3b can be configured to be spaced apart from the third data line DL3 and separate from the circuitry of the third sub-pixel SPX3. The signal from the third-second bypass data line DL3b can be excluded from the circuitry of the third sub-pixel SPX3 on the same pixel board pattern 121A. One end of each of the third-first bypass data line DL3a and the third-second bypass data line DL3b can extend to the upper right corner of the pixel board pattern 121A, and the other end of each of the third-first bypass data line DL3a and the third-second bypass data line DL3b can extend to the lower right corner of the pixel board pattern 121A and connect to the third connecting line 183.

[0129] refer to Figure 6A and Figure 6B The low-potential power line VSSL, scan line SL, light emission control line EML, and high-potential power line VDDL extend along the second direction Y on the pixel board pattern 121A. The two opposite ends of each of the low-potential power line VSSL, scan line SL, light emission control line EML, and high-potential power line VDDL can be connected to multiple second connection lines 182.

[0130] A bypass low-potential power line VSSLa, a first bypass scan line SLa, a second bypass scan line SLb, a first bypass light emission control line EMLa, a second bypass light emission control line EMLb, and a bypass high-potential power line VDDLa are disposed on pixel board pattern 121A. The two opposite ends of each of the multiple bypass lines can be connected to multiple third connection lines 183. In this case, the first bypass scan line SLa, the first bypass light emission control line EMLa, the bypass low-potential power line VSSLa, and the bypass high-potential power line VDDLa can be first-type bypass lines, and the second bypass scan line SLb and the second bypass light emission control line EMLb can be second-type bypass lines.

[0131] The bypass low-potential power line VSSLa can be electrically connected to the low-potential power line VSSL. For example, the bypass low-potential power line VSSLa can be connected to the low-potential power line VSSL and receive the low-potential power supply voltage VSS. One end of the bypass low-potential power line VSSLa can extend to the upper left corner of the pixel board pattern 121A, and the other end of the bypass low-potential power line VSSLa can extend to the upper right corner of the pixel board pattern 121A and connect to the third connection line 183.

[0132] A first bypass scan line SLa can be electrically connected to a scan line SL, and a second bypass scan line SLb can be configured to be spaced apart from the scan line SL and the first bypass scan line SLa. The first bypass scan line SLa can be connected to the scan line SL and receive the scan signal SCAN. The second bypass scan line SLb can be separate from the scan line SL and the plurality of sub-pixels SPX, and the signal from the second bypass scan line SLb can not be directly applied to the sub-pixels SPX on the same pixel board pattern 121A. One end of each of the first bypass scan line SLa and the second bypass scan line SLb can extend to the upper left corner of the pixel board pattern 121A, and the other end of each of the first bypass scan line SLa and the second bypass scan line SLb can extend to the upper right corner of the pixel board pattern 121A and connect to the third connecting line 183.

[0133] The first bypass light-emitting control line EML can be electrically connected to the light-emitting control line EML, and the second bypass light-emitting control line EMLb can be configured to be spaced apart from the light-emitting control line EML and the first bypass light-emitting control line EML. The first bypass light-emitting control line EML can be connected to the light-emitting control line EML and receive the light-emitting control signal EM. The second bypass light-emitting control line EMLb can be separate from the light-emitting control line EML and the plurality of sub-pixels SPX, and the signal from the second bypass light-emitting control line EMLb can not be directly applied to the sub-pixels SPX on the same pixel board pattern 121A. One end of each of the first bypass light-emitting control line EMLa and the second bypass light-emitting control line EMLb can extend to the lower left corner of the pixel board pattern 121A, and the other end of each of the first bypass light-emitting control line EMLa and the second bypass light-emitting control line EMLb can extend to the lower right corner of the pixel board pattern 121A and connect to the third connecting line 183.

[0134] The bypass high-potential power line VDDLa can be electrically connected to the high-potential power line VDDL. For example, the bypass high-potential power line VDDLa can be connected to the high-potential power line VDDL and receive the high-potential power supply voltage VDD. One end of the bypass high-potential power line VDDLa can extend to the lower left corner of the pixel board pattern 121A, and the other end of the bypass high-potential power line VDDLa can extend to the lower right corner of the pixel board pattern 121A and connect to the third connection line 183.

[0135] refer to Figure 7 Multiple bypass lines are arranged on the bypass board pattern 121B. Specifically, the bypass reference line RLa, the first-first bypass data line DL1a, the first-second bypass data line DL1b, the second-first bypass data line DL2a, the second-second bypass data line DL2b, the third-first bypass data line DL3a, the third-second bypass data line DL3b, the bypass low-potential power line VSSLa, the first bypass scan line SLa, the second bypass scan line SLb, the first bypass light emission control line EMLa, the second bypass light emission control line EMLb, and the bypass high-potential power line VDDLa are arranged on the bypass board pattern 121B.

[0136] Furthermore, two bypass lines of the same type extending from different pixel board patterns 121A and the third connecting line 183 can be set on a bypass board pattern 121B. That is, a pair of bypass lines can be set on a bypass board pattern 121B, wherein the same signal is applied to the pair of bypass lines. For example, a pair of bypass reference lines RLa, a pair of first-first bypass data lines DL1a, a pair of first-second bypass data lines DL1b, a pair of second-first bypass data lines DL2a, a pair of second-second bypass data lines DL2b, a pair of third-first bypass data lines DL3a, a pair of third-second bypass data lines DL3b, a pair of bypass low-potential power lines VSSLa, a pair of first bypass scan lines SLa, a pair of second bypass scan lines SLb, a pair of first bypass light emission control lines EMLa, a pair of second bypass light emission control lines EMLb, and a pair of bypass high-potential power lines VDDLa can be set on a bypass board pattern 121B.

[0137] Furthermore, the solder portion WD can be positioned between a pair of bypass lines extending from different pixel board patterns 121A and different third connection lines 183. The solder portion WD is configured to selectively connect the pair of bypass lines. The pair of bypass lines can be configured to at least partially overlap each other, with the solder portion WD positioned between them. In this case, the pair of bypass lines can be electrically connected to each other when a soldering process is performed by irradiating the solder portion WD with a laser beam. Therefore, a signal bypass path can be formed by connecting the pair of bypass lines by irradiating the solder portion WD with a laser beam.

[0138] For example, the pair of bypass reference lines RLa may include one bypass reference line RLa extending from the upper right corner of the bypass board pattern 121B toward the welding portion WD, and a remaining bypass reference line RLa extending from the lower right corner of the bypass board pattern 121B toward the welding portion WD. Furthermore, the welding portion WD may be positioned between one bypass reference line RLa and the remaining bypass reference line RLa, and the pair of bypass reference lines RLa may be connected to each other when a welding process is performed by irradiating the welding portion WD with a laser beam LASER. Therefore, when a welding process is performed on the welding portion WD, the reference voltage Vref from the reference line RL can be transmitted through the bypass reference line RLa to the adjacent pixel board pattern 121A in the same column.

[0139] For example, the pair of first-first bypass data lines DL1a may include one first-first bypass data line DL1a extending from the upper right corner of the bypass board pattern 121B, and the remaining first-first bypass data line DL1a extending from the lower right corner of the bypass board pattern 121B. Furthermore, the pair of first-second bypass data lines DL1b may include one first-second bypass data line DL1b extending from the upper right corner of the bypass board pattern 121B, and the remaining first-second bypass data line DL1b extending from the lower right corner of the bypass board pattern 121B.

[0140] Furthermore, the soldered portion WD can be respectively disposed between the first-first bypass data line DL1a extending from the upper right corner of the bypass plate pattern 121B and the first-second bypass data line DL1b extending from the lower right corner of the bypass plate pattern 121B, between the first-second bypass data line DL1b extending from the upper right corner of the bypass plate pattern 121B and the first-first bypass data line DL1a extending from the lower right corner of the bypass plate pattern 121B, and between the first-second bypass data line DL1b extending from the upper right corner of the bypass plate pattern 121B and the first-second bypass data line DL1b extending from the lower right corner of the bypass plate pattern 121B. Therefore, any one of the multiple soldering sections WD is selected, and a soldering process is performed such that a signal from the first data line DL1 can be transmitted to the adjacent pixel board pattern 121A in the same column via a path from the first-first bypass data line DL1a to the first-first bypass data line DL1a, and via either a path from the first-first bypass data line DL1a to the first-second bypass data line DL1b or a path from the first-second bypass data line DL1b to the first-second bypass data line DL1b.

[0141] For example, the pair of second-first bypass data lines DL2a may include one second-first bypass data line DL2a extending from the upper left corner of the bypass board pattern 121B, and the remaining second-first bypass data line DL2a extending from the lower left corner of the bypass board pattern 121B. The pair of second-second bypass data lines DL2b may include one second-second bypass data line DL2b extending from the upper left corner of the bypass board pattern 121B, and the remaining second-second bypass data line DL2b extending from the lower left corner of the bypass board pattern 121B.

[0142] The soldered portion WD can be respectively disposed between the second-first bypass data line DL2a extending from the upper left corner of the bypass plate pattern 121B and the second-second bypass data line DL2b extending from the lower left corner of the bypass plate pattern 121B, between the second-second bypass data line DL2b extending from the upper left corner of the bypass plate pattern 121B and the second-first bypass data line DL2a extending from the lower left corner of the bypass plate pattern 121B, and between the second-second bypass data line DL2b extending from the upper left corner of the bypass plate pattern 121B and the second-second bypass data line DL2b extending from the lower left corner of the bypass plate pattern 121B. Therefore, any one of the multiple soldering sections WD is selected, and a soldering process is performed such that the signal from the second data line DL2 can be transmitted to the adjacent pixel board pattern 121A in the same column via a path from the second-first bypass data line DL2a to the second-first bypass data line DL2a, and via either a path from the second-first bypass data line DL2a to the second-second bypass data line DL2b or a path from the second-second bypass data line DL2b to the second-second bypass data line DL2b.

[0143] For example, the pair of third-first bypass data lines DL3a may include one third-first bypass data line DL3a extending from the upper left corner of the bypass board pattern 121B, and the remaining third-first bypass data line DL3a extending from the lower left corner of the bypass board pattern 121B. The pair of third-second bypass data lines DL3b may include one third-second bypass data line DL3b extending from the upper left corner of the bypass board pattern 121B, and the remaining third-second bypass data line DL3b extending from the lower left corner of the bypass board pattern 121B.

[0144] The soldered portion WD can be respectively located between the third-first bypass data line DL3a extending from the upper left corner of the bypass board pattern 121B and the third-second bypass data line DL3b extending from the lower left corner of the bypass board pattern 121B, between the third-second bypass data line DL3b extending from the upper left corner of the bypass board pattern 121B and the third-first bypass data line DL3a extending from the lower left corner of the bypass board pattern 121B, and between the third-second bypass data line DL3b extending from the upper left corner of the bypass board pattern 121B and the third-second bypass data line DL3b extending from the lower left corner of the bypass board pattern 121B. Therefore, any one of the multiple soldering sections WD is selected, and a soldering process is performed such that the signal from the third data line DL3 can be transmitted to the adjacent pixel board pattern 121A in the same column via a path from the third-first bypass data line DL3a to the third-first bypass data line DL3a, and via either a path from the third-first bypass data line DL3a to the third-second bypass data line DL3b or a path from the third-second bypass data line DL3b to the third-second bypass data line DL3b.

[0145] For example, the pair of bypass low-potential power lines VSSLa may include one bypass low-potential power line VSSLa extending from the lower left corner of the bypass board pattern 121B toward the soldering portion WD, and a remaining bypass low-potential power line VSSLa extending from the lower right corner of the bypass board pattern 121B toward the soldering portion WD. Furthermore, the soldering portion WD may be positioned between one bypass low-potential power line VSSLa and the remaining bypass low-potential power line VSSLa. Therefore, when a soldering process is performed on the soldering portion WD, the low-potential power supply voltage VSS from the low-potential power line VSSLa can be transmitted to the adjacent pixel board pattern 121A in the same row via the bypass low-potential power line VSSLa.

[0146] For example, the pair of first bypass scan lines SLa may include a first bypass scan line Sla extending from the lower left corner of the bypass plate pattern 121B, and a remaining first bypass scan line SLa extending from the lower right corner of the bypass plate pattern 121B. The pair of second bypass scan lines SLb may include a second bypass scan line SLb extending from the lower left corner of the bypass plate pattern 121B, and a remaining second bypass scan line SLb extending from the lower right corner of the bypass plate pattern 121B.

[0147] The welding portion WD can be respectively positioned between the first bypass scan line Sla extending from the lower left corner of the bypass plate pattern 121B and the second bypass scan line SLb extending from the lower right corner of the bypass plate pattern 121B, between the second bypass scan line SLb extending from the lower left corner of the bypass plate pattern 121B and the first bypass scan line SLa extending from the lower right corner of the bypass plate pattern 121B, and between the second bypass scan line SLb extending from the lower left corner of the bypass plate pattern 121B and the second bypass scan line SLb extending from the lower right corner of the bypass plate pattern 121B. Therefore, any one of the multiple welding sections WD is selected, and the welding process is performed such that the signal from the scan line SL can be transmitted to the adjacent pixel board pattern 121A in the same row via the path from the first bypass scan line SLa to the second bypass scan line SLb, and via either the path from the second bypass scan line SLb to the first bypass scan line SLa or the path from the second bypass scan line SLb to the second bypass scan line SLb.

[0148] For example, the pair of first bypass light emission control lines EMLa may include one first bypass light emission control line EMLa extending from the upper left corner of the bypass plate pattern 121B, and the remaining first bypass light emission control line EMLa extending from the upper right corner of the bypass plate pattern 121B. The pair of second bypass light emission control lines EMLb may include one second bypass light emission control line EMLb extending from the upper left corner of the bypass plate pattern 121B, and the remaining second bypass light emission control line EMLb extending from the upper right corner of the bypass plate pattern 121B.

[0149] The soldered portion WD can be respectively disposed between the first bypass light emission control line EMLa extending from the upper left corner of the bypass plate pattern 121B and the second bypass light emission control line EMLb extending from the upper right corner of the bypass plate pattern 121B, between the second bypass light emission control line EMLb extending from the upper left corner of the bypass plate pattern 121B and the first bypass light emission control line EMLa extending from the upper right corner of the bypass plate pattern 121B, and between the second bypass light emission control line EMLb extending from the upper left corner of the bypass plate pattern 121B and the second bypass light emission control line EMLb extending from the upper right corner of the bypass plate pattern 121B. Therefore, any one of the multiple welding sections WD is selected, and the welding process is performed such that the signal from the light emission control line EML can be transmitted to the adjacent pixel board pattern 121A in the same row via the path from the first bypass light emission control line EMLa to the second bypass light emission control line EMLb, and via either the path from the second bypass light emission control line EMLb to the first bypass light emission control line EMLa and the path from the second bypass light emission control line EMLb to the second bypass light emission control line EMLb.

[0150] For example, the pair of bypass high-potential power lines VDDLa may include one bypass high-potential power line VDDLa extending from the upper left corner of the bypass board pattern 121B toward the welding portion WD, and a remaining bypass high-potential power line VDDLa extending from the upper right corner of the bypass board pattern 121B toward the welding portion WD. Furthermore, the welding portion WD may be positioned between one bypass high-potential power line VDDLa and the remaining bypass high-potential power line VDDLa. Therefore, when a welding process is performed on the welding portion WD, the high-potential power voltage VDD from the high-potential power line VDDL can be transmitted to the adjacent pixel board pattern 121A in the same row via the bypass high-potential power line VDDLa. In one example, the high-potential power voltage VDD is higher than the low-potential power voltage VSS. In another example, the amplitude of the high-potential power voltage VDD is greater than the amplitude of the low-potential power voltage VSS.

[0151] Next, refer to Figures 8A to 9B The welded portion WD can have various structures. The welded portion WD may include one or more metal layers overlapping the ends of the pair of bypass lines. In the display device 100 according to an embodiment of the present disclosure, the welded portion WD can be formed by selecting either one embodiment of the welded portion WD including one metal layer or another embodiment of the welded portion WD including multiple metal layers.

[0152] refer to Figure 8AOne embodiment of the solder portion WD includes a first metal layer WDLa. For example, a second-first bypass data line DL2a and a second-second bypass data line DL2b may be disposed between a third interlayer insulating layer 146 and a passivation layer 147 and spaced apart from each other. The first metal layer WDLa of the solder portion WD may overlap with the ends of the second-first bypass data line DL2a and the second-second bypass data line DL2b. Furthermore, the first metal layer WDLa of the solder portion WD may be electrically connected to either the second-first bypass data line DL2a or the second-second bypass data line DL2b, and is configured to be insulated from the other of the second-first bypass data line DL2a and the second-second bypass data line DL2b, wherein the passivation layer 147 is located between the two. For example, the first metal layer WDLa may be configured to be spaced apart from the end of the second-first bypass data line DL2a, wherein the passivation layer 147 is located between the two, and the first metal layer WDLa may be electrically connected to the end of the second-second bypass data line DL2b through contact holes of the passivation layer 147.

[0153] refer to Figure 8B When it is intended to form a signal path between the second-first bypass data line DL2a and the second-second bypass data line DL2b, a welding process can be performed by irradiating the area where the second-first bypass data line DL2a and the first metal layer WDLa overlap. Therefore, the passivation layer 147 between the second-first bypass data line DL2a and the first metal layer WDLa is partially removed by the laser beam, and the first metal layer WDLa and the second-first bypass data line DL2a can come into contact with each other during melting and then sintering. Therefore, during the welding process, the second-first bypass data line DL2a and the second-second bypass data line DL2b can be electrically connected to each other through the first metal layer WDLa.

[0154] refer to Figure 9A Another embodiment of the soldered portion WD includes a first metal layer WDLa and a second metal layer WDLb. The first metal layer WDLa can be electrically connected to the second-second bypass data line DL2b and overlaps with the end of the second-second bypass data line DL2b. The second metal layer WDLb can be disposed between the second interlayer insulation layer 145 and the third interlayer insulation layer 146, and is configured to overlap with the end of the second-first bypass data line DL2a and the end of the second-second bypass data line DL2b. The second metal layer WDLb can be electrically connected to the second-first bypass data line DL2a through contact holes in the third interlayer insulation layer 146, and is configured to be insulated from the second-second bypass data line DL2b, wherein the third interlayer insulation layer 146 is located between the two.

[0155] refer to Figure 9B When the area where the first metal layer WDLa, the second metal layer WDLb, and the second-second bypass data line DL2b overlap is irradiated with a laser beam (LASER), the third interlayer insulation layer 146 can be partially removed, and the first metal layer WDLa, the second metal layer WDLb, and the second-second bypass data line DL2b can be electrically connected to each other. Therefore, during the soldering process, the second-first bypass data line DL2a and the second-second bypass data line DL2b can be electrically connected to each other through the second metal layer WDLb.

[0156] Next, refer to Figure 10 Multiple third connecting lines 183 can be arranged as a multi-layer structure on multiple first line patterns 122 to connect multiple bypass lines on pixel board pattern 121A and bypass board pattern 121B. For example, multiple third lower connecting lines 183a and multiple third upper connecting lines 183b can be arranged on one first line pattern 122.

[0157] For example, multiple third lower connection lines 183a connecting the first bypass light-emitting control line EMLa, the second bypass light-emitting control line EMLb, and the bypass high-potential power supply line VDDLa can be set in the location of the third lower connection line 183a. Figure 2 On the first line pattern 122 in region (1), where region (1) is the region between the lower right corner of pixel board pattern 121A and the upper left corner of bypass board pattern 121B. In addition, the third interlayer insulating layer 146 can be disposed on multiple third lower connecting lines 183a, and multiple third upper connecting lines 183b connecting the second-first bypass data line DL2a, the second-second bypass data line DL2b, the third-first bypass data line DL3a, and the third-second bypass data line DL3b can be disposed on the third interlayer insulating layer 146.

[0158] Multiple third-level connecting lines 183a, connecting the first bypass light-emitting control line EMLa, the second bypass light-emitting control line EMLb, and the bypass high-potential power line VDDLa, can be set in... Figure 2 In region (2), that is, on the first line pattern 122 between the lower left corner of the pixel board pattern 121A and the upper right corner of the bypass board pattern 121B. The third interlayer insulating layer 146 can be disposed on multiple third lower connecting lines 183a, and multiple third upper connecting lines 183b connecting the first-first bypass data line DL1a, the first-second bypass data line DL1b and the bypass reference line RLa can be disposed on the third interlayer insulating layer 146.

[0159] Multiple third lower connecting lines 183a connecting the first bypass scan line SLa, the second bypass scan line SLb, and the bypass low-potential power line VSSLa can be disposed in region (3), that is, disposed on the first line pattern 122 disposed between the upper right corner of the pixel board pattern 121A and the lower left corner of the bypass board pattern 121B. The third interlayer insulating layer 146 can be disposed on the multiple third lower connecting lines 183a, and multiple third upper connecting lines 183b connecting the second-first bypass data line DL2a, the second-second bypass data line DL2b, the third-first bypass data line DL3a, and the third-second bypass data line DL3b can be disposed on the third interlayer insulating layer 146.

[0160] Multiple third lower connection lines 183a connecting the first bypass scan line SLa, the second bypass scan line SLb, and the bypass low-potential power line VSSLa can be disposed in region (4), that is, disposed on the first line pattern 122 between the upper left corner of the pixel board pattern 121A and the lower right corner of the bypass board pattern 121B. The third interlayer insulating layer 146 can be disposed on the multiple third lower connection lines 183a, and multiple third upper connection lines 183b connecting the first-first bypass data line DL1a, the first-second bypass data line DL1b, and the bypass reference line RLa can be disposed on the third interlayer insulating layer 146.

[0161] The following describes a method for forming a bypass signal path using a third connection line 183 and a bypass plate pattern 121B when a defective subpixel XSPX occurs.

[0162] Figure 11 This is an enlarged top view of the display area of ​​a display device according to an embodiment of the present disclosure. Figures 12A to 12C This is an enlarged top plan view of a plurality of bypass board patterns of a display device according to embodiments of the present disclosure. Specifically, Figure 11 This is a top view showing the state of the line bypass process when a defective subpixel XSPX occurs. Figure 12A yes Figure 11 An enlarged top view of the first bypass plate pattern 121B' in the diagram. Figure 12B yes Figure 11 An enlarged top view of pattern 121B'' of the second bypass plate in the diagram, and Figure 12C yes Figure 11 An enlarged top view of pattern 121B''' of the third bypass plate in the diagram. For ease of description, in Figure 11 In the diagram, path (a) is represented by a thick solid line, path (b) by a dashed line, and path (c) by a dotted-dash line. Paths (a), (b), and (c) can be referred to as the first path, the second path, and the third path, respectively. Furthermore, in... Figures 12A to 12CIn the diagram, only bypass lines on the signal transmission path are shaded, bypass lines to which no signal is transmitted are indicated by dashed lines and are not shaded, and welded parts on which soldering processes have been performed are shaded with black lines.

[0163] refer to Figure 11 When defective pixel board patterns 121AX' and 121AX'', including a defective sub-pixel XSPX, are detected in a plurality of pixel board patterns 121A, the first connecting line 181 and the second connecting line 182 connected to the defective pixel board patterns 121AX' and 121AX'' can be removed. For example, the first connecting line 181 and the second connecting line 182 can be disconnected by at least partially removing the first connecting line 181 and the second connecting line 182 connected to the defective pixel board patterns 121AX' and 121AX''. The first connecting line 181 and the second connecting line 182 can be removed, and the first line pattern 122 having the first connecting line 181 and the second connecting line 182 can be removed, so that signals to be transmitted to the lines connected to the defective sub-pixel XSPX can be blocked, thereby suppressing bright spot defects, etc., of the defective sub-pixel XSPX.

[0164] At the same time, for ease of description, Figure 11 The first connecting line 181 and the second connecting line 182 between the defective pixel board patterns 121AX' and 121AX'' and the normal pixel board pattern 121A are not shown. However, the actually disconnected first connecting line 181 and the second connecting line 182 may exist on the lower substrate 111. However, the embodiments of this disclosure are not limited to this. For example, the first connecting line 181 and the second connecting line 182 are disconnected by at least partially removing them, such that erroneous operation of the defective pixel board patterns 121AX' and 121AX'' can be suppressed, and the remaining portions of the disconnected first connecting line 181 and the second connecting line 182 can remain on the lower substrate 111. Furthermore, the portion of the first line pattern 122 disposed below the disconnected first connecting line 181 and the second connecting line 182 may exist on the lower substrate 111.

[0165] In the following text, the signal bypassing method will be described by assuming that the first pixel plate pattern 121AX' and the second pixel plate pattern 121AX'' adjacent to the first pixel plate pattern 121AX' in the first direction X are defective pixel plate patterns 121AX' and 121AX'' including defective sub-pixels XSPX, respectively.

[0166] First, when a defective subpixel XSPX is formed on the first pixel plate pattern 121AX' and the second pixel plate pattern 121AX'', the first connecting line 181 and the second connecting line 182 connected to the first pixel plate pattern 121AX' and the second pixel plate pattern 121AX'' can be removed, and the first line pattern 122 supporting the first connecting line 181 and the second connecting line 182 can be removed.

[0167] Next, the bypass path of the bypass board pattern 121B can be connected so that the signal can be transmitted to other pixel board patterns 121A adjacent to the first pixel board pattern 121AX' and the second pixel board pattern 121AX''. In this case, the signal bypass path can be configured as any of paths (a), (b), and (c).

[0168] First, path (a) is the path through which the signal of pixel plate pattern 121A, which includes only normal sub-pixels SPX, is transmitted to the bypass lines on the first pixel plate pattern 121AX' and the second pixel plate pattern 121AX'', which includes defective sub-pixels XSPX. The signal that has previously been transmitted to the adjacent pixel plate pattern 121A via the first connection line 181 and the second connection line 182 can be transmitted to the adjacent pixel plate pattern 121A via the third connection line 183 and multiple bypass lines on pixel plate pattern 121A and bypass plate pattern 121B. Therefore, path (a) can be a signal path via the bypass line on pixel plate pattern 121A including normal sub-pixels SPX, one of the third connection lines 183, the bypass line on bypass plate pattern 121B, another of the third connection lines 183, and the bypass lines on the first pixel plate pattern 121AX' and the second pixel plate pattern 121AX''.

[0169] In this case, to suppress bright spot defects where signals are transmitted to the defective sub-pixel XSPX and thus the defective sub-pixel XSPX continuously emits light independent of the image, path (a) can preferentially use a second type of bypass path among the multiple bypass paths on the first pixel plate pattern 121AX' and the second pixel plate pattern 121AX''. For example, a first type of bypass path that receives signals directly from existing lines can be used between bypass plate pattern 121B and pixel plate pattern 121A, which includes normal sub-pixels SPX, and a second type of bypass path that is separate from the existing lines and the circuitry of sub-pixels SPX can be preferentially used between bypass plate pattern 121B and the first pixel plate pattern 121AX'. Therefore, signal paths are preferentially formed on the second type of bypass path among the multiple bypass paths on the first pixel plate pattern 121AX' and the second pixel plate pattern 121AX'', thereby suppressing the operation of the defective sub-pixel XSPX.

[0170] However, some bypass paths may only contain Type I bypass paths, allowing paths for signals such as low-potential power supply voltage VSS, high-potential power supply voltage VDD, and reference voltage Vref to be formed on these Type I bypass paths. However, data voltage Vdata, emission control signal EM, and scan signal SCAN, etc., transmitted via Type II bypass paths are not applied to the defective sub-pixel XSPX, rendering the defective sub-pixel XSPX inoperable and thus suppressing bright spot defects.

[0171] Path (b) is a signal transmission path between a bypass line on the second pixel plate pattern 121AX'' and a bypass line on the first pixel plate pattern 121AX'', which includes the defective sub-pixel XSPX. For example, the first pixel plate pattern 121AX'' and the second pixel plate pattern 121AX'' can be configured to be adjacent to each other in the first direction X. In this case, the signals (i.e., the data voltage Vdata and the reference voltage Vref) of the lines extending in the first direction X can be transmitted to the normal pixel plate pattern 121A below the second pixel plate pattern 121AX'' via the bypass line on the first pixel plate pattern 121AX'' and the bypass line on the second pixel plate pattern 121AX''. Therefore, path (b) can be a signal path via the bypass line on the first pixel plate pattern 121AX'', one of the third connecting lines 183, the bypass line on the bypass plate pattern 121B, another of the third connecting lines 183, and the bypass line on the second pixel plate pattern 121AX''.

[0172] In this case, path (b) can preferentially use a second type of bypass path to suppress bright spot defects in the defective sub-pixel XSPX of the second pixel plate pattern 121AX'' that emit light via a signal transmitted from the first pixel plate pattern 121AX'' to the second pixel plate pattern 121AX''. For example, a signal from the first pixel plate pattern 121AX'' can be transmitted to a second type of bypass path on the second pixel plate pattern 121AX''. If the line for the signal only includes a first type of bypass path among the multiple bypass paths on the second pixel plate pattern 121AX'', the signal is transmitted to the first type of bypass path. However, if the line for the signal includes both the first type of bypass path and the second type of bypass path, the signal can be transmitted to the second type of bypass path. Therefore, the signal path is preferentially formed on a second type of bypass path among the multiple bypass paths on the second pixel plate pattern 121AX'', thereby suppressing the operation of the defective sub-pixel XSPX.

[0173] Path (c) is the path through which signals are transmitted from multiple bypass lines on the first pixel board pattern 121AX' and the second pixel board pattern 121AX'', which includes the defective sub-pixel XSPX, to multiple lines on the pixel board pattern 121A, which includes only the normal sub-pixel SPX. Signals transmitted via paths (a) and (b) to the multiple bypass lines on the first pixel board pattern 121AX' and the second pixel board pattern 121AX'' can be transmitted along the third connecting line 183 on path (c) and multiple bypass lines on the bypass board pattern 121B to the adjacent pixel board pattern 121A. Therefore, path (c) can be a signal path through a bypass line on the first pixel plate pattern 121AX' and the second pixel plate pattern 121AX'' including the defective sub-pixel XSPX, one of the third connecting lines 183, a bypass line on the bypass plate pattern 121B, another of the third connecting lines 183, and multiple lines and bypass lines on the pixel plate pattern 121A that only includes the normal sub-pixel SPX.

[0174] In this configuration, to transmit a signal to multiple lines on the pixel board pattern 121A including the normal sub-pixel SPX, path (c) can transmit the signal to a first-type bypass line among the multiple bypass lines provided on the pixel board pattern 121A including the normal sub-pixel SPX. Since the first-type bypass line is directly connected to the multiple lines, the signal can be transmitted to the multiple lines by transmitting the signal to the first-type bypass line. Therefore, the normal sub-pixel SPX can be operated by forming a signal path by connecting the first-type bypass line among the multiple bypass lines provided on the pixel board pattern 121A including the normal sub-pixel SPX to the third connection line 183.

[0175] refer to Figure 11 and Figure 12A The signal transmission paths of paths (a) and (b) can be formed on the first bypass plate pattern 121B', which is located between the lower left end of the first pixel plate pattern 121AX' and the upper left end of the second pixel plate pattern 121AX''.

[0176] For example, the light emission control signal EM and the high-potential power supply voltage VDD can be transmitted to the path (a) between the first pixel board pattern 121AX' and the pixel board pattern 121A located to the left of the first pixel board pattern 121AX'. Therefore, on the first bypass board pattern 121B', a welding process can be performed on the welding portion WD between the first bypass light emission control line EMLa and the second bypass light emission control line EMLb and the welding portion WD between a pair of bypass high-potential power supply lines VDDLa.

[0177] Therefore, the light emission control signal EM from the pixel plate pattern 121A located on the left side of the first pixel plate pattern 121AX' can be transmitted to the second bypass light emission control line EMLb on the first pixel plate pattern 121AX' via the third connection line 183 and the first bypass light emission control line EMLa and the second bypass light emission control line EMLb on the first bypass plate pattern 121B'. Furthermore, the high-potential power supply voltage VDD from the pixel plate pattern 121A located on the left side of the first pixel plate pattern 121AX' can be transmitted to the bypass high-potential power supply line VDDLa on the first pixel plate pattern 121AX' via the third connection line 183 and the bypass high-potential power supply line VDDLa on the first bypass plate pattern 121B'. In this case, the second bypass light emission control line EMLb is separated from the circuitry of the defective sub-pixel XSPX, thereby suppressing the operation of the defective sub-pixel XSPX.

[0178] For example, the low-potential power supply voltage VSS and the scan signal SCAN can be transmitted to the path (a) between the second pixel board pattern 121AX'' and the pixel board pattern 121A located to the left of the second pixel board pattern 121AX''. Therefore, on the first bypass board pattern 121B', a welding process can be performed on the welding portion WD between the first bypass scan line SLa and the second bypass scan line SLb, and on the welding portion WD between a pair of bypass low-potential power supply lines VSSLa.

[0179] Therefore, the scan signal SCAN from the pixel plate pattern 121A located on the left side of the second pixel plate pattern 121AX'' can be transmitted to the second bypass scan line SLb on the second pixel plate pattern 121AX'' via the third connection line 183 and the first bypass scan line SLa and the second bypass scan line SLb on the first bypass plate pattern 121B'. Furthermore, the low-potential power supply voltage VSS from the pixel plate pattern 121A located on the left side of the second pixel plate pattern 121AX'' can be transmitted to the bypass low-potential power supply line VSSLa on the second pixel plate pattern 121AX'' via the third connection line 183 and the bypass low-potential power supply line VSSLa on the first bypass plate pattern 121B'.

[0180] For example, the reference voltage Vref and the first data voltage can be transmitted to the path (b) between the first pixel board pattern 121AX' and the second pixel board pattern 121AX''. Therefore, on the first bypass board pattern 121B', a soldering process can be performed on the soldering portion WD between a pair of first-second bypass data lines DL1b and the soldering portion WD between a pair of bypass reference lines RLa.

[0181] Therefore, the first data voltage from the first pixel board pattern 121AX' can be transmitted to the first-second bypass data line DL1b on the second pixel board pattern 121AX'' via the third connection line 183 and a pair of first-second bypass data lines DL1b on the first bypass board pattern 121B'. Furthermore, the reference voltage Vref from the first pixel board pattern 121AX' can be transmitted to the bypass reference line RLa on the second pixel board pattern 121AX'' via the third connection line 183 and a pair of bypass reference lines RLa on the first bypass board pattern 121B'.

[0182] refer to Figure 11 and Figure 12B The signal transmission paths of paths (b) and (c) can be formed on the second bypass plate pattern 121B'', which is located between the lower right end of the first pixel plate pattern 121AX' and the upper right end of the second pixel plate pattern 121AX''.

[0183] For example, the light emission control signal EM and the high-potential power supply voltage VDD can be transmitted to the path (c) between the first pixel board pattern 121AX' and the pixel board pattern 121A located to the right of the first pixel board pattern 121AX'. Therefore, on the second bypass board pattern 121B'', a welding process can be performed on the welding portion WD between the second bypass light emission control line EMLb and the first bypass light emission control line EMLa and the welding portion WD between a pair of bypass high-potential power supply lines VDDLa.

[0184] Therefore, the light emission control signal EM from the first pixel board pattern 121AX' can be transmitted through the third connection line 183 and the second bypass light emission control line EMLb and the first bypass light emission control line EMLa on the second bypass board pattern 121B'' to the first bypass light emission control line EMLa and the light emission control line EML on the right side of the pixel board pattern 121A.

[0185] Furthermore, the high-potential power supply voltage VDD from the first pixel board pattern 121AX' can be transmitted via the third connecting line 183 and the bypass high-potential power supply line VDDLa on the second bypass board pattern 121B'' to the bypass high-potential power supply line VDDLa and the high-potential power supply line VDDL on the pixel board pattern 121A located to the right of the first pixel board pattern 121AX'. Therefore, the signal from the pixel board pattern 121A located to the left of the first pixel board pattern 121AX' can be transmitted via paths (a) and (c) to the pixel board pattern 121A located to the right of the first pixel board pattern 121AX'.

[0186] For example, the low-potential power supply voltage VSS and the scan signal SCAN can be transmitted to the path (c) between the second pixel board pattern 121AX'' and the pixel board pattern 121A located to the right of the second pixel board pattern 121AX''. Therefore, on the second bypass board pattern 121B'', a welding process can be performed on the welding portion WD between the second bypass scan line SLb and the first bypass scan line SLa, and on the welding portion WD between a pair of bypass low-potential power supply lines VSSLa.

[0187] Therefore, the scan signal SCAN from the second pixel board pattern 121AX'' can be transmitted via the third connection line 183 and the second bypass scan line SLb and the first bypass scan line SLa on the second bypass board pattern 121B'' to the first bypass scan line SLa and scan line SL on the pixel board pattern 121A to the right of the second pixel board pattern 121AX''. Furthermore, the low-potential power supply voltage VSS from the second pixel board pattern 121AX'' can be transmitted via the third connection line 183 and the bypass low-potential power supply line VSSLa on the second bypass board pattern 121B'' to the bypass low-potential power supply line VSSLa and low-potential power supply line VSSL on the pixel board pattern 121A to the right of the second pixel board pattern 121AX''.

[0188] For example, the second data voltage and the third data voltage can be transmitted to the path (b) between the first pixel board pattern 121AX' and the second pixel board pattern 121AX''. Therefore, on the second bypass board pattern 121B'', a welding process can be performed on the welding portion WD between a pair of second-second bypass data lines DL2b and the welding portion WD between a pair of third-second bypass data lines DL3b.

[0189] Therefore, the second data voltage from the first pixel board pattern 121AX' can be transmitted to the second-second bypass data line DL2b on the second pixel board pattern 121AX'' via the third connection line 183 and the pair of second-second bypass data lines DL2b on the second bypass board pattern 121B''. Furthermore, the third data voltage from the first pixel board pattern 121AX' can be transmitted to the third-second bypass data line DL3b on the second pixel board pattern 121AX'' via the third connection line 183 and the pair of third-second bypass data lines DL3b on the second bypass board pattern 121B''.

[0190] refer to Figure 11 and Figure 12C The signal transmission paths of paths (a) and (c) can be formed on the third bypass plate pattern 121B''', which is adjacent to the lower left end of the second pixel plate pattern 121AX''.

[0191] For example, the light emission control signal EM and the high-potential power supply voltage VDD can be transmitted to the path (a) between the second pixel board pattern 121AX'' and the pixel board pattern 121A located to the left of the second pixel board pattern 121AX''. Therefore, on the third bypass board pattern 121B''', a welding process can be performed on the welding portion WD between the first bypass light emission control line EMLa and the second bypass light emission control line EMLb and the welding portion WD between a pair of bypass high-potential power supply lines VDDLa.

[0192] Therefore, the light emission control signal EM from the pixel plate pattern 121A located on the left side of the second pixel plate pattern 121AX'' can be transmitted to the second bypass light emission control line EMLb on the second pixel plate pattern 121AX'' via the third connecting line 183 and the first bypass light emission control line EMLa and the second bypass light emission control line EMLb on the third bypass plate pattern 121B'''. Furthermore, the high-potential power supply voltage VDD from the pixel plate pattern 121A located on the left side of the second pixel plate pattern 121AX'' can be transmitted to the bypass high-potential power supply line VDDLa on the second pixel plate pattern 121AX'' via the third connecting line 183 and the bypass high-potential power supply line VDDLa on the third bypass plate pattern 121B'''.

[0193] For example, the reference voltage Vref and the first data voltage can be transmitted to the path (c) between the second pixel board pattern 121AX'' and the pixel board pattern 121A below the second pixel board pattern 121AX''. Therefore, on the third bypass board pattern 121B''', a soldering process can be performed on the soldering portion WD between the first-second bypass data line DL1b and the first-first bypass data line DL1a, and on the soldering portion WD between a pair of bypass reference lines RLa.

[0194] Therefore, the first data voltage from the second pixel board pattern 121AX'' can be transmitted via the first-second bypass data line DL1b and the first-first bypass data line DL1a on the third connection line 183 and the third bypass board pattern 121B''' to the first-first bypass data line DL1a and the first data line DL1 on the pixel board pattern 121A below the second pixel board pattern 121AX''. Furthermore, the reference voltage Vref from the second pixel board pattern 121AX'' can be transmitted via the third connection line 183 and the pair of bypass reference lines RLa on the third bypass board pattern 121B''' to the bypass reference lines RLa and RL on the pixel board pattern 121A below the second pixel board pattern 121AX''.

[0195] Therefore, in the display device 100 according to an embodiment of the present disclosure, signals can be transmitted to normal sub-pixels SPX by using multiple bypass board patterns 121B and multiple bypass lines. For example, both the first connection line 181 and the second connection line 182 connected to the pixel board pattern 121A with defective sub-pixels XPSX can be removed, thereby suppressing bright spot defects in the defective sub-pixels XPSX. In this case, various types of signals transmitted to adjacent pixel board patterns 121A via the existing first connection line 181 and second connection line 182 can be transmitted to pixel board patterns 121A in the same row or column via multiple bypass lines and multiple third connection lines 183 on the pixel board pattern 121A and bypass board patterns 121B. Therefore, even if the first connection line 181 and the second connection line 182 connected to the pixel board pattern 121A with defective sub-pixels XPSX are removed, signals can still be transmitted to the remaining pixel board patterns 121A by using bypass lines.

[0196] Furthermore, the display device 100 according to embodiments of this disclosure may include a second type of bypass line separate from the circuitry and multiple lines of the sub-pixel SPX, thereby suppressing the application of signals to the defective sub-pixel XSPX. The first type of bypass line may be directly connected to the multiple lines and receive signals. In the case of a signal being transmitted to the first type of bypass line among the multiple bypass lines on the pixel board pattern 121A having the defective sub-pixel XSPX, the defective sub-pixel XSPX may malfunction abnormally by receiving signals via the first type of bypass line and the lines connected to the first type of bypass line. Therefore, bypass signal paths may be preferentially formed on the second type of bypass line on the pixel board pattern 121A having the defective sub-pixel XSPX, thereby suppressing abnormal operation of the defective sub-pixel XSPX.

[0197] Various examples and aspects of this disclosure are described below. These are provided as examples and do not limit the scope of this disclosure.

[0198] According to one aspect of this disclosure, a display device includes: a substrate; a pattern layer disposed on the substrate and including a plurality of pixel board patterns, a plurality of bypass board patterns, and a plurality of first line patterns; a plurality of sub-pixels disposed on the plurality of pixel board patterns, each of the plurality of sub-pixels including circuitry and a light-emitting element configured to be operated by the circuitry; a plurality of lines disposed on the plurality of pixel board patterns and connected to the plurality of circuitry; a plurality of bypass lines disposed on the plurality of pixel board patterns and the plurality of bypass board patterns; and a plurality of connecting lines disposed on the plurality of first line patterns.

[0199] Multiple first line patterns are respectively disposed between at least some pixel board patterns in a plurality of pixel board patterns and between the plurality of pixel board patterns and a plurality of bypass board patterns. Some lines on some pixel board patterns in the plurality of lines are configured to receive signals from corresponding lines on one or more adjacent pixel board patterns in the plurality of lines. Some lines on some remaining pixel board patterns in the plurality of lines are configured to receive signals from corresponding bypass lines on some bypass board patterns in the plurality of bypass lines. The plurality of pixel board patterns includes the aforementioned pixel board patterns and the remaining pixel board patterns.

[0200] The multiple connecting lines may include: multiple first connecting lines, which extend in a first direction and connect to multiple lines on multiple pixel board patterns; multiple second connecting lines, which extend in a second direction different from the first direction and connect to multiple lines on multiple pixel board patterns; and multiple third connecting lines, which extend in a direction different from the first and second directions and connect to multiple bypass lines on multiple pixel board patterns and multiple bypass lines on multiple bypass board patterns.

[0201] Multiple bypass lines may include first-type bypass lines electrically connected to multiple lines respectively, and second-type bypass lines separate from the circuitry of the multiple lines and multiple sub-pixels. Some of the first-type bypass lines on the multiple pixel board patterns can be connected to corresponding bypass lines on the multiple bypass board patterns via corresponding third connection lines. One or more first-type bypass lines on the bypass board pattern can be located on two opposite sides of each pixel board pattern in the multiple pixel board patterns. Some of the second-type bypass lines on the multiple pixel board patterns can be connected to corresponding bypass lines on the multiple bypass board patterns via corresponding third connection lines. One or more second-type bypass lines on the bypass board pattern can be located on two opposite sides of each pixel board pattern in the multiple pixel board patterns. On each of the multiple bypass board patterns, a pair of first-type bypass lines connected to corresponding first-type bypass lines of different pixel board patterns can be spaced apart from each other, and a pair of second-type bypass lines connected to corresponding second-type bypass lines of different pixel board patterns can be spaced apart from each other.

[0202] The display device may further include multiple welded portions, which are respectively disposed on multiple bypass plate patterns and respectively disposed between any one of a pair of first-type bypass lines and any one of a pair of second-type bypass lines, as well as between a pair of second-type bypass lines. At least some of the multiple bypass lines can be electrically connected to each other through corresponding welded portions of the multiple welded portions.

[0203] The plurality of lines may include: a reference line extending in a first direction and electrically connected to a corresponding first connection line among a plurality of first connection lines; a first data line extending in a first direction and electrically connected to a corresponding first connection line among a plurality of first connection lines; a second data line extending in a first direction and electrically connected to a corresponding first connection line among a plurality of first connection lines; a third data line extending in a first direction and electrically connected to a corresponding first connection line among a plurality of first connection lines; a low-potential power line extending in a second direction and electrically connected to a corresponding second connection line among a plurality of second connection lines; a scan line extending in a second direction and electrically connected to a corresponding second connection line among a plurality of second connection lines; a light emission control line extending in a second direction and electrically connected to a corresponding second connection line among a plurality of second connection lines; and a high-potential power line extending in a second direction and electrically connected to a corresponding second connection line among a plurality of second connection lines.

[0204] Multiple bypass lines may include a bypass reference line electrically connected to a reference line, a bypass low-potential power line electrically connected to a low-potential power line, and a bypass high-potential power line electrically connected to a high-potential power line. A first-type bypass line may include a bypass reference line, a bypass low-potential power line, and a bypass high-potential power line.

[0205] Multiple bypass lines may include a first-first bypass data line electrically connected to a first data line, a first-second bypass data line separate from the first data line, a second-first bypass data line electrically connected to a second data line, a second-second bypass data line separate from the second data line, a third-first bypass data line electrically connected to a third data line, a third-second bypass data line separate from the third data line, a first bypass scan line electrically connected to a scan line, a second bypass scan line separate from the scan line, a first bypass light emission control line electrically connected to a light emission control line, and a second bypass light emission control line separate from the light emission control line. A first type of bypass line may include a first-first bypass data line, a second-first bypass data line, a third-first bypass data line, a first bypass scan line, and a first bypass light emission control line, and a second type of bypass line may include a first-second bypass data line, a second-second bypass data line, a third-second bypass data line, a second bypass scan line, and a second bypass light emission control line.

[0206] A defective pixel pattern with defective sub-pixels in a plurality of pixel pattern can be separated from the corresponding first connecting line and the corresponding second connecting line and connected to the corresponding third connecting line.

[0207] Signals from the line on the pixel board pattern located on one side of the defective pixel board pattern among the multiple lines can be transmitted along the first path to the corresponding bypass line on the defective pixel board pattern among the multiple bypass lines.

[0208] The first path may be a path through a corresponding first type bypass line on the pixel board pattern on the said side, a first corresponding third connecting line among a plurality of third connecting lines, a bypass line on a first bypass board pattern located between the defective pixel board pattern and the pixel board pattern on the said side among a plurality of bypass lines, a second corresponding third connecting line among a plurality of third connecting lines, and a corresponding bypass line on the defective pixel board pattern among a plurality of bypass lines, and the corresponding bypass line among a plurality of bypass lines may include one or more of bypass reference lines, bypass low-potential power lines, bypass high-potential power lines, first-second bypass data lines, second-second bypass data lines, third-second bypass data lines, second bypass scan lines, and second bypass light emission control lines.

[0209] The signal transmitted along the first path to the corresponding bypass line on the defective pixel board pattern among the multiple bypass lines can be transmitted along the third path to a line on the pixel board pattern located on the other side of the defective pixel board pattern among the multiple lines.

[0210] The third path can be a path through a third corresponding third connecting line among multiple third connecting lines, a bypass line on a second bypass board pattern located between the defective pixel board pattern and the pixel board pattern on the other side among multiple bypass lines, a fourth corresponding third connecting line among multiple third connecting lines, a first type bypass line on the pixel board pattern on the other side, and a path through a line on the pixel board pattern on the other side among multiple lines.

[0211] The defective pixel board pattern may include a first pixel board pattern. A second pixel board pattern may be adjacent to the first pixel board pattern, and the second pixel board pattern may be another defective pixel board pattern. A signal transmitted to a bypass line located on the first pixel board pattern in one of the multiple bypass lines may be transmitted along a second path to a bypass line located on the second pixel board pattern in one of the multiple bypass lines.

[0212] The second path can be a path that corresponds to the fifth of a plurality of third connecting lines, a bypass path on a third bypass plate pattern located between the first pixel plate pattern and the second pixel plate pattern among a plurality of bypass paths, a path that corresponds to the sixth of a plurality of third connecting lines, and a path on a bypass path located on the second pixel plate pattern among a plurality of bypass paths.

[0213] Each of the first path, the second path, and the third path can be connected by a pair of bypass lines located on a corresponding bypass plate pattern among a plurality of bypass lines, and the pair of bypass lines can be electrically connected to each other by a welded portion.

[0214] According to one or more aspects of this disclosure, a display device includes: a substrate; a pattern layer disposed on the substrate and including a plurality of pixel board patterns, a plurality of bypass board patterns, and a plurality of first line patterns; a plurality of sub-pixels disposed on the plurality of pixel board patterns, each of the plurality of sub-pixels including circuitry and a light-emitting element configured to be operated by the circuitry; a plurality of lines respectively disposed on the plurality of pixel board patterns and connected to the plurality of circuitry; a plurality of bypass lines respectively disposed on the plurality of pixel board patterns and the plurality of bypass board patterns; and a plurality of connecting lines respectively disposed on the plurality of first line patterns. The plurality of first line patterns may be respectively disposed between the plurality of pixel board patterns and between the plurality of pixel board patterns and the plurality of bypass board patterns.

[0215] The multiple lines may include a reference line extending in a first direction, a first data line extending in the first direction, a second data line extending in the first direction, and a third data line extending in the first direction. The multiple bypass lines may include a bypass reference line connected to the reference line on the pixel board pattern, a first-first bypass data line connected to the first data line on the pixel board pattern, a second-first bypass data line connected to the second data line on the pixel board pattern, and a third-first bypass data line connected to the third data line on the pixel board pattern. One end of each of the bypass reference line, the first-first bypass data line, the second-first bypass data line, and the third-first bypass data line may extend to either the upper left corner or the upper right corner of the pixel board pattern, and the other end of each of the bypass reference line, the first-first bypass data line, the second-first bypass data line, and the third-first bypass data line may extend to either the lower left corner or the lower right corner of the pixel board pattern.

[0216] The multiple bypass lines may further include: a first-second bypass data line disposed on the pixel board pattern and spaced apart from the first data line; a second-second bypass data line disposed on the pixel board pattern and spaced apart from the second data line; and a third-second bypass data line disposed on the pixel board pattern and spaced apart from the third data line, wherein one end of each of the first-second bypass data line, the second-second bypass data line and the third-second bypass data line may extend to either the upper left corner and the upper right corner of the pixel board pattern, and the other end of each of the first-second bypass data line, the second-second bypass data line and the third-second bypass data line may extend to either the lower left corner and the lower right corner of the pixel board pattern.

[0217] The multiple lines may further include low-potential power lines extending in the second direction, scan lines extending in the second direction, light-emitting control lines extending in the second direction, and high-potential power lines extending in the second direction. The multiple bypass lines may also include bypass low-potential power lines connected to the low-potential power lines on the pixel board pattern, first bypass scan lines connected to the scan lines on the pixel board pattern, first bypass light-emitting control lines connected to the light-emitting control lines on the pixel board pattern, and bypass high-potential power lines connected to the high-potential power lines on the pixel board pattern. One end of each of the bypass low-potential power lines, the first bypass scan lines, the first bypass light-emitting control lines, and the bypass high-potential power lines may extend to either the upper left corner or the lower left corner of the pixel board pattern, and the other end of each of the bypass low-potential power lines, the first bypass scan lines, the first bypass light-emitting control lines, and the bypass high-potential power lines may extend to either the upper right corner or the lower right corner of the pixel board pattern.

[0218] The multiple bypass lines may also include a second bypass scan line disposed on the pixel plate pattern and spaced apart from the scan line, and a second bypass light emission control line disposed on the pixel plate pattern and spaced apart from the light emission control line. One end of each of the second bypass scan line and the second bypass light emission control line may extend to either the upper left corner or the lower left corner of the pixel plate pattern, and the other end of each of the second bypass scan line and the second bypass light emission control line may extend to either the upper right corner or the lower right corner of the pixel plate pattern.

[0219] In each of the multiple bypass board patterns, one end of each of the bypass reference line, the first-first bypass data line, the second-first bypass data line, the third-first bypass data line, the first-second bypass data line, the second-second bypass data line, and the third-second bypass data line can extend to either the upper left corner or the upper right corner of the corresponding bypass board pattern, and the other end of each of the bypass reference line, the first-first bypass data line, the second-first bypass data line, the third-first bypass data line, the first-second bypass data line, the second-second bypass data line, and the third-second bypass data line can extend to either the lower left corner or the lower right corner of the corresponding bypass board pattern. In each of the multiple bypass board patterns, one end of each of the bypass low-potential power line, the first bypass scan line, the first bypass light emission control line, the bypass high-potential power line, the second bypass scan line, and the second bypass light emission control line can extend to either the upper left corner or the lower left corner of the corresponding bypass board pattern, and the other end of each of the bypass low-potential power line, the first bypass scan line, the first bypass light emission control line, the bypass high-potential power line, the second bypass scan line, and the second bypass light emission control line can extend to either the upper right corner or the lower right corner of the corresponding bypass board pattern.

[0220] Two of the multiple bypass lines can be provided on each of the multiple bypass plate patterns, and the display device can also include multiple welded parts provided on the multiple bypass plate patterns and between the multiple bypass lines.

[0221] Among the multiple soldering sections, at least one soldering section can be disposed between a pair of bypass reference lines, at least one soldering section can be disposed between a pair of first-first bypass data lines, at least one soldering section can be disposed between a pair of second-first bypass data lines, at least one soldering section can be disposed between a pair of third-first bypass data lines, at least one soldering section can be disposed between the first-first bypass data line and the first-second bypass data line, at least one soldering section can be disposed between the second-first bypass data line and the second-second bypass data line, at least one soldering section can be disposed between the third-first bypass data line and the third-second bypass data line, at least one soldering section can be disposed between a pair of bypass low-potential power lines, at least one soldering section can be disposed between a pair of first bypass scan lines, at least one soldering section can be disposed between a pair of first bypass light emission control lines, at least one soldering section can be disposed between a pair of bypass high-potential power lines, at least one soldering section can be disposed between the first bypass scan line and the second bypass scan line, and at least one soldering section can be disposed between the first bypass light emission control line and the second bypass light emission control line.

[0222] According to one or more aspects of this disclosure, a display device includes: a plurality of pixel plate patterns; a plurality of bypass plate patterns; a plurality of sub-pixels disposed on the plurality of pixel plate patterns, each of the plurality of sub-pixels including a light-emitting element; a plurality of lines disposed on the plurality of pixel plate patterns; a plurality of bypass lines disposed on the plurality of pixel plate patterns and the plurality of bypass plate patterns; and a plurality of connecting lines.

[0223] A first subset of multiple connecting lines can be set between adjacent pixel board patterns in multiple pixel board patterns. A second subset of multiple connecting lines can be set between multiple pixel board patterns and multiple bypass board patterns.

[0224] Multiple pixel patterns can form island-like structures that are separated from each other.

[0225] Multiple bypass plate patterns can form islands that are separate from each other and from multiple pixel plate patterns.

[0226] Each pixel board pattern in a plurality of pixel board patterns can be larger than any bypass board pattern adjacent to the corresponding pixel board pattern.

[0227] One or more transistors can be disposed on each of the multiple pixel board patterns.

[0228] No transistors are placed on any of the multiple bypass board patterns.

[0229] No light-emitting elements are set on any of the multiple bypass plate patterns.

[0230] Multiple lines on a multi-pixel plate pattern can extend straight in a first direction or a second direction perpendicular to the first direction.

[0231] Multiple side lines set on a multi-pixel plate pattern can extend in a direction that is inclined to both the first direction and the second direction.

[0232] Multiple bypass lines arranged on multiple bypass plate patterns can extend straight in the first direction or the second direction, and can also extend in a direction inclined to both the first direction and the second direction.

[0233] Multiple bypass lines can include first-type bypass lines and second-type bypass lines. Within a multi-pixel board pattern, first-type bypass lines on the multi-pixel board pattern can be directly connected to multiple lines on the multi-pixel board pattern. Within a multi-pixel board pattern, second-type bypass lines on the multi-pixel board pattern are not connected to multiple lines on the multi-pixel board pattern, nor are they connected to first-type bypass lines on the multi-pixel board pattern.

[0234] The second type of bypass line on the bypass board pattern can prevent signals from being transmitted to defective subpixels on the pixel board pattern.

[0235] Light-emitting elements can be fabricated on a separate base substrate, either individually or as an array. Subsequently, the light-emitting elements can be inverted and placed on a bonding layer, wherein each light-emitting element is inserted or deposited into a corresponding opening defined in the embankment.

[0236] The display device also includes a substrate. Multiple pixel board patterns and multiple bypass board patterns are disposed on the substrate and are more rigid than the substrate.

[0237] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: substrate; A pattern layer is disposed on the substrate and includes a plurality of pixel board patterns, a plurality of bypass board patterns, and a plurality of first line patterns; Multiple sub-pixels are disposed on a multiple pixel plate pattern, each of the multiple sub-pixels including circuitry and a light-emitting element configured to be operated by the circuitry; Multiple lines, which are respectively disposed on the multiple pixel board patterns and connected to the circuit; Multiple bypass lines are respectively disposed on the multiple pixel plate patterns and the multiple bypass plate patterns; as well as Multiple connecting lines, each of which is disposed on one of the multiple first line patterns. The plurality of first line patterns are respectively disposed between at least some of the plurality of pixel plate patterns and between the plurality of pixel plate patterns and the plurality of bypass plate patterns. Among these lines, some lines located on some pixel board patterns of the plurality of pixel board patterns are configured to receive signals from corresponding lines located on one or more adjacent pixel board patterns. Among these, some lines located on some remaining pixel board patterns within the plurality of lines are configured to receive signals from corresponding bypass lines located on some bypass board patterns within the plurality of bypass lines. The plurality of pixel board patterns include some of the pixel board patterns among the plurality of pixel board patterns, as well as the remaining pixel board patterns.

2. The display device according to claim 1, wherein, The multiple connecting lines include: Multiple first connecting lines, which extend in a first direction and connect to the multiple lines on the multiple pixel board patterns; Multiple second connecting lines, each extending in a second direction different from the first direction and connected to the multiple lines on the plurality of pixel board patterns; and Multiple third connecting lines extend in directions different from the first direction and the second direction and connect to the multiple bypass lines on the multiple pixel board patterns and the multiple bypass lines on the multiple bypass board patterns.

3. The display device according to claim 2, wherein, The multiple bypass routes include: A first type of bypass line, wherein the first type of bypass line is electrically connected to the plurality of lines respectively; and The second type of bypass line is separate from the circuitry of the plurality of lines and the plurality of sub-pixels. In this configuration, some of the first-type bypass routes on the plurality of pixel board patterns are connected to corresponding bypass routes on the plurality of bypass board patterns via corresponding third connecting lines. One or more first-type bypass routes on the bypass board pattern are located on two opposite sides of each pixel board pattern in the plurality of pixel board patterns. Among them, some of the second-type bypass lines on the plurality of pixel board patterns are connected to corresponding bypass lines on the plurality of bypass board patterns via corresponding third connecting lines, wherein one or more second-type bypass lines on the bypass board pattern are arranged on two opposite sides of each pixel board pattern in the plurality of pixel board patterns, and In each of the plurality of bypass board patterns, a pair of first-type bypass lines connected to the corresponding first-type bypass lines of different pixel board patterns are set to be spaced apart from each other, and a pair of second-type bypass lines connected to the corresponding second-type bypass lines of different pixel board patterns are set to be spaced apart from each other.

4. The display device according to claim 3, further comprising: Multiple welded portions are respectively disposed on the multiple bypass plate patterns and respectively disposed between any one of the pair of first-type bypass lines and any one of the pair of second-type bypass lines, as well as between the pair of second-type bypass lines. At least some of the multiple bypass lines are electrically connected to each other through corresponding welded portions of the multiple welded portions.

5. The display device according to claim 4, wherein, The multiple lines include: A reference line, which extends in the first direction and is electrically connected to a corresponding first connection line among the plurality of first connection lines; A first data line extends in the first direction and is electrically connected to a corresponding first connection line among the plurality of first connection lines; A second data line extends in the first direction and is electrically connected to a corresponding first connection line among the plurality of first connection lines; A third data line extends in the first direction and is electrically connected to a corresponding first connection line among the plurality of first connection lines; A low-potential power line, which extends in the second direction and is electrically connected to a corresponding second connection line among the plurality of second connection lines; A scan line that extends in the second direction and is electrically connected to a corresponding second connection line among the plurality of second connection lines; A light-emitting control line, the light-emitting control line extending in the second direction and electrically connected to a corresponding second connecting line among the plurality of second connecting lines; and A high-potential power line that extends in the second direction and is electrically connected to a corresponding second connection line among the plurality of second connection lines.

6. The display device according to claim 5, wherein, The multiple bypass routes include: A bypass reference line, which is electrically connected to the reference line; A bypass low-potential power line, the bypass low-potential power line being electrically connected to the low-potential power line; and A bypass high-potential power line is provided, which is electrically connected to the high-potential power line. The first type of bypass line includes the bypass reference line, the bypass low-potential power line, and the bypass high-potential power line.

7. The display device according to claim 6, wherein, The multiple bypass routes include: First-first bypass data line, the first-first bypass data line is electrically connected to the first data line; The first and second bypass data lines are separate from the first data line; The second-first bypass data line is electrically connected to the second data line; The second-second bypass data line is separate from the second data line; The third-first bypass data line is electrically connected to the third data line; The third-second bypass data line is separate from the third data line; The first bypass scan line is electrically connected to the scan line; The second bypass scan line is separate from the scan line; A first bypass light emission control line, the first bypass light emission control line being electrically connected to the light emission control line; and The second bypass light emission control line is separate from the light emission control line. The first type of bypass line includes a first-first bypass data line, a second-first bypass data line, a third-first bypass data line, a first bypass scan line, and a first bypass light emission control line. The second type of bypass line includes the first-second bypass data line, the second-second bypass data line, the third-second bypass data line, the second bypass scan line, and the second bypass light emission control line.

8. The display device according to claim 7, wherein, The defective pixel board pattern with defective sub-pixels in the plurality of pixel board patterns is separated from the corresponding first connecting line and the corresponding second connecting line and connected to the corresponding third connecting line.

9. The display device according to claim 8, wherein, Signals from the line on the pixel board pattern located on one side of the defective pixel board pattern of the plurality of lines are transmitted along the first path to the corresponding bypass line on the defective pixel board pattern of the plurality of bypass lines.

10. The display device according to claim 9, wherein, The first path includes a path through a corresponding first-type bypass line on the pixel board pattern at the said side, a first corresponding third connecting line among the plurality of third connecting lines, a bypass line on a first bypass board pattern located between the defective pixel board pattern and the pixel board pattern at the said side among the plurality of bypass lines, a second corresponding third connecting line among the plurality of third connecting lines, and a path through the corresponding bypass line on the defective pixel board pattern among the plurality of bypass lines. The corresponding bypass line in the plurality of bypass lines includes one or more of the bypass reference line, the bypass low-potential power line, the bypass high-potential power line, the first-second bypass data line, the second-second bypass data line, the third-second bypass data line, the second bypass scan line, and the second bypass light emission control line.

11. The display device according to claim 10, wherein, The signal transmitted along the first path to the corresponding bypass line on the defective pixel board pattern is transmitted along the third path to a line on the pixel board pattern located on the other side of the defective pixel board pattern.

12. The display device according to claim 11, wherein, The third path is a path through a third corresponding third connecting line among the plurality of third connecting lines, a bypass line on a second bypass board pattern located between the defective pixel board pattern and the pixel board pattern on the other side among the plurality of bypass lines, a fourth corresponding third connecting line among the plurality of third connecting lines, a first type bypass line on the pixel board pattern on the other side, and a line on the pixel board pattern on the other side among the plurality of lines.

13. The display device according to claim 12, wherein, The defective pixel board pattern includes the first pixel board pattern. Wherein, the second pixel plate pattern is adjacent to the first pixel plate pattern, and the second pixel plate pattern is another defective pixel plate pattern, and The signal transmitted to the bypass line located on the first pixel plate pattern in the plurality of bypass lines is transmitted along the second path to the bypass line located on the second pixel plate pattern in the plurality of bypass lines.

14. The display device according to claim 13, wherein, The second path is a path through the fifth corresponding third connecting line among the plurality of third connecting lines, the bypass line on the third bypass board pattern located between the first pixel board pattern and the second pixel board pattern among the plurality of bypass lines, the sixth corresponding third connecting line among the plurality of third connecting lines, and the bypass line located on the second pixel board pattern among the plurality of bypass lines.

15. The display device according to claim 14, wherein, Each of the first path, the second path, and the third path passes through a pair of bypass routes located on a corresponding bypass plate pattern among the plurality of bypass routes, and The pair of bypass lines are electrically connected to each other via a welded section.

16. The display device according to claim 2, wherein, The plurality of third connecting lines extend in a direction inclined to both the first direction and the second direction.

17. The display device according to claim 2, wherein, Each of the plurality of third connecting lines includes a third upper connecting line and a third lower connecting line.

18. The display device according to claim 17, wherein, The third connecting line extends to the corner of the bypass board pattern that is adjacent to one of the four corners of the pixel board pattern.

19. A display device, comprising: substrate; A pattern layer is disposed on the substrate and includes multiple pixel board patterns, multiple bypass board patterns, and multiple first line patterns; Multiple sub-pixels are disposed on a multiple pixel plate pattern, each of the multiple sub-pixels including circuitry and a light-emitting element configured to be operated by the circuitry; Multiple lines, which are respectively disposed on the multiple pixel board patterns and connected to the circuit; Multiple bypass lines are respectively disposed on the multiple pixel plate patterns and the multiple bypass plate patterns; as well as Multiple connecting lines, each of which is disposed on one of the multiple first line patterns. The plurality of first line patterns are respectively disposed between the plurality of pixel plate patterns and between the plurality of pixel plate patterns and the plurality of bypass plate patterns.

20. The display device according to claim 19, wherein, The multiple lines include: Reference line, the reference line extending in a first direction; A first data line, the first data line extending in the first direction; A second data line, the second data line extending in the first direction; and The third data line extends in the first direction. The multiple bypass routes include: Bypass reference line, the bypass reference line being connected to the reference line on the pixel board pattern; First-first bypass data line, the first-first bypass data line is connected to the first data line on the pixel board pattern; The second-first bypass data line is connected to the second data line on the pixel board pattern; and The third-first bypass data line is connected to the third data line on the pixel board pattern, and Wherein, one end of each of the bypass reference line, the first-first bypass data line, the second-first bypass data line, and the third-first bypass data line extends to either the upper left corner or the upper right corner of the pixel board pattern, and the other end of each of the bypass reference line, the first-first bypass data line, the second-first bypass data line, and the third-first bypass data line extends to either the lower left corner or the lower right corner of the pixel board pattern.

21. The display device according to claim 20, wherein, The multiple bypass routes also include: The first and second bypass data lines are disposed on the pixel board pattern and spaced apart from the first data line. The second-second bypass data line is disposed on the pixel plate pattern and spaced apart from the second data line; and The third-second bypass data line is disposed on the pixel board pattern and spaced apart from the third data line. Wherein, one end of each of the first-second bypass data line, the second-second bypass data line, and the third-second bypass data line extends to either the upper left corner or the upper right corner of the pixel board pattern, and the other end of each of the first-second bypass data line, the second-second bypass data line, and the third-second bypass data line extends to either the lower left corner or the lower right corner of the pixel board pattern.

22. The display device according to claim 21, wherein, The multiple lines also include: A low-potential power line extending in a second direction; Scan line, the scan line extending in the second direction; A light-emitting control line extending in the second direction; and A high-potential power line extending in the second direction. The multiple bypass routes also include: A bypass low-potential power line is connected to the low-potential power line on the pixel board pattern. A first bypass scan line is connected to the scan line on the pixel plate pattern; A first bypass light emission control line, the first bypass light emission control line being connected to the light emission control line on the pixel board pattern; and A bypass high-potential power line is provided, which is connected to the high-potential power line on the pixel board pattern. Wherein, one end of each of the bypass low-potential power line, the first bypass scan line, the first bypass light emission control line, and the bypass high-potential power line extends to either the upper left corner or the lower left corner of the pixel board pattern, and the other end of each of the bypass low-potential power line, the first bypass scan line, the first bypass light emission control line, and the bypass high-potential power line extends to either the upper right corner or the lower right corner of the pixel board pattern.

23. The display device according to claim 22, wherein, The multiple bypass routes also include: A second bypass scan line, the second bypass scan line being disposed on the pixel plate pattern and spaced apart from the scan line; and The second bypass light emission control line is disposed on the pixel board pattern and spaced apart from the light emission control line. Wherein, one end of each of the second bypass scan line and the second bypass light emission control line extends to either the upper left corner and the lower left corner of the pixel board pattern, and the other end of each of the second bypass scan line and the second bypass light emission control line extends to either the upper right corner and the lower right corner of the pixel board pattern.

24. The display device according to claim 23, wherein, In each of the plurality of bypass board patterns, one end of each of the bypass reference line, the first-first bypass data line, the second-first bypass data line, the third-first bypass data line, the first-second bypass data line, the second-second bypass data line, and the third-second bypass data line extends to either the upper left corner or the upper right corner of the corresponding bypass board pattern, and the other end of each of the bypass reference line, the first-first bypass data line, the second-first bypass data line, the third-first bypass data line, the first-second bypass data line, the second-second bypass data line, and the third-second bypass data line extends to either the lower left corner or the lower right corner of the corresponding bypass board pattern. In each of the plurality of bypass board patterns, one end of each of the bypass low-potential power line, the first bypass scan line, the first bypass light emission control line, the bypass high-potential power line, the second bypass scan line, and the second bypass light emission control line extends to either the upper left corner or the lower left corner of the corresponding bypass board pattern, and the other end of each of the bypass low-potential power line, the first bypass scan line, the first bypass light emission control line, the bypass high-potential power line, the second bypass scan line, and the second bypass light emission control line extends to either the upper right corner or the lower right corner of the corresponding bypass board pattern.

25. The display device according to claim 24, wherein, Two of the multiple bypass routes are set on each of the multiple bypass plate patterns, and The display device further includes multiple welding parts, which are disposed on the multiple bypass plate patterns and between the multiple bypass lines.

26. The display device according to claim 25, wherein, Among the plurality of soldered portions, at least one soldered portion is disposed between a pair of bypass reference lines, at least one soldered portion is disposed between a pair of first-first bypass data lines, at least one soldered portion is disposed between a pair of second-first bypass data lines, at least one soldered portion is disposed between a pair of third-first bypass data lines, at least one soldered portion is disposed between the first-first bypass data line and the first-second bypass data line, at least one soldered portion is disposed between the second-first bypass data line and the second-second bypass data line, at least one soldered portion is disposed between the third-first bypass data line and the third-second bypass data line, at least one soldered portion is disposed between a pair of bypass low-potential power lines, at least one soldered portion is disposed between a pair of first bypass scan lines, at least one soldered portion is disposed between a pair of first bypass light emission control lines, at least one soldered portion is disposed between a pair of bypass high-potential power lines, at least one soldered portion is disposed between the first bypass scan line and the second bypass scan line, and at least one soldered portion is disposed between the first bypass light emission control line and the second bypass light emission control line.

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