An adaptive noise reduction method for a hearing aid

Abstract

The application discloses an adaptive noise reduction method of a hearing aid, and relates to the technical field of audio signal processing, which comprises the following steps: collecting multi-channel audio signals and performing digital conversion; performing double-mode adaptive software filtering to preliminarily enhance and suppress noise for different sound modes; performing real-time hardware layer equalization noise reduction by using a multi-stage biquad equalizer based on a double-buffering architecture, suppressing dynamic environmental noise by loading a negative gain coefficient, and eliminating audio tearing phenomena; adopting a multi-stage linkage smooth gain adjustment mechanism to synchronously adjust multi-stage gains through single parameter mapping, avoiding transient noise and signal distortion in the switching process; and implementing full life cycle data management. The application aims to solve the problems of poor noise reduction flexibility of the hearing aid in a complex acoustic environment and transient noise caused by parameter switching, realizes accurate coverage of dynamic noise through software and hardware collaborative processing, and significantly improves signal resolution and smoothness of gain adjustment.

Description

Technical Field

[0001] This invention relates to the field of audio signal processing technology, and more particularly to an adaptive noise reduction method for hearing aids. Background Technology

[0002] With the rapid development of digital healthcare and consumer electronics technologies, hearing aids, as key medical devices that assist people with hearing impairments in improving sound perception, have their level of digitalization and intelligence directly affecting the user's wearing experience and auditory compensation effect. Traditional analog hearing aids are gradually transforming into high-fidelity, programmable, and adaptively adjustable digital hearing aids, achieving precise capture and enhancement of weak sound signals through high-performance embedded systems. This process involves complex audio acquisition, signal conditioning, and real-time data processing technologies, forming the technological foundation for building modern intelligent hearing aid systems.

[0003] Among them, intelligent digital hearing aids based on high-performance microcontrollers and professional-grade audio codecs can deeply optimize the acquired raw analog sound signals through integrated digital signal processing algorithms. The basic principle is to utilize high-speed communication interfaces and low-power codec chips to perform differentiated gain control and frequency domain filtering for sound components of different frequencies. This approach aims to overcome sound attenuation during transmission through the external auditory canal and improve the ability to recognize speech and important sound signals in complex background noise environments.

[0004] However, existing digital hearing aid solutions struggle to balance signal enhancement and noise suppression in complex acoustic environments, resulting in limited resolution of low-frequency sounds and high-frequency speech. Furthermore, traditional systems often exhibit audio tearing or discontinuous transitions when switching between different hearing compensation modes or applying filter coefficients due to lag in underlying register configuration, severely impacting the smoothness and coherence of the listening experience. In addition, multi-level gain adjustment mechanisms lack precise linear linkage mapping, easily introducing overload distortion or switching noise during signal amplification. Moreover, the lack of standardized on-chip file management logic leads to inefficient local storage and cross-platform transmission of hearing aid data. Summary of the Invention

[0005] The purpose of this invention is to provide an adaptive noise reduction method for hearing aids, in order to solve the problems of poor noise reduction flexibility of hearing aids in complex acoustic environments and transient noise generated by parameter switching.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] An adaptive noise reduction method for hearing aids includes:

[0008] Step 1, Multi-channel audio signal acquisition and digital conversion: The original analog sound signal is acquired through the differential microphone programmable gain amplifier input path of the high-performance audio codec integrated circuit. The original analog sound signal is converted into digital audio data of a predetermined frame length using an on-chip analog-to-digital converter at a preset sampling frequency. The digital audio data is then transmitted to the audio processing buffer of the high-performance microcontroller through the full-duplex interface of the integrated circuit's built-in audio bus and the direct data transfer unit.

[0009] Step 2, Dual-mode adaptive software filtering: According to the currently selected working mode, a Butterworth bandpass filter of the corresponding order is run in the floating-point arithmetic unit of the high-performance microcontroller. The first preset frequency band range is used for the low-frequency compensation mode, and the second preset frequency band range is used for the speech enhancement mode. The digital audio data is convolved in real time through the floating-point coefficient matrix to achieve the initial enhancement of the target frequency band sound signal and the initial suppression of background noise.

[0010] Step 3, Hardware-level double-buffered real-time equalization and noise reduction: The on-chip micro digital signal processor is configured to the audio codec integrated circuit through the serial synchronization interface, and a predetermined number of infinite impulse response high-pass filters are loaded to filter out extremely low frequency interference below the preset frequency. At the same time, a multi-level dual second-order equalizer based on a double-buffered architecture is called. By loading a negative gain coefficient to a specific frequency point in the noise reduction mode, hardware-level real-time suppression of environmental noise in the dynamic acoustic environment is achieved.

[0011] Step 4, Multi-level Linkage Smooth Gain Adjustment: Receive volume control commands from the button state machine, and synchronously adjust the output channel gain of the digital-to-analog converter, the input channel gain of the analog-to-digital converter, the headphone driver gain, and the microphone programmable gain amplifier gain through a single parameter mapping function to ensure a linear and smooth transition of the total gain within the preset parameter range, and avoid transient noise and signal overload distortion generated during gain switching.

[0012] Step 5, Full Lifecycle Data Management and Status Monitoring: The processed digital audio data is written to the serial flash memory in real time through a standardized file system. At the same time, the serial flash memory is mapped to a universal serial bus large-capacity storage device using a mass storage protocol. With the help of an automatic mute detection mechanism and a low-power power management sequence, the complete recording of the hearing aid process, safe operation of the device, and efficient data interaction are achieved.

[0013] Preferably, in step 1, the operating frequency of the high-performance microcontroller is set to a preset operating frequency, and it has a built-in single-precision floating-point arithmetic unit and digital signal processing instruction set to support real-time audio algorithm operation at high sampling rates.

[0014] Preferably, the audio processing buffer is built in an external static random access memory, and the storage depth of the audio frame is expanded by an incremental address space of a predetermined length to ensure the continuity of the audio stream in a complex multitasking environment.

[0015] Preferably, the sampling frequency is matched according to the Nyquist sampling theorem based on the spectral characteristics of the target sound signal, effectively filtering out irrelevant high-frequency environmental noise and reducing computational power consumption.

[0016] Preferably, the audio codec integrated circuit receives register configuration parameters from the main control unit through a multi-line serial synchronization interface, and the differential gain adjustment range of its analog-to-digital conversion input path is set to a predetermined gain range.

[0017] Preferably, in step 2, the Butterworth bandpass filter supports multiple preset order configurations. In low-frequency compensation mode, the numerator and denominator coefficient matrices of the bandpass filter are updated in real time according to a preset sampling frequency, and the value of each sampling point is calculated using a floating-point recursive algorithm.

[0018] Preferably, the bandpass filter coefficient matrix in the speech enhancement mode is pre-calculated using a specific formula and stored in a read-only memory. When the mode switching is triggered, the filter coefficients are replaced instantly by a memory copy instruction of a predetermined time order.

[0019] Preferably, in step 3, the coefficient loading of the on-chip micro digital signal processor adopts a double-buffered architecture, which includes a first buffer and a second buffer. When writing a new set of multi-level dual second-order equalizer coefficients, the system first writes data to the hidden buffer. After all the coefficients have been verified, the hardware switching of the buffer pointer is triggered by the vertical synchronization signal, thereby eliminating audio tearing.

[0020] Preferably, the cutoff frequency of the infinite impulse response high-pass filter is fixed at a preset cutoff frequency, and its coefficient format adopts a fixed-point two's complement form with a predetermined bit width and corresponds to a preset base, ensuring that it has a suppression capability greater than the preset suppression capability for DC offset and extremely low frequency interference.

[0021] Preferably, in noise reduction mode, the multi-level dual second-order equalizer sets attenuation coefficients at multiple preset noise reduction frequency points, and the single-point attenuation is set to a preset attenuation value to construct a targeted acoustic masking effect.

[0022] Preferably, in enhancement mode, the multi-level dual second-order equalizer sets gain coefficients at multiple preset enhancement frequency points, and the single-point gain is set to a preset gain value to enhance the subtle features of the sound signal.

[0023] Preferably, the coefficient writing process involves frequent switching between multiple preset register pages. The system executes a filter disable instruction before the write operation begins and a filter enable instruction after the register write is completed, with the time consumed by a single switch controlled within a preset switch duration.

[0024] Preferably, in step 4, the range of a single volume parameter for multi-level linked gain adjustment is divided into multiple levels. The digital-to-analog conversion channel gain and the headphone drive gain each correspond to their respective predetermined mapping ranges.

[0025] Preferably, the linkage adjustment mechanism employs a piecewise linear mapping function. When the volume parameter is in the low range, the gain of the digital-to-analog converter channel is adjusted first to ensure the signal-to-noise ratio; when the volume parameter is in the high range, the gain of the microphone programmable gain amplifier is adjusted in a coordinated manner to improve the dynamic range.

[0026] Preferably, in step 5, the standardized file system is mounted to a serial flash memory with a predetermined sector size through a driver link layer. The serial flash memory has a predetermined total capacity and is divided into a predetermined number of logical blocks.

[0027] Preferably, the real-time recording process utilizes file handles for streaming writing. To ensure data consistency, the system executes a forced synchronization command after each predetermined amount of data is written, updating the cluster information in the file allocation table.

[0028] Preferably, the descriptor of the Universal Serial Bus mass storage device includes a preset manufacturer identification code and a preset product identification code. When the device is connected to a computer terminal, it achieves plug-and-play functionality through a standard mass storage driver, allowing external devices to read audio files via direct block addressing.

[0029] Preferably, the automatic mute detection mechanism is configured with a first preset detection period. When the system is in a mute state and the signal energy in the audio processing buffer continuously exceeds a preset energy threshold for a second preset duration, the system triggers an automatic unmute operation to respond to sudden hearing aid needs.

[0030] Preferably, the power management logic includes a preset work identity timeout determination. If no key interaction or audio activity is detected within a predetermined time, the system automatically executes a power-saving sequence, including turning off the organic light-emitting diode display unit and cutting off the microphone bias power supply.

[0031] Preferably, the power management logic further includes a multi-stage forced shutdown sequence. The sequence sequentially shuts down the analog power supply, RF power supply, display power supply, and sensor power supply, with preset delays between each stage to ensure that the system state machine completes the normal unloading of the file system before power failure.

[0032] Preferably, the button state machine adopts a preset polling cycle. A multi-state debounce logic is implemented using a counter: when the count value is within a first preset range, it is determined to be an invalid debounce; when the count value is within a second preset range, it is determined to be a single click event; when the count value exceeds a third preset threshold, it is determined to be a long press or continuous firing event.

[0033] Preferably, the organic light-emitting diode display unit is used to draw audio waveforms in real time. The drawing algorithm adopts a dot matrix mapping scheme of predetermined size, refreshes the display content page by page through a double buffer, and the display delay is less than a preset delay threshold.

[0034] Preferably, the battery monitoring process utilizes a multi-bit analog-to-digital converter to periodically acquire battery voltage. The sampling period is adaptively adjusted within a preset adjustment range based on the current discharge rate. When the voltage falls below a preset safety threshold and the cumulative count exceeds a preset number of counts, if the system is not in a charging state, a forced reset and shutdown procedure is executed.

[0035] Preferably, the wireless transmission module is connected to the main control unit via a serial asynchronous communication interface, and the baud rate is set to a preset baud rate. The system supports real-time transmission of the processed audio stream to the smart terminal via Bluetooth Low Energy protocol, enabling remote collaboration.

[0036] Preferably, the method further includes: during the system power-on self-test phase, reading the predetermined sector information of the serial flash memory through the serial peripheral interface, verifying the integrity of the file system, and automatically loading the last saved user configuration parameters.

[0037] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0038] This invention constructs a highly flexible audio processing link by implementing a dual mechanism of high-order Butterworth filtering at the software layer and double-buffered equalization noise reduction at the hardware layer. Compared with traditional techniques that rely on preset scene classification, this invention uses a multi-level dual second-order equalizer at the hardware level to achieve accurate coverage of dynamic noise frequency points with extremely low switching latency. In particular, the coefficient hot-switching technology based on the double-buffered architecture completely solves the problem of audio tearing and discontinuous transitions caused by register configuration lag in existing solutions, greatly improving the smoothness of the user's listening experience.

[0039] This invention has developed a customized independent frequency-band filtering algorithm to address the spectral differences of different audio frequency bands, ensuring clear resolution of both low-frequency and high-frequency characteristic signals even in complex background noise environments. Through a multi-level linkage volume control mechanism, this invention achieves synchronous linear mapping of gains across multiple levels, including digital-to-analog conversion, analog-to-digital conversion, and headphone driving. This avoids signal overload during large gain adjustments and ensures effective pickup even with extremely weak signal input, achieving a balance between noise reduction depth and voice fidelity.

[0040] This invention fully leverages the hardware computing power of high-performance microcontrollers, rationally distributing complex noise reduction tasks to the software algorithm layer and the on-chip digital signal processor layer, thereby reducing the load on the central processing unit and the overall system power consumption. Through adaptive sampling frequency optimization and logic that automatically enters a low-power state after a preset identity timeout, the device's battery life is significantly extended. By mapping serial flash memory to a standard universal serial bus storage device, this invention enables driverless and fast transmission of audio data between different hardware platforms, greatly improving data access efficiency.

[0041] The automatic mute detection and recovery, multi-state button anti-shake, and multi-stage orderly shutdown sequence integrated in this invention jointly construct a comprehensive system defense system. Whether in the operation of quickly switching usage scenarios or under the interference of battery power fluctuations or unexpected operation, the system can maintain logical consistency and data security. The application of a standardized file system combined with forced synchronization instructions ensures the integrity of audio recordings during the storage process, providing solid technical support for building a modern intelligent hearing aid system. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the overall technical solution architecture of an adaptive noise reduction method for hearing aids proposed in this invention;

[0043] Figure 2 This is a schematic diagram of the core principle framework of the linkage between software layer adaptive filtering and hardware layer equalization noise reduction in this invention;

[0044] Figure 3 This is a logical flowchart of the hardware-layer real-time equalization and noise reduction based on a double-buffered architecture in this invention.

[0045] Figure 4 This is a schematic diagram of the logic mapping and control flow of the multi-level linkage smooth gain adjustment in this invention;

[0046] Figure 5 This is a logical flowchart of the full lifecycle data management and equipment operation status monitoring in this invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Example 1

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0050] In this embodiment, the adaptive noise reduction method for hearing aids is implemented based on a high-performance embedded processing platform. The core of this platform includes a high-performance STM32F4xx series microcontroller with a main frequency of 168MHz. This microcontroller integrates a single-precision floating-point arithmetic unit and a digital signal processing instruction set to support real-time audio algorithm operations at high sampling rates. The system integrates the high-performance audio codec integrated circuit TLV320AIC3204 to realize the digital acquisition, processing, and playback of analog sound signals.

[0051] Specifically, the adaptive noise reduction method for a hearing aid includes the following specific steps:

[0052] Step 1, Multi-channel audio signal acquisition and digital conversion: The original analog sound signal is acquired through the differential microphone programmable gain amplifier input path of the high-performance audio codec integrated circuit. The original analog sound signal is converted into digital audio data of a predetermined frame length using an on-chip analog-to-digital converter at a preset sampling frequency. The digital audio data is then transmitted to the audio processing buffer of the high-performance microcontroller through the full-duplex interface of the integrated circuit's built-in audio bus and the direct data transfer unit.

[0053] In practical implementation, the high-performance audio codec integrated circuit TLV320AIC3204 receives weak analog signals from acoustic sensors through its differential microphone programmable gain amplifier input path. The differential gain adjustment range of this differential microphone programmable gain amplifier input path is set from 0dB to 47.5dB, and independent or linked control of the left and right channel gains is achieved by configuring registers 48 and 49 on Page 1. To improve the signal-to-noise ratio, the input path adopts a balanced differential structure to effectively cancel common-mode noise. The on-chip analog-to-digital converter performs analog-to-digital conversion at a preset sampling frequency of 11000Hz. This sampling frequency is determined by matching the spectral characteristics of the hearing aid's target compensation frequency band (20Hz to 1000Hz) with the Nyquist sampling theorem, aiming to ensure signal integrity while effectively filtering irrelevant high-frequency environmental noise and reducing the overall system power consumption.

[0054] The digital audio data is transmitted via the integrated circuit's built-in I2S full-duplex interface. At the hardware connection level, the I2S2 interface is configured in either slave or master mode, with its clock line, frame synchronization line, and data line connected to the corresponding pins of the microcontroller. The direct data transfer unit uses the microcontroller's DMA controller, configured in double-buffered mode. Each frame of digital audio data is pre-defined as 128 sampling points in length. When the DMA completes the transfer of a frame, a transmission completion interrupt is triggered, and the microcontroller's audio processing buffer is updated accordingly. To ensure the continuity of the audio stream in complex multi-tasking environments, the audio processing buffer is established in an external static random access memory (SRAM). The storage depth of the audio frame is expanded using an incremental address space of pre-defined length (256 bytes), thereby providing sufficient temporal redundancy for subsequent algorithm processing.

[0055] Step 2, Dual-mode adaptive software filtering: Based on the currently selected working mode, a Butterworth bandpass filter of the corresponding order is run in the floating-point arithmetic unit of the high-performance microcontroller. The first preset frequency band range is used for the low-frequency compensation mode, and the second preset frequency band range is used for the speech enhancement mode. The digital audio data is convolved in the frequency domain in real time through the floating-point coefficient matrix to achieve the initial enhancement of the target frequency band sound signal and the initial suppression of background noise.

[0056] In this embodiment, the system supports instant switching between low-frequency compensation mode and voice enhancement mode. The Butterworth bandpass filter supports 2nd, 4th, and 6th order configurations. In low-frequency compensation mode, the first preset frequency band range is set to 125Hz to 500Hz. The microcontroller's floating-point unit calculates the value of each sampling point using a floating-point recursive algorithm. The difference equation corresponding to its typical 2nd order Butterworth filter transfer function is described as follows:

[0057]

[0058] Where x(n) represents the input original digital audio data sequence, y(n) represents the filtered output sequence, b0, b1, and b2 are the coefficients in the numerator coefficient matrix, and a1 and a2 are the coefficients in the denominator coefficient matrix. When the sampling frequency is 11000Hz, the floating-point coefficient matrix for the 125Hz to 500Hz frequency band is preset to [0.097, 0, -0.097, 1, -1.787, 0.806].

[0059] For the voice enhancement mode, the second preset frequency band is set to 500Hz to 1000Hz. The bandpass filter coefficient matrix for this mode is pre-calculated using a bilinear transform formula and stored as a constant array in read-only memory. For example, its coefficient matrix can be set to [0.126,0,-0.126,1,-1.607,0.749]. When the user triggers a mode switch via a button state machine, the system instantly replaces the target mode's coefficient matrix in the current algorithm's runtime space using a memory copy instruction within a predetermined time frame. Because a single-precision floating-point arithmetic unit is used, the time consumption of a single convolution operation is controlled to the nanosecond level, thus ensuring real-time performance.

[0060] Step 3, Hardware-level double-buffered real-time equalization and noise reduction: The on-chip micro digital signal processor is configured to the audio codec integrated circuit through the serial synchronization interface, and a predetermined number of infinite impulse response high-pass filters are loaded to filter out extremely low frequency interference below the preset frequency. At the same time, a multi-level dual second-order equalizer based on a double-buffered architecture is called. By loading a negative gain coefficient to a specific frequency point in the noise reduction mode, hardware-level real-time suppression of environmental noise in the dynamic acoustic environment is achieved.

[0061] Specifically, the microcontroller writes configuration data to the Page 8 and Page 9 registers of the TLV320AIC3204 via a 3-wire SPI serial synchronous interface. The on-chip micro digital signal processor incorporates a high-performance processing engine. First, the system loads a first-stage infinite impulse response high-pass filter with a fixed cutoff frequency of 60Hz to remove extremely low-frequency interference caused by DC offset, low-frequency interference, or sensor friction. The filter coefficients are in 24-bit fixed-point two's complement format, corresponding to a preset base of 8388608.

[0062] The multi-level dual second-order equalizer is implemented in hardware, and its coefficient loading process strictly follows a double-buffer architecture. This double-buffer architecture includes a first buffer and a second buffer (commonly referred to as BufferA and BufferB). When writing a new set of equalizer coefficients, the system first executes a filter disable instruction. Subsequently, the system writes data to the currently hidden buffer. After all the 5-level dual second-order equalizer coefficients have been verified, the buffer pointer is hardware-triggered using a vertical sync signal, and finally the filter is re-enabled. This hot-switching mechanism effectively eliminates audio tearing caused by register configuration lag.

[0063] In noise reduction mode (AGAIN0=1), the multi-level dual second-order equalizer sets attenuation coefficients at multiple preset noise reduction frequency points, including 10Hz, 1600Hz, 2219Hz, 4000Hz, and 5400Hz. The single-point attenuation is set to a preset attenuation value of 12dB to create a targeted acoustic masking effect. In enhancement mode (AGAIN0=0), the system applies positive gain coefficients at preset enhancement frequency points, including 110Hz, 176Hz, 330Hz, 581Hz, and 921Hz, with a single-point gain set to a preset gain value of 11dB to enhance subtle features of the sound signal. The transfer function of its dual second-order filter is as follows:

[0064]

[0065] Among them, N0, N1, N2, D1, and D2 are all 24-bit fixed-point coefficients, which are written one by one through the SPI interface according to a specific register address mapping table.

[0066] Step 4, Multi-level Linkage Smooth Gain Adjustment: Receive volume control commands from the button state machine, and synchronously adjust the output channel gain of the digital-to-analog converter, the input channel gain of the analog-to-digital converter, the headphone driver gain, and the microphone programmable gain amplifier gain through a single parameter mapping function. This ensures a linear and smooth transition of the total gain within the preset parameter range, avoiding transient noise and signal overload distortion generated during gain switching.

[0067] In this embodiment, the system defines a single volume parameter dimension, ranging from 0 to 60 levels. The linkage adjustment mechanism employs a piecewise linear mapping function. When the user increases or decreases the volume using buttons, the microcontroller calculates the corresponding gain for each level. Specifically, the gain of the digital-to-analog converter output channel is adjusted in registers 65 and 66 on Page 0, with a mapping range of -63.5dB to +24dB; the gain of the analog-to-digital converter input channel is adjusted in registers 83 and 84 on Page 0, with a mapping range of -12dB to +20dB; the headphone driver gain is adjusted in registers 16 and 17 on Page 1, with a mapping range of -6dB to +29dB; and the microphone programmable gain amplifier gain adjustment range is 0dB to 47.5dB.

[0068] The logic of the piecewise linear mapping function is as follows: When the volume parameter is in the low range of 0 to 20, the system prioritizes adjusting the digital-to-analog converter channel gain to maintain a low noise floor and ensure the signal-to-noise ratio; when the volume parameter is in the middle range of 21 to 40, the headphone driver gain is adjusted accordingly; when the volume parameter is in the high range of 41 to 60, the gain of the microphone programmable gain amplifier is further increased to improve the dynamic pickup range for extremely weak signals. During gain adjustment, the system enables zero-crossing detection through register configuration to ensure that gain changes only occur at the zero-crossing points of the audio signal, thereby completely eliminating the "click" sound caused by sudden gain changes.

[0069] Step 5, Full Lifecycle Data Management and Status Monitoring: The processed digital audio data is written to the serial flash memory in real time through a standardized file system. At the same time, the serial flash memory is mapped to a universal serial bus large-capacity storage device using a mass storage protocol. With the help of an automatic mute detection mechanism and a low-power power management sequence, the complete recording of the hearing aid process, safe operation of the device, and efficient data interaction are achieved.

[0070] Specifically, the standardized file system uses FatFS, which is mounted to an MX25 series SPINOR Flash memory with 4096-byte sectors via a driver link layer. This memory has a total capacity of 8MB and is divided into 2048 logical blocks. During real-time recording, the system uses file handles for streaming writes. To ensure data consistency, the system automatically executes a forced synchronization command (f_sync) after writing every 4096 bytes of data, updating the cluster information in the file allocation table in real time to prevent file corruption due to unexpected power outages.

[0071] Meanwhile, the microcontroller's USBOTGFS interface is configured as a mass storage device. The descriptor for this Universal Serial Bus mass storage device includes a preset manufacturer identifier code 0x0483 and a preset product identifier code 0x5749. When connected to an external computer terminal, the device achieves plug-and-play functionality through a standard MSC driver. The external host reads audio files from the memory using direct block addressing via the SCSI instruction set.

[0072] In addition, the system operates a complex power and status monitoring logic. The automatic mute detection mechanism is configured with a first preset detection period, which is 3000 milliseconds in this embodiment. When the system is in a mute state and the signal energy in the audio processing buffer continuously exceeds a preset threshold for a second preset duration (e.g., 100 milliseconds), the system determines that there is an urgent need to listen and automatically triggers the unmute operation.

[0073] The power management logic includes a preset work status timeout determination. If no key interaction or valid audio activity is detected within a predetermined period of 5 minutes, the system automatically executes a power-saving sequence. This sequence includes turning off the 128x64 pixel OLED display unit, cutting off the microphone bias power supply, and entering the microcontroller's sleep mode. When a shutdown command is detected, the system executes a multi-stage forced shutdown sequence, sequentially shutting down the 4.2V analog power supply, RF power supply, OLED display power supply, and sensor power supply, with a preset delay of 3 seconds between each stage to ensure proper file system unloading.

[0074] The button state machine uses a preset polling cycle of 30 milliseconds. It implements a three-state debounce logic through an internal counter: when the count value is less than 3, it is considered an invalid bounce; when the count value is between 3 and 50, it is considered a single click event; and when the count value exceeds 50, it is considered a long press or rapid-fire event. This logic effectively avoids accidental touches during operation.

[0075] The organic light-emitting diode (OLED) display unit is used to draw audio waveforms in real time. The drawing algorithm adopts a 100-dot by 2-byte dot matrix mapping scheme, and refreshes the display content page by page through the microcontroller's SPI interface and double-buffer technology to ensure that the display latency is less than 20 milliseconds. Simultaneously, the system periodically samples the battery voltage through a 12-bit ADC, with the sampling period adaptively adjusted between 40 and 500 milliseconds based on the current discharge rate or charging state. When the battery voltage falls below a preset safety threshold and the cumulative count exceeds 10, if the system is not in a charging state, a forced reset shutdown procedure is executed to protect battery life.

[0076] During the power-on self-test phase, the system reads predetermined sector information from the NOR Flash via the SPI interface to verify the integrity of the FatFS file system. If the verification passes, it automatically loads the last saved user configuration parameters, including the previously used volume level, filter mode, and display brightness, achieving a seamless user experience. Furthermore, the system connects to a low-power Bluetooth module via a serial asynchronous communication interface with a baud rate set to 115200bps, supporting real-time pass-through of the processed audio stream to smart terminals for convenient remote collaboration.

[0077] Example 2

[0078] Building upon Example 1, this example provides an adaptive optimization scheme for extreme low-frequency noise environments. In this scheme, the hardware-layer double-buffered real-time equalization and noise reduction step further incorporates a dynamic spectrum monitoring mechanism.

[0079] Specifically, the microcontroller performs a Fast Fourier Transform on the acquired digital audio data at the software layer to extract the characteristic spectral distribution of the current background noise. When steady-state interference of a specific frequency is detected in the environment (such as 50Hz octave interference generated by industrial power supply), the system automatically recalculates the coefficients of the multi-level dual second-order equalizer.

[0080] In step 3 above, the parameter loading process of the multi-level dual second-order equalizer is refined into the following sub-steps:

[0081] A. Background noise feature extraction: The microcontroller uses the floating-point unit to perform FFT operation on 1024 data points in the audio processing buffer to identify the 5 noise frequency points with the highest power spectral density;

[0082] B. Dynamic Coefficient Synthesis: Based on the identified noise frequencies, targeted notch filter coefficients are synthesized online using a preset filter design formula. The center frequency of the notch filter is dynamically aligned to the noise frequencies, and the bandwidth is set to a preset bandwidth value.

[0083] C. Hot-switch execution: The newly synthesized coefficients are written to Buffer B of the AIC3204. At this time, Buffer A still maintains the current filter output. After the microcontroller issues a synchronization trigger command, the AIC3204 switches to Buffer B at the beginning of the next audio frame, realizing dynamic updates of noise reduction characteristics.

[0084] During this process, the multi-level linkage smooth gain adjustment step (step 4) also undergoes adaptive correction. When the peak value of the input signal is detected to exceed a preset safety threshold, the single-parameter mapping function automatically introduces a non-linear compression factor to preferentially reduce the gain of the microphone programmable gain amplifier, thereby preventing clipping distortion in the subsequent ADC conversion process. The formula for calculating this compression factor is as follows:

[0085]

[0086] in, The adjusted target gain, The base gain is based on the current volume level, and α is the smoothing attenuation constant. The peak power of the current frame. This is a preset power threshold. Using this formula, the system can respond to sudden, large-amplitude signals within milliseconds, ensuring smooth output audio.

[0087] Furthermore, the storage management step (step 5) in this embodiment adds a cyclic overwrite function. When the remaining capacity of the NOR Flash is detected to be lower than a preset minimum (e.g., 256KB), the file system automatically identifies the earliest created audio file and performs an erase operation to ensure the continuity of the current recording process. The cyclic overwrite strategy, combined with the timestamp provided by the RTC real-time clock, ensures the time-series traceability of the stored data.

[0088] In terms of low-power management, this embodiment introduces an automatic wake-up mechanism based on signal energy. When the system is in a low-power saving sequence and the main microcontroller is in stop mode, the low-power monitoring module of the audio codec integrated circuit remains running. Once the energy of the microphone input signal is detected to exceed a preset wake-up threshold, the integrated circuit wakes up the microcontroller through an external interrupt pin, allowing the system to return to full-function operation within 100 milliseconds.

[0089] Example 3

[0090] Based on the above embodiments, this embodiment describes in detail an enhanced implementation scheme for high-frequency sound feature extraction. In this scheme, the Butterworth filter in the dual-mode adaptive software filtering processing step (step 2) is configured with a high-order architecture.

[0091] Specifically, for hearing aid scenarios requiring the extraction of high-frequency audio features, the system switches to enhanced mode via a button state machine. In this mode, the Butterworth bandpass filter running in the microcontroller's floating-point unit is increased to order 6 to achieve a steeper cutoff characteristic. Its first preset frequency band is precisely locked between 600Hz and 1200Hz. Due to the increased computational load resulting from the increased order, the microcontroller enables the core accelerator and utilizes the Single Instruction Multiple Data (SIMD) instruction set to perform parallel filtering processing on multiple sampling points.

[0092] In the hardware-level double-buffered real-time equalization noise reduction (step 3), the allocation strategy of the 5-level dual second-order equalizer is adjusted as follows: the first two levels are used to construct a broadband enhancer with a center frequency of 800Hz, and the last three levels are used to construct a high-frequency notch filter in the frequency band above 2000Hz to suppress high-frequency thermal noise generated by electronic circuits. Through this hardware and software collaborative configuration, the system improves the clarity of high-frequency noise by a preset ratio while ensuring that the main information of the audio signal is not lost.

[0093] The USB mass storage interface (step 5) in this embodiment further supports bidirectional data interaction. An external computer can not only read audio recordings but also write configuration files containing custom filter coefficients to a specific configuration folder. The microcontroller reads this file during the startup self-test phase and parses its contents using the FatFS interface, loading the custom Butterworth filter coefficients or Biquad equalizer coefficients into RAM. This allows researchers to customize the acoustic response curve of hearing aids according to specific needs.

[0094] Furthermore, this embodiment adds a spectrum view display function to the organic light-emitting diode display unit (step 5). The system performs a fast Fourier transform on each frame of audio data, presenting the frequency distribution in real time as a histogram on a 128x64 screen. This spectrum view uses a 16-level grayscale mapping algorithm, and the display refresh rate is synchronized with the waveform view. Through the spectrum view, users can intuitively observe the intensity changes of specific frequency components, aiding in the identification of sound characteristics.

[0095] In the battery management logic, this embodiment adds a battery internal resistance assessment algorithm. By comparing the voltage drop and current change rate during charging and discharging, the system estimates the battery's state of health (SOH) in real time. When the assessment result shows that the battery has aged below a preset health threshold, a maintenance warning icon will pop up on the OLED screen, prompting the user to replace the power module, thereby ensuring the reliability of the device at critical moments.

[0096] In summary, this invention achieves precise pickup and processing of weak sound signals through a multi-level hardware and software coupled adaptive processing mechanism. Its architecture, based on the STM32F4 and TLV320AIC3204, fully leverages the advantages of embedded systems in real-time signal processing and power management. The logical connections and data interactions between each step have been deeply optimized, ensuring high-quality audio output even in varying acoustic environments. By introducing double-buffered hot-switching technology, linked gain control, and a comprehensive data management protocol, this invention constructs a stable, efficient, and highly practical digital hearing aid technology system.

[0097] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0098] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An adaptive noise reduction method for a hearing aid, characterized in that, Includes the following steps: Step 1, Multi-channel audio signal acquisition and digital conversion: The original analog sound signal is acquired through the differential microphone programmable gain amplifier input path of the high-performance audio codec integrated circuit. The original analog sound signal is converted into digital audio data of a predetermined frame length using an on-chip analog-to-digital converter at a preset sampling frequency. The digital audio data is then transmitted to the audio processing buffer of the high-performance microcontroller through the full-duplex interface of the integrated circuit's built-in audio bus and the direct data transfer unit. Step 2, Dual-mode adaptive software filtering: According to the currently selected working mode, a Butterworth bandpass filter of the corresponding order is run in the floating-point arithmetic unit of the high-performance microcontroller. The first preset frequency band range is used for the low-frequency compensation mode, and the second preset frequency band range is used for the speech enhancement mode. The digital audio data is convolved in real time through the floating-point coefficient matrix to achieve the initial enhancement of the target frequency band sound signal and the initial suppression of background noise. Step 3, Hardware-level double-buffered real-time equalization and noise reduction: The on-chip micro digital signal processor is configured to the audio codec integrated circuit through the serial synchronization interface, and a predetermined number of infinite impulse response high-pass filters are loaded to filter out extremely low frequency interference below the preset frequency. At the same time, a multi-level dual second-order equalizer based on a double-buffered architecture is called. By loading a negative gain coefficient to a specific frequency point in the noise reduction mode, hardware-level real-time suppression of environmental noise in the dynamic acoustic environment is achieved. Step 4, Multi-level Linkage Smooth Gain Adjustment: Receive volume control commands from the button state machine, and synchronously adjust the output channel gain of the digital-to-analog converter, the input channel gain of the analog-to-digital converter, the headphone driver gain, and the microphone programmable gain amplifier gain through a single parameter mapping function to ensure a linear and smooth transition of the total gain within the preset parameter range, and avoid transient noise and signal overload distortion generated during gain switching. Step 5, Full Lifecycle Data Management and Status Monitoring: The processed digital audio data is written to the serial flash memory in real time through a standardized file system. At the same time, the serial flash memory is mapped to a universal serial bus large-capacity storage device using a mass storage protocol. With the help of an automatic mute detection mechanism and a low-power power management sequence, the complete recording of the hearing aid process, safe operation of the device, and efficient data interaction are achieved.

2. The adaptive noise reduction method for hearing aids according to claim 1, characterized in that, In step 1, the audio codec integrated circuit receives register configuration parameters from the main control unit through a multi-line serial synchronization interface. The differential gain adjustment range of its analog-to-digital conversion input path is set to a predetermined gain interval, and the input path achieves independent or linked control of the gain of the left and right channels through specific registers configured in a predetermined register page. The sampling frequency is matched according to the Nyquist sampling theorem based on the spectral characteristics of speech and low-frequency sound signals to filter out irrelevant high-frequency environmental noise. The direct data transfer unit adopts a double-buffered mode, and the length of each frame of digital audio data is set to a predetermined number of sampling points. When the direct data transfer unit completes the transfer of one frame of data, a transmission completion interrupt is triggered, and the audio processing buffer of the microcontroller is updated accordingly.

3. The adaptive noise reduction method for hearing aids according to claim 1, characterized in that, In step 2, the arithmetic unit includes a single-precision floating-point arithmetic unit and a digital signal processing instruction set. In the low-frequency compensation mode, the numerator and denominator coefficient matrices of the bandpass filter are updated in real time according to a preset sampling frequency. The value of each sampling point is calculated by a floating-point recursive algorithm, which is based on a difference equation. The weighted combination coefficients of the input and output sequences are determined by the floating-point coefficient matrix. In the speech enhancement mode, the system enables the kernel accelerator and uses a single-instruction multiple-data-stream instruction set to perform parallel filtering processing on multiple sampling points to cope with the computational load brought by the high-order filter.

4. The adaptive noise reduction method for hearing aids according to claim 1, characterized in that, In step 3, the coefficient loading process of the on-chip micro digital signal processor includes: before writing a new set of multi-level dual second-order equalizer coefficients, the system first executes a filter disable command; then the system writes fixed-point two's complement coefficients of a predetermined width to the buffer currently in a hidden state; after all the equalizer coefficients have been verified, the hardware switching of the buffer pointer is triggered by the vertical synchronization signal, and finally the filter is re-enabled to eliminate audio tearing caused by register configuration lag; the coefficients of the infinite impulse response high-pass filter correspond to a preset base number to ensure that it has a predetermined suppression capability for extremely low frequency interference caused by DC offset and breathing motion.

5. The adaptive noise reduction method for hearing aids according to claim 1, characterized in that, In step 3, the hardware-layer double-buffered real-time equalization noise reduction further introduces a dynamic spectrum monitoring mechanism, including the following sub-steps: Sub-step A, background noise feature extraction: The microcontroller uses the floating-point arithmetic unit to perform a fast Fourier transform on the predetermined size of data in the audio processing buffer to identify multiple noise frequency points with high power spectral density. Sub-step B, dynamic coefficient synthesis: Based on the identified noise frequency, the targeted notch filter coefficients are synthesized online using a preset filter design formula, and the center frequency of the notch filter is dynamically aligned to the noise frequency. Sub-step C, hot switching execution: The newly synthesized notch filter coefficients are written into the hidden buffer of the audio codec integrated circuit. After the microcontroller issues a synchronization trigger command, the audio codec integrated circuit switches the buffer pointer at the beginning of the next audio frame to realize dynamic updating of noise reduction characteristics.

6. The adaptive noise reduction method for a hearing aid according to claim 1, characterized in that, In step 4, the single-parameter mapping function divides the volume parameter into multiple levels. The logic of the piecewise linear mapping function includes: when the volume parameter is in the low range, the system prioritizes adjusting the digital-to-analog converter channel gain to maintain a predetermined signal-to-noise ratio; when the volume parameter is in the middle range, the headphone driver gain is adjusted accordingly; when the volume parameter is in the high range, the gain of the microphone programmable gain amplifier is adjusted accordingly to improve the dynamic pickup range of weak signals; when the peak value of the input signal is detected to exceed a preset safety threshold, the single-parameter mapping function automatically introduces a non-linear compression factor to prioritize reducing the gain of the microphone programmable gain amplifier to prevent clipping distortion during the analog-to-digital conversion process.

7. The adaptive noise reduction method for hearing aids according to claim 1, characterized in that, In step 5, the standardized file system is mounted to the serial flash memory with a predetermined sector size through the driver link layer, and the serial flash memory is divided into a predetermined number of logical blocks. During real-time recording, the system uses file handles for streaming writing and executes a forced synchronization command after each predetermined amount of data is written, updating the cluster information in the file allocation table in real time. When the remaining capacity of the serial flash memory is detected to be lower than a preset minimum value, the standardized file system automatically identifies the earliest created audio file and performs an erase operation to achieve cyclic overwriting of the storage space.

8. The adaptive noise reduction method for a hearing aid according to claim 1, characterized in that, In step 5, the descriptor of the universal serial bus mass storage device includes a preset manufacturer identification code and a preset product identification code. When the device is connected to an external terminal, it achieves plug-and-play functionality through a standard mass storage class driver, allowing external devices to read audio files via direct block addressing. The automatic mute detection mechanism is configured with a preset detection period. When the system is in a mute state and the signal energy in the audio processing buffer continuously exceeds a preset energy threshold for a predetermined duration, the system determines that there is a need for hearing aids and automatically triggers the unmute operation. In addition, when the system is in a low-power mode, the low-power monitoring module of the audio codec integrated circuit monitors the microphone input signal energy. Once the wake-up threshold is exceeded, an interrupt signal is generated to wake up the microcontroller.

9. The adaptive noise reduction method for a hearing aid according to claim 1, characterized in that, The low-power power management sequence in step 5 includes a work identity timeout determination logic: if no key interaction or audio activity is detected within a predetermined time, the system automatically executes a power-saving sequence, turns off the display unit, cuts off the microphone bias power supply, and enters the microcontroller's sleep mode; when a power-off command is received, the system starts a multi-stage forced shutdown sequence, sequentially turning off the analog power supply, RF power supply, display power supply, and sensor power supply in a predetermined order, with preset delays set between each stage to ensure that the system state machine completes the unloading of the standardized file system before power failure.

10. The adaptive noise reduction method for a hearing aid according to claim 1, characterized in that, The method also includes the following monitoring and maintenance steps: System power-on self-test: Reads the predetermined sector information of the serial flash memory through the serial peripheral interface, verifies the integrity of the file system, and automatically loads the last saved user configuration parameters; Key debounce monitoring: The key state machine adopts a preset polling cycle and implements three-state debounce logic through an internal counter. According to the different preset ranges in which the count value is located, it is determined to be invalid debounce, single click event or long press event respectively. Battery status assessment: The battery voltage is periodically collected using a multi-bit analog-to-digital converter, and the sampling period is adaptively adjusted according to the current discharge rate. The battery health status is estimated in real time by comparing the voltage drop and the rate of change of current. When the voltage is lower than the safety threshold or the health status is lower than the preset threshold, a maintenance warning is triggered and a shutdown procedure is executed. Real-time visualization display: The audio waveform view and spectrum view are presented synchronously in the display unit. The spectrum view is rendered by performing a fast Fourier transform on the audio data and using a grayscale mapping algorithm. The display content is refreshed page by page using double buffer technology.

Images