A laminated chip inductor, a manufacturing method thereof, and an electronic device

Abstract

The application belongs to the field of electronic components, and specifically discloses a laminated chip inductor, a preparation method thereof and electronic equipment; the laminated chip inductor comprises end electrodes, and the total length of the end electrodes in the length direction of the laminated chip inductor accounts for 30-80% of the length of the laminated chip inductor; the laminated chip inductor comprises inductance printed sheets arranged in layers; the inductance printed sheets comprise at least one printed sheet B, at least two printed sheets C and at least one printed sheet D; in the printed sheet C, the content of glass components in the inner electrode layer and the end electrode layer is the same; in the printed sheet D, the content of glass components in the inner electrode layer is less than that in the end electrode layer. By adjusting the content of glass components of the inner electrode and the end electrode in the printed sheet C and the printed sheet D, on the one hand, the electrical performance and the resolution of the electrode after sintering can be ensured; on the other hand, the cracking of the laminated chip inductor during sintering can be reduced or even avoided.

Description

Technical Field

[0001] This invention belongs to the field of electronic components, specifically relating to a multilayer chip inductor, its fabrication method, and an electronic device. Background Technology

[0002] As consumer electronics devices become smaller and more portable, inductors need to maintain or improve their performance while meeting the requirements of smaller size and lighter weight. This has driven the development of technologies such as thin-film inductors and multilayer inductors to meet the needs of smart devices. Photolithography is a microelectronics manufacturing technology that uses photosensitive materials and photoexposure technology to transfer circuit patterns on a substrate, and it is widely used in the production of semiconductor chips and circuit boards. Photolithography can also achieve high-precision patterning at the micron or even submicron level, ensuring precise alignment of the conductive layer and ceramic layer of multilayer inductors. To reduce parasitic capacitance, improve Q value and self-resonant frequency, and eliminate the termination step, photolithographic products internally print terminal electrodes, and then use a method of co-sintering the electrodes (including terminal electrodes and internal electrodes) with the ceramic body to form the inductor. That is, the ceramic green body and silver are sintered together. During the sintering process, both the terminal electrodes and the ceramic shrink. Due to the large difference in shrinkage rates between the silver electrodes and the ceramic body, and the different temperatures at which the silver electrodes and the ceramic body begin to shrink during sintering, cracks can easily occur between the ceramic layer and the terminal electrodes, thus affecting the reliability of photolithographic inductors. Summary of the Invention

[0003] In order to overcome at least one of the technical problems existing in the prior art, one of the objectives of the present invention is to provide a multilayer chip inductor.

[0004] The second objective of this invention is to provide a method for fabricating a multilayer chip inductor.

[0005] The third objective of this invention is to provide an electronic device.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The first aspect of the present invention provides a multilayer chip inductor, the three-dimensional schematic diagram of which is shown below. Figure 1 As shown, its front view, top view, and left view are as follows: Figure 2 As shown, it includes terminal electrodes, the total length (i.e., l) of which accounts for 30-80% of the length (i.e., L) of the multilayer chip inductor. The multilayer chip inductor includes stacked inductor printed chips; the inductor printed chips include at least one printed chip B, at least two printed chips C and at least one printed chip D; The printed wafer B includes a ceramic dielectric layer and a terminal electrode layer and a through-hole electrode layer disposed on the ceramic dielectric layer; The printed wafer C includes a ceramic dielectric layer and an end electrode layer and an inner electrode layer disposed on the ceramic dielectric layer; in the printed wafer C, the inner electrode layer and the end electrode layer are electrically connected, and both the inner electrode layer and the end electrode layer contain glass components, and the content of glass components in the inner electrode layer and the end electrode layer is the same; The printed wafer D includes a ceramic dielectric layer and an end electrode layer and an inner electrode layer disposed on the ceramic dielectric layer; in the printed wafer D, the inner electrode layer and the end electrode layer are not connected, and both the inner electrode layer and the end electrode layer contain glass components, wherein the content of glass components in the inner electrode layer is less than the content of glass components in the end electrode layer.

[0007] In this invention, the glass component is formed by sintering glass powder from silver paste m and silver paste n. To prevent cracking of the yellow light product during sintering, this invention introduces the glass component into the inner electrode layer and the terminal electrode layer. On the one hand, this ensures electrical performance, and on the other hand, it reduces or even avoids cracking of the multilayer chip inductor during sintering.

[0008] In this invention, the glass component content in the terminal electrodes of printed wafer C and printed wafer D is different, which can better adjust the sintering performance of the inductor.

[0009] In some embodiments of the present invention, the multilayer chip inductor further includes a nickel plating layer and a tin plating layer; the nickel plating layer and the tin plating layer enable the inductor to be soldered onto a circuit board.

[0010] In some embodiments of the present invention, the inner electrode layers in the multilayer chip inductor are stacked to form a spiral structure, thereby enabling the multilayer chip inductor to meet the electrical requirements during use.

[0011] In some embodiments of the present invention, the total length of the terminal electrodes along the length direction of the multilayer chip inductor is a value within the range of 30%, 40%, 50%, 60%, 70%, 80% or any combination thereof of the length (i.e., l / L) of the multilayer chip inductor. In some preferred embodiments of the present invention, the total length of the terminal electrodes along the length direction of the multilayer chip inductor is 40-60% of the length of the multilayer chip inductor.

[0012] In some embodiments of the present invention, such as Figure 2As shown in the structural schematic diagram, the width (i.e., w) of the terminal electrode along the width direction of the multilayer chip inductor accounts for 20-100% of the total width (i.e., w / W = 20-100%) of the multilayer chip inductor. In some embodiments of the present invention, the width of the terminal electrode along the width direction of the multilayer chip inductor accounts for any value or a range formed by any two of 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, and 100% of the total width of the multilayer chip inductor. In some preferred embodiments of the present invention, the width of the terminal electrode along the width direction of the multilayer chip inductor accounts for 30-50% of the total width of the multilayer chip inductor.

[0013] In some embodiments of the present invention, such as Figure 2 As shown in the structural diagram, the height (i.e., t) of the terminal electrode along the height direction of the multilayer chip inductor accounts for 50-100% of the total height (i.e., t / T = 50-100%) of the multilayer chip inductor. In some embodiments of the present invention, the height of the terminal electrode along the height direction of the multilayer chip inductor accounts for any value or a range formed by any two of 50%, 60%, 70%, 80%, 90%, and 100% of the total height of the multilayer chip inductor. In some preferred embodiments of the present invention, the height of the terminal electrode along the height direction of the multilayer chip inductor accounts for 60-100% of the total height of the multilayer chip inductor. In this invention, the height direction of the multilayer chip inductor refers to the stacking direction of the multilayer chip inductor; the length direction refers to the direction of the side of the multilayer chip inductor with the larger length perpendicular to the height direction, i.e. (LT side, L is the length, T is the height); the width direction refers to the direction of the side of the multilayer chip inductor with the smaller length perpendicular to the height direction (i.e., WT side, W is the width, T is the height), and the angle between the length direction and the width direction is approximately 90°.

[0014] After the terminal electrodes are plated with nickel and tin and soldered onto the circuit board, they need to have a good contact area with the external circuit, so their area should be as large as possible. Generally, only one side of the terminal electrode contacts the contact point on the circuit during soldering, namely the LT side of the terminal electrode (front view, a side along the length of the inductor, which exposes both external electrodes simultaneously). Therefore, the area of ​​the terminal electrode on the LT side needs to be as large as possible, for example, t / T > 60%, l / L > 40%. However, connecting the two ends of the terminal electrodes will cause a short circuit, so the electrodes cannot be connected along the length plane, i.e., l / L < 100%. A certain safety distance needs to be left in the design, for example, l / L of 40-60%. The area of ​​the terminal electrode on the WT side does not need to be too large, as this side has few contact scenarios with the circuit, and its area can be reduced to save silver paste. In some embodiments of the present invention, the inductor printed sheet further includes ≥0 printed sheets A; in some embodiments of the present invention, the inductor printed sheet further includes ≥1 printed sheet A; in some embodiments of the present invention, the inductor printed sheet further includes ≥2 printed sheets A; in some embodiments of the present invention, the inductor printed sheet further includes 0-18 printed sheets A; in some embodiments of the present invention, the inductor printed sheet further includes 4-18 printed sheets A. The purpose of the printed sheets A is to ensure that the thickness of the terminal electrode is sufficient. If the number of printed sheets B, C, and D is sufficient and the terminal electrode can achieve the required thickness, then printed sheets A are not required.

[0015] In some embodiments of the present invention, the printed wafer A includes a ceramic dielectric layer and an end electrode layer disposed on the ceramic dielectric layer.

[0016] In some embodiments of the present invention, the end electrodes in printed wafer A, printed wafer B, and printed wafer D are made of silver paste m. The silver paste m contains 0.2-2.5% glass powder by mass. Since the end electrodes are in large-area contact with the ceramic dielectric layer, sufficient glass material is required to ensure sintering performance and thus prevent cracking.

[0017] In some embodiments of the present invention, the mass percentage of glass powder in the silver paste m is any value or a range formed by any two of the following: 0.2%, 0.4%, 0.5%, 0.6%, 0.8%, 1.0%, 1.2%, 1.4%, 1.5%, 1.6%, 1.8%, 2.0%, 2.2%, 2.4%, and 2.5%. In some preferred embodiments of the present invention, the silver paste m contains 0.5-2% glass powder by mass; in some preferred embodiments of the present invention, the silver paste m contains 0.5-2% but not 0.5% glass powder by mass; in some preferred embodiments of the present invention, the silver paste m contains 1-1.5% glass powder by mass.

[0018] In some embodiments of the present invention, the silver paste m comprises the following components by mass percentage: 0.2-2.5% glass powder, 83-85.5% silver powder, 10-15% additives, and 1-5% solvent.

[0019] In some embodiments of the present invention, the mass percentage of silver powder in the silver paste m is 83-85.3%; in some embodiments of the present invention, the mass percentage of silver powder m in the silver paste m is 83.5-85%.

[0020] In some embodiments of the present invention, based on the total mass percentage of silver paste m as 100%, the additives include the following components by mass percentage: initiator 0.1-1%, resin 8-14%, and dispersant 0.1-1%.

[0021] In some embodiments of the present invention, the through-hole electrode in the printed wafer B, the end electrode in the printed wafer C, the internal electrode in the printed wafer C, and the internal electrode in the printed wafer D are made of silver paste n; the silver paste n contains 0-0.7% glass powder by mass. Since the internal electrode and the through-hole electrode are located inside the inductor and have a small contact area with the ceramic dielectric layer, the risk of cracking is low. Therefore, both the internal electrode and the through-hole electrode use a small amount of glass component to avoid excessive glass component affecting the conductivity of the electrode.

[0022] In some embodiments of the present invention, the mass percentage of glass powder in the silver paste n is any value or a range formed by any combination of 0%, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, and 0.7%. In some preferred embodiments of the present invention, the silver paste n contains 0.1-0.5% glass powder by mass. In some preferred embodiments of the present invention, the silver paste n contains 0.2-0.3% glass powder by mass.

[0023] In some embodiments of the present invention, the silver paste n comprises the following components by mass percentage: 0-0.7% glass powder, 83-85.5% silver powder, 10-15% additives, and 1-5% solvent.

[0024] In some embodiments of the present invention, the mass percentage of silver powder in the silver paste n is 83-85.3%; in some embodiments of the present invention, the mass percentage of silver powder n in the silver paste n is 83.5-85%.

[0025] In some embodiments of the present invention, based on the total mass percentage of silver paste n as 100%, the additives include the following components by mass percentage: initiator 0.1-1%, resin 8-14%, and dispersant 0.1-1%.

[0026] This invention regulates the glass component content in the internal and terminal electrodes of a ceramic inductor by limiting the glass powder content in silver paste n and silver paste m, thereby improving the inductor's cracking caused by sintering. In printed wafer C, both the internal electrode layer and the terminal electrode layer are prepared using silver paste n. If the glass powder content in silver paste n is too low, the risk of cracking during sintering increases, as do the risks of inter-electrode delamination and cracking between the ceramic layer and the internal electrode layer. If the glass powder content in silver paste n is too high, the smoothness and resolution of the internal electrode layer will be affected, thus affecting the electrical performance. In printed wafer D, the internal electrode layer is prepared using silver paste n. If the glass component content (i.e., the glass powder in silver paste n) in the internal electrode layer is too low, it is prone to inter-electrode cracking between the internal electrode layer and the ceramic dielectric layer. If the glass component content (i.e., the glass powder in silver paste n) in the internal electrode layer is too high, the smoothness and resolution of the internal electrode layer will be affected, thus affecting the electrical performance. The terminal electrode is prepared using silver paste m. If the content of glass component (i.e. glass powder in silver paste m) in the terminal electrode layer is too low, it will cause cracking between the terminal electrode layer and the ceramic dielectric layer, which will then cause the terminal electrode layer to fall off. If the content of glass component (i.e. glass powder in silver paste m) in the terminal electrode layer is too high, it will cause the glass to float during sintering, and nickel and tin cannot be plated during electroplating.

[0027] In this invention, when the inner electrode layer and the terminal electrode layer are electrically connected, the glass component content in both the inner and terminal electrode layers is the same; when the inner and terminal electrode layers are not connected, the glass component content in the inner electrode layer is less than that in the terminal electrode layer. The reason for this arrangement is that silver paste m has good adhesion to the ceramic dielectric layer, preventing cracking during sintering, but silver paste m has poor electrical properties. Silver paste n has moderate adhesion to the ceramic dielectric layer, but silver paste n has excellent electrical properties. If both the inner and terminal electrode layers use silver paste m, cracking between the silver layer and the ceramic will not occur during sintering, but the resulting product will have poor electrical properties, reflected in the DC resistance (R). dc The increase in inductance (L value) and instability. If both the inner electrode layer and the terminal electrode layer use silver paste n, the excessive difference in shrinkage between the ceramic dielectric layer and the silver paste during sintering will lead to cracking.

[0028] In multilayer chip inductors, the bonding area between the terminal electrode layer and the ceramic dielectric layer is large, requiring the use of silver paste m to ensure that the terminal electrode layer does not detach after sintering. The inner electrode layer needs good flatness to ensure the accuracy and stability of the inductance value L, requiring the use of silver paste n. In multilayer chip inductor designs, there are generally dozens of inner electrode layers, which are not connected to the terminal electrode layers. There are only two lead-in / lead-out layers, whose inner electrode layers are connected to the terminal electrode layers. Even if these two layers use silver paste m, the impact on the overall electrical performance is minimal. However, because the inner electrode layers and terminal electrode layers use the same silver paste formulation, they do not need to be printed in multiple stages but can be printed in one step, improving overall integrity and avoiding the problem of inconsistent conductivity due to different types of silver paste at the connection points. Using the same high-glass-content silver paste m for the inner electrode layers and terminal electrode layers in both the lead-in and lead-out layers ensures electrical performance while requiring only a single printing step, improving production efficiency and resulting in better overall performance.

[0029] In some embodiments of the present invention, the glass powder in the silver paste m comprises the following components by mass percentage: 45-65wt% Bi2O3, 20-30wt% B2O3, 10-14wt% SiO2, 3-7wt% ZnO, 1.5-2.5wt% Al2O3, and 0.5-1.5wt% Li2O.

[0030] In some embodiments of the present invention, the glass powder in the silver paste n comprises the following components by mass percentage: 45-65 wt% Bi₂O₃, 20-30 wt% B₂O₃, 10-14 wt% SiO₂, 3-7 wt% ZnO, 1.5-2.5 wt% Al₂O₃, and 0.5-1.5 wt% Li₂O. The glass powder in the present invention increases the sintering temperature of the inner electrode, end electrode, and through-hole electrode, and enhances the affinity and bonding strength between the electrodes (i.e., the inner electrode, end electrode, and through-hole electrode) and the ceramic dielectric layer.

[0031] In this invention, the glass powder in silver paste m and silver paste n has a composition similar to that of the ceramic dielectric layer, resulting in better compatibility during sintering. Since the main components of the yellow ceramic dielectric layer include silicon dioxide and alumina, with silicon dioxide accounting for more than 40%, this invention selects glass powder containing silicon dioxide.

[0032] In some embodiments of the present invention, the ceramic dielectric layers in printed sheets A, B, C, and D may be the same, different, or partially the same.

[0033] In some embodiments of the present invention, the ceramic dielectric layer is composed of 40-50% by mass of alumina and 50-60% by mass of silicon dioxide.

[0034] In some embodiments of the present invention, the material of the ceramic dielectric layer is alumina.

[0035] In this invention, during the sintering process of the multilayer chip inductor, glass powder softens and fills the gaps between silver particles. The softened glass powder homogenizes the mass transfer process between silver and ceramic during sintering, resulting in more uniform grain size. During sintering, silver reaches its sintering temperature prematurely and shrinks. The glass powder increases the affinity between silver and ceramic, thus preventing cracking. Simultaneously, the glass powder slightly raises the sintering temperature of silver, reducing the temperature difference between silver and ceramic shrinkage, which also helps alleviate sintering cracking. This invention, by controlling the glass powder content in the silver paste of the inner and terminal electrodes in the inductor printed circuit board, prevents the more prone-to-cracking terminal electrodes from cracking during sintering, achieving better affinity with the ceramic dielectric layer, while maintaining the resolution and electrical performance of the inner electrodes.

[0036] In some embodiments of the present invention, the stacking order of printed sheets A, B, C, and D is as follows: n1 printed sheets A, C, m printed sheets stacked, B, C, and n2 printed sheets A; n1 and n2 are each independently selected from integers 1-17, and m is an integer from 1-15. The stacking structure consists of printed sheets B and D stacked sequentially, with one printed sheet D placed between two adjacent printed sheets B. That is, when m is 8, the stacking is performed in the order of A×n1-CBDBDBDBDBDBDBDBDBCA×n2. The number of printed sheets A, n1 and n2, changes with the ratio of the height of the terminal electrode to the height of the entire stacked chip inductor (i.e., t / T). For example, when t / T = 60%, n1 = 2 and n2 = 2; when t / T = 100%, n1 = 9 and n2 = 9. The structural diagrams of printed sheet A, printed sheet B, printed sheet C and printed sheet D are shown below. Figure 3 As shown, Figure 3 (a), (b), (c), and (d) in the diagram correspond to printed sheet A, printed sheet B, printed sheet C, and printed sheet D, respectively.

[0037] In some embodiments of the present invention, the multilayer chip inductor further comprises at least two dielectric layers. The dielectric layers do not include terminal electrode layers.

[0038] In some embodiments of the present invention, the stacking order of the multilayer chip inductor is as follows: k1 dielectric layers (i.e., dielectric layers K, the quantity of which is denoted as k1), n1 printed wafers A, printed wafer C, m printed wafers stacked together, printed wafer B, printed wafer C, n2 printed wafers A, k2 dielectric layers (i.e., dielectric layers K, the quantity of which is denoted as k2); n1 and n2 are each independently selected from integers 1-17, m is an integer from 1-15, k1 and k2 are each independently selected from integers 1-15, and the printed wafer stacking structure consists of printed wafers B and D stacked sequentially, with one printed wafer D placed between two adjacent printed wafers B. When the value of m is 8, the schematic diagram of the stacking structure of the multilayer chip inductor is shown below. Figure 4 As shown, the structural diagram of the dielectric layer K and the inductor printed circuit board used in its stacking is as follows: Figure 5 As shown, Figure 4 and Figure 5 In this context, K refers to the dielectric layer K, A refers to the printed wafer A, B1 and B2 refer to two printed wafers B with different via electrode positions, C1 and C2 refer to two printed wafers C with different conductive circuits (i.e., different conductive circuits in the inner electrode layer), and D1 and D2 refer to two printed wafers D with different conductive circuits (i.e., different conductive circuits in the inner electrode layer).

[0039] In some embodiments of the present invention, the total height of the multilayer chip inductor is 350-370 μm. In some embodiments of the present invention, the number of printed wafers B is one more than the number of printed wafers D.

[0040] In some embodiments of the present invention, the number of printed sheets D is an integer from 6 to 10.

[0041] The second aspect of the present invention provides a method for fabricating the multilayer chip inductor described in the first aspect of the present invention, comprising the following steps: S1: Coat the ceramic dielectric layer with photosensitive ceramic paste, expose and develop after masking to obtain a ceramic substrate; S2: Depending on the type of inductor printed sheet, photosensitive silver paste for preparing the inner electrode layer, end electrode layer or through-hole electrode layer is coated on the ceramic substrate, and after masking, exposure and development are performed to obtain the inductor printed sheet. S3: The inductor printed sheets are stacked, pressed together, and then sintered to obtain the multilayer chip inductor.

[0042] In some embodiments of the present invention, the masks in S1 and S2 are both created using mask plates. The patterns on the mask plates used in S1 and S2 are different.

[0043] In some embodiments of the present invention, the exposure in S1 and S2 is performed using ultraviolet light.

[0044] In some embodiments of the present invention, the development in S1 and S2 is performed using a developing solution. After development in S1, local grooves are formed on the ceramic substrate to facilitate the coating of photosensitive silver paste in S2.

[0045] In some embodiments of the present invention, the coating in S1 is performed by at least one of printing, roller coating, spraying, and scraping.

[0046] In some embodiments of the present invention, the coating in S2 is performed by at least one of printing, roller coating, spraying, and scraping.

[0047] In some embodiments of the present invention, the sintering temperature is 800-860°C; in some embodiments of the present invention, the sintering temperature is any value of 800°C, 810°C, 820°C, 830°C, 840°C, 850°C, 860°C, or a range formed by any two of them.

[0048] In some embodiments of the present invention, the holding time for sintering is 60-90 min; in some embodiments of the present invention, the holding time for sintering is any value of 60 min, 70 min, 80 min, 90 min, or a range formed by any two of them.

[0049] In some embodiments of the present invention, the sintering atmosphere is an air atmosphere or an oxygen-containing atmosphere. The oxygen-containing atmosphere includes oxygen and at least one gas selected from nitrogen, argon, and helium.

[0050] A third aspect of the present invention provides an electronic device including the multilayer chip inductor described in the first aspect of the present invention.

[0051] The beneficial effects of the present invention are as follows: By making the glass component content of the inner electrode and the end electrode in the printed wafer C the same, and the glass component content of the inner electrode in the printed wafer D is less than the glass component content of the end electrode, the present invention can ensure the electrical performance and the resolution of the electrode after sintering; on the other hand, it can reduce or even avoid the cracking of the multilayer chip inductor during sintering.

[0052] Furthermore, by adjusting the size parameters of the terminal electrodes and the glass powder content in silver paste m and silver paste n, the present invention enables the fabricated multilayer chip inductor to achieve a test pass rate ≥98%, a quality factor Q>14, a DC resistance <950 mΩ, and no cracks or a crack length <5μm. Attached Figure Description

[0053] Figure 1 This is an exploded view of the multilayer chip inductor in this invention.

[0054] Figure 2 These are the front view, left view, and top view of the multilayer chip inductor in this invention.

[0055] Figure 3 This is a schematic diagram of the structure of printing sheet A, printing sheet B, printing sheet C, and printing sheet D in this invention.

[0056] Figure 4 This is a schematic diagram of the stacked structure of the multilayer chip inductor in this invention.

[0057] Figure 5 This is a schematic diagram of the dielectric layer K and the inductor printed sheet in this invention. Detailed Implementation

[0058] The specific implementation of the present invention will be further described in detail below with reference to the accompanying drawings and examples, but the implementation and protection of the present invention are not limited thereto. It should be noted that any processes not specifically described in detail below are those that can be implemented or understood by those skilled in the art by referring to the prior art. Reagents or instruments used without specified manufacturers are all conventional products that can be purchased commercially.

[0059] Example 1 Reference Figure 1-5 This example provides a multilayer chip inductor, which is composed of 30 inductor printed chips and 7 dielectric layers K stacked together; the multilayer chip inductor contains two symmetrically arranged terminal electrodes. In the front view (LT plane, L is length, T is height) of the multilayer chip inductor, the total length of the two terminal electrodes is denoted as l, and the length of the multilayer chip inductor is denoted as L. The ratio between the total length of the two terminal electrodes and the length of the multilayer chip inductor is l / L = 50%. The total height of the terminal electrodes is denoted as t, and the height of the multilayer chip inductor is denoted as T. The ratio between the total height of the terminal electrodes and the height of the multilayer chip inductor is t / T = 80%. In the left view (WT plane, W is width, T is height) and top view (LW plane, L is length, W is width) of the multilayer chip inductor, the total width of the terminal electrodes is denoted as w, and the total width of the multilayer chip inductor is denoted as W. The ratio between the total width of the terminal electrodes and the total width of the multilayer chip inductor is w / W = 40%, as shown in Table 1 below.

[0060] Inductor printed circuit boards are divided into four categories: printed circuit board A, printed circuit board B, printed circuit board C, and printed circuit board D.

[0061] Among them, printed chip A is composed of a ceramic dielectric layer and a terminal electrode layer disposed on the ceramic dielectric layer; the total number of layers of printed chip A in the multilayer chip inductor is 11 layers, and the thickness of each single layer of printed chip A is 10μm; the terminal electrode layer in printed chip A is printed with silver paste. Printed chip B consists of a ceramic dielectric layer and terminal electrode layers and via electrode layers disposed on the ceramic dielectric layer; the total number of printed chip B layers in the multilayer chip inductor is 9, and the thickness of each printed chip B layer is 8.5 μm; the terminal electrode layers in printed chip B are printed with silver paste m, and the via electrode layers are printed with silver paste n. The printed chip C consists of a ceramic dielectric layer and an end electrode layer and an inner electrode layer disposed on the ceramic dielectric layer. The inner electrode layer is connected to one of the end electrode layers. The total number of layers of the printed chip C in the multilayer chip inductor is 2, and the thickness of each single layer of the printed chip C is 10 μm. The end electrode layer and the inner electrode layer in the printed chip C are both printed with silver paste n, which contains glass powder. The content of glass powder in the inner electrode layer and the end electrode layer is the same. The printed chip D consists of a ceramic dielectric layer and an end electrode layer and an inner electrode layer disposed on the ceramic dielectric layer. The inner electrode layer and the end electrode layer are not connected. The total number of layers of the printed chip D in the multilayer chip inductor is 8, and the thickness of each single layer of the printed chip D is 10 μm. The end electrode layer in the printed chip D is printed with silver paste m, and the inner electrode layer is printed with silver paste n. Both silver paste n and silver paste m contain glass powder. The glass powder content in the inner electrode layer is less than that in the end electrode layer. The ceramic dielectric layer in printed sheets A, B, C, and D is made of alumina.

[0062] Based on the structure of multilayer chip inductors, printed circuit board B is divided into B1 and B2 due to the different positions of the through-hole electrodes; printed circuit board C is divided into C1 and C2 due to the different conductive circuits in the inner electrode layer; and printed circuit board D is divided into D1 and D2 due to the different conductive circuits in the inner electrode layer. The multilayer chip inductor in this example can be classified as follows: Figure 4 The stacking method is used to stack the layers.

[0063] Among them, the dielectric layer K is a ceramic dielectric layer (without electrodes), with a thickness of 10μm and 7 layers; All the terminal electrode layers in the inductor printed circuit board are stacked together to form two terminal electrodes.

[0064] In this example, printed wafers A, B, C, and D all contain terminal electrode layers, and the ratio of the total height of the terminal electrodes to the height of the multilayer chip inductor, t / T, is 80%. Therefore, in this example, the top and bottom layers of the multilayer chip inductor (i.e., the two outermost layers in the stacking direction of the inductor printed wafers) need to have blank ceramic dielectric layers (i.e., dielectric layer K, with a thickness of approximately 10 μm) without terminal electrode layers to ensure t / T = 80%. If the ratio of the total height of the terminal electrodes to the height of the multilayer chip inductor, t / T, is 100%, then there is no need to set a blank ceramic dielectric layer, and the blank ceramic dielectric layer does not contain terminal electrode layers.

[0065] The stacking sequence of the multilayer chip inductor in this example is as follows: 3 dielectric layers K, 6 printed wafers A, printed wafer C, 8 printed wafers stacked, printed wafer B, printed wafer C, 5 printed wafers A, and 4 dielectric layers K are stacked in sequence.

[0066] The 8-layer printed sheet stack structure is obtained by repeating the stacking of printed sheet B1, printed sheet D1, printed sheet B2, and printed sheet D2 in four cycles, as shown in the details. Figure 4 As shown.

[0067] Silver paste M is composed of the following components by weight percentage: 84.3 wt% silver powder, 1.2 wt% glass powder, 10 wt% polymethyl methacrylate (PMMA) resin, 0.5 wt% initiator (phosphine triphenyloxide), 0.5 wt% dispersant (polyvinyl alcohol), and 3.5 wt% solvent (diethylene glycol butyl ether). Silver paste n is composed of the following components by mass percentage: 85.25 wt% silver powder, 0.25 wt% glass powder, 10 wt% polymethyl methacrylate (PMMA) resin, 0.5 wt% initiator (triphenylphosphine oxide), 0.5 wt% dispersant (polyvinyl alcohol), and 3.5 wt% solvent (diethylene glycol butyl ether). In both silver paste m and silver paste n, the glass powder is composed of the following components by mass percentage: 55wt% Bi2O3, 25wt% B2O3, 12wt% SiO2, 5wt% ZnO, 2wt% Al2O3, and 1wt% Li2O.

[0068] The multilayer chip inductor in this example can be fabricated using a method that includes the following steps.

[0069] S1: Print a layer of photosensitive ceramic paste onto the ceramic dielectric layer; The photosensitive ceramic paste is composed of the following components by weight percentage: 55wt% glass ceramic powder (Si-Al system), 20wt% photosensitive resin (composed of 17wt% acrylate and 3wt% photoinitiator), 24wt% solvent (terpineol), and 1wt% dispersant (polyvinyl alcohol).

[0070] S2: A mask with a specific pattern is laid on the photosensitive ceramic paste, and ultraviolet light is used to expose the photosensitive ceramic paste, so that the exposed part of the ceramic is solidified to form a ceramic layer; S3: Remove the mask and wash away the remaining uncured ceramic layer with developer. The washed-away areas will form localized grooves. S4: Print a layer of photosensitive silver paste (silver paste n or silver paste m) on the ceramic layer after it has been cured in step S3. After the photosensitive silver paste flows and fills the groove, lay another mask with a specific pattern on the silver layer. Expose the photosensitive silver paste with ultraviolet light so that the exposed part of the silver paste is cured to form an electrode. Coat the photosensitive silver paste according to the type of inductor printed sheet and the type of photosensitive silver paste used. S5: Remove the mask and wash away the remaining uncured silver paste with developer to obtain the inductor printed film.

[0071] S6: After a specific yellow light photosensitive design, the corresponding inductor printed sheets are stacked in sequence into a laminate, and then pressed and cut into yellow light ceramic green bodies; S7: The yellow ceramic green body is sintered in air at a temperature of 840℃ for 80 minutes to obtain the multilayer chip inductor in this example.

[0072] Examples 2-5 The only difference between the multilayer chip inductors in Examples 2-5 and those in Example 1 is the t / T ratio, as shown in Table 1.

[0073] Examples 6-9 The only difference between the multilayer chip inductors in Examples 6-9 and the multilayer chip inductors in Example 1 is that the l / L ratio is different, as shown in Table 1.

[0074] Examples 10-13 The only difference between the multilayer chip inductors in Examples 10-13 and the multilayer chip inductors in Example 1 is the w / W ratio, as shown in Table 1.

[0075] Example 14 The only difference between the multilayer chip inductor in this example and the multilayer chip inductor in Example 1 is that the t / T ratio is different, as shown in Table 1.

[0076] The number of dielectric layers K, printed wafers A, B, C, and D used in the stacked chip inductors of Examples 1-5 and Example 14 is shown in Table 2 below.

[0077] Example 15 The only difference between the multilayer chip inductor in this example and the multilayer chip inductor in Example 1 is the l / L ratio, as shown in Table 1.

[0078] Examples 16-18 The only difference between the multilayer chip inductors in Examples 16-18 and the multilayer chip inductors in Example 1 is the w / W ratio, as shown in Table 1.

[0079] Example 19 The only difference between the multilayer chip inductor in this example and the multilayer chip inductor in Example 1 is the l / L ratio, as shown in Table 1.

[0080] Examples 20-23 The difference between the multilayer chip inductors and their preparation methods in Examples 20-23 and Example 1 is only that the mass percentages of glass powder and silver powder in the silver paste m are different from those in Example 1, as shown in Table 3 below.

[0081] Examples 24-27 The only difference between the multilayer chip inductors and their preparation methods in Examples 24-27 and Example 1 is that the mass percentages of glass powder and silver powder in the silver paste n are different from those in Example 1, as shown in Table 3 below.

[0082] Examples 28-29 The only difference between the multilayer chip inductors and their preparation methods in Examples 28-29 and Example 1 is that the mass percentages of glass powder and silver powder in the silver paste m are different from those in Example 1, as shown in Table 3 below.

[0083] Examples 30-31 The only difference between the multilayer chip inductors and their preparation methods in Examples 30-31 and Example 1 is that the mass percentages of glass powder and silver powder in the silver paste n are different from those in Example 1, as shown in Table 3 below.

[0084] Comparative Example 1 The only difference between the multilayer chip inductor in this example and the multilayer chip inductor in Example 1 is the l / L ratio, as shown in Table 1.

[0085] Comparative Example 2 The only difference between the multilayer chip inductor in this example and that in Example 1 is that the total number of layers of the printed chip C is 1.

[0086] Comparative Example 3 The only difference between the multilayer chip inductor in this example and that in Example 1 is that the inner electrode layer and the terminal electrode layer are not connected in the printed chip C in this example.

[0087] Comparative Example 4 The only difference between the multilayer chip inductor in this example and that in Example 1 is that in the printed chip C in this example, the inner electrode is printed with silver paste m (the same as silver paste m in Example 1), and the terminal electrode is printed with silver paste n (the same as silver paste n in Example 1). That is, the glass powder content in the inner electrode is greater than the glass powder content in the terminal electrode.

[0088] Comparative Example 5 The only difference between the multilayer chip inductor in this example and that in Example 1 is that the terminal electrodes in the printed chip D are printed using silver paste n as in Example 1, and the inner electrodes are printed using silver paste m as in Example 1. That is, the glass powder content in the inner electrodes is greater than the glass powder content in the terminal electrodes.

[0089] Comparative Example 6 The only difference between the multilayer chip inductor in this example and that in Example 1 is that the inner electrode layer and the terminal electrode layer are connected in the printed chip D.

[0090] Table 1. Dimensional parameters of the end electrodes

[0091] Table 2 Number of layers in dielectric layer and inductor printed circuit board

[0092] Table 3. Content of glass powder and silver powder in silver paste m and silver paste n

[0093] The types and contents of the remaining components in silver paste m in Table 3 are the same as those in silver paste m in Example 1, and the types and contents of the remaining components in silver paste n are the same as those in silver paste n in Example 1.

[0094] Performance testing: The inductance value L, quality factor Q, DC resistance RDC, test yield and sintering morphology of the multilayer chip inductors in Examples 1-31 and Comparative Examples 1-6 were tested according to the test items, test instruments and test methods recorded in Table 4 below.

[0095] Table 4 Test Items, Test Instruments and Test Methods

[0096] The performance data of the multilayer chip inductors in Examples 1-19 and Comparative Example 1, measured according to the test methods in Table 4, are shown in Table 5 below. The performance data of the multilayer chip inductors in Examples 20-31 and Comparative Examples 2-6 are shown in Table 6 below.

[0097] Table 5 Performance test results of the multilayer chip inductors in Examples 1-19 and Comparative Example 1

[0098] In Table 5, "-" indicates that it cannot be measured.

[0099] As shown in Table 5, by adjusting the length, width, and height of the terminal electrodes, the multilayer chip inductors manufactured in Examples 1-19 of the present invention achieve a test pass rate of 86.32-99.95%, a quality factor Q of 16.32-19.64, a DC resistance of 423-501 mΩ, and a crack size of 0 μm. Therefore, the multilayer chip inductors in Examples 1-19 of the present invention have better performance than those in Comparative Example 1. Among them, Examples 1-13 further improve the performance of the multilayer chip inductors by further optimizing the size parameters of the terminal electrodes.

[0100] Table 6 shows the performance test results of the multilayer chip inductors in Examples 20-31 and Comparative Examples 2-6.

[0101] As shown in Table 6, by adjusting the glass powder content in silver paste m and silver paste n, the multilayer chip inductors prepared in Examples 1 and 20-31 of the present invention exhibit superior test pass rate, quality factor, and DC resistance, while further reducing the degree of cracking. In particular, Examples 20-27, by further optimizing the glass powder content in silver paste m and silver paste n, achieve a test pass rate of 98.21-99.88%, a quality factor Q of 14.36-26.33, a DC resistance of 320-750 mΩ, and a crack size ≤1μm, demonstrating superior performance across the board.

[0102] The embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A multilayer chip inductor, comprising terminal electrodes, characterized in that: The total length of the terminal electrodes along the length direction of the multilayer chip inductor accounts for 30-80% of the length of the multilayer chip inductor; The multilayer chip inductor includes stacked inductor printed chips; the inductor printed chips include at least one printed chip B, at least two printed chips C and at least one printed chip D; The printed wafer B includes a ceramic dielectric layer and a terminal electrode layer and a through-hole electrode layer disposed on the ceramic dielectric layer; The printed wafer C includes a ceramic dielectric layer and an end electrode layer and an inner electrode layer disposed on the ceramic dielectric layer; in the printed wafer C, the inner electrode layer and the end electrode layer are electrically connected, and both the inner electrode layer and the end electrode layer contain glass components, and the content of glass components in the inner electrode layer and the end electrode layer is the same; The printed wafer D includes a ceramic dielectric layer and an end electrode layer and an inner electrode layer disposed on the ceramic dielectric layer; in the printed wafer D, the inner electrode layer and the end electrode layer are not connected, and both the inner electrode layer and the end electrode layer contain glass components, wherein the content of glass components in the inner electrode layer is less than the content of glass components in the end electrode layer.

2. The multilayer chip inductor according to claim 1, characterized in that: The inductor printed sheet also contains ≥1 printed sheet A; preferably, the printed sheet A includes a ceramic dielectric layer and a terminal electrode layer disposed on the ceramic dielectric layer.

3. The multilayer chip inductor according to claim 2, characterized in that: The terminal electrode layer in printed sheet A, the terminal electrode layer in printed sheet B, and the terminal electrode layer in printed sheet D are made of silver paste m; the silver paste m contains 0.2-2.5% glass powder by mass; preferably, the silver paste m contains 0.5-2% glass powder by mass.

4. The multilayer chip inductor according to claim 2, characterized in that: The through-hole electrode layer in the printed sheet B, the end electrode layer in the printed sheet C, the inner electrode layer in the printed sheet C, and the inner electrode layer in the printed sheet D are made of silver paste n; the silver paste n contains 0-0.7% glass powder by mass; preferably, the silver paste n contains 0.1-0.5% glass powder by mass.

5. The multilayer chip inductor according to claim 3 or 4, characterized in that: In the photosensitive silver paste m and the photosensitive silver paste n, the glass powder comprises the following components by mass percentage: 45-65wt% Bi2O3, 20-30wt% B2O3, 10-14wt% SiO2, 3-7wt% ZnO, 1.5-2.5wt% Al2O3, and 0.5-1.5wt% Li2O.

6. The multilayer chip inductor according to claim 1, characterized in that: The width of the terminal electrode along the width direction of the multilayer chip inductor accounts for 20-100% of the total width of the multilayer chip inductor; preferably, the width of the terminal electrode along the width direction of the multilayer chip inductor accounts for 30-50% of the total width of the multilayer chip inductor.

7. The multilayer chip inductor according to claim 1, characterized in that: The height of the terminal electrode along the height direction of the multilayer chip inductor accounts for 50-100% of the total height of the multilayer chip inductor; preferably, the height of the terminal electrode along the height direction of the multilayer chip inductor accounts for 60-100% of the total height of the multilayer chip inductor.

8. The method for fabricating the multilayer chip inductor according to any one of claims 1-7, characterized in that: Includes the following steps: S1: Coat the ceramic dielectric layer with photosensitive ceramic paste, expose and develop after masking to obtain a ceramic substrate; S2: Depending on the type of inductor printed sheet, photosensitive silver paste for preparing the inner electrode layer, end electrode layer or through-hole electrode layer is coated on the ceramic substrate, and after masking, exposure and development are performed to obtain the inductor printed sheet. S3: The inductor printed sheets are stacked, pressed together, and then sintered to obtain the multilayer chip inductor.

9. The method for fabricating a multilayer chip inductor according to claim 8, characterized in that: The sintering temperature is 800-860℃; And / or, the holding time for sintering is 60-90 min.

10. An electronic device, characterized in that: Including the multilayer chip inductor as described in any one of claims 1-7.

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