A digital predictive zero-current switching control circuit and control method

Abstract

The application discloses a digital predictive zero-current switch control circuit and a control method, and belongs to the technical field of power supply control and integrated circuits. The circuit comprises an analog front-end detection circuit, a digital core circuit, a logic control circuit and a gate drive circuit. The low-power analog front end is used for rough detection with an advance amount, and then linear compensation with nanosecond accuracy is carried out through a programmable digital delay line. The PWM state signal is subjected to logic operation, so as to drive the synchronous rectifier to be turned off at the accurate moment when the inductor current is zero, and the problems of hysteresis and noise sensitivity of pure event-driven logic are overcome.

Description

Technical Field

[0001] This application belongs to the field of power control and integrated circuit technology, and particularly relates to a digital predictive zero-current switching control circuit and control method. Background Technology

[0002] With the popularization of IoT technology, the "burst transmission, long-term monitoring" characteristics of IoT chips pose a key challenge to energy efficiency across the entire load range and improving conversion efficiency under light load conditions. In light load mode, the BUCK usually operates in discontinuous conduction mode (DCM). At this time, zero-current switching (ZCS) technology is needed to accurately turn off the synchronous rectifier (NM) at the moment the inductor current crosses zero to prevent inductor current backflow or excessive conduction of the body diode.

[0003] Existing ZCS schemes mostly employ analog real-time detection architectures based on high-speed comparators (such as the real-time comparator scheme of K.-C. Woo, J.-M. Oh, and B.-D. Yang, "DC-DC buck converter using analog coarse-fineself-tracking zero-current detection scheme," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 11, pp. 1850–1854, Nov. 2019, doi:10.1109 / TCSII.2018.2890267) Woo et al.'s scheme has an inherent drawback: a fundamental "bandwidth-power consumption contradiction." This scheme has the following significant shortcomings: (1) The inherent contradiction between propagation delay and power consumption: In order to improve detection accuracy, analog comparators require extremely high bandwidth and bias current, which significantly increases the static power consumption of the system; while low-power comparators are often accompanied by large propagation delay, resulting in turn-off lag.

[0004] (2) Severely affected by PVT variations: The delay characteristics of analog devices are highly sensitive to changes in process, voltage, and temperature. Under actual operating conditions, the drift of analog delay can cause the turn-off point to deviate from zero, resulting in inductor reverse current (turn-off too late) or body diode conduction loss (turn-off too early), which severely restricts the light-load efficiency and reliability of the converter. Summary of the Invention

[0005] The purpose of this application is to overcome the shortcomings of the prior art by providing a digital predictive zero-current switching control circuit and control method, which can decouple detection accuracy and response speed and automatically compensate for system delay deviation.

[0006] The objective of this application is achieved through the following technical solution: A digital predictive zero-current switching control circuit, applied to a Buck converter, the circuit comprising: An analog front-end detection circuit is connected to the switching node of the Buck converter to monitor the voltage of the switching node. When the voltage of the switching node exceeds a preset threshold, a trigger signal with a time advance is output. The digital core circuit includes a delay compensation circuit and a PWM master control circuit. The delay compensation circuit is connected to the output of the analog front-end detection circuit to apply programmable delay compensation to the trigger signal. The PWM master control circuit outputs a PWM master control status signal. A logic control circuit is connected to the output terminals of the delay compensation circuit and the PWM main control circuit to perform logical operations on the delayed trigger signal and the PWM main control status signal to generate a synchronous rectifier tube turn-off signal. A gate driving circuit, which is connected to the logic control circuit, receives the synchronous rectifier turn-off signal to control the turn-off of the synchronous rectifier.

[0007] Furthermore, the switch control circuit also includes a calibration interface, which receives externally adjusted delay code values ​​and writes them into the digital delay circuit to adjust the length of the delay compensation.

[0008] Furthermore, the digital core circuit also includes an edge detector and a latch, which convert the trigger signal into digital pulses before inputting them into the delay compensation circuit.

[0009] On the other hand, the present invention also provides a control method for a digital predictive zero-current switching control circuit, the method being used to control any of the aforementioned digital predictive zero-current switching control circuits, the method comprising: During the conduction of the synchronous rectifier diode, the analog front-end detection circuit acquires a trigger signal with a time advance. By configuring the delay code value, the delay compensation circuit is controlled to linearly delay the trigger signal in order to compensate for the system propagation delay; Logical operations are performed on the delayed trigger signal and the PWM master control status signal to drive the synchronous rectifier to turn off when the inductor current crosses zero.

[0010] Furthermore, the method also includes: The trigger signal is converted into a digital pulse to shield the subsequent oscillation noise of the switching nodes of the Buck converter.

[0011] Furthermore, the method also includes: After acquiring the trigger signal, the trigger signal is latched.

[0012] Furthermore, the method also includes: By scanning the delay code value, the waveform effect corresponding to different delay code values ​​is found, and the optimal cut-off point is searched so that the delay compensation circuit can maintain stable delay compensation in subsequent cycles.

[0013] The beneficial effects of this application are as follows: This application abandons the traditional real-time analog triggering mechanism and utilizes an analog front-end with a preset offset voltage to acquire a trigger signal with a time advance before the current crosses zero. Subsequently, a delay compensation circuit performs nanosecond-level linear compensation, using a programmable digital delay line (DDL) as the execution unit to perform a nanosecond-level linear delay on the trigger signal, thus canceling the inherent propagation delay of the comparator and drive circuit. Based on the characteristics of the digital delay chain, a preset analog offset is introduced to create a controllable time advance window, transforming the uncontrollable analog propagation delay into a controllable digital delay compensation problem.

[0014] This application enables precise zero-current turn-off (ZCS) in open-loop control mode by traversing delay code values ​​through software to search for and lock the optimal zero-crossing point of the inductor current. This architecture effectively eliminates inductor reverse current and body diode conduction losses, while utilizing the consistency of digital delay to suppress the impact of PVT variations on timing accuracy, significantly improving the light-load efficiency of the Buck converter in DCM mode.

[0015] The preset offset combined with digital delay proposed in this application is less sensitive to noise compared to traditional real-time simulation detection. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the control principle of the digital predictive zero-current switching control circuit of this application; Figure 2 This is a block diagram of the calibration architecture of the digital predictive zero-current switching control circuit of this application. Detailed Implementation

[0017] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0018] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] To improve detection accuracy, existing ZCS schemes require extremely high bandwidth and bias current for the analog comparator, significantly increasing the system's static power consumption. Meanwhile, low-power comparators often involve significant propagation delays, leading to turn-off hysteresis. The delay characteristics of analog devices are highly sensitive to variations in process technology, voltage, and temperature. Under real-world operating conditions, analog delay drift can cause the turn-off point to deviate from zero, inducing reverse inductor current or body diode conduction losses, severely limiting the converter's light-load efficiency and reliability.

[0020] To address the aforementioned technical problems, the present application proposes the following embodiments of a digital predictive zero-current switching control circuit and control method.

[0021] Reference Figure 1 ,like Figure 1 The diagram shown illustrates the control principle of the digital predictive zero-current switching control circuit in this embodiment. In light-load mode, to reduce switching losses, the Buck converter operates in discontinuous conduction mode (DCM). The core of efficient DCM operation lies in the synchronous rectifier diode (…). Precise switching of a zero-current switch (ZCS). Ideally... Should be in the inductor current The moment of zero crossing ( The transistor immediately shuts off to block reverse current flow. However, in actual physical circuits, there is an unavoidable inherent propagation delay from the detection of the zero-point signal to the complete shutdown of the power transistor gate. This delay consists of two parts: the comparator response time ( ) and gate driver logic delay ( ).

[0022] because The existence of actual shutdown time Always lagging behind The hysteresis causes the inductor current to... The inductor had already flowed in reverse before being turned off (i.e., This creates a reverse current, causing current to flow from the output capacitor. Extracting charge wastes energy and causes high-frequency oscillations in the switching node (SW), generating EMI noise and interfering with the RF of the IOT. The resulting conduction losses... It is proportional to the square of the delay, which severely limits the converter's efficiency under light load.

[0023] This embodiment proposes a hybrid ZCS architecture that overcomes the lag and noise sensitivity issues of pure event-driven logic by decoupling the detection and execution stages. The core idea of ​​this architecture is no longer to "detect at zero point," but rather to "detect in advance and execute with a delay." (Refer to...) Figure 2 ,like Figure 2 The diagram shown is a block diagram of the calibration architecture of the digital predictive zero-current switching control circuit of this application. The architecture mainly consists of three parts: an analog ZCS comparator module, a digital ZCS calibration module, and a gate drive stage.

[0024] In order to overcome the inherent propagation delay of the comparator and driver circuit ( In this embodiment, the design strategy of the analog front-end does not pursue extremely fast zero-crossing detection, but rather obtains "time advance" by artificially introducing a fixed analog offset voltage (Built-inOffset). The detection principle is as follows: During the conduction of the synchronous rectifier (MN), as the inductor current decreases linearly, the voltage of the switching node (LX) ( () Gradually approaching the ground potential. Once Once the voltage rises and reaches the preset threshold (4 adjustable reference voltages: -3~15mV), the comparator immediately flips and outputs the ZCS_Trig signal. This threshold setting effectively shields background noise and ensures that an effective detection window is maintained under light load conditions (when the peak current is small), providing ample time margin for subsequent digital delay compensation.

[0025] Because the comparator flips prematurely when the current is non-zero, and due to the inherent propagation delay in the system, directly using ZCS_Trig to turn off MN will lead to timing deviations. Therefore, this application introduces a high-resolution digital delay line into the system. This module receives the analog trigger signal and, after passing through an edge detector and latch, converts the analog signal into a stable digital pulse, effectively shielding the LX node from potential subsequent oscillation noise. The latched pulse passes through a digital delay line composed of multiple delay units. Finally, the delay code value ZCS_SEL of the digital delay line is adjusted cycle-by-cycle by software. Adjusting ZCS_SEL ensures a smooth transition of the LX voltage, without significant negative voltage or oscillation. By dynamically adjusting the delay length, the system can compensate for the time difference between the "analog trigger point" and the "real zero current point" in the time domain. Its turn-off time satisfies: ; in This is the compensation amount corresponding to the k-th level delay coding.

[0026] To ensure the safety of system timing, the calibrated ZCS signal is logically ANDed with the PWM master control state to ensure that the shutdown action only takes effect during the freewheeling phase. The calibrated control signal turns off MN at the precise moment when the inductor current crosses zero, thereby completely eliminating energy loss caused by MN conduction (undercompensation) or current backflow (overcompensation).

[0027] This interlocking mechanism drives the synchronous rectifier (MN) to precisely turn off at the instant the inductor current crosses zero, fundamentally eliminating two key types of DCM losses: Undercompensated losses: Avoids the high on-state voltage drop losses caused by the premature turn-off of MN, which forces current to flow through the body diode. Overcompensation loss: Eliminates reverse current backflow and subsequent reverse recovery loss caused by MN turning off too late.

[0028] As one implementation method, this embodiment can also use software to iterate through the delay code values, search for and lock the optimal zero-crossing point of the inductor current, thereby achieving precise zero-current turn-off (ZCS) in open-loop control mode. This architecture effectively eliminates the inductor reverse current and body diode conduction losses, while utilizing the consistency of digital delay to suppress the impact of PVT variations on timing accuracy, significantly improving the light-load efficiency of the Buck converter in DCM mode.

[0029] This embodiment provides a digital predictive zero-current switching control circuit and method. The circuit includes analog front-end detection and a digital delay line. By decoupling the "detection" and "execution" stages, a low-power analog front-end is first used for coarse detection with advance, followed by linear compensation with nanosecond-level accuracy using a programmable digital delay line. Furthermore, a preset analog offset is introduced based on the characteristics of the digital delay chain (DDL), creating a controllable time advance window and transforming the uncontrollable analog propagation delay into a controllable digital delay compensation problem.

[0030] Furthermore, this embodiment employs cycle-by-cycle adjustment of the delay code value of the digital delay line to precisely control the turn-off time of the synchronous rectifier, thereby achieving accurate zero-current turn-off in discontinuous conduction mode (DCM) and effectively eliminating inductor reverse current. Simultaneously, the "preset offset + digital delay" scheme proposed in this embodiment is less sensitive to noise compared to traditional real-time analog detection.

[0031] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A digital predictive zero-current switching control circuit, applied to a Buck converter, characterized in that, The circuit includes: An analog front-end detection circuit is connected to the switching node of the Buck converter to monitor the voltage of the switching node. When the voltage of the switching node exceeds a preset threshold, a trigger signal with a time advance is output. The digital core circuit includes a delay compensation circuit and a PWM master control circuit. The delay compensation circuit is connected to the output of the analog front-end detection circuit to apply programmable delay compensation to the trigger signal. The PWM master control circuit outputs a PWM master control status signal. A logic control circuit is connected to the output terminals of the delay compensation circuit and the PWM main control circuit to perform logical operations on the delayed trigger signal and the PWM main control status signal to generate a synchronous rectifier tube turn-off signal. A gate driving circuit, which is connected to the logic control circuit, receives the synchronous rectifier turn-off signal to control the turn-off of the synchronous rectifier.

2. The digital predictive zero-current switching control circuit as described in claim 1, characterized in that, The switch control circuit also includes a calibration interface, which receives externally adjusted delay code values ​​and writes them into the digital delay circuit to adjust the length of the delay compensation.

3. The digital predictive zero-current switching control circuit as described in claim 1, characterized in that, The digital core circuit also includes an edge detector and a latch. The edge detector and the latch convert the trigger signal into digital pulses, which are then input into the delay compensation circuit.

4. A control method for a digital predictive zero-current switching control circuit, characterized in that, The method is used to control the digital predictive zero-current switch control circuit according to any one of claims 1-3, the method comprising: During the conduction of the synchronous rectifier diode, the analog front-end detection circuit acquires a trigger signal with a time advance. By configuring the delay code value, the delay compensation circuit is controlled to linearly delay the trigger signal in order to compensate for the system propagation delay; Logical operations are performed on the delayed trigger signal and the PWM master control status signal to drive the synchronous rectifier to turn off when the inductor current crosses zero.

5. The control method for the digital predictive zero-current switching control circuit as described in claim 4, characterized in that, The method further includes: The trigger signal is converted into a digital pulse to shield the subsequent oscillation noise of the switching nodes of the Buck converter.

6. The control method for the digital predictive zero-current switching control circuit as described in claim 4, characterized in that, The method further includes: After acquiring the trigger signal, the trigger signal is latched.

7. The control method for the digital predictive zero-current switching control circuit as described in claim 4, characterized in that, The method further includes: By scanning the delay code value, the waveform effect corresponding to different delay code values ​​is found, and the optimal cut-off point is searched so that the delay compensation circuit can maintain stable delay compensation in subsequent cycles.

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