Chip latch test method

CN122218451APending Publication Date: 2026-06-16ZHEJIANG ZOBOW MECHANICAL & ELECTRICAL TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
ZHEJIANG ZOBOW MECHANICAL & ELECTRICAL TECH
Filing Date
2026-03-30
Publication Date
2026-06-16

AI Technical Summary

Technical Problem

CMOS器件存在闩锁效应风险一旦发生，会导致元器件电源端（VCC）与地端（GND）直接短路，瞬间产生的大电流会快速烧毁芯片，造成电子设备故障，在工业控制、汽车电子、精密仪器等高端应用场景中，闩锁引发的故障可能带来重大损失

Benefits of technology

[0016]The technical solution of this invention involves generating a first power supply voltage through a power supply circuit; transmitting a second power supply voltage to the power supply terminal of the chip under test (DUT) through a voltage conversion circuit to provide operating voltage to the DUT; outputting a first PWM signal to a pulse voltage generation circuit to control the pulse voltage generation circuit to output a pulse voltage to the DUT; and detecting whether the current of the DUT is greater than a preset value. If so, the DUT latches up. This invention can determine whether the DUT has triggered latch-up by judging in real time whether the current of the DUT is greater than a preset value. If latch-up is not triggered, at least one of the first power supply voltage or the first PWM signal output by the power supply circuit is adjusted until the current of the DUT is greater than the preset value. If so, the current of the DUT and the first PWM signal at this time are acquired to determine the latch-up current and latch-up trigger voltage. This timely solution allows for controllable amplitude and pulse width of the pulse voltage used for latch-up testing of the DUT, achieving accurate detection of whether the DUT has latched up and determination of the precise latch-up trigger voltage.

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Abstract

The application discloses a chip latch test method. The chip latch test method comprises the following steps: generating a first power supply voltage through a power supply circuit; transmitting a second power supply voltage to a power supply end of a measured chip through a voltage conversion circuit; outputting a first PWM signal to a pulse voltage generation circuit, and controlling the pulse voltage generation circuit to output a pulse voltage to the measured chip; detecting whether the current of the measured chip is greater than a preset value, and if not, adjusting at least one of the size of the first power supply voltage output by the power supply circuit or the first PWM signal until the current of the measured chip is greater than the preset value; and if yes, acquiring the current of the measured chip and the first PWM signal at this time, and determining a latch current and a latch trigger voltage. The technical scheme of the embodiment of the application can control the amplitude and pulse width of the pulse voltage for the measured chip to perform the latch test, and precise detection of whether the measured chip occurs latch and determination of the precise latch trigger voltage are realized.
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