A method and system for recording PLC fault information

Abstract

This invention belongs to the field of industrial automation control technology and discloses a PLC fault information recording method and system. The method includes monitoring the program running status and power supply voltage of the programmable logic controller (PLC); if a logic running fault is detected from the program running status, capturing the thread context and logical context at the time of the logic running fault; encapsulating the thread context and logical context into a logic fault information packet, verifying and storing the logic fault information packet; if an abnormal power outage is detected in the power supply voltage, initiating emergency power supply; identifying the cause of the power outage, capturing the logical context before the power outage; encapsulating the logical context into a power outage fault information packet, verifying and storing the power outage fault information packet, and stopping the emergency power supply; and exporting fault information and responding to fault query requests based on the stored logic fault information packet and / or power outage fault information packet. This invention achieves full-process coverage of PLC from fault occurrence to information storage.

Description

Technical Field

[0001] This invention relates to the field of industrial automation control technology, and in particular to a PLC fault information recording method and system. Background Technology

[0002] Programmable Logic Controllers (PLCs), as core control devices in the field of industrial automation control technology, are widely used in critical scenarios in production lines, energy, transportation, and other control areas. Because of their central control position, the stability and reliability of PLCs directly determine the safety and continuity of automation control; during PLC operation, fault recording and tracing are crucial for ensuring rapid PLC recovery and minimizing downtime losses.

[0003] Although there are many existing technologies for PLC fault recording and tracing, they mainly have the following shortcomings: First, for logic operation faults, such as accessing abnormal addresses, program logic conflicts, and program crashes caused by software anomalies, traditional PLCs can only record simple error codes or fault occurrence addresses, lacking records of the thread context at the time of the fault, such as the program counter (PC) pointer, register states, function call stacks, and logical context, such as key variable values, I / O interface states, and the current values ​​of timers / counters. This makes it difficult for maintenance personnel to restore the program's running state at the time of the fault, requiring a lot of time to locate the fault, and sometimes even failing to find the root cause. Second, for abnormal power outage faults, such as power fluctuations, external power interruptions, and power outages caused by hardware failures, existing technologies mostly rely on small-capacity capacitors on the PLC board to provide short-term power supply, which can only save a small amount of register data and cannot record the cause of the power outage, such as overvoltage, undervoltage, short circuit, etc., or the complete logical context. Moreover, the capacitor power supply time is limited, and it is easy for data to be lost before the power outage is fully saved. This leads to the loss of power outage fault information and makes it impossible to trace the root cause of the fault. Third, existing fault recording systems are mostly single-function designs, either targeting logical faults or power outage faults, lacking a unified fault information management mechanism. Fault data is stored in a scattered manner, making it inconvenient for maintenance personnel to conduct centralized analysis and troubleshooting.

[0004] In summary, existing PLC fault recording and tracing technologies cannot meet the requirements of various industrial scenarios for comprehensive, reliable, and traceable fault information. There is an urgent need for a technical solution that can accurately record both logic operation faults and abnormal power failure faults at the same time, while ensuring that fault information is not lost. Summary of the Invention

[0005] To achieve the above objectives, the present invention adopts the following technical solution: In one aspect, the present invention provides a method for recording PLC fault information, comprising the following steps: Step S100: Monitor the program running status and power supply voltage of the programmable logic controller (PLC); Step S200: If a logical operation failure is detected from the program running state, capture the thread context and logical context at the time of the logical operation failure; encapsulate the thread context and logical context into a logical failure information packet, verify and store the logical failure information packet; Step S300: If an abnormal power outage is detected in the power supply voltage, start the emergency power supply; identify the cause of the power outage and capture the logical context before the power outage; encapsulate the logical context into a power outage fault information packet, verify and store the power outage fault information packet, and stop the emergency power supply; Step S400: Based on the stored logical fault information packet and / or power failure fault information packet, export the fault information and respond to the fault query request; filter the fault information according to the time range and fault type of logical fault or power failure; and simultaneously report the remaining storage space and media health status.

[0006] Another aspect of the present invention provides a PLC fault information recording system, comprising: The logic fault information capture module is connected to the programmable logic controller (PLC) main control unit. It is used to detect PLC logic operation faults, capture the thread context and logic context at the time of the logic operation fault, and generate a logic fault information packet. The power failure information capture module is connected to the power interface of the programmable logic controller (PLC) and the emergency power supply module. It is used to detect abnormal power failure events of the PLC, identify the cause of the power failure, capture the logic context before the power failure, generate a power failure information package, and trigger the emergency power supply module to start. The emergency power supply module, connected to the logic fault information capture module, the power outage fault information capture module, and the fault information storage module, is used to provide temporary power supply in case of abnormal power outage and ensure complete storage of fault information. The fault information storage module is used to connect with the logic fault information capture module and the power failure fault information capture module via the internal data bus, and is used to store logic fault information packets and power failure fault information packets. The fault information interaction module is connected to the fault information storage module and is used to export fault information and respond to fault query requests.

[0007] This invention integrates monitoring and capture mechanisms for two scenarios: logical operation failures and abnormal power outages, forming a complementary fault recording system. It monitors program running status and power supply voltage in real time, ensuring the complete preservation of threads and logical contexts during logical failures and maintaining the capture and storage of critical data with the help of emergency power during abnormal power outages. The verification and storage process for logical failure information packets and power outage information packets adopts a unified data integrity verification mechanism, improving the reliability and traceability of fault information. Through high-frequency sampling and threshold determination using voltage and current sensors, it achieves rapid identification of power outage causes and context capture, avoiding the loss of fault information due to power interruption. It achieves full-process coverage from fault occurrence to information storage, providing a structured and highly reliable data foundation for fault diagnosis and system recovery. Attached Figure Description

[0008] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 A flowchart for the PLC fault information recording method; Figure 2 A process diagram for monitoring the power supply voltage of a programmable logic controller (PLC); Figure 3 A diagram illustrating the process of encapsulating thread context and logical context into a logical fault information packet; Figure 4 This is a diagram illustrating the process of encapsulating a power failure information packet into a logical context. Figure 5 A flowchart illustrating the process of exporting fault information and responding to fault query requests; Figure 6 A flowchart for a PLC fault information recording system. Detailed Implementation

[0009] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0010] The following detailed description is exemplary and intended to provide further detailed explanation of the invention. Unless otherwise specified, all technical terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this invention is for describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention.

[0011] This invention includes a logic fault information capture module, a power outage fault information capture module, an emergency power supply module, a fault information storage module, and a fault information interaction module. When a logic fault occurs, the logic fault information capture module acquires the thread context and logical context at the moment of program crash. In the event of an abnormal power outage, the emergency power supply module provides temporary energy, the power outage fault capture module records the cause of the power outage and the logical context, and all fault information is stored in the fault information storage module and can be exported through the fault information interaction module. Through the above logical and technical means, comprehensive and reliable recording of PLC fault information is achieved, providing a complete basis for fault location and troubleshooting, and improving the robustness and maintainability of PLC operation.

[0012] like Figure 1 As shown, this embodiment of the invention provides a PLC fault information recording method, which includes the following steps: Step S100: Monitor the program running status and power supply voltage of the programmable logic controller (PLC).

[0013] In step S100, the supercapacitor or lithium battery for emergency power supply is fully charged; logic fault information capture and power failure fault information capture continuously monitor the program running status and power supply voltage of the programmable logic controller (PLC); fault information storage is in standby mode; program running status includes program counter (PC) tracking, memory access legality check, and function call stack integrity monitoring; the monitoring of program running status is mainly handled by the logic fault information capture module, which works in conjunction with the debugging interface of the CPU core through hardware probes; the monitoring of power supply voltage is mainly handled by the power failure fault information capture module, which uses a pre-set analog front-end circuit independent of the PLC CPU.

[0014] Furthermore, such as Figure 2 As shown, the process of monitoring the power supply voltage of a programmable logic controller (PLC) includes the following steps: Step S101: The voltage sensor collects the supply voltage at intervals of ten milliseconds to obtain a discrete voltage sample value sequence. The discrete voltage sample value sequence is sent to a voltage change rate extraction circuit composed of resistors and capacitors. The voltage change rate extraction circuit outputs an analog value reflecting the slope of the instantaneous voltage change. When the analog value exceeds a preset slope threshold of five volts per millisecond, a high-level signal is output, and the high-level signal is registered as a voltage descent rate exceeding limit event. Step S102: The voltage sensor and current sensor synchronously collect the supply voltage and supply current at intervals of ten milliseconds each, obtaining voltage sample values ​​and current sample values; compare the voltage sample value and current sample value at the same sampling moment, compare the voltage sample value with the overvoltage threshold and the undervoltage threshold, and compare the current sample value with the short-circuit current threshold. When the comparison result satisfies both the voltage being lower than the undervoltage threshold and the current being higher than the short-circuit current threshold, output a short-circuit judgment flag; when the comparison result only satisfies the voltage being higher than the overvoltage threshold, output an overvoltage judgment flag; when the comparison result only satisfies the voltage being lower than the undervoltage threshold and the current not being higher than the short-circuit current threshold, output an undervoltage judgment flag. Step S103: Use the received voltage descent rate exceeding limit event, short circuit judgment flag, overvoltage judgment flag, or undervoltage judgment flag as trigger signals; upon receiving any trigger signal, send a start command to the emergency power supply, and switch to supercapacitor or lithium battery power supply after receiving the start command; during the emergency power supply period, write the power outage reason corresponding to the trigger signal into the power outage fault information packet, and store the power outage fault information packet. After the storage completes the storage feedback signal, send a stop command to the emergency power supply, and the emergency power supply stops supplying power. The voltage change rate extraction circuit consists of resistors and capacitors. Its input receives a sequence of discrete voltage samples from a voltage sensor. Utilizing the charging characteristic of the capacitor, the discrete voltage sample sequence is converted into an analog rate-of-change signal. When the power supply voltage of the programmable logic controller (PLC) experiences a rapid drop within milliseconds, the transient change can be extracted into an analog value that can be recognized by subsequent comparators, enabling the system to capture voltage surges that cannot be recorded by a conventional 10-millisecond sampling period. The preset slope threshold is 5 volts per millisecond, based on the rated voltage of the PLC power supply system being 24 volts. When the rate of change of the power supply voltage exceeds this value, it indicates that the voltage drop rate exceeds the power module's ability to maintain a stable output. At this time, the PLC's processor unit has not yet triggered undervoltage protection, but the power supply has entered an unstable state. The preset slope threshold serves as a trigger condition, allowing the power failure fault information capture module to initiate emergency power supply before the voltage drops to the undervoltage threshold. The voltage descent rate exceeding limit event is a status flag recorded internally by the power outage fault information capture module. It is generated by a high-level signal when the analog value output by the voltage change rate extraction circuit exceeds a preset slope threshold. Recorded as a separate type of power outage cause in the power outage fault information packet, distinct from overvoltage, undervoltage, and short circuit causes, it identifies power supply anomalies caused by instantaneous voltage drops that do not meet the undervoltage judgment criteria. The overvoltage threshold is set to the upper limit of the programmable logic controller's rated voltage, the undervoltage threshold is set to 18 volts, and the short-circuit current threshold is set to three to five times the rated operating current. These thresholds are based on the technical specifications of the programmable logic controller power module. The overvoltage threshold identifies voltage increases that may trigger the internal protection circuitry of the power module, the undervoltage threshold corresponds to the minimum operating voltage of the programmable logic controller processor unit, and the short-circuit current threshold distinguishes between overload and short circuit fault types. These three thresholds together form the judgment criteria for power outage cause classification, enabling the power outage fault information capture module to write the identified overvoltage, undervoltage, and short-circuit causes into the corresponding power outage fault information packets.

[0015] Furthermore, the process of switching to supercapacitor or lithium battery power after receiving the start command in step S103 specifically includes the following steps: Step S1031: Upon receiving a voltage descent rate exceeding limit event, start a timer that is proportional to the analog value output by the voltage change rate extraction circuit. The duration of the timer is determined by the magnitude by which the analog value exceeds a preset slope threshold of 5 volts per millisecond. The greater the magnitude of the exceedance, the shorter the duration of the timer. During the timer's timing, keep the disconnect switch between the supercapacitor or lithium battery and the power input terminal of the programmable logic controller in the open state. Simultaneously, continuously receive voltage sampling values. When the timer ends and the voltage sampling value is still not lower than the 18-volt undervoltage threshold, output a closing command to the disconnect switch to connect the supercapacitor or lithium battery to the power supply circuit of the programmable logic controller. Step S1032: After receiving the overvoltage judgment flag, the overvoltage judgment flag is synchronously latched with the current voltage sampling value to form an overvoltage event record; according to the magnitude by which the voltage sampling value in the overvoltage event record exceeds the overvoltage threshold, the corresponding isolation resistor combination is selected and connected to the output circuit of the supercapacitor or lithium battery. The resistance value of the isolation resistor combination is inversely proportional to the magnitude of the exceedance; after the isolation resistor combination is connected, a closing command is output to the isolating switch to connect the supercapacitor or lithium battery output that has been current-limited by the isolation resistor combination to the power supply circuit of the programmable logic controller, so that the power supply voltage is maintained above the undervoltage threshold and the overvoltage protection circuit is not triggered. Step S1033: When an undervoltage judgment flag is received, connect the supercapacitor or lithium battery to the power supply circuit of the programmable logic controller through a set of three forward-connected power diodes, forming a voltage drop path of three power diodes connected in series; when a short-circuit judgment flag is received, connect the supercapacitor or lithium battery to the power supply circuit of the programmable logic controller through another set of two reverse-parallel power diodes, forming a bidirectional voltage limiting path of two power diodes connected in reverse parallel; select the corresponding power diode group for connection according to the type of judgment flag received, and disconnect the connected power diode group after the fault information feedback storage completion signal is received.

[0016] Step S200: If a logical operation failure is detected from the program running state, capture the thread context and logical context at the time of the logical operation failure; encapsulate the thread context and logical context into a logical failure information packet, verify and store the logical failure information packet; In step S200, the thread context includes the program counter (PC) pointer, general-purpose register values, and function call stack; the logical context includes key variable values, I / O interface status, and current timer / counter values; the logical fault information packet is verified by using a CRC algorithm, and after successful verification, it is stored in the corresponding partition, and a data storage confirmation signal is generated; logical operation faults include accessing abnormal addresses and program crashes.

[0017] Furthermore, such as Figure 3 As shown, the process of encapsulating the thread context and logical context into a logical fault information packet in step S200 specifically includes the following steps: Step S201: By linking with the fault interrupt interface of the main control unit of the programmable logic controller, identify the current fault type of accessing abnormal address or program crash, convert the current fault type into a fixed-length fault type identifier code; and concatenate the fault type identifier code with the fault time timestamp output by the internal real-time clock of the logic fault information capture to form the header field of the logic fault information packet. Step S202: Logic Fault Information Capture. At the moment of fault interruption, the current value of the program counter pointer, the current value of the general-purpose register set, and the current storage content of the function call stack are read in parallel from the processor of the main control unit of the programmable logic controller through the hardware probe and the processor debugging interface. The current value of the program counter pointer, the current value of the general-purpose register set, and the current storage content of the function call stack are arranged according to the preset register order to form a thread context field, and the thread context field is appended to the packet header field. Step S203: While reading the thread context, read the current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters from the data bus of the programmable logic controller main control unit; arrange the current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters in the order of variable addresses to form a logical context field; and append the logical context field to the thread context field to obtain a logical fault information packet composed of a packet header field, a thread context field, and a logical context field concatenated in sequence.

[0018] Fault detection in step S200: Real-time monitoring of the PLC program's running status, and identification of logical operation fault types through linkage with the fault interrupt interface of the PLC main control unit, including but not limited to accessing abnormal addresses, program logic conflicts, and program crashes caused by software exceptions; abnormal address access includes out-of-bounds access to data blocks and invalid register addresses; program logic conflicts include infinite loops and conflicts caused by variable redefinition; software exceptions include function call errors and stack overflows; thread context capture: At the moment a logical fault is detected, a thread context capture instruction is triggered to read the thread running data at the time of the fault from the processor of the PLC main control unit, including but not limited to the program counter PC pointer (recording the program execution position at the time of the fault) and general-purpose register values ​​(recording the program execution position at the time of the fault). The system records the current thread's computational data and function call stack (records the function call sequence before the fault occurred, restoring the program execution path); logic context capture: synchronously reads logic-related data during PLC operation, including but not limited to key variable values ​​(such as the current values ​​of global variables, local variables, and data block variables), IO interface status (such as digital input / output status and analog input / output current values), and timer / counter status (such as the remaining duration of the timer and the current count of the counter); data preprocessing: encapsulates the captured thread context and logic context data in a preset format (such as fault type-timestamp-thread context-logic context) to generate a standardized logic fault information package, which is then sent to the fault information storage module through the internal data bus.

[0019] This embodiment combines a fault interrupt interface linkage mechanism with parallel hardware probe acquisition technology to achieve real-time detection and full-dimensional state capture of programmable logic controller (PLC) operational faults. The concatenation of the fault type identifier code and timestamp forms a standardized packet header, ensuring the uniqueness and temporal traceability of the fault event. Thread context capture, through the synchronous extraction of the program counter pointer, general-purpose register set, and function call stack, completely preserves the processor's instruction flow state and function nesting relationships at the moment of the fault. Parallel acquisition of the logical context covers key variables, input / output interfaces, and timer / counters, forming a comprehensive mapping of the controller's logical state. The two types of context data are structured according to register order and variable address order, constructing a complete information packet containing header fields, thread context fields, and logical context fields. This encapsulation method enables fault information to simultaneously possess temporal characteristics, program execution flow characteristics, and system operating state characteristics, providing a three-dimensional data foundation encompassing the hardware, program, and logical layers for fault analysis. Through standardized transmission via the internal data bus, the information packet can be reliably received by the fault storage module, providing high-fidelity, multi-dimensional, and structured data support for offline root cause analysis, program debugging, and system reliability optimization.

[0020] Furthermore, the process of obtaining the logical fault information packet, which is composed of the packet header field, the thread context field, and the logical context field concatenated in sequence, in step S203 includes the following steps: Step S2031: Map the identified access exception address, program logic conflict or software exception corresponding to the fault type to three sets of non-overlapping fault type identification codes respectively; interleave the fault type identification code with the timestamp read from the real-time clock at the time of the fault interrupt interface linkage, so that each bit of the binary value of the timestamp is inserted between the corresponding bits of the fault type identification code to form the packet header field. Step S2032: At the moment of fault interruption, the current value of the program counter pointer, the current value of the general-purpose register set, and the current storage content of the function call stack are read in parallel from the processor of the main control unit of the programmable logic controller through the hardware probe and the processor debugging interface; the current value of the program counter pointer is used as the root node, the current value of the general-purpose register set is appended to the root node as the first-level child node according to the register number order, and the current storage content of the function call stack is appended to the first-level child node as the second-level child node according to the call depth from deep to shallow, forming a thread context field with a three-level tree structure, and the thread context field is appended to the packet header field; Step S2033: While reading the thread context through the hardware probe and processor debugging interface, read the current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters from the data bus of the programmable logic controller main control unit through the same hardware probe; arrange the read current values ​​of key variables according to the offset address of the variables in the data block, arrange the input / output interface status values ​​according to the interface number, and arrange the current values ​​of timers and counters according to the timer and counter number; concatenate the three arrangement results to form a logical context field, perform an XOR operation on each byte value in the logical context field and the corresponding byte value in the thread context field, replace the original byte value in the logical context field with the XOR operation result, and obtain a verified and associated logical context field. The verified and associated logical context field is then appended after the thread context field to obtain a logical fault information packet composed of a packet header field, a thread context field, and a logical context field concatenated in sequence.

[0021] Furthermore, the process of performing an XOR operation between each byte value in the logical context field and the corresponding byte value in the thread context field in step S2033 includes the following steps: Step S20331: Compare the length value of the thread context field with the length value of the logical context field, and take the smaller value as the operation length; determine the range of bytes involved in the operation in the thread context field and the logical context field based on the operation length; extract the byte sequence from the thread context field starting from the starting byte for the operation length, and extract the byte sequence from the logical context field starting from the starting byte for the operation length. Step S20332: Input the first byte of the truncated thread context field byte sequence and the first byte of the logical context field byte sequence into the XOR operation unit, and the XOR operation unit outputs the first result byte; input the second byte of the truncated thread context field byte sequence and the second byte of the logical context field byte sequence into the same XOR operation unit, and the XOR operation unit outputs the second result byte; repeat the above operation in byte order until all bytes within the operation length have been operated on, and obtain the operation result byte sequence composed of the operation result bytes in order; Furthermore, the XOR operation unit in step S20332 includes the following steps: Step S203321: The XOR operation unit receives the first byte and the second byte as input, and aligns the eight binary bits of the first byte with the eight binary bits of the second byte bit by bit; the XOR operation unit is equipped with eight sets of parallel comparison circuits, each set of comparison circuits corresponding to the position of one bit; Step S203322: Each comparison circuit simultaneously inputs the level signal of the corresponding bit of the first byte and the level signal of the corresponding bit of the second byte into a logic judgment structure consisting of two NAND gates and one NOR gate; the logic judgment structure outputs a level signal, outputting a low level when the two input levels are the same, and outputting a high level when the two input levels are different; Step S203323: The eight level signals output by the eight sets of comparison circuits are combined bit by bit into a new byte, which is used as the output result byte of the XOR operation unit and sent out from the output terminal of the XOR operation unit; The comparison circuit consists of eight parallel hardware structures within the XOR operation unit. Each comparison circuit corresponds to a binary bit with the same bit sequence in the first and second bytes. The inputs of the comparison circuits are connected to the level signal outputs of the corresponding bits in the byte sequence extracted from the thread context field and the logical context field, respectively, for comparing the bit level signals from the two sources. The level signal represents the potential state of each binary bit in the byte sequence extracted from the thread context field and the logical context field. The byte sequence extracted from the thread context field is derived from the current value of the program counter pointer, the current value of the general-purpose register set, and the current content of the function call stack, which are read from the processor of the programmable logic controller main control unit through a hardware probe and processor debugging interface, arranged in a tree structure. The level signal of each binary bit in the byte sequence directly reflects the bit-level state of the processor's internal execution path at the time of the fault. The logical judgment structure consists of two NAND gates and one NOR gate connected in parallel at their inputs and in series at their outputs. The inputs of the two NAND gates receive level signals from the corresponding bits of the thread context field and the corresponding bits of the logical context field, respectively. The outputs of the two NAND gates are connected to the two inputs of the NOR gate, and the output of the NOR gate serves as the output of the bit comparison circuit. This logical judgment structure, at the hardware level, implements the function of outputting a low level when the two input levels are the same and outputting a high level when the two input levels are different. Its output level signal is used to indicate the similarity or difference between the thread context field and the logical context field at the time of the fault. The new byte is an eight-bit binary data formed by combining eight level signals output simultaneously by eight sets of comparison circuits in ascending order of the least significant bit. This new byte, as the output byte of the XOR operation unit, replaces the original byte at the corresponding position in the logical context field, ensuring that each byte in the replaced logical context field carries bit-level association information with the corresponding byte in the thread context field, forming a verification association between the two fields.

[0022] Step S20333: Write the first result byte in the result byte sequence to the first byte position of the logical context field, and write the second result byte in the result byte sequence to the second byte position of the logical context field; repeat the above writing operation in byte order until the original byte values ​​in all logical context fields within the operation length are replaced by the result bytes, and obtain the verified and associated logical context fields.

[0023] Step S300: If an abnormal power outage is detected in the power supply voltage, start the emergency power supply; identify the cause of the power outage and capture the logical context before the power outage; encapsulate the logical context into a power outage fault information packet, verify and store the power outage fault information packet, and stop the emergency power supply; In step S300, the power parameters collected by the voltage sensor and current sensor are combined with a preset threshold to determine the cause of power failure. The cause of power failure includes overvoltage, undervoltage, and short circuit. The voltage sensor samples every 10ms, and the current sensor samples every 10ms. Abnormal power failure includes voltage <18V (24V system), or voltage drop rate >5V / ms, or voltage drops from 24V to 0V, which are determined to be power interruption.

[0024] Furthermore, such as Figure 4 As shown, the process of encapsulating the power failure information packet in step S300 includes the following steps: Step S301: Convert the power outage cause corresponding to the voltage descent rate exceeding the limit event, overvoltage judgment flag, undervoltage judgment flag, or short circuit judgment flag into a fixed-length power outage cause identification code; perform bit-interleaving arrangement of the power outage cause identification code and the power outage detection time timestamp output by the real-time clock inside the power outage fault information capture module, so that each bit of the binary value of the timestamp is inserted between the corresponding bits of the power outage cause identification code to form the header field of the power outage fault information packet; Step S302: After receiving the trigger signal, the power failure fault information capture module reads the current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters from the data bus of the main control unit of the programmable logic controller through the same hardware probe; arranges the read current values ​​of key variables in order of their offset address in the data block, arranges the input / output interface status values ​​in order of their interface number, and arranges the current values ​​of timers and counters in order of their timer and counter number; and concatenates the three arrangement results to form a logical context field. Furthermore, step S302, which involves reading the current values ​​of key variables, input / output interface status values, and the current values ​​of timers and counters from the data bus of the programmable logic controller's main control unit using the same hardware probe, includes the following steps: Step S3021: After receiving the voltage descent rate exceeding the limit event, the power failure fault information capture module uses the analog value output by the voltage change rate extraction circuit corresponding to the voltage descent rate exceeding the limit event as the sampling depth coefficient; the address interval for reading the current value of key variables from the data bus of the programmable logic controller main control unit is determined according to the sampling depth coefficient. The larger the sampling depth coefficient value, the larger the address interval. When the address interval increases, the intermediate variables located between adjacent addresses are skipped, and only the current value of the key variable selected by the interval is read, so as to obtain the compressed key variable value sequence associated with the amplitude of the voltage descent rate exceeding the limit event. Furthermore, the process of using the analog value output by the voltage change rate extraction circuit corresponding to the voltage descent rate exceeding the limit event as the sampling depth coefficient in step S3021 includes the following steps: Step S30211: The power failure information capture module receives analog values ​​from the output of the voltage change rate extraction circuit and inputs the analog values ​​into the internal preset quantization mapping table. The quantization mapping table stores the correspondence between analog value ranges and digital quantization levels. The quantization mapping table outputs the corresponding digital quantization level according to the range to which the analog value belongs, and obtains the digital quantization level value corresponding to the voltage change rate amplitude. Step S30212: Obtain the reference level value corresponding to the digital quantization level value and the preset slope threshold stored in the power failure fault information capture module, calculate the difference between the digital quantization level value and the reference level value, and compare the difference with zero. When the difference is positive, output the excess amplitude value. The excess amplitude value is the difference between the digital quantization level value and the reference level value. When the difference is less than or equal to zero, output zero value as the excess amplitude value. Step S30213: Based on the inverse mapping relationship between the amplitude range and the sampling depth coefficient, obtain the sampling depth coefficient corresponding to the range to which the amplitude value belongs, and output the sampling depth coefficient as the control parameter for address interval selection to the address interval selector.

[0025] Furthermore, step S30213, based on the inverse mapping relationship between the amplitude range and the sampling depth coefficient, includes the following steps: Step S302131: Divide the possible range of values ​​that exceed the amplitude into multiple consecutive amplitude exceedance intervals, each amplitude exceedance interval corresponding to an interval number; take the maximum possible amplitude of the analog value exceeding the preset slope threshold in the voltage descent rate over-limit event as the upper limit value, and zero as the lower limit value; divide the intervals in ascending order of amplitude exceedance, the number of intervals is equal to the number of preset sampling depth coefficient levels, and assign a unique interval number to each interval; Step S302132: Establish a sampling depth coefficient level sequence. The values ​​in the sampling depth coefficient level sequence are arranged in descending order. The number of levels is equal to the number of amplitude ranges exceeded. The first level in the sampling depth coefficient level sequence corresponds to the largest sampling depth coefficient, and the last level corresponds to the smallest sampling depth coefficient. The amplitude range numbers are matched one-to-one with the levels in the sampling depth coefficient level sequence. The smaller the range number, the larger the corresponding sampling depth coefficient level value. The larger the range number, the smaller the corresponding sampling depth coefficient level value, forming an inverse correspondence between the amplitude range numbers and the sampling depth coefficient. Furthermore, the process of sequentially mapping the out-of-amplitude interval numbers to the levels in the sampling depth coefficient level sequence in step S302132 includes the following steps: Step S3021321: Arrange the interval numbers that exceed the amplitude range in ascending order of value to form an interval number list; arrange the sampling depth coefficient level sequence in descending order of value to form a level list; create an empty mapping table containing an interval number field and a level value field; write the first interval number in the interval number list and the first level value in the level list into the first record of the mapping table. Step S3021322: Write the second interval number in the interval number list and the second gear value in the gear list into the second record of the mapping table. Write them in the order of the interval number list and the gear list until all interval numbers in the interval number list have been written, forming a mapping table in which the interval numbers and gear values ​​correspond in order. Step S3021323: Store the mapping table in the data storage area accessible to the depth coefficient generator. The data storage area uses the interval number as the index key value, and each index key value corresponds to storing a gear value. After receiving the value exceeding the amplitude and determining the interval number to which it belongs, the depth coefficient generator retrieves the corresponding gear value from the data storage area using the interval number as the index key value, and uses the retrieved gear value as the output sampling depth coefficient.

[0026] Furthermore, the process of using the range number as the index key value in the data storage area in step S3021323 includes the following steps: Step S30213231: Convert all interval numbers in the interval number list into fixed-length binary key values. Each interval number corresponds to a unique binary key value. Arrange all binary key values ​​in ascending order of interval numbers to form a key value sequence. Extract the gear position values ​​corresponding to the interval numbers in the mapping table in the same order as the interval numbers to form a value sequence. Write the key value sequence and the value sequence in pairs into a key value storage area. The key value storage area uses each key value in the key value sequence as a storage index. Each index position stores the corresponding gear position value, forming a direct mapping structure between key values ​​and gear position values. Step S30213232: Construct a hash index table on top of the key-value storage area. The hash index table contains multiple hash buckets. Each hash bucket corresponds to a range number of binary key-value pairs, and the hash value is calculated by a hash function. Store the binary key-value pairs of each range number and their corresponding digit values ​​into the corresponding hash buckets. The hash buckets are sorted according to the size of the range number values ​​to form a two-level retrieval structure with the hash value as the first-level index and the range number sorting as the second-level index. Step S30213233: After receiving the value exceeding the amplitude and determining its interval number, the depth coefficient generation unit inputs the binary key value of the interval number into the hash function to obtain the hash value. Based on the hash value, it locates the corresponding hash bucket in the hash index table. Within the hash bucket, it uses a binary search method with the binary key value of the interval number as the keyword to retrieve the corresponding gear value. The retrieved gear value is used as the output sampling depth coefficient.

[0027] Step S302133: The inverse correspondence between the excess amplitude interval number and the sampling depth coefficient level is fixed in the mapping storage area inside the depth coefficient generation unit. The mapping storage area uses the interval number as the index address, and each index address stores the corresponding sampling depth coefficient level value. After the depth coefficient generation determines the interval number to which the input excess amplitude value belongs, it reads the corresponding sampling depth coefficient level value from the mapping storage area using the interval number as the index address, and uses the sampling depth coefficient level value as the output sampling depth coefficient.

[0028] Step S3022: After receiving the undervoltage judgment flag, the power failure information capture module retrieves the interface number set associated with the undervoltage fault based on the input of the undervoltage judgment flag. The interface number set includes the numbers of the power supply monitoring interface, the power status feedback interface, and the voltage sampling interface. According to the order in the interface number set, the input and output interface status values ​​corresponding to the above interface numbers are read sequentially from the data bus of the programmable logic controller main control unit through hardware probes to obtain the interface status value sequence associated with the undervoltage fault. Step S3023: After receiving the short circuit judgment flag, the power failure fault information capture module reads the current values ​​of all timers and counters from the data bus of the programmable logic controller main control unit according to the input of the short circuit judgment flag. At the same time, it compares the voltage fluctuation amplitude on the data bus during the reading process with the preset reading stability threshold. When the voltage fluctuation amplitude on the data bus exceeds the reading stability threshold, the reading operation is paused, and the current values ​​of the timers and counters that have been read are locked as valid data according to the reading order. The current values ​​of the unread timers and counters are replaced with the default values ​​pre-stored in the system configuration field, so as to obtain the timer and counter value sequence formed by splicing the read valid data and the default values.

[0029] Step S303: Perform an XOR operation on each byte value in the logical context field and the corresponding byte value in the system configuration field pre-stored inside the power failure fault information capture module. Replace the original byte value in the logical context field with the XOR operation result to obtain the verified and associated logical context field. Concatenate the packet header field and the verified and associated logical context field in sequence to obtain the power failure fault information packet composed of the packet header field and the logical context field.

[0030] In this embodiment, it is linked with the PLC power interface and emergency power supply module to detect abnormal power outage events, identify the cause of the power outage, and capture the logical context before the power outage. Specific functions include: Power outage detection: Through a voltage detection unit connected to the PLC power interface, it monitors changes in the PLC power supply voltage in real time. When a sudden voltage drop, below the normal operating voltage threshold, or a voltage interruption is detected, it is determined as an abnormal power outage event, and the power outage fault handling process is immediately triggered; Power outage cause identification: Through integrated voltage and current sensors, it collects power parameters before the power outage, such as voltage fluctuation amplitude and current change trend, and combines them with preset power outage cause determination rules. If the voltage exceeds the upper limit of the normal range, it is determined to be overvoltage; if it falls below the lower limit, it is determined to be undervoltage; if the voltage drops to zero after a sudden increase in current, it is determined to be a short circuit. The cause of the power outage is identified and recorded. Logic context capture: After triggering the power outage fault handling process, the current logic context data of the PLC is immediately read and is consistent with the logic context data content of the logic fault information capture module to ensure data format uniformity and avoid data loss due to power outage. Emergency linkage: When an abnormal power outage is detected, a start command is simultaneously sent to the emergency power supply module to trigger emergency power supply, providing energy support for the fault information storage module and subsequent data processing of this module until the data is completely saved.

[0031] Step S400: Based on the stored logical fault information packet and / or power failure fault information packet, export the fault information and respond to the fault query request; filter the fault information according to the time range and fault type of logical fault or power failure; and simultaneously report the remaining storage space and media health status.

[0032] Furthermore, such as Figure 5 As shown, the process of exporting fault information and responding to fault query requests in step S400 includes the following steps: Step S401: Receive query conditions containing fault time range and fault type from external devices. Convert the fault time range in the query conditions into a range of start and end timestamps, and convert the fault type into a fault type identifier code. Using the start and end timestamps as the first-level filtering conditions, read the index records of all logical fault information packets and power failure fault information packets whose timestamps fall within this range to obtain a preliminary set of filtered index records. Step S402: Compare the fault type identifier code corresponding to each index record in the initially filtered index record set with the fault type identifier code in the query conditions, and remove the index records whose fault type identifier codes do not match to obtain the final filtered index record set; according to the index records in the final filtered index record set, read the corresponding logical fault information packets or power failure fault information packets in sequence, and arrange all the read fault information packets in ascending order of timestamp to form a fault information packet sequence to be exported; Step S403: Unpack each fault information packet in the sequence of fault information packets to be exported according to the preset export format, convert the timestamp and fault type identifier in the packet header field into a readable time string and fault type description, convert the binary data in the thread context field and logical context field into text or table format field values, and generate an export file; at the same time, read the remaining storage space value and media health status value fed back by the fault information storage module, and append the remaining storage space value and media health status value to the end of the export file to form a complete export data stream containing fault information and status information.

[0033] In this embodiment, the interface for exchanging fault information with external devices facilitates maintenance personnel in obtaining and analyzing fault data. Specific functions include: data export, providing an Ethernet interface (e.g., Modbus TCP protocol) or a USB interface, allowing maintenance personnel to export fault information from the storage module via a host computer (e.g., an industrial computer, a touchscreen), or an external storage device (e.g., a USB flash drive). Export formats support common text formats (e.g., TXT) or table formats (e.g., CSV) for easy reading by analysis software; fault query, supporting input of query conditions such as fault time range and fault type via the interactive interface to filter corresponding fault information from the storage module and feed it back to the host computer, enabling rapid fault location; and status feedback, providing real-time feedback to the PLC main control unit or host computer on the status of the fault information storage module, such as remaining storage space and storage media health status. When storage space is insufficient or the media is abnormal, an early warning signal is issued to remind maintenance personnel to handle the situation promptly.

[0034] Steps S100-S400 in this embodiment include: Logic fault capture software: A fault interrupt driver is embedded in the operating system of the PLC's main control unit. When a logic fault is detected, an interrupt is triggered and the programmable gate array FPGA is notified to capture the thread context. At the same time, the logic context data is read through the PLC's variable access interface and encapsulated into a standardized information packet. Power failure handling software: Write a power monitoring program in the ARM Cortex-M4 microcontroller to process voltage / current sensor data in real time. Based on a preset threshold, such as a normal power supply voltage of 24V, when the voltage is lower than 18V, it is determined to be a power failure and triggers the power failure handling process, calling the logic context to read the interface and store the interface. Storage management software: Divide the FRAM chip into logical fault partitions and power failure fault partitions, write data storage and verification programs, and realize the classified storage, CRC verification and integrity confirmation of fault information; Interactive software: Develop fault information management software in the host computer, which supports communication with the interactive module via Modbus TCP protocol to realize the export, query and display of fault information. The software interface provides a list and detailed display of fault time, type and context data.

[0035] The emergency power supply module in this embodiment provides energy assurance for the PLC fault recording system. It is connected to the PLC main power supply and various fault handling modules. Its specific functions include: energy storage, using a rechargeable battery on the PLC board, such as a lithium thionyl chloride battery, which has long-term low-power supply capability, or a large-capacity capacitor, such as a supercapacitor, which has fast charging and discharging capability, as an energy storage carrier. During normal power supply, the PLC main power supply charges the battery / capacitor to maintain a fully charged state; emergency start: after receiving the start command from the power failure fault information capture module, it immediately switches the power supply path, with the battery / capacitor providing power to the logic fault information capture module. If data processing, the power failure fault information capture module, and the fault information storage module are still required, the power supply duration is sufficient for complete storage of fault information until the storage module confirms that the data has been saved; power supply monitoring: it monitors the remaining power of the emergency power supply in real time. When the power is insufficient, it sends a priority data saving command to the fault information storage module to ensure that core fault information is stored first.

[0036] This embodiment uses a non-volatile storage medium for long-term, reliable storage of fault information. Specific functions include: Storage medium selection: FRAM (Ferroelectric RAM) or EEPROM (Electrically Erasable Programmable Read-Only Memory) is used as the main storage medium, featuring data retention after power failure, fast read / write speed, and long erase / write lifespan, preventing fault information loss due to storage medium issues; Data classification storage: Two types of fault information storage partitions are established—a logical fault partition and a power failure fault partition—to store logical fault information packets and power failure fault information packets respectively. The format of the power failure fault information packet is power failure reason-timestamp-logical context. Each fault information packet is accompanied by a unique identifier, such as a timestamp + fault type code, facilitating subsequent querying and correlation analysis; Data integrity verification: When receiving fault information packets, a CRC (Cyclic Redundancy Check) algorithm is used to verify the data, ensuring no damage during data transmission; After data saving is completed, a data saving confirmation signal is generated and fed back to the corresponding capture module to ensure reliable data storage.

[0037] This embodiment integrates monitoring and capture mechanisms for two scenarios: logical operation failures and abnormal power outages, forming a complementary fault recording system. It monitors program running status and power supply voltage in real time, ensuring the complete preservation of threads and logical contexts during logical failures and maintaining the capture and storage of critical data with the help of emergency power during abnormal power outages. The verification and storage process for logical failure information packets and power outage information packets adopts a unified data integrity verification mechanism, improving the reliability and traceability of fault information. Through high-frequency sampling and threshold determination using voltage and current sensors, it achieves rapid identification of power outage causes and context capture, avoiding the loss of fault information due to power interruption. It achieves full-process coverage from fault occurrence to information storage, providing a structured and highly reliable data foundation for fault diagnosis and system recovery.

[0038] This embodiment achieves comprehensive PLC fault information: for PLC logic operation faults, it achieves complete capture of thread context and logical context for the first time, enabling the reconstruction of the program's running state at the time of the fault; for abnormal power outage faults, it not only records the logical context but also identifies and records the cause of the power outage, solving the problem of fragmented fault information in existing technologies and providing a complete basis for fault location. Data storage reliability is ensured by using an emergency power supply module with batteries or large capacitors to provide temporary energy, ensuring that fault information is completely preserved during power outages; non-volatile storage media FRAM / EEPROM are used to prevent the loss of fault information due to power outages or damage to the storage media, ensuring long-term traceability of fault information. Maintenance convenience is achieved through a fault information interaction module, enabling standardized export and precise query of fault information. Maintenance personnel can quickly obtain fault data without disassembling the PLC or relying on specialized software, significantly reducing the difficulty of fault diagnosis and shortening downtime. System compatibility: This system adopts a modular design and can be adapted to different brands and models of PLCs, such as Siemens, Beckhoff, and Inovance. Only the module connection method needs to be adjusted according to the PLC main control unit interface. There is no need to make major modifications to the original PLC control program, which has good compatibility and scalability.

[0039] like Figure 6 As shown, the PLC fault information recording system provided in this embodiment of the invention includes: The logic fault information capture module is connected to the programmable logic controller (PLC) main control unit. It is used to detect PLC logic operation faults, capture the thread context and logic context at the time of the logic operation fault, and generate a logic fault information packet.

[0040] The logic fault information capture module includes a fault detection unit, a thread context capture unit, a logic context capture unit, and a data preprocessing unit. The logic fault information capture module monitors the PLC program's running status in real time; it determines whether a logic fault is detected, such as accessing an abnormal address or a program crash; if not, it continues monitoring; if yes, it triggers thread context capture, reading the PC pointer, register values, and function call stack; it synchronously triggers logic context capture, reading variable values, I / O status, and timer / counter status; it encapsulates the thread context and logic context into a logic fault information packet, attaching a timestamp and fault type code; it sends the logic fault information packet to the fault information storage module via the internal data bus; the fault information storage module receives the data, performs CRC verification, and stores it in the logic fault partition; the storage module generates a data saving confirmation signal and sends it back to the logic fault information capture module; the logic fault information capture module receives the confirmation signal, and the logic fault handling process ends. The fault detection unit is used to monitor the running status of the PLC program and identify the types of logical operation faults. The types of logical operation faults include accessing abnormal addresses, program logic conflicts, and program crashes caused by software abnormalities. The thread context capture unit is used to read the program counter (PC) pointer, general-purpose register values, and function call stack at the time of the fault. The logical context capture unit is used to read the values ​​of key variables, I / O interface status, and current values ​​of timers / counters at the time of a fault. The data preprocessing unit is used to encapsulate the thread context and logical context into a logical fault information packet, and attach a timestamp and fault type code; In this embodiment, comprehensive capture and structured recording of PLC program logic execution faults are achieved. The fault detection unit continuously monitors the operating status, identifying fault types such as accessing abnormal addresses, program logic conflicts, and crashes caused by software anomalies, providing triggering conditions for subsequent capture. The thread context capture unit instantly reads the program counter pointer, general-purpose register values, and function call stack information when a fault occurs, preserving the execution context at the processor level. The logic context capture unit synchronously collects key variable values, I / O interface status, and real-time values ​​of timers and counters, saving the data state at the program logic level. The data preprocessing unit encapsulates the thread context and logic context into a logic fault information package, attaching a precise timestamp and fault type code to form a complete and orderly fault snapshot. Overall, the system can simultaneously capture the hardware execution context and software logic state at the moment a fault occurs, generating structured fault information with timestamps and type classifications, providing a comprehensive and traceable data foundation for subsequent fault analysis, diagnosis, and program debugging.

[0041] The power failure information capture module is connected to the power interface of the programmable logic controller (PLC) and the emergency power supply module. It is used to detect abnormal power failure events of the PLC, identify the cause of the power failure, capture the logic context before the power failure, generate a power failure information package, and trigger the emergency power supply module to start.

[0042] The power outage fault information capture module includes a power outage detection unit, a power outage cause identification unit, a logic context capture unit, and an emergency linkage unit. The module monitors the PLC power supply voltage in real time using a voltage sensor; it determines whether a voltage drop or interruption is detected, indicating an abnormal power outage; if not, it continues monitoring; if yes, it sends a start command to the emergency power supply module to switch to emergency power supply; it collects power parameters before the power outage using voltage / current sensors to identify the cause of the power outage (overvoltage / undervoltage / short circuit, etc.); it captures the current logic context of the PLC, variable values, IO status, and timer / counter status; it encapsulates the power outage cause, timestamp, and logic context into a power outage fault information packet; and it sends the power outage fault information packet to the fault information storage module via the internal data bus; the fault information storage module receives the data, performs CRC verification, and stores it in the power outage fault partition; the storage module generates a data save confirmation signal and feeds it back to the power outage fault information capture module; the power outage fault information capture module receives the confirmation signal and sends a power supply stop command to the emergency power supply module; the emergency power supply module stops supplying power, and the abnormal power outage fault handling process ends. The power failure detection unit is used to monitor the PLC power supply voltage through a voltage sensor and determine abnormal power failure events. The power outage cause identification unit is used to identify the cause of power outage by combining the power parameters collected by voltage and current sensors with preset rules; the causes of power outage include overvoltage, undervoltage, and short circuit. The logical context capture unit is used to read the values ​​of key variables, I / O interface status, and current values ​​of timers / counters before power failure. The emergency response unit is used to send a start command to the emergency power supply module; In this embodiment, the monitoring, analysis, and emergency response to abnormal power outage events in the PLC are implemented. The power outage detection unit continuously monitors the supply voltage using a voltage sensor to accurately determine the occurrence of an abnormal power outage event. The power outage cause identification unit, combining power parameters collected by voltage and current sensors, identifies the cause of the power outage as overvoltage, undervoltage, or short circuit according to preset rules, providing a basis for fault classification. The logic context capture unit reads key variable values, IO interface status, and the current values ​​of timers and counters instantaneously before the power outage, saving the program logic state at the moment of power outage. The emergency linkage unit sends a start command to the emergency power supply module based on the identification results, triggering the backup power supply switch. Overall, the system enables rapid diagnosis and continuous operation assurance throughout the entire process from monitoring power outage events, identifying the cause of power outages, saving the logic context, to initiating emergency power supply, providing support for system reliability maintenance and fault tracing.

[0043] The emergency power supply module, connected to the logic fault information capture module, the power outage fault information capture module, and the fault information storage module, is used to provide temporary power supply during abnormal power outages and ensure the complete storage of fault information.

[0044] The emergency power supply module includes an energy storage unit, an emergency start-up unit, and a power supply monitoring unit. The energy storage unit is used to charge the PLC main power supply when the onboard rechargeable battery or large-capacity capacitor is in normal power supply. The emergency start unit is used to receive instructions from the power failure information capture module and switch to emergency power supply; The power supply monitoring unit is used to monitor the remaining power of the emergency power supply and send a priority saving instruction to the fault information storage module; In this embodiment, complete emergency power supply and status management capabilities are provided for PLC abnormal power outage scenarios. The energy storage unit, via an onboard rechargeable battery or large-capacity capacitor, is charged by the main power supply during normal power supply periods to store emergency power. The emergency start unit receives instructions from the power outage fault information capture module to achieve rapid switching from main power to emergency power, ensuring the continuous operation of critical circuits. The power supply monitoring unit continuously monitors the remaining emergency power and sends a priority saving instruction to the fault information storage module when the power is insufficient, ensuring that critical data is written to non-volatile memory in a timely manner. Overall, the system can automatically switch to backup power when the main power is abnormally interrupted, maintaining the operation of some critical PLC functions. Through power monitoring and storage priority control, the system maximizes the protection of program status and fault information, improving data integrity and recoverability during power outages.

[0045] The fault information storage module is used to connect with the logic fault information capture module and the power failure fault information capture module via the internal data bus, and is used to store logic fault information packets and power failure fault information packets.

[0046] The fault information storage module uses a non-volatile storage medium, which is either FRAM or EEPROM. The fault information storage module is divided into a logical fault partition and a power failure fault partition, which store logical fault information packets and power failure fault information packets respectively, and the data integrity is verified by the CRC algorithm.

[0047] In this embodiment, logical fault and power failure information is classified, stored, and protected for integrity. Non-volatile storage media, such as FRAM or EEPROM, are used to ensure long-term data retention after power failure. By dividing the system into logical fault and power failure partitions, logical fault information packets and power failure information packets are stored separately, facilitating classification management and rapid retrieval. A CRC algorithm is used to verify the integrity of the stored data, detecting and identifying potential storage errors or data corruption. Overall, the system reliably stores two types of critical fault information, ensuring a clear structure and complete content in non-volatile storage, providing an accurate and durable data foundation for fault analysis, system diagnosis, and reliability improvement.

[0048] The fault information interaction module is connected to the fault information storage module and is used to export fault information and respond to fault query requests.

[0049] The fault information interaction module includes a data export unit, a fault query unit, and a status feedback unit. The data export unit is used to export fault information via Ethernet or USB interface, supporting TXT or CSV format. The fault query unit is used to support filtering fault information based on fault time range and fault type. The status feedback unit is used to provide feedback on the remaining storage space and media health status of the fault information storage module. In this embodiment, flexible output, filtering, and storage status management of stored fault information are achieved. The data export unit supports exporting fault information in TXT or CSV format via Ethernet or USB interfaces, facilitating cross-platform reading and subsequent analysis. The fault query unit allows filtering based on fault time range and fault type, quickly locating specific fault records and improving diagnostic efficiency. The status feedback unit monitors the remaining storage space and media health status of the fault information storage module, providing a basis for storage capacity planning and media maintenance. Overall, the system can transform internally stored fault data into exportable and queryable structured information, and achieve visualized management of storage resources through status feedback, thereby supporting efficient system maintenance, fault tracing, and data analysis.

[0050] The system in this embodiment includes the following stages: During normal operation: the supercapacitor and lithium battery of the emergency power supply module are fully charged; the logic fault information capture module and the power failure fault information capture module continuously monitor the PLC status; the fault information storage module is in standby mode.

[0051] During the logic fault occurrence phase: When the PLC encounters an abnormal address that causes the program to crash, the logic fault information capture module triggers an interrupt. Within 100 microseconds, it captures and records the PC pointer at the crash location, the value of the operation data register, and the function call stack of the call path. Simultaneously, it reads the global variable production count and the status of the IO interface conveyor belt start / stop signal, encapsulates them into a logic fault information packet, and sends it to the storage module for storage.

[0052] Abnormal power outage stage: When the external power supply to the PLC is interrupted, the power outage fault information capture module detects that the voltage drops suddenly from 24V to 0V, determines that the power is interrupted, and immediately starts the emergency power supply module. Within 50 microseconds, it captures the logical context, such as the current production batch and equipment operating mode, encapsulates it into a power outage fault information packet, and sends it to the storage module for storage; after storage is completed, the emergency power supply module stops supplying power.

[0053] During the troubleshooting phase: maintenance personnel connect to the fault information interaction module via the host computer, query fault records from the past month, export logical fault information packages, reconstruct the program crash path through the function call stack, and locate the logical error of accessing undefined data blocks by combining variable values; export power outage fault information packages, confirm that the cause of the power outage is an external power interruption, and confirm that the equipment was in normal production mode when the fault occurred by combining the logical context, which is convenient for subsequent development of power backup plans.

[0054] In this embodiment, the logic fault capture module monitors the operating status of the PLC main control unit, captures the thread context and logic context in real time when logic anomalies occur, and forms a structured fault data packet to ensure that runtime logic faults are traceable. The power failure fault capture module monitors the power supply status and identifies the cause of the power failure. It saves the logic context at the moment of abnormal power failure and triggers the emergency power supply module to start temporary power supply, so that the fault data can be completely written to the storage module, avoiding data loss due to power failure. The fault information storage module receives and stores the two types of fault data packets through the internal data bus, establishes a fault archive database with timestamp indexes, and ensures that the data is still accessible after the system restarts. The fault information interaction module provides a standardized data export interface and query protocol, supporting maintenance personnel to analyze historical faults offline or retrieve real-time fault records online, providing a complete data foundation for fault root cause analysis. The modules work together to form a closed loop of fault monitoring-capture-storage-output, realizing the full life cycle recording of PLC hardware and software faults, significantly improving the maintainability and operational continuity of the industrial control system.

[0055] In the above embodiments, the logic fault information capture module uses a Field-Programmable Gate Array (FPGA) as its core processing chip, connected to the PLC main control unit via a PCIe interface to receive PLC program execution data in real time. The FPGA integrates fault detection logic, enabling it to respond to PLC fault interrupt signals in microseconds and quickly capture thread and logic contexts. The power failure fault information capture module uses a Hall effect voltage sensor connected in series with the PLC main power supply circuit to collect the supply voltage in real time; a shunt-type current sensor is connected in parallel with the power supply circuit to collect current changes. The module's core processor is an ARM Cortex-M4 microcontroller, linked to the emergency power supply module via an SPI interface. The emergency power supply module uses a combination of supercapacitors and rechargeable lithium batteries. The supercapacitor capacity meets the instantaneous high-current power supply requirements, supporting rapid data writing to the fault information storage module. The lithium battery meets the long-term low-power supply requirements, preventing data loss when the supercapacitor's power is insufficient. The module has a built-in charging management chip that automatically charges the capacitor and battery during normal power supply. Fault Information Storage Module: Uses an FRAM chip as the main storage medium. The storage capacity is configured according to the PLC's fault record requirements, such as supporting the storage of over 1000 fault information entries. The chip connects to the internal data bus via an I2C interface, supporting high-speed data writing and reading. Fault Information Interaction Module: Integrates an Ethernet controller, supporting Modbus TCP protocol and USB 2.0 interface. It communicates with the host computer via an RJ45 network port and connects to external storage devices via a USB interface. The module core uses an ARM Cortex-A7 processor, supporting fault information format conversion and query processing.

[0056] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or its equivalents are included in this invention.

[0057] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0058] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0059] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0060] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for recording PLC fault information, characterized in that, Includes the following steps: Obtain the program running status and power supply voltage of the programmable logic controller; When a logical operation failure is detected during program execution, the thread context and logical context at the moment the logical operation failure occurs are captured; when the power supply voltage reaches the abnormal power outage threshold, emergency power supply is activated, the cause of the power outage is identified, and the logical context before the power outage is captured. The thread context and logical context are encapsulated into a logical fault information packet, and the logical context before the power failure is encapsulated into a power failure fault information packet.

2. The PLC fault information recording method as described in claim 1, characterized in that, The process of encapsulating thread context and logical context into a logical fault information packet includes the following steps: By linking with the fault interrupt interface of the main control unit of the programmable logic controller, the current fault type of accessing abnormal address or program crash is identified, and the current fault type is converted into a fixed-length fault type identifier code. The fault type identifier code is then concatenated with the fault time timestamp output by the internal real-time clock of the logic fault information capture to form the header field of the logic fault information packet. At the moment a fault interrupt is triggered, logic fault information is captured by using a hardware probe and a processor debugging interface to read in parallel the current value of the program counter pointer, the current value of the general-purpose register set, and the current stored content of the function call stack from the processor of the main control unit of the programmable logic controller. The current value of the program counter pointer, the current value of the general-purpose register set, and the current stored content of the function call stack are arranged in a preset register order to form a thread context field, and the thread context field is appended to the packet header field. While reading the thread context, the current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters are read from the data bus of the programmable logic controller main control unit. The current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters are arranged in the order of variable addresses to form a logical context field. The logical context field is then appended to the thread context field to obtain a logical fault information packet composed of a packet header field, a thread context field, and a logical context field concatenated in sequence.

3. The PLC fault information recording method as described in claim 2, characterized in that, The process of obtaining a logical fault information packet, which is composed of a header field, a thread context field, and a logical context field concatenated sequentially, includes the following steps: The identified access exception address, program logic conflict or software exception corresponding to the fault type are mapped to three sets of non-overlapping fault type identification codes; the fault type identification codes and the timestamp read from the real-time clock at the time of the fault interrupt interface are bit-interleaved, so that each bit of the binary value of the timestamp is inserted between the corresponding bits of the fault type identification code to form the packet header field. At the moment of fault interruption, the current value of the program counter pointer, the current value of the general-purpose register set, and the current storage content of the function call stack are read in parallel from the processor of the main control unit of the programmable logic controller through the hardware probe and the processor debugging interface. The current value of the program counter pointer is used as the root node, the current value of the general-purpose register set is appended to the root node as the first-level child node according to the register number order, and the current storage content of the function call stack is appended to the first-level child node as the second-level child node according to the call depth from deep to shallow, forming a thread context field with a three-level tree structure. The thread context field is then appended to the packet header field. While reading the thread context through the hardware probe and processor debugging interface, the same hardware probe reads the current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters from the data bus of the programmable logic controller (PLC) main control unit. The read current values ​​of key variables are arranged in order of their offset addresses in the data block, the input / output interface status values ​​are arranged in order of their interface numbers, and the current values ​​of timers and counters are arranged in order of their timer and counter numbers. The three arrangements are then concatenated to form a logical context field. Each byte value in the logical context field is XORed with the corresponding byte value in the thread context field. The result of the XOR operation replaces the original byte value in the logical context field, resulting in a verified and associated logical context field. This verified and associated logical context field is then appended to the thread context field, resulting in a logical fault information packet composed of a header field, a thread context field, and a logical context field concatenated sequentially.

4. The PLC fault information recording method as described in claim 1, characterized in that, The process of encapsulating a power failure information packet into a logical context includes the following steps: The power outage cause corresponding to the voltage descent rate exceeding the limit event, overvoltage judgment flag, undervoltage judgment flag, or short circuit judgment flag is converted into a fixed-length power outage cause identification code; the power outage cause identification code and the power outage detection time timestamp output by the real-time clock inside the power outage fault information capture module are bit-interleaved, so that each bit of the binary value of the timestamp is inserted between the corresponding bits of the power outage cause identification code, forming the header field of the power outage fault information packet; After receiving a trigger signal, the power failure information capture module reads the current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters from the data bus of the programmable logic controller main control unit through the same hardware probe. The current values ​​of key variables are arranged in order of their offset addresses in the data block, the input / output interface status values ​​are arranged in order of their interface numbers, and the current values ​​of timers and counters are arranged in order of their timer and counter numbers. The three arrangements are then concatenated to form a logical context field. Perform an XOR operation on each byte value in the logical context field and the corresponding byte value in the system configuration field pre-stored inside the power failure fault information capture module. Replace the original byte value in the logical context field with the XOR operation result to obtain the verified and associated logical context field. Concatenate the packet header field and the verified and associated logical context field in sequence to obtain the power failure fault information packet composed of the packet header field and the logical context field.

5. The PLC fault information recording method as described in claim 4, characterized in that, The process of reading the current values ​​of key variables, input / output interface status values, and current values ​​of timers and counters from the data bus of the programmable logic controller's main control unit using the same hardware probe includes the following steps: After receiving a voltage descent rate exceeding the limit event, the power failure information capture module uses the analog value output by the voltage change rate extraction circuit corresponding to the voltage descent rate exceeding the limit event as the sampling depth coefficient. The address interval for reading the current value of key variables from the main control unit data bus of the programmable logic controller is determined based on the sampling depth coefficient. The larger the sampling depth coefficient, the larger the address interval. When the address interval increases, intermediate variables located between adjacent addresses are skipped, and only the current value of the key variable selected by the interval is read, so as to obtain a compressed key variable value sequence associated with the magnitude of the voltage descent rate over-limit event. After receiving the undervoltage judgment flag, the power failure information capture module retrieves the set of interface numbers associated with the undervoltage fault based on the input of the undervoltage judgment flag. The set of interface numbers includes the numbers of the power supply monitoring interface, the power status feedback interface, and the voltage sampling interface. According to the order in the set of interface numbers, the module reads the input and output interface status values ​​corresponding to the interface numbers from the data bus of the programmable logic controller main control unit through hardware probes to obtain the sequence of interface status values ​​associated with the undervoltage fault. After receiving the short-circuit judgment flag, the power failure information capture module reads the current values ​​of all timers and counters from the data bus of the programmable logic controller main control unit according to the input of the short-circuit judgment flag. At the same time, it compares the voltage fluctuation amplitude on the data bus during the reading process with the preset reading stability threshold. When the voltage fluctuation amplitude on the data bus exceeds the reading stability threshold, the reading operation is paused, and the current values ​​of the timers and counters that have been read are locked as valid data in the reading order. The current values ​​of the unread timers and counters are replaced with the default values ​​pre-stored in the system configuration field, resulting in a sequence of timer and counter values ​​formed by concatenating the read valid data and the default values.

6. The PLC fault information recording method as described in claim 5, characterized in that, The process of using the analog value output by the voltage change rate extraction circuit corresponding to the voltage descent rate exceeding the limit event as the sampling depth coefficient includes the following steps: The power failure information capture module receives analog values ​​from the output of the voltage change rate extraction circuit and inputs the analog values ​​into the internal preset quantization mapping table. The quantization mapping table stores the correspondence between analog value ranges and digital quantization levels. The quantization mapping table outputs the corresponding digital quantization level according to the range to which the analog value belongs, thus obtaining the digital quantization level value corresponding to the voltage change rate amplitude. Obtain the reference level value corresponding to the digital quantization level value and the preset slope threshold stored in the power failure fault information capture module. Calculate the difference between the digital quantization level value and the reference level value, and compare the difference with zero. When the difference is positive, output the excess amplitude value, which is the difference between the digital quantization level value and the reference level value. When the difference is less than or equal to zero, output zero as the excess amplitude value. Based on the inverse mapping relationship between the amplitude range and the sampling depth coefficient, the sampling depth coefficient corresponding to the range to which the amplitude value exceeds is obtained, and the sampling depth coefficient is output to the address interval selector as the control parameter for address interval selection.

7. The PLC fault information recording method as described in claim 6, characterized in that, The process based on the inverse mapping relationship between the amplitude range and the sampling depth coefficient includes the following steps: The possible range of values ​​exceeding the amplitude value is divided into multiple consecutive amplitude exceeding intervals, each amplitude exceeding interval corresponding to an interval number; the maximum possible amplitude exceeding the preset slope threshold in the voltage descent rate exceeding event is taken as the upper limit value, and zero is taken as the lower limit value. The intervals are divided in ascending order of the magnitude of the exceedance, and the number of intervals is equal to the number of preset sampling depth coefficient levels. Each interval is assigned a unique interval number. Establish a sampling depth coefficient level sequence, with values ​​arranged in descending order. The number of levels is equal to the number of amplitude ranges exceeded. The first level in the sampling depth coefficient level sequence corresponds to the largest sampling depth coefficient, and the last level corresponds to the smallest sampling depth coefficient. Then, map the amplitude range numbers to the levels in the sampling depth coefficient level sequence in sequence. The smaller the range number, the larger the corresponding sampling depth coefficient level value, and vice versa. This forms an inverse correspondence between the amplitude range numbers and the sampling depth coefficients. The inverse correspondence between the amplitude exceedance interval number and the sampling depth coefficient level is fixed in the mapping storage area inside the depth coefficient generation unit. The mapping storage area uses the interval number as the index address, and each index address stores the corresponding sampling depth coefficient level value. After determining the interval number to which the input amplitude exceedance value belongs, the depth coefficient generation unit reads the corresponding sampling depth coefficient level value from the mapping storage area using the interval number as the index address, and uses the sampling depth coefficient level value as the output sampling depth coefficient.

8. The PLC fault information recording method as described in claim 7, characterized in that, The process of sequentially mapping the amplitude range numbers to the levels in the sampling depth coefficient level sequence includes the following steps: Arrange the interval numbers beyond the amplitude range in ascending order of value to form an interval number list; arrange the sampling depth coefficient level sequence in descending order of value to form a level list; create an empty mapping table containing an interval number field and a level value field; write the first interval number in the interval number list and the first level value in the level list into the first record of the mapping table. Write the second interval number in the interval number list and the second gear value in the gear list into the second record of the mapping table. Write them in the order of the interval number list and the gear list until all interval numbers in the interval number list have been written, forming a mapping table in which the interval numbers and gear values ​​correspond in order. The mapping table is stored in the data storage area accessible to the depth coefficient generator. The data storage area uses the interval number as the index key value, and each index key value corresponds to a gear value. After receiving the excess amplitude value and determining its interval number, the depth coefficient generator retrieves the corresponding gear value from the data storage area using the interval number as the index key value, and uses the retrieved gear value as the output sampling depth coefficient.

9. The PLC fault information recording method as described in claim 8, characterized in that, The process of using range numbers as index keys in a data storage area includes the following steps: Convert all interval numbers in the interval number list into fixed-length binary key values. Each interval number corresponds to a unique binary key value. All binary key values ​​are arranged in ascending order of interval number to form a key value sequence. Extract the gear position values ​​corresponding to the interval numbers in the mapping table in the same order as the interval numbers to form a value sequence. Write the key value sequence and the value sequence in pairs into a key value storage area. The key value storage area uses each key value in the key value sequence as a storage index. Each index position stores the corresponding gear position value, forming a direct mapping structure between key values ​​and gear position values. A hash index table is built on top of the key-value storage area. The hash index table contains multiple hash buckets. Each hash bucket corresponds to a binary key value of a range number, which is calculated by a hash function to obtain the hash value. The binary key value of each range number and its corresponding digit value are stored in the corresponding hash bucket. The hash buckets are sorted according to the size of the range number, forming a two-level retrieval structure with the hash value as the first-level index and the range number as the second-level index. After receiving the value exceeding the amplitude and determining its interval number, the depth coefficient generation unit inputs the binary key value of the interval number into the hash function to obtain the hash value. Based on the hash value, it locates the corresponding hash bucket in the hash index table. Within the hash bucket, it uses a binary search method with the binary key value of the interval number as the keyword to retrieve the corresponding gear value. The retrieved gear value is then used as the output sampling depth coefficient.

10. A PLC fault information recording system, used to implement the PLC fault information recording method according to any one of claims 1-9, characterized in that, Include: The logic fault information capture module is connected to the programmable logic controller (PLC) main control unit. It is used to detect PLC logic operation faults, capture the thread context and logic context at the time of the logic operation fault, and generate a logic fault information packet. The power failure information capture module is connected to the power interface of the programmable logic controller (PLC) and the emergency power supply module. It is used to detect abnormal power failure events of the PLC, identify the cause of the power failure, capture the logic context before the power failure, generate a power failure information package, and trigger the emergency power supply module to start. The emergency power supply module, connected to the logic fault information capture module, the power outage fault information capture module, and the fault information storage module, is used to provide temporary power supply in case of abnormal power outage and ensure complete storage of fault information. The fault information storage module is used to connect with the logic fault information capture module and the power failure fault information capture module via the internal data bus, and is used to store logic fault information packets and power failure fault information packets. The fault information interaction module is connected to the fault information storage module and is used to export fault information and respond to fault query requests.

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