High-dimensional four-value logic-based scalable bit-width parallel computing device and operation method

Abstract

The application belongs to the technical field of computer architecture, multi-value logic operation and super large scale parallel computing, and discloses a scalable bit width parallel computing device and operation method based on high-dimensional four-value logic, aiming at the defects of fixed bit width, poor expansion capability, and difficult to balance cost and performance of the existing computing architecture; the device adopts a 6400-bit four-value logic operation unit, a 2300-bit MSD carry-free adder and 4.3 billion pieces of hardware parallel logic rule base, and can realize super wide range operation of 50-bit to 50000-bit and larger bit number through bit width dynamic configuration, segmented operation, pipeline cascading and module stacking, while supporting 10 / 70 / 100-bit and other lightweight economic operation; the device is engineering realizable, stable and mass producible, has high parallelism, strong operation certainty and room temperature operation, and is suitable for high-end computing scenes such as password cracking, big data optimization and artificial intelligence, and has controllable cost and future scalability.

Description

Technical Field

[0001] This invention relates to computer architecture, and in particular to a scalable bit-width parallel computing device and operation method based on high-dimensional four-valued logic. Background Technology

[0002] The current computer field is mainly divided into two major technical routes: traditional binary computers and quantum computers. Both have insurmountable technical bottlenecks, and existing multi-valued logic computing devices have not resolved the core contradiction between bit width expansion and cost control. The specific shortcomings are as follows: I. Traditional binary computers: They adopt a binary logic architecture with a fixed bit width (such as 32-bit, 64-bit, 128-bit). The improvement of computing power is highly dependent on the iteration of chip manufacturing process, and they cannot support both short-bit-width economical computing and ultra-high-bit-width high-computing-power computing on a unified hardware platform at the same time. If adapted to short-bit-width scenarios, the utilization rate of hardware resources is extremely low, resulting in cost waste. If adapted to ultra-high-bit-width scenarios, the chip needs to be redesigned, leading to the obsolescence of existing hardware and extremely high expansion costs. At the same time, the parallelism of binary logic is limited, making it difficult to meet the needs of ultra-large-scale computing.

[0003] II. Quantum Computers: Based on the superposition and entanglement properties of qubits, they achieve efficient computing and have a theoretical computing power far exceeding that of traditional binary computers. However, they are extremely difficult to engineer, require operation in extremely low temperature (close to absolute zero) environments, have high equipment costs, and have uncertain computation results. They cannot be adapted to scenarios with high computational determinism requirements, and it is difficult to achieve mass production and widespread adoption in the short term.

[0004] III. Existing multi-valued logic devices: Although they have overcome the limitations of binary logic and partially adopted a four-valued logic architecture, they have problems such as fixed bit width or limited expansion capabilities. They cannot achieve full-range compatibility of "short bit width - medium bit width - ultra-high bit width", and have not formed a standardized expansion architecture. It is difficult to balance engineering feasibility, cost controllability and future scalability, and cannot meet the differentiated computing needs of different scenarios.

[0005] Furthermore, existing parallel computing architectures (such as SIMD architecture) suffer from drawbacks such as ISA bloat, heavy compiler burden, large number of dynamic instructions, and high energy consumption. They also require additional bookkeeping code to handle edge cases, further limiting the flexibility and computational efficiency of bit-width expansion. While high-dimensional quantum computing can achieve an exponential increase in information capacity, it is difficult to engineer, relies on complex error correction mechanisms for noise resistance, and cannot achieve room-temperature operation and low-cost applications. This invention addresses all the shortcomings of the above-mentioned existing technologies by proposing a parallel computing scheme that balances engineering feasibility, cost control, ultra-wide bit-width compatibility, and future unlimited scalability. Summary of the Invention

[0006] In view of this, the present invention aims to solve the technical problems of existing computing architectures, such as high engineering difficulty, fixed bit width, poor scalability, difficulty in balancing cost and performance, and insufficient computational determinism.

[0007] The technical solution of this invention is implemented as follows: A scalable bit-width parallel computing device based on high-dimensional quaternary logic includes a 6400-bit quaternary logic operation unit, a 2300-bit MSD carry-free adder, a C hardware parallel logic rule base, a bit-width dynamic configuration module, and a standardized extension interface. The device can support operations of 50 bits to 50000 bits and larger, and can selectively implement lightweight and economical operation of 50 bits, 70 bits, and 100 bits, and can complete bit-width switching and expansion without replacing hardware.

[0008] Preferably, the 6400-bit four-valued logic operation unit adopts a high-dimensional four-valued logic architecture, with the four-valued logic variables taking values ​​of {0, 1, 2, 3}, corresponding to two binary bits (00, 01, 10, 11). The operation logic is provided by a hardware parallel logic rule library of approximately 4.3 billion logic rules per bit, and the core operation expression is: Where A and B are input four-value variables, C is output four-value variable, and f is a preset logical function in the rule base.

[0009] Preferably, the 2300-bit MSD carry-free adder adopts the modified signed digit (MSD) number system, utilizing its redundancy characteristics to eliminate carry propagation chains. The core summation formula is as follows: in , , These are the i-th bits of the two input quaternary numbers, and g is the MSD no-carry addition logic, which works in conjunction with the 6400-bit quaternary logic arithmetic unit.

[0010] Preferably, the hardware parallel logic rule library with approximately 4.3 billion logic rules per bit uses high-speed ROM storage, is divided into a short bit-width rule subset, a standard rule subset, and an ultra-high bit-width rule subset, supports dynamic scheduling, and reserves space for rule expansion, so that new logic rules can be added according to future computing needs.

[0011] Preferably, the bit width dynamic configuration module is implemented using an FPGA chip and a custom chip. It can automatically detect the bit width requirements and operation type of the computing task, dynamically allocate hardware resources, and achieve seamless switching between short bit width, medium bit width, and ultra-long bit width modes. In the short bit width mode, redundant hardware resources can be put to sleep to reduce energy consumption.

[0012] Preferably, the standardized expansion interface adopts a high-speed PCIe 4.0 interface and a direct connection interface, which supports the stacking and cascading of multiple computing devices. Each device acts as an independent expansion module, working together to complete ultra-high bit-width operations. The expansion process does not require modification of the existing hardware core structure.

[0013] Preferably, in the lightweight and economical operating mode, the 6400-bit quaternary logic device consumes ≤30W, has a hardware resource utilization rate ≥90%, and a computational latency ≤1ns, making it suitable for low-cost, low-power embedded devices and simple data processing scenarios.

[0014] Preferably, a scalable bit-width parallel computing method based on high-dimensional four-valued logic is provided. Includes the following steps: Step 1: Input the computation task; the bit width dynamic configuration module detects the bit width requirement and computation type of the task. Step 2: Dynamically configure hardware resources according to bit width requirements and call the corresponding subset of logical rules; Step 3: The quaternary logic unit and the MSD carry-free adder work together to complete the calculation task; Step 4: When performing ultra-long bit-width operations, the operation results are integrated through segmented operations, pipeline cascading, and module stacking. Step 5: Output the calculation results and restore hardware resources to standby mode.

[0015] Preferably, in the segmentation process of the ultra-long bit-width operation, 6400 bits are divided into a segment, and the ultra-high bit-width data is divided into several independent sub-operation tasks. Each sub-operation task works collaboratively in a pipelined cascade manner, and data transmission and result connection are realized through a standardized interface.

[0016] Preferably, the method is adaptable to various application scenarios such as cryptography, big data optimization, artificial intelligence, quantum simulation, and embedded devices, with a computational accuracy of 100% and a computational efficiency that is 3-5 times higher than that of traditional binary computers.

[0017] The embodiments of the present invention have the following advantages due to the adoption of the above technical solutions: I. Strong engineering feasibility: The current 6400-bit hardware architecture adopts a standardized design with clear parameters and a reasonable structure. Based on mature quaternary logic circuit design technology (such as current-mode CMOS circuits), it can be stably mass-produced, solving the problems of high engineering difficulty of quantum computers and limited expansion of traditional binary computers. Moreover, the manufacturing cost is controllable and meets the needs of industrial production. 2. Excellent bit width expansion capability: Through the collaborative design of segmented operation, pipeline cascading, and module stacking, it achieves compatibility with an ultra-wide range of 50 bits to 50,000 bits and larger bits. In the future, it can be infinitely expanded through module stacking. Moreover, the expansion process does not require replacing existing hardware or eliminating existing equipment, which greatly reduces long-term application costs and solves the problems of poor expansion capability and waste of hardware iteration in the existing architecture. Third, it balances cost and performance: It supports 50-bit, 70-bit and 100-bit lightweight and economical operation. Through dynamic hibernation of hardware resources and simplified rule calling, it reduces energy consumption and cost in low computing scenarios. At the same time, it has high parallelism and excellent computing efficiency in ultra-high bit width mode, which can be adapted to high-end computing scenarios and achieve the unity of "low cost-high performance-scalability", filling the gap of existing technology. IV. High determinism and efficiency in computation: The system uses a hardware-fixed library of 4.3 billion parallel logic rules, which eliminates the need for software intervention during computation, thus avoiding the uncertainty of quantum computer computation results. At the same time, the MSD carry-free adder eliminates carry delay, and dynamic rule scheduling reduces redundant overhead. The computation efficiency is 3-5 times higher than that of traditional binary computers and 1.5-2 times higher than that of existing multi-valued logic devices. V. Wide compatibility and adaptability: Based on the natural compatibility between high-dimensional four-valued logic and binary logic, it can be directly adapted to existing binary computing software and data without large-scale software modification. At the same time, it supports the needs of different bit widths and different operation types, and is suitable for various scenarios such as cryptography, big data optimization, artificial intelligence, and embedded devices. Its application scope far exceeds that of existing computing devices. VI. Simple architecture and low maintenance cost: The hardware architecture adopts a standardized design, with each module having independent functions and strong synergy. Expansion and maintenance do not require modification of the core structure. At the same time, the rule base supports dynamic expansion, and new rules can be added according to future computing needs, reducing maintenance and upgrade costs and solving the problems of complex maintenance and high upgrade costs of the existing architecture.

[0018] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the invention will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a diagram of the core hardware architecture of the computing device of the present invention; Figure 2 This is a flowchart of the scalable bit-width operation mode of the present invention; Figure 3 This is a schematic diagram of the ultra-long bit-width segmented operation pipeline of the present invention; Figure 4 This is a diagram of the multi-device stacking extended architecture of the present invention; Figure 5 This is a timing diagram of the complete operation flow of the present invention. Detailed Implementation

[0021] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0022] It is important to note that terms such as "first," "second," "symmetric," and "array" are used only to distinguish between descriptive and positional descriptions and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified with terms such as "first" or "symmetric" may explicitly or implicitly include one or more of that feature; similarly, when the quantity of certain features is not limited by words such as "two" or "three," it should be noted that such features also explicitly or implicitly include one or more features. In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," and "fixation" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral molding; they can refer to a mechanical connection, a direct connection, a welding connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the accompanying drawings and specific circumstances.

[0023] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] like Figure 1-5 As shown, this invention provides a scalable bit-width parallel computing device based on high-dimensional four-valued logic and a corresponding operation method. The core idea is to construct standardized hardware units based on high-dimensional four-valued logic, and achieve full-range compatibility and infinite expansion of bit width through a collaborative design of segmented operation, pipeline cascading, rule-based dynamic scheduling, and module stacking. At the same time, lightweight and economical operation is achieved through dynamic configuration of hardware resources. The technical solution is coherent and each link is causally related, as detailed below: Hardware architecture design The current hardware of this computing device adopts a standardized design to ensure engineering feasibility and mass production, while reserving standardized interfaces for bit-width expansion. The specific hardware composition and parameters are as follows, and the design of each hardware unit addresses a specific technical problem: I. 6400-bit Quad-Valued Logic Operation Unit: As the core operation carrier, it adopts a high-dimensional quad-valued logic architecture. The quad-valued logic variables take values ​​{0, 1, 2, 3}, corresponding to two bits of binary logic (00, 01, 10, 11). It achieves compatibility with binary logic without complex logic conversions, and the information transmission volume is twice that of traditional binary operation units, with significantly improved parallelism. The operation logic of this unit is provided by a hardware parallel logic rule base, and the core operation expression is: Here, A and B are input four-valued variables, C is the output four-valued variable, and f is a preset logic function in the rule base, covering all basic operations of four-valued logic such as MAX, MIN, inversion, addition, and subtraction, which can be dynamically called according to computational needs. The 6400-bit fixed design not only meets the needs of current mainstream computing scenarios, but also serves as the basic unit for segmented operations, providing support for ultra-wide bit width expansion and solving the fundamental problems of engineering feasibility and bit width expansion.

[0025] II. 2300-bit MSD Carry-Free Adder: This adder, in conjunction with a four-valued logic unit, achieves efficient addition operations. It employs a modified Signed Digit (MSD) number system, leveraging its redundancy to completely eliminate the carry propagation chain of traditional addition, limiting carry propagation to an extremely small range. This significantly improves parallel computing efficiency and solves the technical bottleneck of carry delay in ultra-wide bit-width operations. Its core summation formula is: ,in , , These represent the i-th bits of the two input quaternions, respectively, and g is the MSD no-carry addition logic, ensuring the efficiency and determinism of the addition operation. The 2300-bit design works in conjunction with the 6400-bit quaternion logic arithmetic unit to balance computational efficiency and hardware cost, avoiding resource waste.

[0026] III. A hardware-based parallel logic rule base of 4.3 billion rules: This base stores all operational rules for high-dimensional four-valued logic, covering preset rules for different bit widths and operation types (logical and arithmetic operations). It supports dynamic scheduling—automatically calling the corresponding rule subset based on the current operation's bit width requirements and operation type, without requiring additional software compilation or bookkeeping code. This reduces computational overhead, improves operational efficiency, and solves the problems of instruction redundancy and complex scheduling in existing parallel architectures. The rule base adopts a hardware-fixed design to ensure deterministic operation, while reserving rule extension interfaces to add new logic rules according to future operational needs, providing support for unlimited expansion.

[0027] IV. Bit Width Dynamic Configuration Module: This module enables automatic switching between different bit width modes. It has a built-in bit width detection unit and resource scheduling unit. It can dynamically allocate hardware resources (quad-value logic operation unit, MSD carry-free adder, logic rule base) according to the bit width requirements of the input operation task. No manual intervention is required, achieving "allocation on demand" while balancing operation performance and energy consumption cost.

[0028] V. Standardized Expansion Interfaces: Module Cascading Interface and Rule Expansion Interface are set up. The module cascading interface is used to realize the stacking and cascading of multiple computing devices, and the rule expansion interface is used to supplement new operation rules, providing a standardized path for the unlimited expansion of bit width in the future and ensuring that existing hardware is not obsolete.

[0029] Bit width expansion implementation method This invention achieves full compatibility across a range of bit widths from 50 to 50,000 and even larger through a collaborative approach of "segmented operation + pipelined cascading + dynamic rule scheduling + module stacking." The steps are causally related, and the specific implementation process is as follows: I. Segmented Operation: For ultra-high bit width (over 6400 bits) operation tasks, the bit width dynamic configuration module divides the operation data into segments of 6400 bits each, splitting them into several independent sub-operation tasks. Each sub-operation task is completed by a 6400-bit four-valued logic operation unit and a 2300-bit MSD carry-free adder, avoiding the efficiency drop caused by the large amount of data in a single segment operation and solving the problem of the difficulty in implementing ultra-high bit width operations. 2. Pipeline Cascading: The segmented sub-operation tasks are cascaded in a pipeline manner. The operation result of the previous segment is used as the input of the next segment. Data is transmitted quickly through a standardized interface. At the same time, the cascading rules in the 4.3 billion logical rule library are called to ensure the coordination of the operation of each segment and the accuracy of the results. This greatly improves the efficiency of ultra-high bit width operation and solves the problem of poor data connection in segmented operation. 3. Dynamic rule scheduling: During segmented operation and pipeline cascading, the bit width dynamic configuration module automatically calls the corresponding logical rules from the 4.3 billion rule library according to the current bit width and operation type of the segment, without manual intervention, ensuring the adaptability of different bit widths and operation types, while reducing the call of invalid rules, reducing energy consumption, and solving the problems of low rule calling efficiency and high energy consumption. IV. Module Stacking: When the computational bit width exceeds the maximum cascading capacity of a single computing device (50,000 bits), multiple computing devices can be stacked through standardized expansion interfaces. Each device acts as an expansion module, working together to complete ultra-high bit width computations, achieving unlimited bit width expansion. Moreover, the stacking process does not require modification of the existing hardware structure and rules, ensuring that the existing hardware is not obsolete and solving the problem of high future expansion costs.

[0030] Lightweight and economical operation implementation methods To achieve lightweight and economical operation at 50-bit, 70-bit, and 100-bit speeds, and to reduce costs and energy consumption, this invention utilizes dynamic hibernation of hardware resources and simplified rule-based resource allocation, as detailed below: When the computation task is short-bit width (50 / 70 / 100 bits), the bit-width dynamic configuration module detects the demand and automatically puts the unused parts of the 6400-bit four-value logic operation unit (e.g., only the 50-bit operation unit is used for 50-bit operations, and the rest are put to sleep) and the redundant parts of the MSD no-carry adder to sleep. At the same time, it calls a subset of short-bit width exclusive rules from the 4.3 billion logic rule library to reduce the redundancy of rule calls and reduce hardware power consumption and resource occupation. At this time, the device operates in low-power mode, and the hardware cost and power consumption are reduced by more than 60% compared with the standard mode. It is suitable for low-cost, low-power economical application scenarios (such as small embedded devices and simple data processing terminals), solving the problem that existing devices cannot take into account both high-end computing and economical applications.

[0031] Complete calculation process The parallel computing method of this invention, based on the above-mentioned hardware architecture and extension method, realizes full-process automation from data input to result output. The specific steps are as follows (each step is causally related to ensure the continuity and accuracy of the operation): Step 1: Input the computation task. The bit width dynamic configuration module detects the bit width requirement (short bit width / medium bit width / ultra-long bit width) and the operation type (logical operation / arithmetic operation) of the input task. Step 2: Dynamically configure hardware resources according to bit width requirements: In short bit width mode, sleep redundant hardware resources and call the short bit width exclusive rule subset; in medium bit width (2048 / 4096 bits) mode, enable the corresponding part of the 6400-bit four-value logic operation unit and call the standard rule subset; in ultra-long bit width mode, perform segmented operation, pipeline cascading, and module stacking when necessary. Step 3: The 6400-bit quaternary logic unit and the 2300-bit MSD carry-free adder work together to complete the operation tasks of each segment or the whole according to the called logic rules. During the operation, the rule call is adjusted in real time through the rule dynamic scheduling module to ensure the operation efficiency. Step 4: For segmented operations with very long bit widths, the results of each segment are connected and integrated through a pipelined cascade interface to generate a complete operation result; Step 5: Output the calculation result. At the same time, the bit width dynamic configuration module restores the hardware resources to standby state, waiting for the next calculation task, to ensure efficient use of resources.

[0032] In this embodiment, the present invention operates as follows: The first stage involves inputting the computation task and detecting the bit width: the target computation task (such as 50,000-bit four-value addition, 100-bit logical operation, etc.) is input, and the bit width dynamic configuration module automatically detects the bit width requirement (short bit width / medium bit width / ultra-long bit width) and operation type (logical operation / arithmetic operation). At the same time, it verifies the format of the input data, removes invalid data and format errors, and ensures the accuracy and efficiency of subsequent operations. The following stage involves dynamic hardware resource configuration and rule scheduling: Based on the detected bit width requirements and operation type, hardware resources are dynamically allocated. In short bit width mode, redundant hardware units are put to sleep (e.g., for 50-bit operations, only 50-bit four-value logic operation units are used, and the rest are put to sleep), and a subset of short bit width rules is called to reduce power consumption. In medium bit width mode, operation units of the corresponding bit width are enabled, and a subset of standard rules is called to ensure operation efficiency. In ultra-long bit width mode, the data is segmented into 6400-bit units, and a subset of ultra-high bit width rules is called. At the same time, the interface resources required for pipeline cascading and module stacking are initialized to prepare for ultra-high bit width operations. Finally, there is the parallel computation execution and result output stage: the 6400-bit quad-valued logic unit and the 2300-bit MSD carry-free adder work together to perform the operation. The ultra-long bit-width task completes the segment operation through pipeline cascading, and then integrates to generate the complete result. After the operation is completed, the final operation result is output. The bit-width dynamic configuration module restores the hardware resources to a low-power standby state, waiting for the next operation task, so as to realize the efficient recycling of resources.

[0033] The following are several other specific embodiments of the application of this invention: Example 1: Short-bit-width embedded scenario (50-bit logic operation, smart wearable device) First, low-power task input and bit width recognition are performed: 50-bit four-value logic operation tasks (such as health data encryption and status logic judgment) are received from smart wearable devices. The bit width dynamic configuration module quickly identifies the bit width as 50-bit short bit width, marks the operation type as lightweight logic operation, and starts low-power preprocessing and turns off non-core hardware clocks to reduce standby power consumption. Then, lightweight resource configuration and rule invocation are performed: all redundant units other than 50 bits in the 6400-bit four-value logic operation unit are automatically put to sleep, and only the 50-bit core operation path is retained. At the same time, the 2300-bit MSD carry-free adder is switched to the 50-bit simplified mode, and the short-bit-width logic operation subset in the 4.3 billion rule base is called to remove irrelevant rules to reduce scheduling overhead. Finally, low-power computation and result output are performed: the core computing unit completes the logic operation in 1GHz low-frequency mode with a computation latency of ≤1ns and a total power consumption of ≤8W. The computation result is directly output to the control unit of the smart wearable device. After the computation is completed, all redundant hardware enters a deep sleep state, and the standby power consumption is reduced to less than 3% of the working state, meeting the requirements for long-term battery life.

[0034] Example 2: Median-width big data processing scenario (4096-bit arithmetic operations, AI inference) First, the big data computing task is analyzed: the input is a 4096-bit four-value matrix multiplication task (used for AI large model inference and high-dimensional data feature extraction). The bit width dynamic configuration module analyzes the bit width as 4096 bits, the operation type is high-precision arithmetic operation, and at the same time, the input matrix data is formatted and redundant padding bits are removed. Then, standard mode resource allocation and rule scheduling are performed: 4096-bit operation path in the 6400-bit four-value logic operation unit is enabled, the 2300-bit MSD carry-free adder is fully enabled, the standard arithmetic operation subset in the 4.3 billion rule base is called, the matrix multiplication-specific parallel rules are loaded, the instruction scheduling of the operation pipeline is optimized, and the data path is ensured to be unblocked. Finally, parallel computation and result integration are performed: the four-valued logic operation unit and the MSD carry-free adder work together to perform matrix multiplication. By utilizing the carry-free addition feature, carry delay is eliminated, and the computation efficiency is improved by 4 times compared with the traditional 64-bit binary CPU. The total computation time for 4096-bit operations is ≤10μs. The results are output to the memory buffer of the big data processing platform to support subsequent high-dimensional data analysis and model inference.

[0035] Example 3: Ultra-long bit-width cipher breaking scenario (50,000-bit addition operation, cipher breaking) First, the ultra-high bit width task is broken down: Input a 50,000-bit four-value number addition task (used for large integer factorization and password hash collision cracking). The bit width dynamic configuration module recognizes it as an ultra-long bit width requirement and splits the 50,000-bit data into 8 segments of 6,400 bits each (the first 7 segments are 6,400 bits each, and the 8th segment is 3,200 bits each). At the same time, the operation type is marked as high-precision arithmetic operation. Then, the ultra-long bit-width mode resource configuration and pipeline initialization are performed: the 6400-bit four-value logic operation unit and the 2300-bit MSD carry-free adder are fully enabled, the ultra-high bit-width cascade operation subset in the 4.3 billion rule base is called, the pipeline cascade interface is initialized, and independent operation sequence is allocated to the 8 segments to avoid data conflicts. Finally, pipelined cascaded operations and result integration are performed: each segment performs a carry-free addition operation in the pipeline order, and the result of the previous segment is directly transmitted to the next segment as input. The total operation delay is ≤50μs. The results of the 8 segments are automatically concatenated into a complete result of 50,000 bits and output to the cryptographic decryption platform for subsequent key derivation and collision verification.

[0036] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in the present invention, and these should all be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A scalable bit-width parallel computing device based on high-dimensional four-valued logic, characterized in that, It includes a 6400-bit four-valued logic operation unit, a 2300-bit MSD carry-free adder, a hardware parallel logic rule library of 4.3 billion rules, a bit-width dynamic configuration module, and a standardized expansion interface; the device can support operations of 50 bits to 50,000 bits and larger, and can selectively implement lightweight and economical operation such as 50 bits, 70 bits, and 100 bits, and can complete bit-width switching and expansion without replacing hardware.

2. The apparatus according to claim 1, characterized in that, The 6400-bit quaternary logic operation unit adopts a high-dimensional quaternary logic architecture. The quaternary logic variables take values ​​of {0, 1, 2, 3}, corresponding to two binary digits (00, 01, 10, 11). The operation logic is provided by the approximately 4.3 billion (4,294,967,296) hardware parallel logic rule base. The core operation expression is: Where A and B are input four-value variables, C is output four-value variable, and f is a preset logical function in the rule base.

3. The apparatus according to claim 1, characterized in that, The 2300-bit MSD carry-free adder uses a modified signed digit (MSD) number system, utilizing its redundancy to eliminate carry propagation chains. The core summation formula is: in , , These are the i-th bits of the two input quaternary numbers, and g is the MSD no-carry addition logic, which works in conjunction with the 6400-bit quaternary logic arithmetic unit.

4. The apparatus according to claim 1, characterized in that, The approximately 4.3 billion hardware parallel logic rules library is stored in high-speed ROM and is divided into short-width rule subsets, standard rule subsets, and ultra-high-width rule subsets. It supports dynamic scheduling and reserves space for rule expansion, allowing new logic rules to be added according to future computing needs.

5. The apparatus according to claim 1, characterized in that, The bit width dynamic configuration module is implemented using an FPGA chip. It can automatically detect the bit width requirements and operation type of the computing task, dynamically allocate hardware resources, and achieve seamless switching between short bit width, medium bit width, and ultra-long bit width modes. In the short bit width mode, redundant hardware resources can be put to sleep to reduce energy consumption.

6. The apparatus according to claim 1, characterized in that, The standardized expansion interface adopts a high-speed PCIe 4.0 interface, which supports the stacking and cascading of multiple computing devices. Each device acts as an independent expansion module, working together to complete ultra-high bit-width operations. The expansion process does not require modification of the existing hardware core structure.

7. The apparatus according to claim 1, characterized in that, In the lightweight and economical operating mode, the device power consumption is ≤10W, the hardware resource utilization rate is ≥90%, and the operation latency is ≤1ns, making it suitable for low-cost, low-power embedded devices and simple data processing scenarios.

8. A scalable bit-width parallel computing method based on high-dimensional four-valued logic, characterized in that, Implemented using the computing device according to any one of claims 1-7, the method includes the following steps: Step 1: Input the computation task; the bit width dynamic configuration module detects the bit width requirement and computation type of the task. Step 2: Dynamically configure hardware resources according to bit width requirements and call the corresponding subset of logical rules; Step 3: The quaternary logic unit and the MSD carry-free adder work together to complete the calculation task; Step 4: When performing ultra-long bit-width operations, the operation results are integrated through segmented operations, pipeline cascading, and module stacking. Step 5: Output the calculation results and restore hardware resources to standby mode.

9. The method according to claim 8, characterized in that, In the segmentation process of the ultra-long bit-width operation, the ultra-high bit-width data is divided into several independent sub-operation tasks in segments of 6400 bits each. Each sub-operation task works collaboratively in a pipelined cascade manner, and data transmission and result connection are realized through a standardized interface.

10. The method according to claim 8, characterized in that, The method can be adapted to various application scenarios such as cryptography, big data optimization, artificial intelligence, quantum simulation, and embedded devices. It has a 100% accuracy rate and a 3-5 times higher computational efficiency compared to traditional binary computers.

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