Central processor power-on timing verification method, device, equipment and medium

By combining the debugging fixture and the embedded controller, the power-on pins and sequence of the central processing unit are automatically set, level status data is collected and waveforms are plotted, solving the problems of low efficiency and error susceptibility in the existing technology and achieving efficient timing verification.

CN122220131APending Publication Date: 2026-06-16SHENZHEN WEIBU INFORMATION
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHENZHEN WEIBU INFORMATION
Filing Date
2026-01-29
Publication Date
2026-06-16

AI Technical Summary

⚠Technical Problem

Existing technologies rely on manual operation and multiple hardware devices for power-on timing verification of central processing units, resulting in low efficiency and a high risk of errors, making it impossible to achieve automated and batch verification.

⚗Method used

The system obtains user instructions through a debugging tool, switches the embedded controller to debug mode, obtains the configuration file to set the pins and power-on sequence, collects level status data and plots waveforms using the embedded controller's debug channel, calculates timing deviation values ​​and compares them with threshold ranges, and automatically determines whether the timing is normal.

🎯Benefits of technology

It enables automated and batch verification of the power-on sequence of the central processing unit, simplifies the hardware testing process, and improves debugging efficiency and accuracy.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application relates to the field of time sequence data processing and verification technology, and discloses a central processor power-on time sequence verification method, which comprises the following steps: obtaining a debugging instruction input by a user through a debugging tool to switch an embedded controller to a debugging mode, setting a power-on pin and a power-on sequence of the central processor according to a configuration file corresponding to the debugging mode, powering on the central processor according to the power-on sequence, collecting level state data of the power-on pin through a debugging channel of the embedded controller, analyzing the level state data and drawing a time sequence waveform diagram, respectively calculating time sequence deviation values of each time sequence parameter in the time sequence waveform diagram and corresponding expected time sequence parameters in the configuration file, and judging whether the central processor power-on time sequence is normal according to a comparison result of the time sequence deviation values and corresponding preset threshold intervals. The application simplifies a hardware test process of the central processor for power-on time sequence verification and improves the debugging efficiency.
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