Three-dimensional memory devices, manufacturing methods, and memory systems

Abstract

Embodiments of the present application disclose a three-dimensional memory device, a manufacturing method and a memory system. The method comprises the following steps: providing a substrate; the substrate comprises a substrate, a stack structure and a channel structure penetrating through the stack structure, the stack structure being located on the substrate and comprising gate layers and insulating layers which are alternately stacked; the gate layers comprise a top selection gate layer located at the top of the stack structure; the channel structure comprises a memory layer, a channel layer and a channel oxide which are sequentially arranged along a radial direction from outside to inside; a plurality of top selection gate cuts penetrating through the top selection gate layer are formed; the top selection gate cuts are filled to form a top selection gate cut line; the top selection gate cut line divides the stack structure into a plurality of storage areas; wherein the top selection gate cut line partially penetrates through a first channel structure and is in contact with the channel oxide in the first channel structure; the first channel structure is a channel structure located in different storage areas and adjacent to each other.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202210049580.8, filed on January 17, 2022, entitled "A three-dimensional storage device, manufacturing method and storage system". Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a three-dimensional memory device, manufacturing method and memory system. Background Technology

[0003] In current 3D NAND structures, integration density is increased by arranging memory cells three-dimensionally on a substrate. The gate is divided into three parts: the bottom select gate, the middle select gate, and the top select gate (TSG). Typically, a top select gate cut (TSG cut) is placed in the pointer memory region to separate the top select gate of the pointer memory region into two parts. A dummy channel hole (DCH) structure is placed below the top select gate cut. Since the top select gate cut is formed on the dummy channel hole, it wastes channel hole space, ultimately leading to a significant decrease in memory density. How to further improve memory density is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the main objective of this application is to provide a three-dimensional storage device, a manufacturing method, and a storage system.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows: This application provides a method for manufacturing a three-dimensional storage device, the method comprising: A substrate is provided; the substrate includes a substrate, a stacked structure on the substrate consisting of alternating gate layers and insulating layers, and a channel structure through the stacked structure; the gate layers include a top select gate layer located on top of the stacked structure; the channel structure includes a memory layer, a channel layer, and a channel oxide arranged radially from the outside to the inside. Forming a plurality of top select gate cutouts that penetrate the top select gate layer; The top select gate cutout is filled to form a top select gate tangent; the top select gate tangent divides the stacked structure into multiple memory regions; wherein the top select gate tangent partially passes through a first channel structure and contacts the channel oxide in the first channel structure; the first channel structure is a channel structure located in different and adjacent memory regions.

[0006] In the above scheme, the step of forming the top select gate notch includes: The top select gate layer and the first channel structure are etched to remove the memory layer and part of the channel layer of the first channel structure located in the top select gate layer, forming multiple first cuts; The first notch is used to remove the channel layer of the first channel structure located in the top selected gate layer to form a plurality of the top selected gate notches.

[0007] In the above scheme, the inner diameter of the first cut is greater than the distance between adjacent channel structures located in different storage areas.

[0008] In the above scheme, the step of forming the top select gate notch includes: The top selected gate layer located between the first channel structures is etched to form multiple first notches; The memory layer and channel layer of the first channel structure located in the top select gate layer are removed through the first cut to form a plurality of the top select gate cuts.

[0009] In the above scheme, the inner diameter of the first cut is greater than the distance between adjacent first channel structures and less than the distance between the channel oxides of adjacent first channel structures.

[0010] In the above scheme, the top select gate tangent extends in a first direction parallel to the substrate; the top select gate tangent is spaced apart in a second direction parallel to the substrate; wherein the first direction and the second direction are perpendicular to each other.

[0011] In the above scheme, the number of rows of channel structures between adjacent top selected gate tangents is the same.

[0012] This application also provides a three-dimensional storage device, including: The substrate includes a substrate, a stacked structure consisting of alternating gate layers and insulating layers on the substrate, and a channel structure penetrating the stacked structure; the gate layer includes a top select gate layer located on top of the stacked structure; the channel structure includes a memory layer, a channel layer, and a channel oxide arranged radially from the outside to the inside. Multiple top-select gate tangents penetrate the top-select gate layer to divide the stacked structure into multiple memory regions; The top selected gate tangent partially passes through the first channel structure and contacts the channel oxide in the first channel structure; the first channel structure is an adjacent channel structure located in different memory regions.

[0013] In the above scheme, the top select gate tangent extends in a first direction parallel to the substrate; the top select gate tangent is spaced apart in a second direction parallel to the substrate; wherein the first direction and the second direction are perpendicular to each other.

[0014] In the above scheme, the number of rows of channel structures between adjacent top selected gate tangents is the same.

[0015] In the above scheme, the material of the top selected gate tangent includes an insulating material.

[0016] In the above scheme, the top select gate tangent includes an air gap, which is formed in the top select gate tangent by the insulating material.

[0017] In the above scheme, the orthographic projection of the top selected gate tangent on the substrate partially overlaps with the orthographic projection of the first channel structure on the substrate.

[0018] This application also provides a memory system, including: At least one three-dimensional storage device as described in any of the above embodiments; and A controller coupled to the three-dimensional storage device and configured to control the three-dimensional storage device.

[0019] The method for manufacturing a three-dimensional memory device provided in this application includes: providing a substrate; the substrate including a substrate, a stacked structure consisting of alternating gate layers and insulating layers on the substrate, and a channel structure penetrating the stacked structure; the gate layer including a top select gate layer located on top of the stacked structure; the channel structure including a memory layer, a channel layer, and a channel oxide arranged radially from the outside to the inside; forming a plurality of top select gate cutouts penetrating the top select gate layer; filling the top select gate cutouts to form a top select gate tangent; the top select gate tangent dividing the stacked structure into a plurality of memory regions; wherein the top select gate tangent partially passes through a first channel structure and contacts the channel oxide in the first channel structure; the first channel structure is a channel structure located in different and adjacent memory regions. The top select gate tangent formed by the method provided in this application only partially passes through the portion of the first channel structure located in the top select gate layer, without destroying the function of the first channel structure itself. Therefore, a top select gate tangent can be formed without introducing a dummy channel structure, thereby improving memory density. Furthermore, the channel oxide in the first channel structure is in direct contact with the top select gate tangent, which to some extent reduces the leakage problem caused by the loss of gate control in the channel layer of the first channel structure. Attached Figure Description

[0020] Figure 1 A top view of a three-dimensional storage device in related technologies. Figure 1 ; Figure 2 A top view of a three-dimensional storage device in related technologies. Figure 2 ; Figure 3 A cross-sectional structural schematic diagram of a three-dimensional storage device provided in an embodiment of this application; Figure 4 A top view of the three-dimensional storage device provided in the embodiments of this application; Figure 5 A schematic diagram illustrating the implementation flow of the manufacturing method for the three-dimensional storage device provided in this application embodiment; Figures 6A-6E A cross-sectional schematic diagram of an exemplary process for manufacturing a three-dimensional storage device provided in an embodiment of this application; Figure 7 for Figure 6E A partial top-view structural schematic diagram; Figures 8A-8F A cross-sectional schematic diagram of an exemplary process for manufacturing a three-dimensional storage device according to another embodiment of this application; Figure 9 for Figure 8F A schematic diagram of a partial cross-sectional structure; Figure 10 This is a block diagram of a memory system according to an exemplary embodiment of this application; Figure 11A This is a schematic diagram of a memory card according to an exemplary embodiment of this application; Figure 11B This is a schematic diagram of a solid-state drive (SSD) according to an exemplary embodiment of this application. Detailed Implementation

[0021] The technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0022] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present application.

[0023] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0024] In embodiments of this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal planes at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces.

[0025] It should be noted that the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0026] Please see Figure 1 , Figure 1 This is a top view diagram of a three-dimensional storage device provided in related technologies. Figure 1 The three-dimensional storage device includes multiple gate line slits 10 extending in the X direction. The stacked structure and channel structure 22 between adjacent gate line slits 10 form a block structure (e.g., block) 20. Each block structure 20 has a TSG cut 21 extending in the X direction. The TSG cut 21 divides the block structure 20 into two storage areas (e.g., fingers) 20a, thus allowing independent control of the TSG in each storage area 20a. Figure 1 As shown, one of the block structures 20 has nine rows of channel structures along the Y direction. The position of the middle row of channel structures is sacrificed and set as a virtual channel structure 23 due to the existence of TSG Cut. Figure 2 A top view of a three-dimensional storage device in the related art is shown. Figure 2 Between two adjacent GLS 101, multiple (greater than or equal to 2) TSG Cut 105s can be set to divide the block structure 102 into multiple (>2) storage areas 102a. Figure 2 Setting multiple TSG Cuts between adjacent GLSs allows for the addition of more rows of channel structures 104 along the Y direction within a single block structure 102, and each channel structure 104 in each storage area can be controlled independently. However, since each TSG Cut requires a row of channel structures as a virtual channel structure 103, the issue of storage density remains. Here, the X direction is the first direction, and the Y direction is the second direction.

[0027] Based on this, a three-dimensional storage device is provided in one embodiment of this application. Please refer to [link / reference]. Figure 3, Figure 3 This is a cross-sectional view of a three-dimensional memory device provided in an embodiment of this application. The three-dimensional memory device includes a substrate and a stacked structure 300 on the substrate, consisting of alternating gate layers 320 and insulating layers 310, and a channel structure penetrating the stacked structure. The gate layer 320 includes a top select gate layer located on top of the stacked structure 300. The channel structure includes a memory layer 420, a channel layer 410, and a channel oxide 424 arranged radially from the outside to the inside. The memory layer 420 may include a barrier layer 423, a charge trapping layer 422, and a tunneling layer 421 arranged radially from the outside to the inside along the channel aperture. Multiple top select gate tangents 425 penetrate the top select gate layer to divide the stacked structure 300 into multiple memory regions. This three-dimensional memory device allows the top select gate tangents to be formed directly between the first channel structures 400 without compromising the function of the first channel structure itself. This avoids the area waste caused by occupying the space of an additional row of channel structures to form the top select gate tangents, thereby improving the device's storage density. Specifically, please refer to the top view of the three-dimensional storage device provided in the embodiments of this application. Figure 4 In this embodiment, the channel structure includes a first channel structure and a second channel structure. The first channel structure 400 consists of adjacent channel structures located in different memory regions 402a. The second channel structure 430 consists of channel structures other than the first channel structure 400, i.e., channel structures not traversed by the top select gate tangent 425. The top select gate tangent 425 between adjacent gate line gaps 401 is formed between the first channel structures 400. Figure 4 Examples (A)-(C) in the diagram provide examples of 1-3 top-select gate tangents between adjacent gate line gaps 401. Generally, the more top-select gate tangents between adjacent gate line gaps, the higher the storage density of the device. In practical applications, the number of top-select gate tangents can be selected according to needs. It should be noted that... Figure 3 Only the structure of the first channel is shown in the diagram.

[0028] Based on the research and analysis of the three-dimensional memory devices in the above embodiments of this application, the inventors have further improved the top select gate tangent, so that the final top select gate tangent is in direct contact with the channel oxide of the adjacent channel structure located in different memory regions. This reduces the leakage problem caused by the loss of gate control in some channel layers due to the top select gate tangent penetrating the top select gate layer to a certain extent.

[0029] This application provides a method for manufacturing a three-dimensional storage device. Figure 5 This is a schematic diagram illustrating the implementation flow of the manufacturing method for the three-dimensional storage device provided in the embodiments of this application. Figures 6A-6EThis is a cross-sectional schematic diagram illustrating an exemplary process of manufacturing a three-dimensional storage device according to an embodiment of this application. Figure 7 for Figure 6E A partial top-view schematic diagram, illustrating the manufacturing method of this three-dimensional storage device, combining 6A-6E and... Figure 7 An explanation is needed. It should be noted that... Figure 6A-8E This is a sectional view along the ZOY plane. Figure 7 This is a sectional view along the XOY plane. (Example) Figure 5 , Figures 6A-6E and Figure 7 As shown, the specific steps of the manufacturing method of this three-dimensional storage device include: Step S501: Provide a substrate; the substrate includes a substrate, a stacked structure 500 on the substrate consisting of alternating layers of gate layer 520 and insulating layer 510, and a channel structure through the stacked structure 500; the gate layer includes a top select gate layer located on top of the stacked structure; the channel structure includes a memory layer 620, a channel layer 610, and a channel oxide 624 arranged radially from the outside to the inside. Step S502: Form a plurality of top select gate cutouts 626 through the top select gate layer; Step S503: Fill the top select gate cutout 626 to form a top select gate tangent 627; the top select gate tangent divides the stacked structure into multiple memory regions; wherein the top select gate tangent partially passes through the first channel structure 600 and contacts the channel oxide 624 in the first channel structure 600; the first channel structure 600 is a channel structure located in different memory regions and adjacent to each other.

[0030] In this embodiment, the channel structure includes a first channel structure and a second channel structure, both of which have the same structure and function. The first channel structure is an adjacent channel structure located in different memory regions, i.e., a channel structure traversed by the top selected gate tangent; the second channel structure is any channel structure other than the first channel structure, i.e., a channel structure not traversed by the top selected gate tangent. It should be noted that... Figures 6A-6E and Figure 7 Only the structure of the first channel is shown in the diagram.

[0031] In some embodiments, the substrate (not shown) may be a semiconductor substrate. The semiconductor substrate may be a single-element semiconductor material substrate (e.g., a silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator substrate, germanium-on-insulator (GeOI) substrate, etc. The material of the insulating layer 510 may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The material of the gate layer 520 may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or polycrystalline silicon, doped silicon, or any combination thereof. The gate layer 520 may also be a dummy gate layer, the material of which may be, for example, a silicon nitride layer; the dummy gate layer may be replaced with the gate layer when appropriate. The deposition methods for the pseudo gate layer and insulating layer can include chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, etc., which are deposited alternately on the substrate to form a stacked structure.

[0032] In some embodiments, please refer to Figure 6A Along the radial direction of the first channel structure 600, from the outside to the inside, are sequentially disposed a memory layer 620, a channel layer 610, and a channel oxide 624. The memory layer 620 may include a barrier layer 623, a charge trapping layer 622, and a tunneling layer 621, sequentially disposed along the radial direction of the channel via. The barrier layer 623 and the tunneling layer 621 may be made of silicon oxide, and the charge trapping layer 622 may be made of silicon nitride. The channel oxide 624 disposed within the channel layer 610 can act as a support, and the material of the channel layer 610 may include semiconductor materials such as monocrystalline silicon and polycrystalline silicon. The memory layer 620, the channel layer 610, and the channel oxide 624 can be formed in the channel via using one or more thin-film deposition processes, such as ALD, CVD, PVD, or any combination thereof.

[0033] Specifically, step S502 of forming the top select gate notch further includes: etching the top select gate layer and the first channel structure to remove the memory layer 620 and part of the channel layer 610 of the first channel structure located in the top select gate layer, forming a plurality of first notches 625, as shown in the figure. Figure 6BAs shown, the inner diameter of the first notch 625 is greater than the distance between adjacent channel structures located in different memory regions. Specifically, in the step of forming multiple first notches 625, the top select gate layer can be etched first using, for example, a dry etching process. By adjusting the etching process parameters, the depth of the first notch can be controlled to the number of select gate layers required for optimal device performance, for example, between 1 and 10 layers in a stacked structure. Then, the barrier layer 623, charge trapping layer 622, tunneling layer 621, and part of the channel layer 610 within the memory layer are etched sequentially. The etching method can be dry etching, such as plasma etching. In the embodiments of this application, please refer to... Figure 6C The first channel structure located in the top selected gate layer is removed through the first notch 625 to form a plurality of top selected gate notches 626. Specifically, the channel layer can be removed by an etching process, such as a dry etching process.

[0034] In some embodiments, please refer to Figure 6D The top select gate cutout 626 is filled to form the top select gate tangent 627. The insulating material filling the top select gate cutout can be silicon oxide. Depending on the formation method (e.g., CVD, ALD, spin coating, etc.), the surface flatness of the structure after filling may be poor. When the flatness is poor, it can be planarized by chemical mechanical polishing (CMP) process.

[0035] In this embodiment, the top select gate tangent 627 extends in a first direction parallel to the substrate; the top select gate tangent 627 is spaced apart in a second direction parallel to the substrate; wherein the first direction and the second direction are perpendicular to each other. In some embodiments, the top select gate tangent divides the top select gate into multiple mutually isolated regions, and the number of rows of channel structures between adjacent top select gate tangents along the second direction is the same. In one specific embodiment, the number of rows can be 4. Here, the X direction is the first direction, and the Y direction is the second direction.

[0036] In this embodiment, the top selected gate tangent 627 may include an air gap 628. (See also...) Figure 6EThe air gap 628 is formed in the top select gate tangent by the insulating material. In some embodiments, the top select gate tangent is partially vacuum-treated during filling to form an air gap, which electrically isolates the memory regions of the three-dimensional memory device from each other. Because the air gap has a lower dielectric constant, it provides more effective insulation between the memory regions, resulting in better overall memory performance.

[0037] Figure 6E It shows the way Figure 5 The schematic diagram of the cross-sectional structure of the three-dimensional storage device formed by the method shown is as follows. Figure 6E and Figure 7 As shown, the three-dimensional memory device includes: a substrate, the substrate including a base, a stacked structure 500 consisting of alternating gate layers 520 and insulating layers 510 on the base, and a channel structure penetrating the stacked structure; the gate layer 520 includes a top select gate layer located on top of the stacked structure 500; the channel structure includes a memory layer 620, a channel layer 610, and a channel oxide 624 arranged radially from the outside to the inside; a plurality of top select gate tangents 627 penetrating the top select gate layer to divide the stacked structure 500 into a plurality of memory regions; the top select gate tangents 627 partially pass through a first channel structure 600 and contact the channel oxide 624 in the first channel structure; the first channel structure is a channel structure located in different memory regions and adjacent to each other.

[0038] In this embodiment, the orthographic projection of the top select gate tangent on the substrate partially overlaps with the orthographic projection of the first channel structure on the substrate. In some embodiments, the depth of the top select gate tangent in the third direction perpendicular to the stacked structure can be controlled by etching process parameters (e.g., etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, with a constant etching rate, a longer etching time results in a deeper top select gate tangent in the third direction. In one embodiment, the depth of the top select gate cut can be controlled to the number of select gate layers required for optimal device performance, such as a stacked structure of 1 to 10 layers, by adjusting the etching process parameters. The etching method can be dry etching, such as plasma etching.

[0039] This application also provides a method for manufacturing a three-dimensional storage device. Figure 5 This is a schematic diagram illustrating the implementation flow of the manufacturing method for the three-dimensional storage device provided in the embodiments of this application. Figures 8A-8F This is a cross-sectional schematic diagram illustrating an exemplary process of manufacturing a three-dimensional storage device according to an embodiment of this application. Figure 9 for Figure 8FA partial cross-sectional schematic diagram shows the manufacturing method of this three-dimensional storage device, combining 8A-8F and... Figure 9 An explanation is needed. It should be noted that... Figures 8A-8F This is a sectional view along the ZOY plane. Figure 9 This is a sectional view along the XOY plane. (Example) Figure 5 , Figures 8A-8F and Figure 9 As shown, the specific steps of the manufacturing method of this three-dimensional storage device include: Step S501: Provide a substrate; the substrate includes a substrate, a stacked structure 700 on the substrate consisting of alternating layers of gate layer 720 and insulating layer 710, and a channel structure through the stacked structure 700; the gate layer includes a top select gate layer located on top of the stacked structure; the channel structure includes a memory layer 820, a channel layer 810, and a channel oxide 824 arranged radially from the outside to the inside. Step S502: Form a plurality of top select gate cutouts 826 through the top select gate layer; Step S503: Fill the top select gate notch 826 to form a top select gate tangent 827; the top select gate tangent divides the stacked structure into multiple memory regions; wherein, The top selected gate tangent partially passes through the first channel structure 800 and contacts the channel oxide 824 in the first channel structure 800; the first channel structure 800 is a channel structure located in different and adjacent memory regions.

[0040] In this embodiment, the channel structure includes a first channel structure and a second channel structure, both of which have the same structure and function. The first channel structure is an adjacent channel structure located in different memory regions, i.e., a channel structure traversed by the top selected gate tangent; the second channel structure is any channel structure other than the first channel structure, i.e., a channel structure not traversed by the top selected gate tangent. It should be noted that... Figures 8A-8E and Figure 9 Only the structure of the first channel is shown in the diagram.

[0041] In some embodiments, the substrate (not shown) may be a semiconductor substrate. The semiconductor substrate may be a single-element semiconductor material substrate (e.g., a silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator substrate, germanium-on-insulator (GeOI) substrate, etc. The material of the insulating layer 710 may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The material of the gate layer 720 may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or polycrystalline silicon, doped silicon, or any combination thereof. The gate layer 720 may also be a dummy gate layer, the material of which may be, for example, a silicon nitride layer. The dummy gate layer may be replaced with the gate layer when appropriate. The deposition method of the dummy gate layer and the insulating layer may include various methods such as CVD, ALD, or PVD such as MBE, thermal oxidation, evaporation, sputtering, etc., which are sequentially deposited on the substrate alternately to form a stacked structure.

[0042] In some embodiments, please refer to Figure 8A Along the radial direction of the first channel structure 800, from the outside to the inside, are sequentially disposed a memory layer 820, a channel layer 810, and a channel oxide 824. The memory layer 820 may include a barrier layer 823, a charge trapping layer 822, and a tunneling layer 821, sequentially disposed along the radial direction of the channel via. The barrier layer 823 and the tunneling layer 821 may be made of silicon oxide, and the charge trapping layer 822 may be made of silicon nitride. The channel oxide 824 disposed within the channel layer 810 can act as a support, and the material of the channel layer 810 may include semiconductor materials such as monocrystalline silicon and polycrystalline silicon. The memory layer 820, the channel layer 810, and the channel oxide 824 can be formed in the channel via using one or more thin-film deposition processes, such as ALD, CVD, PVD, or any combination thereof.

[0043] Specifically, step S502 of forming the top select gate notch further includes: etching the top select gate layer located between the first channel structures to form a plurality of first notches 825. In a specific example, the top select gate layer located between the first channel structures and the barrier layer of the first channel structures are etched to form a plurality of first notches 825. Figure 8B As shown, the inner diameter of the first notch 825 is larger than the distance between the memory layers 820 of adjacent first channel structures 800, and smaller than the distance between the channel oxides 824 of adjacent first channel structures 800. The memory layer 820 of the first channel structure located at the top select gate layer is removed through the first notch 825 to form an intermediate stage notch 826' (e.g., Figure 8C (as shown), and then continue removing the channel layer to form multiple of the top select gate cutouts 826 (as shown). Figure 8D(As shown). The first notch can be formed by using a patterned mask for exposure, photolithography, and etching. The etching method can be dry etching, such as plasma etching.

[0044] In some embodiments, please refer to Figure 8E The top select gate notch 826 is filled to form the top select gate tangent 827. The insulating material filling the top select gate notch can be silicon oxide. Depending on the formation method (e.g., CVD, ALD, spin coating, etc.), the surface flatness of the structure after filling may be poor. When the flatness is poor, it can be planarized by CMP process.

[0045] In this embodiment, the top select gate tangent 827 extends in a first direction parallel to the substrate; the top select gate tangent 827 is spaced apart in a second direction parallel to the substrate; wherein the first direction and the second direction are perpendicular to each other. In some embodiments, the top select gate tangent divides the top select gate into multiple mutually isolated regions, and the number of rows of channel structures between adjacent top select gate tangents along the second direction is the same. In one specific embodiment, the number of rows can be 4. Here, the X direction is the first direction, and the Y direction is the second direction.

[0046] In this embodiment, the top selected gate tangent 827 may include an air gap 828. (See also...) Figure 8F The air gap 828 is formed in the top select gate tangent by the insulating material. In some embodiments, the top select gate tangent is partially vacuum-treated during filling to form an air gap, which electrically isolates the memory regions of the three-dimensional memory device from each other. Because the air gap has a lower dielectric constant, it provides more effective insulation between the memory regions, resulting in better overall memory performance.

[0047] Figure 8F It shows the way Figure 5 A schematic cross-sectional view of another three-dimensional storage device formed by the method shown is as follows: Figure 8F and Figure 9As shown, the three-dimensional memory device includes: a substrate, the substrate including a base, a stacked structure 700 consisting of alternating gate layers 720 and insulating layers 710 on the base, and a channel structure penetrating the stacked structure; the gate layer 720 includes a top select gate layer located on top of the stacked structure 700; the channel structure includes a memory layer 820, a channel layer 810, and a channel oxide 824 arranged radially from the outside to the inside; a plurality of top select gate tangents 827 penetrating the top select gate layer to divide the stacked structure 700 into a plurality of memory regions; the top select gate tangents 827 partially pass through a first channel structure 800 and contact the channel oxide 824 in the first channel structure; the first channel structure is a channel structure located in different memory regions and adjacent to each other.

[0048] In this embodiment, the orthographic projection of the top select gate tangent on the substrate partially overlaps with the orthographic projection of the first channel structure on the substrate. In some embodiments, the depth of the top select gate tangent in the third direction perpendicular to the stacked structure can be controlled by etching process parameters (e.g., etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, with a constant etching rate, a longer etching time results in a deeper top select gate tangent in the third direction. In one embodiment, the depth of the top select gate cut can be controlled to the number of select gate layers required for optimal device performance, such as a stacked structure of 1 to 10 layers, by adjusting the etching process parameters. The etching method can be dry etching, such as plasma etching.

[0049] Figure 10 A block diagram of an exemplary memory system 100 having a three-dimensional storage device according to some aspects of this application is shown. The memory system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 10 As shown, system 100 may include a host 1008 and a storage system 1002. The storage system 1002 includes one or more three-dimensional storage devices 1004 and a controller 1006. The three-dimensional storage device 1004 includes a memory cell array and multiple page buffers. The host 1008 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 1008 may be configured to send data to or receive data from the three-dimensional storage device 1004.

[0050] The three-dimensional storage device 1004 can be any three-dimensional storage device of this application. According to some embodiments, a controller 1006 is coupled to the three-dimensional storage device 1004 and the host 1008 and is configured to control the three-dimensional storage device. The controller 1006 can manage data stored in the three-dimensional storage device and communicate with the host 1008. In some embodiments, the controller 1006 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 1006 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., and as enterprise storage devices. The controller 1006 can be configured to control the operation of the three-dimensional storage device 1004, such as read, erase, and program operations. The controller 1006 can also be configured to manage various functions relating to data stored or to be stored in the 3D storage device 1004, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 1006 is also configured to process error correction codes (ECC) relating to data read from or written to the 3D storage device 1004. The controller 1006 can also perform any other suitable function, such as formatting the 3D storage device 1004. The controller 1006 can communicate with external devices (e.g., the host 1008) according to a specific communication protocol. For example, the controller 1006 can communicate with external devices through at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0051] The controller 1006 and one or more three-dimensional storage devices 1004 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 1002 can be implemented and packaged into different types of end electronic products. Figure 11AIn one example shown, controller 1006 and a single three-dimensional storage device 1004 can be integrated into memory card 1102. Memory card 1102 may include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 1102 may also include a connection between memory card 1102 and host computer (e.g., Figure 10 The memory card connector 1104 is coupled to the host 1008. Figure 11B In another example shown, the controller 1006 and multiple three-dimensional storage devices 1004 can be integrated into the SSD 1106. The SSD 1106 may also include a connection between the SSD 1106 and a host (e.g., Figure 10 The SSD connector 1108 is coupled to the host 1008. In some embodiments, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102.

[0052] This application provides a three-dimensional memory device, a manufacturing method, and a memory system. The method includes: providing a substrate; the substrate includes a substrate, a stacked structure on the substrate consisting of alternating gate layers and insulating layers, and a channel structure penetrating the stacked structure; the gate layer includes a top select gate layer located on top of the stacked structure; the channel structure includes a memory layer, a channel layer, and a channel oxide arranged radially from the outside to the inside; forming a plurality of top select gate cutouts penetrating the top select gate layer; filling the top select gate cutouts to form top select gate tangents; the top select gate tangents dividing the stacked structure into a plurality of memory regions; wherein the top select gate tangents partially pass through a first channel structure and contact the channel oxide in the first channel structure; the first channel structure is an adjacent channel structure located in different memory regions. The top select gate tangents formed by the method provided in this application only partially pass through the portion of the first channel structure located in the top select gate layer, without destroying the function of the first channel structure itself. Therefore, top select gate tangents can be formed without introducing a dummy channel structure, thereby improving memory density. Furthermore, the channel oxide in the first channel structure is in direct contact with the top select gate tangent, which to some extent reduces the leakage problem caused by the loss of gate control in the channel layer of the first channel structure.

[0053] It should be understood that the phrases "an embodiment" or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0054] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A three-dimensional storage device, characterized in that, include: A stacked structure comprising a plurality of gate layers and insulating layers alternately stacked along a stacking direction, wherein the gate layers include a top selected gate layer located at the top of the stacked structure; Multiple channel structures, each channel structure extending through the stacked structure along the stacking direction, wherein each channel structure includes a memory layer, a channel layer, and a channel oxide layer arranged radially from the outside to the inside; and Multiple top-select gate tangents, which penetrate the top-select gate layer along the stacking direction, divide the stacked structure into multiple memory regions; wherein... The channel structure includes a first channel structure, which is an adjacent channel structure located in different storage areas among the plurality of channel structures. The top selected gate tangent partially passes through the first channel structure and contacts the channel oxide in the first channel structure.

2. The storage device according to claim 1, characterized in that: The top selected gate tangent extends in a first direction, and The plurality of top selected gate tangents are spaced apart in a second direction, wherein the stacking direction, the first direction and the second direction are perpendicular to each other.

3. The storage device according to claim 1, characterized in that: The number of rows of the channel structure is the same between adjacent top selected gate tangents.

4. The storage device according to claim 1, characterized in that: The material of the top selected gate tangent includes an insulating material.

5. The storage device according to claim 1, characterized in that: The top selected gate tangent overlaps with the first channel structure in the stacking direction.

6. The storage device according to claim 2, characterized in that, Also includes: Multiple grid line gaps; among them, The grid line slots extend along the first direction, and a plurality of the grid line slots are arranged along the second direction. The stacked structure between two adjacent grid line gaps and the channel structure form a block structure.

7. The storage device according to claim 2, characterized in that: Multiple grid line gaps; among them, The grid line slots extend along the first direction, and the plurality of grid line slots are arranged along the second direction. The top selected gate tangents are included between two adjacent gate line gaps.

8. The storage device according to claim 1, characterized in that: The channel structure includes a second channel structure, wherein the second channel structure and the top selected gate tangent do not overlap in the stacking direction.

9. The storage device according to claim 8, characterized in that: The first channel structure has the same function as the second channel structure.

10. The storage device according to claim 1, characterized in that: The top selected gate tangent extends through the plurality of top selected gate layers along the stacking direction.

11. The storage device according to claim 1, characterized in that: The channel layer includes a first sub-section and a second sub-section that are in contact with each other. The first sub-section is located on the sidewall of the channel oxide, and the second sub-section is located on the top of the channel oxide. The top selected gate tangent contacts the sidewall of the second sub-section.

12. The storage device according to claim 1, characterized in that: The gate layer comprises a conductive material, which includes tungsten metal.

13. The storage device according to claim 1, characterized in that: The channel layer includes a semiconductor material, which includes polycrystalline silicon.

14. A method for manufacturing a three-dimensional storage device, characterized in that, include: Provide intermediates; The intermediate includes a stacked structure of alternating gate layers and insulating layers and a plurality of channel structures through the stacked structure. The gate layer includes a top select gate layer located on top of the stacked structure. The channel structure includes a memory layer, a channel layer and a channel oxide arranged radially from the outside to the inside. Forming a plurality of top select gate cutouts that penetrate the top select gate layer; The top select gate cutout is filled to form a top select gate tangent; the top select gate tangent divides the stacked structure into multiple memory regions; wherein the top select gate tangent partially passes through a first channel structure and contacts the channel oxide in the first channel structure; the first channel structure is an adjacent channel structure located in different memory regions among the multiple channel structures.

15. The method according to claim 14, characterized in that: The top selected gate tangent extends along a first direction, and The plurality of top selected gate tangents are spaced apart in a second direction, wherein the stacking direction, the first direction and the second direction are perpendicular to each other.

16. The method according to claim 14, characterized in that: The number of rows of the channel structure is the same between adjacent top selected gate tangents.

17. The method according to claim 14, characterized in that: Filling the top select gate cutout to form the top select gate tangent includes: An insulating material is filled into the top selected gate cutout to form the top selected gate tangent.

18. The method according to claim 14, characterized in that: The insulating material is silicon dioxide.

19. The storage device according to claim 14, characterized in that: Forming the plurality of top select gate cutouts through the top select gate layer includes: A top select gate cutout is formed along multiple top select gate layers using an etching process.

20. The storage device according to claim 19, characterized in that: The etching process includes dry etching.

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