Recorded latency events are used for debugging

Abstract

Methods, systems, and apparatuses are described for recording latency events for debugging. A memory system and a host system can each be configured to store information associated with latency events. A synchronization operation can be performed to synchronize clocks of the memory system and the host system. The host system can output a command that can indicate a time associated with an experienced latency event, and the memory system can report information corresponding to the latency event that occurred at or around the indicated time. Thus, the host system can determine an operation or condition that caused the latency event, and can perform one or more debugging operations based on the identified event.

Description

Technical Field

[0001] The following describes one or more systems for use with memory, which include recording delay events for debugging. Background Technology

[0002] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) states to the memory cell.

[0003] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-select memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described according to volatile or non-volatile configurations. Memory cells configured as non-volatile can maintain their stored logic state for a long time, even without external power. Memory cells configured as volatile will lose their stored state when disconnected from external power. Attached Figure Description

[0004] Figure 1 This document presents an example of a system that supports logging latency events for debugging, based on the examples disclosed herein.

[0005] Figure 2 This document presents an example of a system that supports logging latency events for debugging, based on the examples disclosed herein.

[0006] Figure 3 This document demonstrates an example of a process that supports logging latency events for debugging, based on the examples disclosed herein.

[0007] Figure 4 A block diagram is shown illustrating a memory system that supports logging latency events for debugging, based on the examples disclosed in this document.

[0008] Figure 5A block diagram illustrating a host system for debugging that supports logging latency events based on the examples disclosed in this document.

[0009] Figure 6 and 7 The flowchart illustrates one or more methods for debugging that support logging latency events based on the examples disclosed in this document. Detailed Implementation

[0010] In some instances, one or more operations (e.g., procedures) performed at the memory system can cause latency. For example, operations such as garbage collection, error detection or correction, or other operations or conditions can cause unwanted or unexpected latency in the memory system (e.g., in response to one or more commands issued by the host system), which may degrade overall system performance and the associated user experience. In some cases, it may be desirable to determine the cause of latency events at the memory system in order to perform debugging operations and improve system performance. However, replicating or otherwise determining the conditions associated with latency events in the memory system can be difficult. Therefore, it may be difficult to perform debugging operations or other actions to remedy the latency experienced by the memory system. Therefore, a system configured to record latency events in order to perform debugging operations to improve system performance and user experience is desirable.

[0011] Based on the examples described herein, the memory system can be configured to store information associated with latency events in a buffer or memory cell block (e.g., a non-volatile memory cell block). Additionally, the host system can be configured to store information associated with latency events, such as in response to one or more commands. To identify latency events and perform debugging operations, the host system and memory system can synchronize their respective clocks. The memory system can store indications of latency events that meet a threshold (e.g., relatively long latency events) and can provide these events to the host system in response to commands. In some examples, the memory system can output an indication of a single latency event to the host system in response to receiving a command (e.g., based on a timestamp and a synchronized clock); in other examples, the memory system can output an indication of each stored latency event. The host system can receive the indications and can perform one or more debugging operations to improve the overall performance of the memory system.

[0012] Beyond the memory systems described herein, techniques for logging latency events for debugging can also be implemented to support edge computing applications. Edge computing is a distributed computing paradigm that brings computing and data storage closer to the data source than traditional cloud services. As edge computing increasingly provides computing, storage, and networking services at geographically closer locations to end users, many devices and systems can benefit from improved processing, performance, and storage at the edge. For example, increasing the memory density, capacity, and processing power of edge devices can reduce the device's reliance on remote computing or other devices, which would otherwise increase latency for operations performed at the device. Implementing the techniques described herein can support edge computing technologies by allowing debugging operations to reduce latency events, which can improve response times associated with edge computing devices and other benefits.

[0013] Features of this disclosure are described and illustrated in the context of systems, apparatus, and circuits. Features of this disclosure are further described and illustrated in the context of processes and flowcharts.

[0014] Figure 1 This document demonstrates an example of a system 100 that supports logging latency events for debugging, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110. System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle, Internet of Things (IoT) enabled device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked commercial device), or any other computing device that includes memory and processing devices.

[0015] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other devices.

[0016] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to the examples described herein. Host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, host system 105 may use memory system 110 to write data to and read data from memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0017] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include (but are not limited to) SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DIMM slot interfaces supporting DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be included in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface of each memory device 130 included in memory system 110 or via a corresponding physical host interface of each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0018] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0019] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0020] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0021] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include a circuit system having dedicated (e.g., hard-coded) logic that performs the operations attributed to the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit system.

[0022] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130, and the data may be available in local memory 120 for subsequent retrieval by the host system 105 or manipulated by the host system 105 (e.g., updates) according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0023] although Figure 1 The example of memory system 110 described herein includes memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0024] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0025] In some instances, memory device 130 may include (e.g., on the same die, within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115 or perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described herein, memory device 130-a may include local controller 135-a and memory device 130-b may include local controller 135-b. Local controller 135 may be or include a microcontroller, a special-purpose logic circuit system (e.g., field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processor (DSP)) or any other suitable processor or processing circuit system.

[0026] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0027] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) when configured to store two bits of information, a three-level cell (TLC) when configured to store three bits of information, a four-level cell (QLC) when configured to store four bits of information, or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity to support the circuitry.

[0028] In some cases, plane 165 may refer to several groups of blocks 170, and in some cases, concurrent operations can be performed on different planes 165. For example, concurrent operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which concurrent operations can occur. For example, concurrent operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d respectively, and blocks 170-a, 170-b, 170-c, and 170-d can be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0029] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled to a common word line), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled to a common digital line).

[0030] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level or a portion thereof) but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., partially concurrently programmed or read as a single programming or read operation), and block 170 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., partially concurrently erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, a used page 175 cannot be updated until the entire block 170 containing page 175 has been erased.

[0031] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, wiping, block scanning, health monitoring, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting until all pages 175 in block 170 contain invalid data before erasing and reusing block 170, an algorithm called "garbage collection" may be invoked to allow block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example: selecting block 170 containing valid and invalid data; selecting pages 175 in the block containing valid data; copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected pages 175 as invalid; and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, making more blocks 170 available for storing subsequent data (e.g., data subsequently received from host system 105).

[0032] In some instances, operations are performed by memory system 110, for example, in response to commands (e.g., read commands, write commands) from host system 105. For instance, media management operations or other conditions at memory system 110 can cause latency when an operation is performed in response to one or more commands issued by host system 105. In some cases, it may be difficult to determine the conditions associated with the latency or the cause of the latency at memory system 105, which could make it difficult for host system 105 to address the cause of the latency by performing operations (e.g., debugging operations).

[0033] According to the examples described herein, memory system 110 (e.g., memory system controller 115) may be configured to store information associated with latency events in a buffer or memory cell block 170 (e.g., a non-volatile memory cell block). Additionally, host system 105 may be configured to store information associated with latency events, such as in response to one or more issued commands. To identify latency events and perform debugging operations, host system 105 and memory system 110 may synchronize their respective clocks. Memory system 110 may store indications of latency events that meet a threshold (e.g., relatively long latency events) and may provide events to host system 105 in response to commands. In some examples, memory system 110 may output an indication of a single latency event to host system 105 in response to receiving a command (e.g., based on a timestamp and a synchronized clock), while in other examples, memory system 105 may output an indication for each stored latency event. Host system 105 may receive indications and may perform one or more debugging operations to improve the overall performance of memory system 110.

[0034] System 100 may include any number of non-transitory computer-readable media that support recording delay events for debugging. For example, host system 105 (e.g., host system controller 106), memory system 110 (e.g., memory system controller 115), or memory device 130 (e.g., local controller 135), or any combination thereof, may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to host system 105, memory system 110, or memory device 130, or combinations thereof. For example, such instructions, when executed by host system 105 (e.g., host system controller 106), memory system 110 (e.g., memory system controller 115), or memory device 130 (e.g., local controller 135), may cause host system 105, memory system 110, or memory device 130 to perform the associated functions described herein.

[0035] Figure 2 This document demonstrates an example of a system 200 that supports logging latency events for debugging, based on the examples disclosed herein. System 200 may be used as a reference. Figure 1 The system 100 or an example of its aspects is described. System 200 may include a memory system 210 configured to store data received from host system 205 and send data to host system 205 when requested by host system 205 using access commands (e.g., read commands or write commands). System 200 may implement references Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0036] Memory system 210 may include one or more memory devices 240 to (e.g., in response to receiving an access command from host system 205) store data transferred between memory system 210 and host system 205. Memory device 240 may include references. Figure 1 The memory device 240 may include one or more memory devices. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point or other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM or OxRAM and other examples.

[0037] Memory system 210 may include a memory controller 230 for controlling the direct transfer of data to and from memory device 240 (e.g., for storing data, retrieving data, and determining memory locations where data is stored and retrieved). The memory controller 230 may communicate directly with memory device 240 or via a bus (not shown), and may include protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230 (e.g., different memory controllers 230 for each type of memory device 240). In some cases, the memory controller 230 may implement a reference... Figure 1 Aspects of the local controller 135 described.

[0038] The memory system 210 may include an interface 220 for communicating with the host system 205 and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may support the translation of data between the host system 205 and the memory device 240 (e.g., as shown by data path 250) and may be collectively referred to as the data path components.

[0039] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, which reduces latency between commands and supports arbitrary data sizes associated with commands. This also allows command bursts to be handled, and buffered data can be stored or transmitted, or both (e.g., after the burst stops). Buffer 225 may contain relatively fast memory (such as some type of volatile memory, such as SRAM or DRAM) or hardware accelerators, or both, to allow data to be quickly stored in and retrieved from buffer 225. Buffer 225 may contain data path switching components for bidirectional data transfer between buffer 225 and other components.

[0040] Temporary data storage in buffer 225 can refer to data being stored in buffer 225 during the execution of an access command. For example, after an access command completes, the associated data may no longer be stored in buffer 225 (e.g., it can be overwritten by data from an additional access command). In some instances, buffer 225 may be a non-cached buffer. For example, data may not be read directly from buffer 225 by host system 205. In some instances, read commands may be added to a queue without requiring an operation to match the address with an address already in buffer 225 (e.g., no cached address matching or lookup operation is required).

[0041] The memory system 210 may also include a memory system controller 215 for executing commands received from the host system 205, which may include control data path components for data movement. The memory system controller 215 may be a reference... Figure 1 An example of a memory system controller 115 is described. Bus 235 can be used for communication between system components.

[0042] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, if more than one access command from host system 205 is processed concurrently by memory system 210. As an example of a possible implementation, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and memory controller 230, respectively. However, the queues can be located anywhere within memory system 210 during implementation.

[0043] Data transferred between host system 205 and memory device 240 may be routed within memory system 210 along a different path than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0044] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220 (e.g., according to a protocol, such as the UFS protocol or eMMC protocol). Therefore, interface 220 can be considered the front end of memory system 210. After receiving each access command, interface 220 can (e.g., via bus 235) relay the command to memory system controller 215. In some cases, each command can be added to command queue 260 via interface 220 to relay the command to memory system controller 215.

[0045] The memory system controller 215 can determine that an access command has been received based on communication from interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving the command from command queue 260. The command can be removed from command queue 260 after it has been retrieved (e.g., via memory system controller 215). In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260 (e.g., via bus 235).

[0046] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may include obtaining data from one or more memory devices 240 and transferring data to the host system 205. For a write command, this may include receiving data from the host system 205 and moving data to one or more memory devices 240. In either case, the memory system controller 215 may use a buffer 225 to temporarily store data received from or sent to the host system 205, as well as other data. The buffer 225 may be considered as an intermediate layer of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0047] In order to process a write command received from host system 205, memory system controller 215 may determine whether buffer 225 has sufficient available space for storing data associated with the command. For example, memory system controller 215 may (e.g., via firmware, via controller firmware) determine the amount of space within buffer 225 available for storing data associated with the write command.

[0048] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 may be moved to buffer queue 265 by memory system controller 215 and may remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. For example, a pointer indicating the location in buffer 225 where the data associated with each command is stored may be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least a portion of the access commands can be processed concurrently.

[0049] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "transfer ready" indication) to host system 205, which may be executed according to a protocol (e.g., UFS protocol, eMMC protocol). When interface 220 receives data associated with a write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 (e.g., from buffer 225, from buffer queue 265). Interface 220 may indicate to memory system controller 215 (e.g., via bus 235) whether the data transfer to buffer 225 has been completed.

[0050] After data is written and stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240, which may involve the operation of memory controller 230. For example, memory system controller 215 may cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back end of memory system 210. Memory controller 230 may (e.g., via bus 235) indicate to memory system controller 215 that data transfer to one or more memory devices 240 has been completed.

[0051] In some cases, memory queue 270 may support write data transfers. For example, memory system controller 215 may push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain an entry for each access command. In some instances, memory queue 270 may additionally contain a buffer pointer (e.g., an address) indicating the location in buffer 225 where the data associated with the command is stored, and a memory pointer (e.g., an address) indicating the location in memory device 240 where the data is associated. In some cases, memory controller 230 may obtain the location within buffer 225 from which data is obtained (e.g., from buffer 225, from buffer queue 265, from memory queue 270). Memory controller 230 may manage the location within memory device 240 to store data (e.g., perform wear leveling, perform garbage collection). Entries may be added to memory queue 270 (e.g., by memory system controller 215). Entries can be removed from storage queue 270 after data transfer is complete (e.g., by storage controller 230, by memory system controller 215).

[0052] In order to process a read command received from host system 205, memory system controller 215 may determine whether buffer 225 has sufficient available space for storing data associated with the command. For example, memory system controller 215 may (e.g., via firmware, via controller firmware) determine the amount of space within buffer 225 available for storing data associated with the read command.

[0053] In some cases, buffer queue 265 can support buffered storage of data associated with read commands in a manner similar to that discussed with regard to write commands. For example, if buffer 225 has sufficient space to store read data, then memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can (e.g., via bus 235) indicate to memory system controller 215 whether data transfer to buffer 225 has been completed.

[0054] In some cases, the storage queue 270 can be used to facilitate data transfer. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data retrieved from one or more memory devices 240 (e.g., from buffer 225, from storage queue 270). In some cases, the storage controller 230 can obtain the location of data stored in buffer 225 (e.g., from buffer queue 265). In some cases, the storage controller 230 can obtain the location of data stored in buffer 225 (e.g., from storage queue 270). In some cases, the memory system controller 215 can move commands processed by the storage queue 270 back to the command queue 260.

[0055] After data is stored in buffer 225 by storage controller 230, the data can be transferred from buffer 225 to host system 205. For example, memory system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205 (e.g., according to a protocol, such as UFS or eMMC). For example, interface 220 can process commands from command queue 260 and can (e.g., via bus 235) indicate to memory system controller 215 that the data transfer to host system 205 has been completed.

[0056] The memory system controller 215 can execute received commands according to a sequence (e.g., first-in-first-out order, or according to the order of command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to be shifted into and out of buffer 225, as described herein. While data is shifted into and stored in buffer 225, the command may remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been shifted out of buffer 225), then the command may be (e.g., by the memory system controller 215) removed from buffer queue 265. If the command is removed from buffer queue 265, then the address where data associated with this command was previously stored can be used to store data associated with the new command.

[0057] In some instances, the memory system controller 215 may be configured for operations associated with one or more memory devices 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. For example, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the described operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0058] According to the examples described herein, memory system 210 may be configured to store information associated with one or more latency events. For example, memory system 210 may store entries corresponding to latency events at latency event log 245, which may be stored at a memory location of memory system 210. In some instances, the memory location may include a buffer (e.g., a reserved buffer, such as a 4-kilobyte reserved buffer) allocated for storing latency event log 245. Alternatively, latency event log 245 may be stored at one or more memory blocks (e.g., NAND blocks) of memory device 240. In some cases, the memory location for storing latency event log 245 may be allocated based on commands (e.g., instructions) from host system 205 or may be established (e.g., set) during the manufacture of memory system 210.

[0059] In some instances, entries stored in the latency event log 245 may be stored in response to the detection of a latency event and may include a timestamp associated with the latency event (e.g., an indication of the timestamp). In some cases, each entry may be written to the latency event log 245 based on the latency event meeting a threshold. That is, entries may be stored in the latency event log 245 based on the corresponding event being associated with a duration exceeding a latency threshold, which may be a configurable threshold (e.g., via host system 205 or during fabrication in memory system 210). In some instances, the corresponding entry may include an indication of the duration associated with the latency event.

[0060] Alternatively, each entry may contain an indication of the event type associated with the latency event, such as an event that may be associated with experienced latency. For example, if a command is received from host system 205, memory system 210 may be performing one or more operations (e.g., garbage collection). The operations associated with the command can cause additional latency compared to operations that are not in progress after the command is received, due to the ongoing operations. Therefore, by storing the event types associated with latency events, memory event log 245 can be used to determine which operations of memory system 210 may be causing latency.

[0061] For example, an entry may use an identifier corresponding to the respective event type to indicate the event type selected from a set of event types. In some instances, a group of event types may include table update events (e.g., associated with updating logic to a physical table or another table), open block stream events, read retry events (e.g., associated with retrying read operations), interconnect layer event types (e.g., UFS Interconnect (UIC) layer events, such as receiving UIC-based commands), refresh event types (e.g., associated with performing a refresh operation), defragmentation event types (e.g., associated with performing a defragmentation operation), error handling event types (e.g., associated with detecting or correcting one or more errors), read command event types (e.g., associated with performing a read operation), write command event types (e.g., associated with performing a write operation), unmapping event types, synchronization event types, garbage collection event types (e.g., associated with performing garbage collection), background operation event types (e.g., associated with performing background operations, such as media management operations), other event types, or any combination thereof.

[0062] In some instances, host system 205 may be configured to store information associated with latency events at latency log 255. For example, host system 205 may include one or more buffers (e.g., 64-kilobyte buffers) for latency log 255. In some instances, for each entry in latency log 255, host system 205 may include an indication of the logical block address, block size, or both of the command issued, associated with the latency event. Alternatively, host system 205 may store additional information in latency log 255, such as a relatively long latency associated with a command, the duration of the latency, or an indication of no response received from memory system 210 (e.g., timeout). In some instances, each entry may include a timestamp associated with the issued command or the experienced latency.

[0063] In some cases, host system 205 and memory system 210 may execute a clock synchronization procedure. For example, the synchronization procedure may include synchronizing the clock of memory system 210 with a clock external to memory system 210 (e.g., the clock of host system 205). In some instances, the synchronization procedure may include enabling the real-time clock (RTC) of memory system 210 (e.g., based on one or more commands from host system 205), and the synchronization procedure may include host system 205 indicating a clock value for setting or synchronizing the RTC of memory system 210. Alternatively, the synchronization procedure may include host system 205 indicating the clock frequency of the clock of memory system 210, and memory system 210 may set the clock to the indicated frequency, clock value, or both. Thus, by executing the synchronization procedure, the clocks of host system 205 and memory system 210 can be synchronized. Therefore, timestamps can be stored along with entries in delay event log 245 and delay log 255, which can support correlating entries in delay event log 245 with entries in delay log 255 to determine the cause of delay events.

[0064] Host system 205 may output (e.g., transmit) a command requesting information associated with one or more delay events. For example, host system 205 may indicate a time value (e.g., an RTC time value) to memory system 210 via a command. Alternatively, the time value may be an indication of a timestamp of a delay event stored in memory system 210. In some cases, the command may be an instance of a vendor-unique (VU) command. Memory system 210 may identify one or more entries in delay event log 245 based on the indicated time value in response to the command. For example, memory system 210 may determine one or more entries with timestamps that match the indicated time value or have a threshold (e.g., configured by host system 205) for the indicated time value. Memory system 210 may then output (e.g., transmit) one or more corresponding indications (e.g., associated entries) for the identified delay events to host system 205.

[0065] In some cases, host system 205 may output (e.g., transmit) a command requesting indications for all entries stored in latency event log 245. In some instances, to request indications for all entries, host system 205 may indicate an invalid time value (e.g., an invalid RTC time value) via a command. For example, an invalid time value may have a specific (e.g., configuration) value or may be any value not associated with a valid time value (or timestamp). In some cases, an invalid time value may be 0xFFFFFFFF. Memory system 210 may output an indication for each entry stored in latency event log 245 in response to a command indicating an invalid time value.

[0066] Therefore, host system 205 can compare entries at latency log 255 with entries at latency event log 245 and can perform debugging operations based on determining the cause of the latency event. For example, if an error event is determined to cause latency, host system 205 can instruct memory system 210 to perform error correction, refresh operations, or both. Alternatively, if one or more operations at memory system 210, such as refresh operations, background operations, or other operations, are determined to cause latency (e.g., latency duration exceeds a threshold, number of latency events exceeds a threshold), host system 205 can adjust the frequency of these operations. Therefore, the operations described herein can improve the overall performance of memory system 210.

[0067] Figure 3 This document demonstrates an example of procedure 300 for debugging, which supports logging latency events based on the examples disclosed herein. Procedure 300 describes the communication between host system 205 and memory system 210, which may be referenced herein. Figure 1 and 2 Examples of the corresponding apparatus described. In some instances, the steps shown in process 300 may be omitted or performed in a different order than shown. Alternatively, additional steps not shown may be added to process 300.

[0068] Aspects of process 300 may be implemented by one or more controllers and other components. Alternatively, aspects of process 300 may be implemented as instructions stored in one or more memories (e.g., firmware stored in one or more memories coupled to host system 105, memory system 110, or both). For example, instructions executed by one or more controllers (e.g., host system controller 106 and / or memory controller 115) may cause one or more controllers (or devices or systems) to perform the operation of process 300.

[0069] At 305, clock synchronization can be performed. In some examples, host system 205 and memory system 210 can perform clock synchronization. For example, a first clock of memory system 210 can be synchronized with a second clock external to the memory system (e.g., host system 205). Alternatively, host system 205 can be configured with one or more settings for logging latency events. For example, host system 205 can enable RTC for memory system 210. In some instances, host system 205 can configure a latency threshold for memory system 210, which can be associated with the logging of latency events. Alternatively, host system 205 can enable a Backtrack System Debug Solution (BSDS), which can be associated with the reporting of firmware information (e.g., via a UFS interface, such as UIC). In some instances, the BSDS system can be enabled by changing a value stored in a mode register. For example, fields in the mode register can be assigned to indicate one or more parameters of the BSDS system. An example of a parameter stored in the mode register is whether the BSDS system is enabled or disabled. The host system 205 can be configured to write to and / or read from the mode register to set and / or determine one or more parameters (including whether they are enabled or disabled) regarding the BSDS system. The memory system 210 can be configured to write to and / or read from the mode register to set and / or determine one or more parameters (including whether they are enabled or disabled) regarding the BSDS system.

[0070] Alternatively or concurrently, at or before point 305, the debug level can be communicated between host system 205 and storage system 210. In some instances, host system 205 can set a default debug level by transmitting a VU command or one or more attributes to storage system 210. The VU command can indicate one of several levels for performing debug operations. For example, the default debug level can notify storage system 210 that host system 205 is performing (or will perform) one or more debug operations and whether SCSI command latency will be affected by the debug operations.

[0071] At 310, one or more commands may be issued to memory system 210. In some examples, host system 205 may issue one or more commands to memory system 210 (e.g., during the runtime of memory system 210). For example, host system 205 may issue one or more write commands, read commands, or other commands to memory system 210.

[0072] At point 315, one or more latency events can be detected. In some instances, host system 205 can detect latency events with a relatively long duration. For example, host system 205 can determine that the latency of a command has met a threshold, and host system 205 can store an indication of the latency event in a buffer of host system 205. In some cases, the indication of the latency event may include a timestamp associated with the latency event (e.g., based on the detection of the latency event). Alternatively or additionally, the indication of the latency event may include the logical block address associated with the command, an error (e.g., error type) associated with the command or latency event, a block size associated with the command (e.g., for a read or write operation), or a combination thereof. In some instances, different command types (e.g., read commands, write commands, other command types) may be associated with different corresponding thresholds, such that if the corresponding threshold is met, then an indication of the latency event is stored.

[0073] At 320, one or more delay events can be detected and indications of the corresponding delay events can be stored. In some instances, memory system 210 can detect delay events and store indications of delay events in a portion of the memory system (e.g., a reserved buffer, one or more NAND blocks). In some instances, the indication of a delay event may include a timestamp associated with the delay event based on the synchronization of a first clock and a second clock. Alternatively, the indication may include an event type corresponding to the delay event, which may be selected from a set of event types described herein.

[0074] In some instances, the indication may include the duration of the delay associated with the delay event (e.g., measured using one or more timers). Alternatively, the indication may include a value based on a synchronized second clock (e.g., the clock of host system 205). In other instances, the indication may include the LBA or block size of the operation associated with the delay event. For example, a single VU command may indicate multiple indications to host system 205. In other instances, the indication may include an opcode associated with the delay event. The opcode may indicate one (or more) operations associated with the delay event.

[0075] In some instances, indications of latency events may be stored based on whether the latency event meets a latency threshold that may have been configured by the host system 205. For example, if the duration of a corresponding latency event meets (e.g., equal to or greater than) a latency threshold, then the memory system 210 may store an indication of the corresponding latency event at a memory location (e.g., stored in a buffer or NAND block).

[0076] In some cases, the memory system 210 may store indications of latency events even if a latency threshold is not met. For example, the memory system 210 may be configured to store indications of latency events for one or more types of events even if the corresponding latency duration does not meet a latency threshold. In some cases, the memory system 210 may store indications of latency events corresponding to interconnect layer events (e.g., UIC layer events) without checking whether the corresponding event meets a threshold latency.

[0077] At point 325, a command to retrieve one or more delay events can be issued. In some instances, host system 205 can output (e.g., issue, transmit) a command to retrieve one or more delay events stored at a memory location of memory system 210. In some cases, the command can be output during the idle duration of memory system 210 (e.g., the idle time of memory system 210). In some instances, the command can request one or more delay events stored at the memory location with the same (or similar) timestamps as delay events stored in a buffer of host system 205. In some cases, for example, host system 205 can indicate the timestamp of a delay event stored in a buffer of host system 205 or otherwise indicate (e.g., request) delay events with the same or similar timestamps stored at a memory location of memory system 210. In other examples, as described herein, the command can request each entry (e.g., all entries) stored at a memory location of memory system 210.

[0078] At 330, indications of one or more delay events may be issued. In some instances, memory system 210 may output (e.g., issue, transmit) indications of one or more delay events indicated (e.g., requested) by a command. For example, memory system 210 may determine (e.g., identify) one or more delay events having timestamps that match the timestamps contained in a command received from host system 205. In some cases, memory system 210 may identify one or more delay events occurring within a threshold duration of the timestamps contained in the command (e.g., configured by host system 205, e.g., within 1 minute). The indication of one or more delay events may include some or all of the data for each entry stored at a memory location of memory system 210, such as the timestamp, duration, event type, or a combination thereof for each entry. In other instances, as described herein, a command may request each entry (e.g., all entries) stored at a memory location of memory system 210, so memory system 210 may output each entry stored at the memory location.

[0079] At 335, one or more debugging operations can be performed. In some instances, host system 205 may perform one or more debugging operations in response to receiving indications of one or more latency events from memory system 210. For example, host system 205 may determine the cause of latency based on indications of one or more latency events. For instance, host system 205 may determine the cause of latency based on indications of each event type, which may allow host system 205 to trigger error correction, refresh operations, or change the operating frequency at memory system 210, which may result in reduced latency and improved overall performance of memory system 210.

[0080] At 340, a second command may be issued. In some instances, host system 205 may output (e.g., issue, transmit) a second command requesting an indication of each delay event stored at a memory location in memory system 210. In some instances, to request an indication of each delay event, host system 205 may indicate an invalid clock value for the synchronization clock (e.g., as part of the second command, as a separate input to memory system 210). Alternatively or additionally, host system 205 may request an indication of each delay event by setting an invalid clock value (e.g., an invalid RTC value) to a timestamp of the delay event stored in a buffer of host system 205, and the timestamp of the delay event stored in the buffer may be indicated by the second command. In other instances, host system 205 may request an indication of each delay event stored at a memory location at 325.

[0081] At 345, an indication of each entry stored at the memory location can be issued. In some instances, memory system 210 may output (e.g., issue, transmit) an indication of each entry at the memory location corresponding to each delay event in response to a second command. In other instances, the memory system may output an indication of each entry stored at the memory location at 330.

[0082] At position 350, debugging operations can be performed. In some instances, host system 205 can perform debugging operations based on latency events to resolve or otherwise remedy operations performed by memory system 210 that cause latency. Therefore, the operations described herein can improve the overall performance of memory system 210.

[0083] Figure 4 A block diagram 400 illustrates a memory system 420 for debugging that supports logging latency events according to the examples disclosed herein. The memory system 420 may be used as a reference. Figures 1 to 3Examples of aspects of the described memory system. Memory system 420 or its various components may be examples of constructs for performing recording delay events for debugging purposes, as described herein. For example, memory system 420 may include synchronization component 425, indication component 430, command manager 435, delay event component 440, threshold manager 445, or any combination thereof. Components of each of these components or their sub-components (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0084] Synchronization component 425 may be configured or otherwise supported to support means for synchronizing a first clock of the memory system with a second clock associated with a device external to the memory system. Indication component 430 may be configured or otherwise supported to support means for storing indications of one or more delay events in a portion of the memory system in response to a threshold being met by synchronizing the first clock with the second clock, wherein the indication includes a timestamp and type of the delay event. Command manager 435 may be configured or otherwise supported to support means for receiving commands to retrieve one or more delay events stored in a portion of the memory system during a period of memory system idle time. Delay event component 440 may be configured or otherwise supported to support means for transmitting one or more delay events indicated by a command.

[0085] In some instances, the indicator includes the value of a second clock, and the delay event component 440 may be configured or otherwise supported to support a component for identifying a portion of the memory system containing a first delay event with a timestamp matching the value of the second clock, wherein transmitting one or more delay events includes transmitting the first delay event.

[0086] In some instances, the indication is for each delay event of the portion stored in the memory system. In some instances, transmitting one or more delay events includes each delay event of transmitting the portion stored in the memory system.

[0087] In some instances, the command indicates an invalid value for the synchronization clock. In some instances, the transmission of one or more delayed events is based on the command.

[0088] In some instances, to support synchronization of the first clock with the second clock, the command manager 435 may be configured or otherwise supported to support components for receiving a second command indicating the frequency of the second clock. In some instances, to support synchronization of the first clock with the second clock, the synchronization component 425 may be configured or otherwise supported to support components for adjusting the frequency of the first clock based on the received second command.

[0089] In some instances, the threshold manager 445 may be configured or otherwise supported to include components for receiving a third command indicating a threshold. In some instances, the threshold manager 445 may be configured or otherwise supported to include components for setting a threshold based on the received third command, wherein the storage of indications of one or more delay events is based on setting the threshold.

[0090] In some instances, latency event types include table update events, open block stream events, read retry events, interconnect layer event types, refresh event types, defragmentation event types, error handling event types, read command event types, write command event types, unmapping event types, synchronization event types, garbage collection event types, or background operation event types, or any combination thereof.

[0091] In some instances, the delay event component 440 may be configured or otherwise supported to support means for detecting the occurrence of a first delay event among one or more delay events. In some instances, the threshold manager 445 may be configured or otherwise supported to support means for determining whether a first delay event satisfies a threshold, wherein each indication stored in the memory system is associated with a delay event that satisfies the threshold.

[0092] In some instances, portions of the memory system contain buffers or blocks of non-volatile memory cells. In some instances, each timestamp contains the duration associated with the corresponding delayed event. In some instances, the command contains VU commands. In some instances, devices external to the memory system contain the host system.

[0093] In some instances, the described functionality of memory system 420 or its various components may be supported by or refer to at least a portion of at least one processor, wherein such at least one processor may comprise one or more processing elements (e.g., controller, microprocessor, microcontroller, digital signal processor, state machine, discrete gate logic, discrete transistor logic, discrete hardware component, or any combination of one or more of such elements). In some instances, the described functionality of memory system 420 or its various components may be implemented at least in part by instructions executable by such at least one processor (e.g., stored in memory, non-transitory computer-readable medium).

[0094] Figure 5 A block diagram 500 illustrates a host system 520 for debugging, supporting the logging of latency events based on the examples disclosed herein. Host system 520 may be used as a reference. Figures 1 to 3Examples of aspects of the described host system. Host system 520 or its various components may be examples of constructs for performing various aspects of logging latency events for debugging, as described herein. For example, host system 520 may include a synchronization manager 525, an instruction manager 530, a command component 535, a latency event manager 540, a debugging component 545, a threshold component 550, or any combination thereof. Components of each of these components or their sub-components (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0095] Synchronization manager 525 may be configured or otherwise supported to support components for synchronizing a first clock of the host system with a second clock associated with a device external to the host system. Indication manager 530 may be configured or otherwise supported to store indications of one or more delay events in a buffer of the host system in response to a delay event satisfying a threshold, based on synchronizing the first clock with the second clock, wherein the indications include timestamps. Command component 535 may be configured or otherwise supported to transmit a command for retrieving a first set of delay events stored in a buffer during a period of host system idle time, wherein the first set of delay events corresponds to a second set of delay events stored on a device external to the host system. Delay event manager 540 may be configured or otherwise supported to receive indications of a second set of delay events from a device external to the host system in response to transmitting a command, wherein the second set of delay events received from the device external to the host system includes a timestamp and delay event type for each corresponding delay event. Debug component 545 may be configured or otherwise supported to perform debugging operations based on received indications.

[0096] In some instances, the command includes a request for a first delayed event stored on a device outside the host system, having the same timestamp as the second delayed event stored in the buffer. In some instances, the request is for each delayed event stored on a device outside the host system. In some instances, the request for each delayed event stored on a device outside the host system includes an invalid value for the synchronization clock.

[0097] In some instances, latency event types include table update events, open block stream events, read retry events, interconnect layer event types, refresh event types, defragmentation event types, error handling event types, read command event types, write command event types, unmapping event types, synchronization event types, garbage collection event types, or background operation event types, or any combination thereof.

[0098] In some instances, to support synchronization with a second clock, the synchronization manager 525 may be configured or otherwise support components for transmitting a second command indicating the frequency of the first clock.

[0099] In some instances, the threshold component 550 may be configured or otherwise support a component for transmitting a third command indicating a threshold delay value for storing delay events. In some instances, the command includes a VU command. In some instances, a device external to the host system includes a memory system.

[0100] In some instances, the described functionality of the host system 520 or its various components may be supported by or refer to at least a portion of at least one processor, wherein the at least one processor may comprise one or more processing elements (e.g., a controller, microprocessor, microcontroller, digital signal processor, state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some instances, the described functionality of the host system 520 or its various components may be implemented at least in part by instructions executable by the at least one processor (e.g., stored in memory, non-transitory computer-readable media).

[0101] Figure 6 The flowchart illustrates a method 600 for debugging that supports logging latency events according to the examples disclosed herein. The operation of method 600 can be implemented by the memory system or its components described herein. For example, the operation of method 600 can be implemented by reference to... Figures 1 to 4 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0102] At 605, the method may include synchronizing a first clock of the memory system with a second clock associated with a device external to the memory system. In some instances, aspects operating at 605 may be referenced. Figure 4 The described synchronization component 425 is executed.

[0103] At 610, the method may include storing an indication of one or more delay events into a portion of a memory system in response to a corresponding delay event among one or more delay events satisfying a threshold, based on synchronizing a first clock with a second clock. The indication includes a timestamp and type of the delay event. In some instances, aspects of operation 610 may be referenced. Figure 4 The description indicates that component 430 is executed.

[0104] At 615, the method may include receiving a command to retrieve one or more delayed events stored in a portion of the memory system during a period of memory system idle time. In some instances, aspects of operation 615 may be referenced. Figure 4 The command manager 435 described is executed.

[0105] At 620, the method may include transmitting one or more delayed events indicated by a command. In some instances, aspects of operation 620 may be referenced. Figure 4 The delayed event component 440 is executed as described.

[0106] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing processor-executable instructions) for performing aspects of this disclosure, or any combination thereof:

[0107] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising, or any combination thereof, instructions for: synchronizing a first clock of a memory system with a second clock associated with a device external to the memory system; storing an indication of one or more delay events in a portion of the memory system in response to a corresponding delay event of one or more delay events satisfying a threshold, based on synchronizing the first clock with the second clock, wherein the indication includes a timestamp and type of the delay event; receiving a command to retrieve the one or more delay events stored in the portion of the memory system during a period of idle time of the memory system; and transmitting the one or more delay events indicated by the command.

[0108] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1, wherein the indication includes the value of the second clock, and the method, apparatus, or non-transitory computer-readable medium further includes an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: identifying a first delay event having a timestamp matching the value of the second clock stored in the portion of the memory system, wherein transmitting the one or more delay events includes transmitting the first delay event.

[0109] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 2, wherein the indication is for each delay event stored in the portion of the memory system, and transmitting the one or more delay events includes transmitting each delay event stored in the portion of the memory system.

[0110] Aspect 4: The method, device, or non-transitory computer-readable medium according to aspect 3, wherein the command indicates an invalid value for the synchronization clock, and the transmission of the one or more delay events is based on the command.

[0111] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4, wherein synchronizing the first clock with the second clock comprises operations, features, circuitry, logic, components, or instructions or any combination thereof for: receiving a second command indicating the frequency of the second clock; and adjusting the frequency of the first clock according to receiving the second command.

[0112] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 5, further comprising an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: receiving a third command indicating the threshold; and setting the threshold according to receiving the third command, wherein the indication storing the one or more delay events is based on setting the threshold.

[0113] Aspect 7: The method, device, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein the type of the latency event includes a table update event, an open block stream event, a read retry event, an interconnect layer event type, a refresh event type, a defragmentation event type, an error handling event type, a read command event type, a write command event type, an unmapping event type, a synchronization event type, a garbage collection event type, or a background operation event type, or any combination thereof.

[0114] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7, further comprising an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: detecting the occurrence of a first delay event among the one or more delay events; and determining whether the first delay event satisfies the threshold, wherein each indication stored in the portion of the memory system is associated with a delay event that satisfies the threshold.

[0115] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 8, wherein the portion of the memory system comprises a buffer or a block of non-volatile memory cells.

[0116] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein each timestamp contains a duration associated with the corresponding delay event.

[0117] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 10, wherein the command comprises a VU command.

[0118] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein the means external to the memory system comprises a host system.

[0119] Figure 7 The flowchart illustrates method 700 for debugging, which supports logging latency events based on the examples disclosed herein. The operation of method 700 can be implemented by the host system or its components described herein. For example, the operation of method 700 can be implemented by [reference needed]. Figures 1 to 3 The host system described in section 5 performs the functions described. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0120] At 705, the method may include synchronizing a first clock of the host system with a second clock associated with a device external to the host system. In some instances, aspects of operation 705 may be referenced. Figure 5 The described synchronization manager 525 is executed.

[0121] At 710, the method may include storing an indication of one or more delay events into a buffer of the host system in response to a delay event satisfying a threshold, based on synchronizing a first clock with a second clock, wherein the indication includes a timestamp. In some instances, aspects of operation 710 may be referenced. Figure 5 The description indicates that the manager 530 is executing.

[0122] At 715, the method may include transmitting a command to retrieve a first set of delay events stored in a buffer during a duration of host system idle time, wherein the first set of delay events corresponds to a second set of delay events stored in a device outside the host system. In some instances, aspects of operation 715 may be referenced. Figure 5 The command component 535 described is executed.

[0123] At 720, the method may include an indication to receive a second set of delay events from a device external to the host system in response to a transmission command, wherein the second set of delay events received from the device external to the host system includes a timestamp and a delay event type for each corresponding delay event. In some instances, aspects of operation 720 may be referenced from [reference needed]. Figure 5 The described delay event manager 540 is executed.

[0124] At 725, the method may include performing debugging operations based on received instructions. In some instances, aspects of operating 725 may be referenced. Figure 5 The described debug component 545 is executed.

[0125] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing processor-executable instructions) for performing aspects of this disclosure, or any combination thereof:

[0126] Aspect 13: A method, apparatus, or non-transitory computer-readable medium comprising, or any combination thereof, instructions for: synchronizing a first clock of a host system with a second clock associated with a device external to the host system; storing an indication of one or more delay events in a buffer of the host system in response to delay events satisfying a threshold, wherein the indication includes a timestamp, based on synchronizing the first clock with the second clock; transmitting a command to retrieve a first set of delay events stored in the buffer during a duration of idle time of the host system, wherein the first set of delay events corresponds to a second set of delay events stored in the device external to the host system; receiving an indication of the second set of delay events from the device external to the host system in response to transmitting the command, wherein the second set of delay events received from the device external to the host system includes a timestamp and delay event type for each corresponding delay event; and performing a debugging operation based on receiving the indication.

[0127] Aspect 14: The method, device, or non-transitory computer-readable medium according to aspect 13, wherein the command includes a request for a first delayed event stored outside the host system on the device having the same timestamp as the second delayed event stored in the buffer.

[0128] Aspect 15: The method, device, or non-transitory computer-readable medium according to aspect 14, wherein the request is for each time-delayed event of the device stored outside the host system.

[0129] Aspect 16: The method, apparatus, or non-transitory computer-readable medium according to aspect 15, wherein the request for each delay event of the device stored outside the host system includes an invalid value of the synchronization clock.

[0130] Aspect 17: The method, device, or non-transitory computer-readable medium according to any one of aspects 13 to 16, wherein the latency event type includes table update event, open block stream event, read retry event, interconnect layer event type, refresh event type, defragmentation event type, error handling event type, read command event type, write command event type, unmapping event type, synchronization event type, garbage collection event type, or background operation event type, or any combination thereof.

[0131] Aspect 18: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 17, wherein synchronization with the second clock includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for transmitting a second command indicating the frequency of the first clock.

[0132] Aspect 19: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 18 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for transmitting a third command indicating a threshold delay value for storing a delay event.

[0133] Aspect 20: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 19, wherein the command comprises a VU command.

[0134] Aspect 21: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 20, wherein the means external to the host system includes a memory system.

[0135] It should be noted that the described techniques include possible implementations, and the operation and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0136] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a signal bus, where the bus can have various bit widths.

[0137] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0138] The term "coupling" (e.g., "electrical coupling") can refer to a condition that changes from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals can travel between components via conductive paths). If, for example, a component of a controller couples other components together, then the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted to allow signals.

[0139] The term "isolation" refers to the relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, if a switch positioned between two components is turned on, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0140] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe the connection between conditional actions, conditional procedures, or parts of a procedure.

[0141] The term "in response to" can refer to a condition or action that occurs at least partially (if not entirely) due to a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least partially due to the occurrence of a preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0142] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some other instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0143] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0144] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other instances." "Detailed Description" contains specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concept of the described instances.

[0145] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a hyphen after the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0146] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored as one or more instructions (e.g., code) on or transmitted via a computer-readable medium. Due to the nature of software, the functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can be physically located at various locations, including distributed portions of the functions implemented at different physical locations.

[0147] The descriptive blocks and modules described herein may be implemented or executed by one or more processors (e.g., DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. The processor may be an instance of a microprocessor, controller, microcontroller, state machine, or other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0148] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0149] As used herein (included in the claims), the article “a” preceding a noun is open-ended and should be understood to mean “at least one” or “one or more” of the nouns. Therefore, the terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. For example, if a claim refers to a “component” performing one or more functions, then each of the individual functions can be performed by a single component or any combination of components. Therefore, the term “component” having a characteristic or performing a function can refer to “at least one of one or more components” having a particular characteristic or performing a particular function. The subsequent use of the term “the / said” to refer to a component introduced by the article “a” can refer to any or all of one or more components. For example, a component introduced by the article “a” can be understood to mean “one or more components,” and the subsequent reference to “the component” in a claim can be understood to be equivalent to “at least one of the one or more components.” Similarly, the term "the / said" used subsequently to refer to a component introduced as "one or more components" can refer to any or all of the one or more components. For example, the reference to "the one or more components" in the subsequent claims can be understood as equivalent to referring to "at least one of the one or more components".

[0150] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media or combination of media that is accessible by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code elements in the form of instructions or data structures and are accessible by a computer or one or more processors.

[0151] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: One or more memory devices; and A processing circuitry system coupled to and configured such that the memory system: Synchronize the first clock of the memory system with a second clock associated with a device external to the memory system; Synchronizing the first clock with the second clock, and storing an indication of one or more delay events in a portion of the memory system in response to a corresponding delay event in one or more delay events satisfying a threshold, wherein the indication includes a timestamp and type of the corresponding delay event; During the duration of the memory system's idle period, a command is received to retrieve the one or more delay events stored in the portion of the memory system; and Transmit the one or more delay events indicated by the command.

2. The memory system of claim 1, wherein the indication includes the value of the second clock, and the processing circuitry system is further configured such that the memory system: Identify a first delay event stored in the portion of the memory system having a timestamp that matches the value of the second clock, wherein transmitting the one or more delay events includes transmitting the first delay event.

3. The memory system of claim 1, wherein the indication is for each delay event stored in the portion of the memory system, and wherein transmitting the one or more delay events includes transmitting each delay event stored in the portion of the memory system.

4. The memory system of claim 3, wherein the command indicates an invalid value for the synchronization clock, and wherein the transmission of the one or more delay events is based on the command.

5. The memory system of claim 1, wherein synchronizing the first clock with the second clock includes configuring the processing circuitry system such that the memory system: Receive a second command indicating the frequency of the second clock; and The frequency of the first clock is adjusted according to the received second command.

6. The memory system of claim 1, wherein the processing circuitry is further configured such that the memory system: Receive a third command indicating the threshold; and The threshold is set according to the received third command, wherein the indication storing the one or more delay events is based on setting the threshold.

7. The memory system of claim 1, wherein the type of the corresponding latency event includes table update event, open block stream event, read retry event, interconnect layer event type, refresh event type, defragmentation event type, error handling event type, read command event type, write command event type, unmapping event type, synchronization event type, garbage collection event type, or background operation event type, or any combination thereof.

8. The memory system of claim 1, wherein the processing circuitry is further configured such that the memory system: Detecting the occurrence of the first delay event among the one or more delay events; and Determine whether the first delay event satisfies the threshold, wherein each indication stored in the portion of the memory system is associated with a delay event that satisfies the threshold.

9. The memory system of claim 1, wherein the portion of the memory system comprises a buffer or a block of non-volatile memory cells.

10. The memory system of claim 1, wherein each timestamp includes a duration associated with the corresponding delay event.

11. The memory system of claim 1, wherein the command includes vendor-unique (VU) commands.

12. The memory system of claim 1, wherein the device outside the memory system includes a host system.

13. A host system comprising: One or more interfaces, which include one or more signal paths operable to communicate with at least one memory system; and A processing circuitry system coupled to and configured to cause the host system to: Synchronize the first clock of the host system with the second clock associated with a device external to the host system; Synchronize the first clock with the second clock, and store a first indication of one or more delay events in the buffer of the host system in response to a delay event meeting a threshold, wherein the first indication includes a timestamp; During the duration of the host system's idle period, a command is transmitted to retrieve a first set of latency events stored in the buffer, wherein the first set of latency events corresponds to a second set of latency events stored in the device outside the host system; A second indication is received from the device outside the host system in response to the transmission of the command, wherein the second set of delay events received from the device outside the host system includes a timestamp and delay event type for each corresponding delay event; and Perform debugging operations based on the received second instruction.

14. The host system of claim 13, wherein the command includes a request for a first delay event stored outside the host system on the device having the same timestamp as the second delay event stored in the buffer.

15. The host system of claim 14, wherein the request is for each latency event of the device stored outside the host system.

16. The host system of claim 15, wherein the request for each delay event of the device stored outside the host system includes an invalid value for the synchronization clock.

17. The host system of claim 13, wherein the latency event type of each corresponding latency event includes a table update event, an open block stream event, a read retry event, an interconnect layer event type, a refresh event type, a defragmentation event type, an error handling event type, a read command event type, a write command event type, an unmapping event type, a synchronization event type, a garbage collection event type, or a background operation event type, or any combination thereof.

18. The host system of claim 13, wherein synchronization with the second clock includes the processing circuitry being configured such that the host system: Transmit a second command indicating the frequency of the first clock.

19. The host system of claim 13, wherein the processing circuitry is further configured such that the host system: The transmission indicates a third command used to store the threshold delay value for delay events.

20. The host system of claim 13, wherein the command includes a vendor-unique (VU) command.

21. The host system of claim 13, wherein the device external to the host system includes a memory system.

22. A non-transitory computer-readable medium storing code, said code comprising instructions executable by one or more processors to perform the following operations: Synchronize the first clock of the memory system with a second clock associated with a device external to the memory system; Synchronizing the first clock with the second clock, and storing an indication of one or more delay events in a portion of the memory system in response to a corresponding delay event in one or more delay events satisfying a threshold, wherein the indication includes a timestamp and type of the corresponding delay event; During the duration of the memory system's idle period, a command is received to retrieve the one or more delay events stored in the portion of the memory system; and Transmit the one or more delay events indicated by the command.

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