Methods, equipment, and media for supporting in-word RAID striping interleaving in Sub Page Program mode

By writing data in batches using flash memory dies in Sub Page Program mode and performing an XOR operation before physical programming each subpage, the problem of misaligned writing timing between RAID stripe interleaved data and parity information is solved, thus achieving reliable data protection.

CN122240019APending Publication Date: 2026-06-19SUZHOU UNIONMEMORY INFORMATION SYST LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SUZHOU UNIONMEMORY INFORMATION SYST LTD
Filing Date
2026-03-16
Publication Date
2026-06-19

AI Technical Summary

Technical Problem

In Sub Page Program mode, the timing of writing RAID stripe interleaved data and parity information is misaligned, resulting in invalid parity information and posing a risk of data protection mechanism failure.

Method used

By employing address allocation and stripe allocation strategies, the synchronous writing of RAID stripe interleaved data and parity information is ensured. Specific measures include writing in batches based on flash dies and performing an XOR operation before physical programming each subpage to ensure the validity of the parity data.

Benefits of technology

It achieves reliable protection of RAID striped interleaved data in subpage programming mode, ensuring that the parity information is always valid during the writing process and preventing data loss or damage.

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Abstract

This invention discloses a method for supporting RAID stripe interleaving within a word line in Sub Page Program mode, relating to the field of solid-state drive technology. The method includes: organizing user data into multiple RAID stripes, each RAID stripe containing multiple data subpages and a parity subpage distributed within the same word line; responding to a write command and determining the programming order of the target word line and its subpages; processing each target subpage within the target word line sequentially according to this order. The processing includes: before writing the target subpage to the NAND flash memory, performing an XOR operation on the RAID stripe to which it belongs to generate parity data, and then writing the complete RAID stripe information containing the target subpage and the corresponding parity data to the NAND flash memory. The subpage programming order is controlled by an address allocation strategy, ensuring that subpages within the target word line are written in batches using flash dies; the RAID stripe is controlled by a stripe allocation strategy, ensuring that data subpages and parity pages within the same RAID stripe are distributed across different flash dies. This invention effectively prevents parity failure due to write timing misalignment.
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