Read management method and storage device

Abstract

This invention provides a read management method and a storage device. The method includes: triggering a prefetch function for a memory module; and after triggering the prefetch function, determining a prefetch mode corresponding to the prefetch function based on instruction load information, wherein the instruction load information reflects the total amount of data to be read. This improves the data read performance of the storage device.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a read management method and storage device. Background Technology

[0002] Generally, to improve data read performance, some types of storage devices support data prefetching. For example, during sequential read operations by the host system, the data to be read later by the host system (also known as prefetch data) is predicted and cached in a buffer memory using prefetching technology. Then, when the host system receives a read instruction for this prefetch data, the memory controller can directly transfer the prefetch data from the buffer memory to the host system, thereby improving the data read performance of the storage device.

[0003] However, common prefetching mechanisms typically cache a fixed amount of prefetched data in an external buffer after the prefetching function is triggered, awaiting retrieval by the host system. However, a common problem in practice is that when the prefetched data occupies too much cache space, it can negatively impact the storage device's performance for regular data retrieval, thus causing the opposite effect. Summary of the Invention

[0004] This invention provides a read management method and a storage device that can improve the above-mentioned problems and thereby enhance the data read performance of the storage device.

[0005] This invention provides a read management method for a storage device, wherein the storage device includes a memory module, and the read management method includes: triggering a pre-read function for the memory module; and after triggering the pre-read function, determining a pre-read mode corresponding to the pre-read function based on instruction load information, wherein the instruction load information reflects the total amount of data to be read.

[0006] This invention also provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute a read management method.

[0007] Based on the above, after triggering the prefetch function for the memory module, the prefetch mode corresponding to the prefetch function can be dynamically determined according to the instruction load information. Therefore, the prefetch function can be optimized by dynamically determining or adjusting the prefetch mode under different instruction load conditions. This effectively improves the data reading performance of the memory device. Attached Figure Description

[0008] Figure 1This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram illustrating the determination of a prefetch mode based on the numerical relative relationship between instruction load information and at least one critical information, according to an embodiment of the present invention.

[0012] Figure 5 This is a schematic diagram illustrating the caching of prefetched data in the first prefetch mode according to an embodiment of the present invention;

[0013] Figure 6 This is a schematic diagram illustrating the caching of prefetched data in the second prefetch mode according to an embodiment of the present invention;

[0014] Figure 7 This is a flowchart illustrating a read management method according to an embodiment of the present invention. Detailed Implementation

[0015] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0016] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0017] The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0018] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0019] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0020] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0021] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0022] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0023] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0027] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(C). Each physical unit includes multiple storage units for non-volatile storage of data.

[0028] In one embodiment, an entity unit may include at least one entity programmable unit. For example, an entity programmable unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on an entity programmable unit to write data to that entity programmable unit, multiple memory cells in that entity programmable unit may be synchronously programmed to store the corresponding data. For example, when programming an entity programmable unit, a write voltage may be applied to that entity programmable unit to change the threshold voltage of at least some of the memory cells in that entity programmable unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell. In one embodiment, an entity programmable unit is also referred to as an entity page. For example, the storage capacity of an entity programmable unit may be 16 kilobytes, and the invention is not limited thereto.

[0029] In one embodiment, an entity programming unit includes multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0030] In one embodiment, a physical erase unit may include multiple physical programmable units. For example, the multiple physical programmable units in a physical erase unit may be erased simultaneously. For example, when an erase operation is performed on a physical erase unit, an erase voltage may be applied to the multiple physical programmable units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programmable units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0031] In one embodiment, an entity unit may include at least one entity erasure unit. In another embodiment, if an entity unit includes multiple entity erasure units, this entity unit is also referred to as a virtual block. Multiple entity erasure units contained in the same virtual block can operate synchronously.

[0032] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0033] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0034] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0035] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LCA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0036] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0037] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0038] In one embodiment, the memory control circuit 23 may perform a read operation on the memory module 122. For example, this read operation is used to read data from at least one physical cell in the memory module 122.

[0039] In one embodiment, the read operation includes a pre-read operation. This pre-read operation is used to read specific data (also referred to as pre-read data) from the memory module 122. For example, this pre-read data may include data that the host system 11 has not yet instructed to read, but the memory control circuitry 23 predicts may be read by the host system 11 next. In one embodiment, this pre-read data may also include data that the host system 11 is currently instructing to read. That is, this pre-read data may be a mixture of data that the host system 11 is currently instructing to read and data that the host system 11 may read in the future.

[0040] In one embodiment, during a sequential read operation performed by the host system 11, the memory control circuit 23 can predict the data that the host system 11 may subsequently read (i.e., pre-fetch data) based on at least one previously received read instruction from the host system 11. Then, the memory control circuit 23 can use pre-fetching technology to read and cache this pre-fetch data from the memory module 122 before actually receiving or processing the read instruction from the host system 11 for this pre-fetch data. Subsequently, when the read instruction from the host system 11 for this pre-fetch data is actually processed, the memory control circuit 23 can directly transmit the cached pre-fetch data to the host system 11, thereby improving the data read performance of the storage device 12. In other words, during a sequential read operation performed by the host system 11, the memory control circuit 23 can perform a pre-fetch operation on the memory module 122 based on at least one previously received read instruction from the host system 11.

[0041] In one embodiment, suppose that multiple read instructions previously received from the host system 11 indicate the sequential reading of data belonging to logic units LCA(1)-LCA(10). Based on these read instructions, the memory control circuit 23 can predict that the host system 11 may subsequently read data belonging to logic unit LCA(11) following these read instructions. Therefore, based on the prediction, the memory control circuit 23 can determine the data belonging to logic unit LCA(11) as pre-read data. Then, before actually receiving or processing a read instruction indicating the reading of data belonging to logic unit LCA(11), the memory control circuit 23 can perform a pre-read operation on the memory module 122 to read the data belonging to logic unit LCA(11). Subsequently, when the host system 11 actually processes the read instruction for logic unit LCA(11), the memory control circuit 23 can directly transmit the pre-read data belonging to logic unit LCA(11) to the host system 11, thereby improving the data reading performance of the storage device 12.

[0042] In one embodiment, the memory control circuit 23 may automatically trigger a prefetch function for the memory module 122. For example, before triggering this prefetch function, the memory control circuit 23 may not perform and / or support the aforementioned prefetch operation. After triggering this prefetch function, the memory control circuit 23 may automatically perform the aforementioned prefetch operation according to a read instruction from the host system 11.

[0043] In one embodiment, the memory control circuit 23 can automatically trigger the prefetch function for the memory module 122 according to preset rules. For example, during the sequential read operation performed by the host system 11, the memory control circuit 23 can automatically trigger the prefetch function for the memory module 122. For example, if (or in response to) the host system 11 performing the sequential read operation, the memory control circuit 23 can automatically trigger the prefetch function for the memory module 122. However, if (or in response to) the host system 11 not performing the sequential read operation, the memory control circuit 23 may not trigger the prefetch function for the memory module 122.

[0044] In one embodiment, if the host system 11 indicates that it is reading more than a predetermined proportion of a logical address range within a certain period of time, the memory control circuit 23 can determine that the host system 11 is performing a sequential read and automatically trigger the prefetch function for the memory module 122. For example, this predetermined proportion can be 80% and can be adjusted according to practical needs. For example, assuming that the host system 11 indicates that it is reading more than 80% of a logical address range within a certain period of time, the memory control circuit 23 can determine that the host system 11 is performing a sequential read and automatically trigger the prefetch function for the memory module 122. In one embodiment, the preset rule for triggering the prefetch function for the memory module 122 can be set or adjusted according to practical needs, and the present invention does not limit it.

[0045] In one embodiment, the memory control circuit 23 can determine a mode (also called a prefetch mode) corresponding to the triggered prefetch function based on specific information (also called instruction load information). Specifically, this instruction load information relates to the total amount of data to be read. For example, this instruction load information may reflect the total amount of data to be read. The memory control circuit 23 can then execute the currently triggered prefetch function (or prefetch operation) based on this prefetch mode.

[0046] In one embodiment, the memory control circuit 23 can acquire various evaluation information. This evaluation information can be used to assess the total amount of data to be read. The memory control circuit 23 can determine instruction load information based on this evaluation information.

[0047] In one embodiment, various evaluation information includes instruction count information and data block size information. Instruction count information reflects the total number of read instructions to be processed. For example, each read instruction to be processed may be cached in the instruction queue of buffer memory 24 and await processing. Furthermore, data block size information reflects the amount of data read corresponding to a single read instruction.

[0048] In one embodiment, the memory control circuit 23 can obtain the total number of read instructions currently cached in the instruction queue, and obtain instruction count information based on this total number. For example, assuming the total number of read instructions currently cached in the instruction queue is a specific number, the memory control circuit 23 can obtain instruction count information based on this specific number. For example, this instruction count information can reflect this specific number. In one embodiment, the instruction count information may include queue depth information. This queue depth information can reflect the current depth of the instruction queue.

[0049] In one embodiment, the memory control circuit 23 can obtain the size (i.e., dimensions) of data blocks processed (e.g., read) by at least a portion of the read instructions currently cached in the instruction queue. For example, the size of a data block processed (e.g., read) by a particular read instruction can reflect the amount of data processed (e.g., read) by that read instruction. Then, the memory control circuit 23 can obtain data block size information based on the obtained size of at least one data block. For example, this data block size information can reflect the size of at least one statistically significant data block (e.g., average size).

[0050] In one embodiment, the memory control circuit 23 can determine the instruction load information based on the instruction quantity information and the data block size information. For example, the memory control circuit 23 can obtain the instruction load information by multiplying the instruction quantity information and the data block size information. For example, the memory control circuit 23 can obtain the instruction load information according to the following formula (1).

[0051]

[0052] In formula (1), P can represent instruction load information, N can represent instruction quantity information, and M can represent data block size information. For example, assuming N=10 and M=128 KB, it means that the total number of read instructions currently cached in the instruction queue is 10, and the amount of data read by a single read instruction is 128 KB. It should be noted that formula (1) can also be adjusted according to practical needs, and this invention does not impose any restrictions.

[0053] In one embodiment, the memory control circuit 23 can convert formula (1) into the following formula (2).

[0054]

[0055] In formula (2), the memory control circuit 23 can convert the product of N and M in the original formula (1) into the product of QD (i.e., queue depth) and BS (i.e., data block size). Here, QD can be the same as N, and BS can be the same as M. It should be noted that formula (2) can also be adjusted according to practical needs, and the present invention does not impose any restrictions.

[0056] In one embodiment, the memory control circuit 23 may pre-set multiple prefetch modes (also known as candidate prefetch modes). Based on the instruction load information, the memory control circuit 23 may determine (i.e. select) the prefetch mode (also known as the target prefetch mode) corresponding to the currently triggered prefetch function from these candidate prefetch modes.

[0057] In one embodiment, the plurality of candidate prefetch patterns include one prefetch pattern (also referred to as the first prefetch pattern) and another prefetch pattern (also referred to as the second prefetch pattern). The first prefetch pattern is different from the second prefetch pattern.

[0058] In one embodiment, in the first prefetch mode, the prefetch data (also referred to as the first prefetch data) read from the memory module 122 via the prefetch function can be cached in a certain storage space (also referred to as the first storage space) to await being read by the host system 11. Furthermore, in the second prefetch mode, the prefetch data (also referred to as the second prefetch data) read from the memory module 122 via the prefetch function can be cached in another storage space (also referred to as the second storage space) to await being read by the host system 11.

[0059] In one embodiment, the first storage space includes a buffer memory (also referred to as a first type buffer) external to the memory module 122, and the second storage space does not include this buffer memory (i.e., the first type buffer). The first type buffer may be located external to the memory module 122 and used to cache pre-fetched data read in real time from the memory module 122 via a pre-fetch function. For example, the first type buffer may include buffer memory 24.

[0060] In one embodiment, both the first storage space and the second storage space include a buffer (also referred to as a second type of buffer) within the memory module 122. The second type of buffer may be located within the memory module 122. Similar to the first type of buffer, the second type of buffer can also be used to cache pre-fetched data read in real-time from the memory module 122 via a pre-fetch function. For example, the second type of buffer may include buffer circuitry within the memory module 122.

[0061] In other words, in one embodiment, the first storage space may include a first type of buffer disposed outside the memory module 122 and a second type of buffer disposed inside the memory module 122. However, the second storage space only includes the second type of buffer disposed inside the memory module 122.

[0062] In one embodiment, the first type of buffer may include DRAM or other types of volatile memory. In another embodiment, the second type of buffer may include a NAND flash memory module or other types of rewritable non-volatile memory modules.

[0063] In one embodiment, the memory control circuit 23 can obtain the numerical relative relationship between instruction load information and at least one critical information. Then, the memory control circuit 23 can determine a target prefetch mode from multiple candidate prefetch modes based on this numerical relative relationship. That is, the memory control circuit 23 can determine one of the multiple candidate prefetch modes as the target prefetch mode based on this numerical relative relationship. After determining the target prefetch mode, the memory control circuit 23 can perform a prefetch function (or prefetch operation) based on this target prefetch mode.

[0064] In one embodiment, the numerical relative relationship includes one numerical relative relationship (also referred to as the first numerical relative relationship) and another numerical relative relationship (also referred to as the second numerical relative relationship). If the numerical relative relationship between the instruction load information and at least one critical information is the first numerical relative relationship, the memory control circuit 23 can determine the first prefetch mode as the target prefetch mode based on the first numerical relative relationship. However, if the numerical relative relationship between the instruction load information and at least one critical information is the second numerical relative relationship, the memory control circuit 23 can determine the second prefetch mode as the target prefetch mode based on the second numerical relative relationship.

[0065] In one embodiment, at least one critical information includes a certain critical value (also referred to as a first critical value) and another critical value (also referred to as a second critical value). The second critical value may be greater than the first critical value. For example, the second critical value may be 4096 KB, and the first critical value may be 1024 KB. It should be noted that both the first and second critical values ​​can be adjusted according to practical needs, and the present invention does not impose any limitations on them.

[0066] In one embodiment, the memory control circuit 23 can compare instruction load information with at least one threshold information to obtain a comparison result. If the comparison result shows that the instruction load information is less than a first threshold value, the memory control circuit 23 can determine that the numerical relative relationship between the instruction load information and the at least one threshold information is a first numerical relative relationship. Then, the memory control circuit 23 can determine the first prefetch mode as the target prefetch mode based on this first numerical relative relationship.

[0067] On the other hand, if the comparison result reflects that the instruction load information is between the first threshold and the second threshold (or the instruction load information is not less than the first threshold), then the memory control circuit 23 can determine that the numerical relative relationship between the instruction load information and at least one threshold information is the second numerical relative relationship. Then, the memory control circuit 23 can determine the second prefetch mode as the target prefetch mode based on this second numerical relative relationship.

[0068] Figure 4This is a schematic diagram illustrating the determination of the prefetch mode based on the numerical relative relationship between instruction load information and at least one critical information, according to an embodiment of the present invention. Please refer to... Figure 4 Assuming the instruction load information reflects the total amount of data to be read, if (or in response to) the instruction load information is less than the threshold THR(1) (i.e., the first threshold), the memory control circuit 23 can determine the first prefetch mode as the target prefetch mode. Furthermore, if (or in response to) the instruction load information is between the threshold THR(1) and THR(2) (i.e., the second threshold), the memory control circuit 23 can determine the second prefetch mode as the target prefetch mode.

[0069] In one embodiment, the memory control circuit 23 can acquire hardware resource information of the storage device 12. This hardware resource information can reflect the total channel bandwidth of the memory module 122 and the total chip bandwidth of the memory module 122. The total channel bandwidth can reflect (e.g., positively correlated with) the available resource amount of all channels of the current memory module 122. The total chip bandwidth can reflect (e.g., positively correlated with) the available resource amount of all chips of the current memory module 122.

[0070] In one embodiment, the first threshold value can be determined based on the total channel bandwidth of the memory module 122. For example, the memory control circuit 23 can determine the first threshold value based on the total channel bandwidth of the memory module 122. For example, assuming that the current total channel bandwidth of the memory module 122 is 1024 KB of data transmitted per second, the memory control circuit 23 can determine the first threshold value as 1024 KB. In one embodiment, the memory control circuit 23 can monitor the channel usage of the memory module 122 to obtain the total channel bandwidth of the memory module 122 in real time.

[0071] In one embodiment, the second threshold value can be determined based on the total bandwidth of the memory module 122's chip. For example, the memory control circuit 23 can determine the second threshold value based on the total bandwidth of the memory module 122's chip. For example, assuming that the current total bandwidth of the memory module 122's chip is 4096 KB of data transmitted per second, the memory control circuit 23 can determine the second threshold value as 4096 KB. In one embodiment, the memory control circuit 23 can monitor the chip usage status of the memory module 122 to obtain the total bandwidth of the memory module 122's chip in real time. However, both the first and second threshold values ​​can be adjusted according to practical needs, and the present invention does not impose any limitations on them.

[0072] In one embodiment, the memory control circuit 23 can determine the logical address range to which the prefetch data to be read from the memory module 122 via the prefetch function belongs based on the data block size information. Then, the memory control circuit 23 can read data belonging to this logical address range from the memory module 122 as prefetch data according to the determined logical address range.

[0073] In one embodiment, the memory control circuit 23 may obtain (e.g., receive) a read instruction from the host system 11. The memory control circuit 23 may parse this read instruction to obtain the starting logical address corresponding to the data to be read. Then, the memory control circuit 23 may determine a logical address range based on this starting logical address and data block size information.

[0074] In one embodiment, the memory control circuit 23 may obtain the starting logical address corresponding to the pre-fetched data in other ways. For example, the memory control circuit 23 may determine the last logical address of a sequential read performed within a past period. Then, the memory control circuit 23 may determine this last logical address or the next logical address following this last logical address as the starting logical address corresponding to the pre-fetched data.

[0075] In one embodiment, after obtaining the starting logical address, the memory control circuit 23 can extend the data block size information by a predetermined multiple from this starting logical address to obtain a logical address range. For example, this predetermined multiple can be 2 times or other multiples, and the present invention is not limited thereto. For example, assuming the starting logical address is LCA(i) and the predetermined multiple is 2 times, the memory control circuit 23 can define the logical address range as being between LCA(i) and LCA(k). LCA(k) can be equal to or close to LCA(i) + 2 × BS.

[0076] In one embodiment, in the first prefetch mode, after reading prefetch data from memory module 122, memory control circuit 23 may cache a portion of this prefetch data (also referred to as the first portion of data) in a buffer memory (i.e., a first type of buffer) outside memory module 122, and cache another portion of this prefetch data (also referred to as the second portion of data) in a buffer (i.e., a second type of buffer) within memory module 122. For example, the amount of the first portion of data may conform to the amount of data defined by the data block size information (i.e., BS). The sum of the amount of the first portion of data and the amount of the second portion of data will be equal to the total amount of prefetch data.

[0077] Figure 5 This is a schematic diagram illustrating the caching of pre-fetched data in a first pre-fetch mode according to an embodiment of the present invention. Please refer to... Figure 5In the first prefetch mode, after reading the prefetch data 51 from the memory module 122, the memory control circuit 23 can split this prefetch data 51 into two parts: data 511 (i.e., the first part of the data) and 512 (i.e., the second part of the data). The amount of data 511 can conform to the amount of data defined by the data block size information (i.e., BS). For example, assuming that the starting logical address corresponding to the prefetch data 51 is LCA(i), then the logical address range to which data 511 belongs can be between LCA(i) and LCA(j). LCA(j) can be equal to or close to LCA(i) + BS. In addition, the logical address range to which data 512 belongs can be between LCA(j) and LCA(k).

[0078] It should be noted that if the predetermined multiple is not 2, the logical address range to which data 512 belongs can be adjusted accordingly. For example, assuming the predetermined multiple is 3, the logical address range to which data 512 belongs can be adjusted to be between LCA(j) and LCA(s). LCA(s) can be equal to or close to LCA(i) + 3 × BS. Alternatively, assuming the predetermined multiple is 4, the logical address range to which data 512 belongs can be adjusted to be between LCA(j) and LCA(r). LCA(r) can be equal to or close to LCA(i) + 4 × BS, and so on.

[0079] In the first read-ahead mode, after reading data 511 from memory module 122, memory control circuit 23 can cache data 511 in a buffer memory (i.e., a first type of buffer) outside memory module 122. Furthermore, after reading data 512 from memory module 122, memory control circuit 23 can cache data 512 in a buffer memory (i.e., a second type of buffer) inside memory module 122.

[0080] In one embodiment, in the second prefetch mode, after reading the prefetch data from the memory module 122, the memory control circuit 23 can cache all the data in this prefetch data in a buffer (i.e., a second type of buffer) in the memory module 122.

[0081] Figure 6 This is a schematic diagram illustrating the caching of prefetched data in the second prefetch mode according to an embodiment of the present invention. Please refer to... Figure 6 In the second prefetch mode, after reading the prefetch data 61 from the memory module 122, the memory control circuit 23 can directly cache the data 61 in the buffer (i.e., the second type of buffer) inside the memory module 122.

[0082] In one embodiment, Figure 5The caching operation for pre-fetched data shown in the embodiment can be considered as caching the pre-fetched data in a first storage space. The first storage space includes a first type of buffer and a second type of buffer. On the other hand, Figure 6 The caching operation for pre-fetched data shown in the embodiment can be considered as caching the pre-fetched data in a second storage space. The second storage space includes only a second type of buffer.

[0083] In one embodiment, after caching the pre-fetch data in a first or second storage space, the memory control circuit 23 may acquire (e.g., receive or process) a read instruction from the host system 11. This read instruction instructs the reading of at least a portion of the pre-fetch data (also referred to as target data). The memory control circuit 23 may then respond to the read instruction by reading the target data from a buffer memory (i.e., a first-type buffer) outside the memory module 122 or a buffer within the memory module 122 (i.e., a second-type buffer) according to the pre-fetch mode (i.e., the target pre-fetch mode) and the logical address information carried by the read instruction. For example, the logical address information may reflect the logical address to which the data (i.e., the target data) instructed to be read by the read instruction belongs.

[0084] In one embodiment, if the prefetch mode previously used to read the prefetched data (i.e., the target prefetch mode) is the first prefetch mode, then in the first prefetch mode, the memory control circuit 23 can read the target data from at least one of the buffer memory (i.e., the first type of buffer) outside the memory module 122 and the buffer (i.e., the second type of buffer) in the memory module 122, according to the logical address information and the data block size information. Then, the memory control circuit 23 can send this target data back to the host system 11 in response to this read command.

[0085] In one embodiment, in the first prefetch mode, if the logical address information carried by the read instruction is within a sub-range (also called the first sub-range) of the logical address range to which the prefetched data belongs, the memory control circuit 23 can read the target data from the buffer memory (i.e., the first type of buffer) outside the memory module 122. However, if the logical address information is within another sub-range (also called the second sub-range) of the logical address range, the memory control circuit 23 can switch to reading the target data from the buffer (i.e., the second type of buffer) in the memory module 122.

[0086] by Figure 5For example, in the first prefetch mode, the memory control circuit 23 can determine which sub-range of the logical address range (i.e., LCA(i) to LCA(k)) the prefetched data 51 belongs to, the logical address information carried by the read instruction. If the logical address information carried by this read instruction is within LCA(i) to LCA(j) (i.e., the first sub-range), the memory control circuit 23 can read the target data (e.g., data 511) from the buffer memory (i.e., the first type of buffer) outside the memory module 122. However, if the logical address information carried by this read instruction is within LCA(j) to LCA(k) (i.e., the second sub-range), the memory control circuit 23 can read the target data (e.g., data 512) from the buffer (i.e., the second type of buffer) in the memory module 122.

[0087] On the other hand, if the prefetch mode previously used to read the prefetched data (i.e., the target prefetch mode) is the second prefetch mode, then in the second prefetch mode, the memory control circuit 23 can (only) read the target data from the buffer (i.e., the second type of buffer) in the memory module 122. Then, the memory control circuit 23 can send this target data back to the host system 11 in response to this read command.

[0088] by Figure 6 For example, in the second pre-read mode, according to the read instruction, the memory control circuit 23 can directly read the target data (e.g., data 61) from the buffer (i.e., the second type of buffer) in the memory module 122.

[0089] Figure 7 This is a flowchart illustrating a read management method according to an embodiment of the present invention. Please refer to... Figure 7 In step S701, the prefetch function for the memory module is triggered. After the prefetch function is triggered, in step S702, the prefetch mode corresponding to the prefetch function is determined according to the instruction load information, wherein the instruction load information reflects the total amount of data to be read.

[0090] However, Figure 7 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 7 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 7 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0091] In summary, the read management method and storage device proposed in this invention can optimize the read-ahead function by dynamically determining or adjusting the read-ahead mode under different instruction load conditions. For example, under different instruction load conditions, by dynamically calling low-latency external buffers (i.e., buffers outside the memory module) and bandwidth-saving internal buffers (i.e., buffers inside the memory module) to cache read-ahead data, a good balance can be achieved between read-ahead efficiency and bandwidth control in the storage device. This effectively improves the overall data read performance of the storage device.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A reading management method, characterized in that, For use in a storage device, wherein the storage device includes a memory module, and the read management method includes: Trigger the read-ahead function for the memory module; and Based on the instruction load information, a pre-read mode corresponding to the pre-read function is determined, wherein the instruction load information is related to the total amount of data to be read.

2. The read management method according to claim 1 further includes: Obtain instruction quantity information and data block size information, wherein the instruction quantity information reflects the total number of read instructions to be processed, and the data block size information reflects the amount of data read corresponding to a single read instruction; and The instruction load information is determined based on the instruction quantity information and the data block size information.

3. The read management method according to claim 1, wherein the step of determining the pre-read mode corresponding to the pre-read function based on the instruction load information includes: The prefetch mode is determined from multiple candidate prefetch modes based on the instruction load information.

4. The read management method according to claim 3, wherein the plurality of candidate pre-read modes includes a first pre-read mode and a second pre-read mode. In the first pre-read mode, the first pre-read data read from the memory module through the pre-read function is cached in the first storage space, awaiting reading by the host system. In the second prefetch mode, the second prefetch data read from the memory module through the prefetch function is cached in the second storage space, waiting to be read by the host system.

5. The read management method according to claim 4, wherein the first storage space includes a buffer memory outside the memory module, and the second storage space does not include the buffer memory.

6. The read management method according to claim 5, wherein both the first storage space and the second storage space include a buffer in the memory module.

7. The read management method according to claim 3, wherein the step of determining the pre-read mode from the plurality of candidate pre-read modes based on the instruction load information includes: The prefetch pattern is determined from the plurality of candidate prefetch patterns based on the numerical relative relationship between the instruction load information and at least one critical information.

8. The read management method according to claim 7, wherein the numerical relative relationship includes a first numerical relative relationship and a second numerical relative relationship; the step of determining the pre-read mode from the plurality of candidate pre-read modes according to the numerical relative relationship between the instruction load information and the at least one critical information includes: Based on the first numerical relative relationship, the first pre-read mode among the plurality of candidate pre-read modes is determined as the pre-read mode; as well as Based on the second numerical relative relationship, the second pre-read mode among the plurality of candidate pre-read modes is determined as the pre-read mode.

9. The read management method according to claim 8, wherein the at least one critical information includes a first critical value and a second critical value, the second critical value being greater than the first critical value, and the step of determining the pre-read mode from the plurality of candidate pre-read modes based on the numerical relative relationship between the instruction load information and the at least one critical information further includes: If the instruction load information is less than the first threshold value, then the numerical relative relationship between the instruction load information and the at least one threshold value is determined to be the first numerical relative relationship. as well as If the instruction load information is between the first threshold and the second threshold, then the numerical relative relationship between the instruction load information and the at least one threshold information is determined to be the second numerical relative relationship.

10. The read management method according to claim 9, further comprising: The first threshold value is determined based on the total channel bandwidth of the memory module.

11. The read management method according to claim 9, further comprising: The second threshold value is determined based on the total chip bandwidth of the memory module.

12. The read management method according to claim 1, further comprising: Based on the data block size information, determine the logical address range to which the prefetched data read from the memory module through the prefetch function belongs.

13. The read management method according to claim 12, wherein the step of determining the logical address range to which the pre-read data read from the memory module through the pre-read function belongs, based on the data block size information, includes: Parse the read instruction to obtain the starting logical address corresponding to the pre-read data; as well as The logical address range is determined based on the starting logical address and the data block size information.

14. The read management method according to claim 13, wherein the step of determining the logical address range based on the starting logical address and the data block size information includes: Starting from the initial logical address, the data block size information is extended by a predetermined multiple to obtain the logical address range.

15. The read management method according to claim 12, further comprising: In the first prefetch mode, the first part of the prefetch data is cached in a buffer memory outside the memory module, and the second part of the prefetch data is cached in a buffer within the memory module.

16. The read management method according to claim 15, wherein the data volume of the first part of the data conforms to the data volume defined by the data block size information, and the sum of the data volume of the first part of the data and the data volume of the second part of the data is equal to the total data volume of the pre-read data.

17. The read management method according to claim 1, further comprising, after reading the pre-read data from the memory module through the pre-read function: Receive read commands from the host system; as well as Based on the pre-read mode and the logical address information carried by the read instruction, the target data in the pre-read data is read from the buffer memory outside the memory module or the buffer in the memory module in response to the read instruction.

18. The read management method according to claim 17, wherein the step of reading the target data from the pre-read data from the buffer memory outside the memory module or the buffer in the memory module according to the pre-read mode and the logical address information carried by the read instruction includes: In the first read-ahead mode, the target data is read from at least one of the buffer memory and the buffer according to the logical address information and the data block size information; as well as In the second read-ahead mode, the target data is read only from the buffer.

19. The read management method according to claim 18, wherein in the first pre-read mode, the step of reading the target data from at least one of the buffer memory and the buffer according to the logical address information and the data block size information includes: If the logical address information is within the first sub-range of the logical address range to which the pre-read data belongs, the target data is read from the buffer memory; as well as If the logical address information is within the second sub-range of the logical address range, the target data is read from the buffer.

20. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the read management method according to any one of claims 1 to 19.

Images