A method, device and storage medium for hardening NAND Flash data

Abstract

This application provides a method, device, and storage medium for hardening Nand Flash data. The method includes: reading target encoded data from Nand Flash; performing LDPC row decoding on each group of page data to obtain error row location information; performing RS column decoding on the page data and column check pages after LDPC row decoding based on the error row location information to obtain column decoding results; correcting the initial symbol confidence table according to the column decoding results to obtain a target symbol confidence table; and performing LDPC decoding on the target page data for which row decoding failed to succeed to obtain the original data. Through a collaborative decoding process of marking error rows with LDPC row decoding, correcting confidence with RS column decoding, and performing deep error correction with LDPC secondary decoding, high-error-risk areas can be accurately located, the error correction efficiency of RS decoding can be improved, and the performance of LDPC decoding can be enhanced by the corrected confidence table. This effectively improves the LDPC error level bottleneck, reduces the number of uncorrectable pages, and thus improves the success rate and reliability of original data recovery.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a method, device and storage medium for hardening Nand Flash data. Background Technology

[0002] As the mainstream storage medium, NAND Flash is prone to data errors during use due to cell wear and charge leakage, requiring encoding reinforcement and corresponding decoding to ensure reliable data recovery. Furthermore, with the miniaturization of NAND Flash manufacturing processes and the increase in storage density, its bit error rate has risen significantly, making the reliability requirements for error control coding (ECC) and decoding schemes increasingly stringent.

[0003] Currently, different types of Nand Flash memory employ different mainstream ECC schemes. Among them, LDPC encoding is widely used in high-performance storage scenarios due to its significantly superior error correction capabilities compared to traditional encoding. However, LDPC encoding has obvious limitations. When the bit error rate exceeds its own error correction threshold, an error correction bottleneck occurs, resulting in a large number of data pages failing to be effectively corrected. Furthermore, the insufficient collaborative error correction and inaccurate error localization of related decoding schemes are becoming increasingly prominent, making it difficult to meet the requirements for original data recovery efficiency and reliability. Therefore, it is necessary to provide a data hardening method to improve data recovery efficiency and reliability. Summary of the Invention

[0004] The main purpose of this application is to provide a method, device and storage medium for hardening Nand Flash data, which can at least solve the problems of low data recovery efficiency and reliability in related technologies.

[0005] To achieve the above objectives, the first aspect of this application provides a method for hardening Nand Flash data. The method includes: reading target encoded data corresponding to a target address from a preset Nand Flash; wherein the target encoded data includes multiple sets of page data and column check pages, and the page data includes original data and row check bits; performing LDPC row decoding on each set of page data to obtain error row location information; based on the error row location information, performing RS column decoding on the LDPC-decoded page data and the column check pages to obtain a column decoding result; correcting an initial symbol confidence table according to the column decoding result to obtain a target symbol confidence table; and performing LDPC decoding on the target page data for which row decoding failed to succeed to obtain the original data.

[0006] The second aspect of this application provides a solid-state storage device, including: Nand Flash and a storage controller, wherein the storage controller is used to execute a computer program, and when the storage controller executes the computer program, it implements the steps in the Nand Flash data hardening method provided in the first aspect of this application.

[0007] The third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the steps of the Nand Flash data hardening method provided in the first aspect of this application.

[0008] As can be seen from the above, the Nand Flash data hardening method, device and storage medium provided in this application can accurately locate high error risk areas and improve the error correction efficiency of RS decoding by using the collaborative decoding process of LDPC row decoding to mark error rows, RS column decoding to correct confidence, and LDPC secondary decoding for deep error correction. Furthermore, by using the corrected confidence table to enhance the performance of LDPC secondary decoding, the bottleneck of LDPC error level can be effectively improved, the number of uncorrectable pages can be reduced, and the success rate and reliability of original data recovery can be significantly improved, which is suitable for the high error rate scenario requirements of high-density Nand Flash. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the basic process of a Nand Flash data hardening method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a data block stored in a Nand Flash according to an embodiment of this application; Figure 3 A detailed flowchart illustrating a Nand Flash data hardening method provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a solid-state storage device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of another solid-state storage device provided in an embodiment of this application. Detailed Implementation

[0011] To make the inventive objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0012] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0013] To address the issues of low data recovery efficiency and reliability in related technologies, one embodiment of this application provides a Nand Flash data hardening method, such as... Figure 1 This is a basic flowchart illustrating the NAND Flash data hardening method provided in this embodiment. The NAND Flash data hardening method includes the following steps: Step 101: Read the target encoding data corresponding to the target address from the preset Nand Flash.

[0014] In this embodiment, when stored data needs to be accessed, the corresponding business module can issue a read command. This command can carry parameters such as the target address and data length. Upon receiving the command, the target encoded data corresponding to the target address can be read from the Nand Flash, and the read data can be written to a preset buffer. The target encoded data stored in the preset Nand Flash includes multiple sets of page data and multiple sets of column check pages. Each set of page data includes the original data and row check bits, for example... Figure 2 The diagram shows the encoded data structure.

[0015] In some embodiments of this example, the Nand Flash data hardening method further includes: paging the original data and segmenting each group of original page data to obtain multiple data blocks; using each data block as an LDPC information bit and encoding each data block using LDPC system code to generate corresponding row check bits; concatenating each group of original page data with the corresponding row check bits to obtain a page data set; performing RS column encoding and integration on the page data set to obtain encoded data, and writing it into the Nand Flash.

[0016] In this embodiment, each piece of raw data to be written to the Nand Flash can be processed in blocks. For example... Figure 2 The data structure diagram shows that a raw data block can consist of M+16 pages (the extra 16 pages are column check sheets forming a column check area). Each group of pages can be divided into n data blocks. Error correction encoding is performed on the raw data blocks in both row and column directions. In the row direction (within each page), LDPC encoding is used for reinforcement, generating n LDPC codewords per page. In the column direction (between multiple pages within a block), RS encoding is used for reinforcement. During RS encoding, the LDPC check bits are also encoded.

[0017] Specifically, the original data block to be encoded is divided into 176 groups of page data. For each of the 176 groups of page data, LDPC encoding is performed according to the following process to generate complete page data containing the data area and the row check area: First, the data of a single 16KB data area is divided into 8 segments (n=8), with each segment having a length of 16KB / 8=2KB. Using a preset LDPC generation matrix, the information bits of each 2KB segment are encoded to generate check bits, resulting in 8 LDPC codewords. The information bits (totaling 16KB, i.e., the original data area data) and check bits (row check area data) of the 8 LDPC codewords are concatenated to form a single page of data. Combining all groups of single page data, a page data set is obtained. Then, the page data set is encoded using RS column encoding. Through integration, the encoded data is obtained and written to NandFlash.

[0018] Furthermore, in some embodiments of this example, RS column encoding and integration are performed on the page data set to obtain encoded data, including: extracting M bytes from each column of the page data set as code elements to obtain column direction information bits; where M is the total number of rows in the page data set; encoding the column direction information bits corresponding to each column using RS system code to generate corresponding RS check bits; integrating the RS check bits corresponding to all columns to obtain a column check page, and concatenating it with the page data set to obtain encoded data.

[0019] In this embodiment, code elements are extracted from the 176 sets of LDPC-encoded page data in the column direction. Each column includes 176 bytes, and each byte serves as a code element in the Galois field GF(256). Therefore, each column forms a 176-byte column-directed information bit, which contains bytes corresponding to the LDPC information bit and the parity bit. The RS(192, 176, t=16) system code (GF(256) field) can be used to encode the 176-byte column-directed information bit of each column to obtain the RS parity bit. The RS parity bits corresponding to all columns are integrated in units of pages to form a 16-page column parity page set (corresponding to Figure 2The column parity area (in the image) is used to concatenate the set of column parity pages with the set of page data obtained after LDPC encoding to obtain a complete encoded data block. The total number of pages in this data block is 176 + 16 = 192 pages, which matches the size of the entire Flash memory block. Therefore, the two-dimensional parity structure in this embodiment can more effectively combat page failures compared to traditional methods of lengthening LDPC or reducing the bit rate. By including the LDPC parity bits in the RS protection range, the error correction blind spot caused by parity bit failure can be eliminated.

[0020] In other embodiments of this example, the Nand Flash data hardening method further includes: interleaving the encoded data; and writing the interleaved encoded data into the Nand Flash.

[0021] In this embodiment, the encoded block of data can also be interleaved, such as row-column interleaving or pseudo-random interleaving, to achieve data rearrangement, thereby avoiding the concentrated occurrence of sudden errors and improving the ability to resist sudden errors. Finally, the interleaved block of data is written to Flash.

[0022] Therefore, this embodiment employs a two-dimensional concatenated encoding architecture of LDPC+RS. Row-oriented LDPC encoding enables fine-grained error correction of local errors within a page, while column-oriented RS (192, 176, t=16) encoding covers both LDPC information bits and parity bits, enabling deep error correction of global errors across pages within a block. This two-dimensional collaboration significantly improves error correction efficiency. Furthermore, the interleaving range covers 192 pages of complete encoded data, dispersing continuous errors and avoiding the risk of local failures caused by centralized storage of parity data, further enhancing storage reliability.

[0023] Step 102: Perform LDPC row decoding on each group of page data to obtain the error row location information.

[0024] In this embodiment, after the target encoded data is obtained, LDPC hard decision decoding can be performed page by page to determine the location information of the erroneous row and the preliminary decoding result, providing input for the subsequent RS column decoding to generate the erasure polynomial.

[0025] In some implementations of this embodiment, LDPC line decoding is performed on each group of page data, including: LDPC line decoding is performed on each group of page data after deinterleaving.

[0026] In this embodiment, when the acquired encoded data is interleaved during the encoding process, the acquired data can be deinterleaved to restore the page-level data organization form during encoding, so that the subsequent LDPC row decoding and RS column decoding can accurately match the original encoding dimension.

[0027] In some implementations of this embodiment, LDPC row decoding is performed on each group of page data to obtain error row location information, including: generating LDPC codewords based on the LDPC information bits and row check bits corresponding to the original data; decoding each LDPC codeword using a hard-decision decoding algorithm and calculating the syndrome of each LDPC codeword; counting the total number of non-zero elements in all syndromes of each group of page data; if the total number is zero, outputting successfully decoded data; if the total number is greater than zero, determining the error row location and outputting undecoded data and error row location information.

[0028] In this embodiment, during row decoding, LDPC codewords are generated based on the information bits and check bits of each group of page data. Then, an LDPC hard-decision decoding algorithm with an adapted codeword length is used to decode each LDPC codeword separately. During decoding, the 0 / 1 hard-decision result is used as input, and the syndrome of each codeword is calculated through iterative update of information transmission. The syndrome of each decoded codeword is checked, and the total number of non-zero elements in the syndrome (denoted as UNSAT, i.e., the unsatisfied check number) is counted. The total UNSAT value of the i-th page is the sum of the UNSAT values ​​corresponding to all codewords on that page. If UNSAT... i =0 indicates that the hard-decision decoding of this page was successful and there are no residual errors in the data; if UNSAT = 0, it means that the hard-decision decoding of this page was successful and there are no residual errors in the data; i A value greater than 0 indicates that the page contains uncorrected errors and requires further processing. The total UNSAT value of all 176 pages can be stored in the UNSAT statistics table in the cache to record the residual error status of each page, providing a basis for subsequent error line marking.

[0029] Furthermore, in some implementations of this embodiment, determining the location of the erroneous line includes: sorting the total number of all page data (UNSAT) in descending order to obtain a count sequence; obtaining the first N target total numbers in the count sequence, and taking the row number of the corresponding page data as the location of the erroneous line; where N is a positive integer less than or equal to the number of redundant code elements of the RS code.

[0030] In this embodiment, the total UNSAT values ​​of the 176 pages are sorted in descending order to obtain a sorted UNSAT sequence. The pages corresponding to the first N sorted UNSAT values ​​are taken as the PAGE_FAIL row (N is a configurable parameter, for example, N≤16, matching the 16 redundant code elements of RS(192,176), ensuring that RS decoding can cover erasure errors). The page numbers of the PAGE_FAIL row are stored in the error row record table, and the erasure positions of these pages in the subsequent RS column decoding are marked, providing input for generating the erasure polynomial.

[0031] Step 103: Based on the error row location information, perform RS column decoding on the page data and column check page after LDPC row decoding to obtain the column decoding result.

[0032] In this embodiment, after row decoding of the acquired encoded data, the RS(192, 176, t=16) decoder is called to perform mixed decoding on the data block in the column direction, while handling erasure errors and random errors to correct the confidence table.

[0033] In some implementations of this embodiment, based on the error row location information, RS column decoding is performed on the page data and column check page after LDPC row decoding to obtain column decoding results. This includes: extracting data by column from the page data and column check page after LDPC row decoding to obtain multiple columns of RS codewords; marking the byte corresponding to the error row location information as an erasure item in each column of RS codewords; generating an erasure polynomial based on the location information of all erasure items; inputting the RS codewords and erasure polynomials into the RS hybrid decoding algorithm model, while correcting random errors in the error row and the remaining rows; if the syndrome of the decoded RS codeword is zero, then the data of successful column decoding is obtained.

[0034] In this embodiment, the data block after LDPC decoding is expanded into a two-dimensional matrix (containing 192 rows = 176 data pages + 16 column check areas). Data is extracted by column, with each column containing 192 bytes (176 data page bytes + 16 column check area bytes), which can be denoted as the RS codeword of the j-th column. Based on the PAGE_FAIL page number in the error row record table, the bytes of the corresponding row in each column of RS codeword are marked as erased, generating an erase position set. An erase polynomial is generated based on the erase position and used as an input for RS hybrid decoding. An RS hybrid decoding algorithm model in the GF(256) field is adopted, using RS codeword and erase polynomial as inputs, to correct two types of errors simultaneously: marked erase errors and random errors in other rows. If the syndrome of the decoded RS codeword is 0, it means that the column decoding is successful and the error has been completely corrected; if the syndrome is not 0, it means that the error in the column exceeds the RS error correction capability and the decoding fails. The decoding results (success / failure) of each column can be stored in the RS decoding result table, which can be used to correct the symbol confidence table (LLR table).

[0035] Step 104: Correct the initial symbol confidence table based on the column decoding results to obtain the target symbol confidence table.

[0036] In this embodiment, the initial value in the initial symbol confidence table can be set to 0 (no confidence bias). The initial symbol confidence table is then modified based on the column decoding results. For columns that are successfully decoded in the RS decoding result table, the LLR values ​​corresponding to the symbols in all rows (including page data and column check areas) of that column are set to high confidence (e.g., LLR=10). Since successful RS decoding ensures that the symbols in that column are error-free, assigning high confidence can improve the convergence speed of subsequent soft-decision decoding. For columns that fail to decode, the LLR values ​​corresponding to the symbols in all rows of that column are set to low confidence (e.g., LLR=-10). Because the error in that column exceeds the RS error correction capability, the probability of symbol errors is extremely high; assigning low confidence can prevent error information from interfering with subsequent soft-decision iterations. Additionally, for the column corresponding to the PAGE_FAIL row, if the RS decoding of that column is successful, an additional LLR value (e.g., LLR=12) is added on top of the high confidence level to strengthen the probability of correctness for erroneous row symbols; if the decoding of that column fails, the LLR value is further reduced on top of the low confidence level (e.g., LLR=-12) to highlight the error risk. The corrected LLR table is stored in a cache for subsequent soft-decision decoding.

[0037] Step 105: Based on the target symbol confidence table, perform LDPC decoding on the page data that failed to be decoded in row decoding to obtain the original data.

[0038] In this embodiment, for a single LDPC decoding failure, i.e., UNSAT i Pages with values ​​greater than 0 can further undergo LDPC soft-decision decoding based on the modified LLR table to achieve deep error correction and prevent the entire data block from failing due to sudden errors exceeding the LDPC error correction capacity. Highly reliable raw data can be obtained through secondary LDPC soft-decision decoding.

[0039] In some implementations of this embodiment, based on the target symbol confidence table, LDPC decoding is performed on the target page data whose row decoding failed to obtain the original data. This includes: obtaining the confidence value corresponding to the target page data whose row decoding failed to obtain the confidence value from the target symbol confidence table; integrating the confidence values ​​according to the byte order within the target page data to obtain a confidence sequence; decoding the LDPC codewords of the target page data based on the confidence sequence and the LDPC soft-decision decoding algorithm, and calculating the syndrome of all LDPC codewords; counting the total number of non-zero elements in all syndromes of each group of page data; and extracting information bits from all page data with a total count of zero to obtain the original data.

[0040] In this embodiment, for the i-th page (UNSAT) where line decoding failed... i>0), extract the corresponding LLR value for the page from the corrected LLR table, and arrange it according to the byte order within the page to obtain the soft-decision input sequence. An LDPC soft-decision decoding algorithm with adapted code length is used to decode multiple LDPC codewords for the page. During decoding, probability information is transmitted based on the LLR value, and the codeword decision result is optimized through multiple rounds of iteration. After decoding, the syndrome of all codewords is recalculated, and the total UNSAT value for each page is calculated: if UNSAT >0, the total UNSAT value for each page is calculated. i =0 indicates that the secondary decoding of this page was successful and the data has been restored to normal; if UNSAT... i A UNSAT value >0 indicates that the page error remains uncorrected, and decoding has failed. Therefore, if the final UNSAT value of all 176 pages is 0, the entire data block has been successfully decoded. The first 16KB of information bits (raw data area) are extracted from the LDPC decoding result of each page, organized into complete raw data blocks in page order, and output to the upper-layer business module. If at least one page has a final UNSAT value >0, decoding has failed, triggering a tiered exception handling mechanism. This includes reporting a UECC (Uncorrectable Error Complaint) alarm; initiating the underlying RAID / replica recovery mechanism to read backup data from other blocks in redundant storage to replace the erroneous block data; and recording the address and UNSAT statistics of the erroneous block to provide a basis for bad block management of the Flash storage medium.

[0041] Based on the technical solution of the above embodiments of this application, target encoded data corresponding to the target address is read from a preset Nand Flash. The target encoded data includes multiple sets of page data and column check pages, with each page data including original data and row check bits. LDPC row decoding is performed on each set of page data to obtain error row location information. Based on the error row location information, RS column decoding is performed on the LDPC-decoded page data and column check pages to obtain column decoding results. The initial symbol confidence table is corrected according to the column decoding results to obtain the target symbol confidence table. Based on the target symbol confidence table, LDPC decoding is performed on the target page data for which row decoding failed to obtain the original data. This solution employs a collaborative decoding process involving LDPC row decoding to mark erroneous rows, RS column decoding to correct confidence levels, and LDPC secondary decoding for deep error correction. This enables precise location of high-risk error regions and improves the error correction efficiency of RS decoding. Furthermore, by leveraging the corrected confidence table to enhance the performance of LDPC secondary decoding, it effectively mitigates the LDPC error level bottleneck, reduces the number of uncorrectable pages, and ultimately significantly improves the success rate and reliability of original data recovery, making it suitable for high-error-rate scenarios in high-density NandFlash.

[0042] Figure 3 The method described in this application is a refined NAND Flash data hardening method provided in an embodiment of this application. This NAND Flash data hardening method includes: Step 301: Paginate the original data and segment each group of original page data to obtain multiple data blocks; Step 302: Use each data block as an LDPC information bit, and encode each data block using the LDPC system code to generate the corresponding row check bit; Step 303: Concatenate each group of LDPC information bits with the corresponding row check bits to obtain the page data set; Step 304: Encode and integrate the page data set using RS columns to obtain encoded data, interleave the encoded data, and write it into Nand Flash. Step 305: Read the target encoding data corresponding to the target address from the Nand Flash; Step 306: Perform LDPC row decoding on each group of page data after deinterleaving to obtain the error row location information; Step 307: Based on the error row location information, perform RS column decoding on the page data and column check page after LDPC row decoding to obtain the column decoding result; Step 308: Correct the initial symbol confidence table based on the column decoding results to obtain the target symbol confidence table; Step 309: Based on the target symbol confidence table, perform LDPC decoding on the target page data that failed to be decoded in row decoding to obtain the original data.

[0043] It should be understood that the sequence number of each step in this embodiment does not imply the order in which the steps are executed. The execution order of each step should be determined by its function and internal logic, and should not constitute a unique limitation on the implementation process of this application embodiment.

[0044] In this embodiment, the entire block of data to be written is paginated. Each row (page) of n data segments is encoded using an LDPC generator matrix, generating system codes. Excess check data is placed at the end of each row. After all rows are encoded, one byte of data is taken from each page column-wise as a Galois field GF(256) code, resulting in M-byte information bits. RS encoding is performed on each column's information bits to generate check codes. All check codes corresponding to each column are placed in a new row, ultimately yielding the encoded data block corresponding to the entire Flash memory space. The encoded data block is then interleaved using methods such as row-column interleaving or pseudo-random interleaving to achieve data rearrangement, thus preventing sudden, concentrated errors. The interleaved data block is then written to the Flash memory.

[0045] When reading data from Nand Flash, the entire block of data is placed in a buffer and deinterleaved, rearranging the data and breaking down concentrated data errors caused by page corruption. Then, row decoding is performed, reading the data area and row parity area of ​​each page, combining them into LDPC codewords for hard-decision decoding, and counting the number of non-zero values ​​in the final iterative syntactic expression (UNSAT, the unsatisfied parity number). This value can approximate the number of error bits; UNSAT is 0 when decoding is successful. After hard-decision decoding of all rows of the data block, the total UNSAT value of each row is obtained. All rows' UNSAT values ​​are sorted by size, and the row containing the largest N (configurable parameter, N less than or equal to the number of redundant code elements in the RS code) UNSAT values ​​is marked as the PAGE_FAIL row. Then, column decoding is performed, using the row marked with PAGE_FAIL as the erase position, generating an erase polynomial, and the RS decoder executes a hybrid decoding mode, simultaneously correcting erase errors and random errors. The RS decoder will correct errors as much as possible, and then perform different operations based on the decoding results of each column. For each column, if RS decoding is successful, the symbolic representation of the RS code in the corresponding row is corrected, and its corresponding LLR can be set to high confidence; if RS decoding fails, it is considered that the symbolic representation of the RS code in the corresponding row has a high probability of error, and its LLR can be set to low confidence. After RS ​​decoding of all columns is completed, the corrected confidence table is obtained. For all rows with non-zero UNSAT values, the corrected confidence table is used as the initial probability to execute the soft-decision LDPC decoding algorithm. If decoding is successful, the data is successfully recovered; otherwise, it is reported to UECC, triggering RAID / replica recovery.

[0046] Therefore, this embodiment achieves accurate location of high error risk areas and improves the error correction efficiency of RS decoding through a collaborative decoding process of LDPC row decoding to mark erroneous rows, RS column decoding to correct confidence, and LDPC secondary decoding for deep error correction. Furthermore, by using the corrected confidence table to enhance the performance of LDPC secondary decoding, it effectively improves the LDPC error level bottleneck, reduces the number of uncorrectable pages, and ultimately significantly improves the success rate and reliability of original data recovery, thus adapting to the high error rate scenarios of high-density NAND Flash.

[0047] Figure 4 A solid-state storage device is provided as an embodiment of this application. This solid-state storage device can be used to implement the Nand Flash data hardening method in the foregoing embodiments, mainly including: Nand Flash 401 and storage controller 402 are communicatively connected. Storage controller 402 may include a storage medium and a processor. The storage medium stores a computer program, and when the processor executes the computer program, it implements the methods described in the foregoing embodiments. The number of storage controllers may be one or more.

[0048] For the above embodiments, the storage controller of this solution can be implemented using the following key modules, for example... Figure 5 As shown, the two-dimensional encoding unit, as an encoding component, integrates an LDPC row encoding module and an RS column encoding module to complete intra-page row-oriented LDPC encoding and intra-block column-oriented RS encoding, respectively, realizing two-dimensional hardened encoding of data; the two-dimensional decoding unit, as a decoding component, integrates an LDPC hard / soft decision decoding module and an RS hybrid decoding module to complete LDPC hard decision decoding, RS hybrid decoding, and LDPC soft decision deep error correction in sequence; the interleaving / deinterleaving unit, as a data processing component, realizes the interleaving processing (when writing to storage) and deinterleaving processing (when reading from storage) of the entire block of encoded data, ensuring the data error dispersion characteristics; the confidence fusion unit, as a decoding auxiliary component, obtains the decoding status through error statistics, combines hardware lookup table method to realize the addition and subtraction offset correction of symbol confidence LLR value, and outputs the optimized confidence table; the shared on-chip cache array, as a storage support component, provides data block cache space for the entire encoding and decoding process, supporting temporary data storage and interaction between modules; the data interaction interface module, as a communication component with Nand Flash, builds Nand... The data transmission channel between Flash and shared on-chip cache enables interactive reading and writing of stored data; the master control state machine, as the scheduling core, uniformly schedules and manages the entire process of data reading, writing, encoding, decoding, and secondary decoding, ensuring that all modules work together in an orderly manner.

[0049] Furthermore, this application embodiment also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the Nand Flash data hardening method described in the foregoing embodiments. Further, the computer-readable storage medium can be any medium capable of storing program code, such as a USB flash drive, external hard drive, read-only memory (ROM), RAM, magnetic disk, or optical disk.

[0050] The technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0051] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0052] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0053] The above is a description of the Nand Flash data hardening method, device and storage medium provided in this application. For those skilled in the art, based on the ideas of the embodiments of this application, there will be changes in the specific implementation and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for hardening NAND Flash data, characterized in that, include: Read the target encoded data corresponding to the target address from the preset Nand Flash; wherein, the target encoded data includes multiple sets of page data and column check pages, and the page data includes the original data and row check bits; Perform LDPC line decoding on each group of page data to obtain the error line location information; Based on the error row location information, RS column decoding is performed on the page data after LDPC row decoding and the column check page to obtain the column decoding result; The initial symbol confidence table is corrected based on the decoding results to obtain the target symbol confidence table; Based on the target symbol confidence table, LDPC decoding is performed on the target page data that failed to be decoded in row decoding to obtain the original data.

2. The Nand Flash data hardening method according to claim 1, characterized in that, Also includes: The original data is paginated, and each group of original page data is segmented to obtain multiple data blocks; Each data block is used as an LDPC information bit, and each data block is encoded using LDPC system code to generate the corresponding row check bit. Each set of LDPC information bits is concatenated with the corresponding row check bits to obtain a page data set; The page data set is encoded and integrated using RS columns to obtain encoded data, which is then written to Nand Flash.

3. The Nand Flash data hardening method according to claim 2, characterized in that, The process of encoding and integrating the page data set using RS columns to obtain encoded data includes: M bytes are extracted from each column of the page data set as code elements to obtain column-oriented information bits; where M is the total number of rows in the page data set; The RS system code is used to encode the column-direction information bits corresponding to each column to generate the corresponding RS check bits; The RS check bits corresponding to all columns are integrated to obtain a column check page, which is then concatenated with the page data set to obtain the encoded data.

4. The Nand Flash data hardening method according to claim 2, characterized in that, Also includes: The encoded data is interleaved; The interleaved encoded data is written into Nand Flash; The step of performing LDPC row decoding on each group of page data includes: Each set of page data after deinterleaving is then subjected to LDPC row decoding.

5. The Nand Flash data hardening method according to claim 1, characterized in that, The step of performing LDPC line decoding on each group of page data to obtain error line location information includes: Based on the LDPC information bits corresponding to the original data and the row check bits, generate LDPC codewords; Each LDPC codeword is decoded using a hard-decision decoding algorithm, and the first syndrome of each LDPC codeword is calculated. Count the total number of non-zero elements in all the associated expressions in each group of page data; If the total number is zero, output the data indicating successful decoding; If the total number is greater than zero, the location of the erroneous line is determined, and the data that failed to be decoded and the location information of the erroneous line are output.

6. The Nand Flash data hardening method according to claim 5, characterized in that, Determining the location of the erroneous line includes: Sort the total number of all page data in descending order to obtain a sequence of numbers; Obtain the total number of the first N targets in the count sequence, and use the corresponding row number of the page data as the error row position; where N is a positive integer less than or equal to the number of redundant code elements of the RS code.

7. The Nand Flash data hardening method according to claim 1, characterized in that, Based on the error row location information, RS column decoding is performed on the page data and the column check page after LDPC row decoding to obtain the column decoding result, including: The page data and the column check page after LDPC row decoding are extracted by column to obtain multiple columns of RS codewords; In each column of the RS codeword, the byte corresponding to the error row position information is marked as an erased item; Generate an erasure polynomial based on the position information of all the erased items; The RS codeword and the erasure polynomial are input into the RS hybrid decoding algorithm model to correct the random errors in the erroneous rows and the remaining rows. If the syndrome of the decoded RS codeword is zero, then the data is successfully decoded.

8. The Nand Flash data hardening method according to claim 1, characterized in that, The step of performing LDPC decoding on the target page data that failed row decoding based on the target symbol confidence table to obtain the original data includes: Obtain the confidence value corresponding to the target page data whose row decoding failed from the target symbol confidence table; The confidence values ​​are integrated by byte order within the target page data to obtain a confidence sequence; Based on the confidence sequence and the LDPC soft-decision decoding algorithm, the LDPC codewords of the target page data are decoded respectively, and the syndrome of all the LDPC codewords is calculated. Count the total number of non-zero elements in all the interpolations of each set of page data; Extract the information bits from all pages of data with a total count of zero to obtain the original data.

9. A solid-state storage device, characterized in that, It includes a Nand Flash and a storage controller, the storage controller being used to execute a computer program, and when the storage controller executes the computer program, it implements the steps in the Nand Flash data hardening method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps in the Nand Flash data hardening method as described in any one of claims 1 to 8.

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