A timing-driven global placement method based on two-layer delay model

Abstract

This invention belongs to the field of VLSI physical design automation technology, specifically providing a timing-driven global placement method based on a two-layer delay model to improve the timing performance of global placement. This invention constructs a new timing delay model based on the critical path and introduces it as a timing cost into the gradient descent optimization framework. The delay model is divided into two layers: a pin pair layer and a path layer. In the pin pair layer, a drive strength factor is introduced to more accurately characterize the RC delay characteristics of the pin pair. In the path layer, adaptive weights are assigned to different paths based on timing margin differences—paths with tight timing margins receive larger weights, while paths with ample margins receive smaller weights. This effectively improves the total negative timing margin (TNS) and worst-case negative timing margin (WNS) of the circuit while controlling line length growth.

Description

Technical Field

[0001] This invention belongs to the field of automated physical design technology for very large-scale integrated circuits (VLSI), specifically providing a timing-driven global placement method based on a two-layer delay model. Background Technology

[0002] In VLSI physical design, global placement is a core step connecting circuit logic description and physical implementation, directly affecting the line length distribution, congestion level, and signal propagation delay of the chip's physical circuitry. Timing-driven global placement refers to explicitly introducing timing constraints during placement optimization. Through static timing analysis, critical paths affecting timing in the circuit are identified in real time, and timing information is mapped to constraints or weights recognizable by the placement engine, thereby guiding logic cells on the critical paths to move closer together in physical space. As semiconductor processes advance to nanometer-scale nodes, adjusting signal transmission paths in the early stages through timing-driven global placement has become a crucial means to ensure timing convergence and performance compliance of modern high-performance chips.

[0003] Currently, based on the way timing information is processed, timing-driven global placement methods are mainly divided into network-based methods and path-based methods. Network-based methods adjust network weights or constraints through timing analysis, thereby guiding the placeholder to optimize timing violation networks. This method has low computational overhead and is easy to implement, but it is limited because it does not directly optimize the timing objective and does not fully utilize timing information. Path-based methods, by directly modeling the critical path in the timing graph, can provide a more accurate timing view and are an important research direction for high-performance placeholders. However, existing path-based timing-driven global placement methods still need improvement in timing performance metrics: on the one hand, by simplifying logic units to ideal nodes and ignoring the differences in drive resistance between different units, the pin-to-pin delay model cannot accurately reflect RC delay characteristics; on the other hand, timing weighting is based on pin pairs rather than the entire path, thus ignoring the differences in timing importance of different paths. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of the prior art by providing a timing-driven global layout method based on a two-layer delay model, thereby improving the timing performance of global layout.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A timing-driven global layout method based on a two-layer delay model, characterized by the following steps:

[0007] A1. Gradient Descent Optimization Layout:

[0008] A1-1. Construct the objective function: Let the vector coordinates of the center of the layout unit be... , , ,in, and The first The x and y coordinates of each layout unit, , Define the number of layout cells; define the line length based on the layout cell coordinates. ,density and timing Three cost functions; , and The objective function is obtained by weighted summation of the three functions. :

[0009] ,

[0010] in, and These are the weighting coefficients for density and time series terms, respectively; This is a binary time-series enable variable, with an initial value of 0;

[0011] A1-2. Set the iteration counter to an initial value of 0. ;

[0012] A1-3. Single-step gradient descent: Minimizing the objective function using gradient descent. Currently, a single-step update is being performed, and the iteration counter is being updated. This yields the updated vector coordinates of the layout units;

[0013] A2. Determine whether to perform a time series evaluation: Let... and These are the preset number of preheating steps and the timing evaluation interval, respectively. Exceeding the number of preheating steps And the time-series evaluation interval If divisible, then set a binary timing enable variable. If the result is 1, proceed to step A3; otherwise, proceed to step A1-3.

[0014] A3. Critical Path Extraction: Use static timing analysis tools to perform timing analysis, identify all path endpoint pins with timing margin slack < 0, and for each endpoint pin, construct the path from the starting pin to that endpoint pin. Define the path with the smallest slack as the critical path and add it to the critical path set. In the middle; let's assume that the final set of critical paths is generated. The CCP includes The critical path, namely ,in, For the first Critical path ;

[0015] A4. Constructing the temporal cost function: Define the temporal cost as the set of critical paths. The weighted sum of the temporal costs of all paths in the process is expressed as:

[0016] ,

[0017] in, For path The corresponding time series cost is expressed as:

[0018] ,

[0019] in, For path upper connected pins With pins The pin pair formed; As the driving intensity factor, , set pin Belongs to layout unit pin Belongs to layout unit ,but and They are layout units Width and height, and Pins Relative to layout unit The horizontal and vertical offsets of the center and Pins Relative to layout unit The horizontal and vertical offsets of the center;

[0020] For path The corresponding time-series cost weights are expressed as:

[0021] ,

[0022] in, For path Timing margin, set of critical paths All paths in The minimum value, and These are preset parameters;

[0023] A5. Determine if convergence has occurred: If the line length and density meet the convergence conditions, proceed to step A6; otherwise, proceed to step A1-3.

[0024] A6. Legalization: By moving the components, the component positions are transformed into legal layouts that satisfy physical constraints, and the final layout result is output.

[0025] Furthermore, in step A1, the line length Using a weighted average line length model, density An electrostatic field model is used.

[0026] Furthermore, in step A4, preset parameters are used. The range of values ​​for is: .

[0027] Furthermore, in step A4, preset parameters are used. The range of values ​​for is: .

[0028] Furthermore, in step A5, the convergence condition is that the line length of the current iteration is greater than the minimum line length before the current iteration and the density overflow rate of the current iteration is less than the threshold.

[0029] Based on the above technical solution, the beneficial effects of the present invention are as follows:

[0030] This invention provides a timing-driven global placement method based on a two-layer delay model. This method constructs a new timing delay model based on the critical path and introduces it as a timing cost into the gradient descent optimization framework. The delay model is divided into two layers: the pin pair layer and the path layer. In the pin pair layer, a driving strength factor is introduced to more accurately characterize the RC delay characteristics of the pin pair. In the path layer, adaptive weights are assigned to different paths according to the timing margin difference - paths with tight timing margins receive larger weights, and paths with sufficient margins receive smaller weights. Thus, while controlling the increase in line length, the timing performance of the circuit, such as the total negative timing margin (TNS) and the worst negative timing margin (WNS), is effectively improved. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating the timing-driven global layout method based on a two-layer delay model according to the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0033] This embodiment provides a timing-driven global layout method based on a two-layer delay model, the process of which is as follows: Figure 1As shown below, the steps are explained using the SuperBlue1 circuit from the ICCAD 2015 public test benchmark circuit set as an example. This circuit contains 1,159,346 layout cells and a total of 3,767,494 pins.

[0034] The specific steps of the time-driven global layout method based on the two-layer delay model are as follows:

[0035] A1. Gradient Descent Optimization Layout:

[0036] A1-1. Construct the objective function: Let the vector coordinates of the center of the layout unit be... , , ,in, and The first The x and y coordinates of each layout unit, , Define the number of layout cells; define the line length based on the layout cell coordinates. ,density and timing Three cost functions; , and The objective function is obtained by weighted summation of the three functions. :

[0037] ,

[0038] in, and These are the weighting coefficients for density and time series terms, respectively; This is a binary time-series enable variable, with an initial value of 0;

[0039] In this embodiment, the line length and density Both adopt the classic layout method used in DREAMPlace 4.0, i.e. Using a weighted average line length model, An electrostatic field model is used; before enabling the timing evaluation, due to the binary timing enable variables... The timing cost term can be ignored; it is set here. ;

[0040] A1-2. Set the iteration counter to an initial value of 0. ;

[0041] A1-3. Single-step gradient descent: Minimizing the objective function using gradient descent. Currently, a single-step update is being performed, and the iteration counter is being updated. This yields the updated vector coordinates of the layout units;

[0042] In this embodiment, the updated layout unit vector coordinates are obtained by performing a single-step update according to Nesterov's Accelerated Gradient Descent (NAG) method.

[0043] A2. Determine whether to perform a time series evaluation: Let... and These are the preset number of preheating steps and the timing evaluation interval, respectively. Exceeding the number of preheating steps And the time-series evaluation interval If divisible, then set a binary timing enable variable. If the result is 1, proceed to step A3; otherwise, proceed to step A1-3.

[0044] In this embodiment, the number of preheating steps is set. Time series evaluation interval Therefore, when the iteration counter At that time, set a binary timing enable variable. If the value is 1, proceed to step A3. Before this, proceed to steps A1-3 and continue performing single-step gradient descent.

[0045] A3. Critical Path Extraction: Use static timing analysis tools to perform timing analysis, identify all path endpoint pins with timing margin slack < 0, and for each endpoint pin, construct the path from the starting pin to that endpoint pin. Define the path with the smallest slack as the critical path and add it to the critical path set. In the middle; let's assume that the final set of critical paths is generated. The CCP includes The critical path, namely ,in, For the first Critical path ;

[0046] In this embodiment, the static timing analysis tool OpenTimer is used for timing analysis. For example, 26,326 path endpoint pins with timing margin slack < 0 were identified. A critical path was obtained from each endpoint pin and added to the critical path set. In the end, it was formed ;

[0047] A4. Constructing the temporal cost function: Define the temporal cost as the set of critical paths. The weighted sum of the temporal costs of all paths in the process, i.e.:

[0048] ,

[0049] in, For path The corresponding time series cost is specifically expressed as:

[0050] ,

[0051] in, For path upper connected pins With pins The pin pair formed; As the driving intensity factor, , set pin Belongs to layout unit pin Belongs to layout unit ,but and They are layout units Width and height, and Pins Relative to layout unit The horizontal and vertical offsets of the center and Pins Relative to layout unit The horizontal and vertical offsets of the center;

[0052] For path The corresponding time-series cost weights are specifically represented as follows:

[0053] ,

[0054] in, For path Timing margin, set of critical paths All paths in The minimum value, and These are preset parameters;

[0055] In this embodiment, with For example, the first critical path It is an electrical path that starts from the starting pin A1_B1_C1_D12_o534273:q, passes through 60 paired placement cells, and finally ends at the ending pin A1_B1_C5_o554880:d; therefore, the critical path It contains 59 pairs of pins for connecting layout units, such as the first pin pair being (A1_B1_C1_D12_o534273:q, A1_B1_C1_D12_o134359:a) and the last pin pair being (A1_B1_C5_o28075:o, A1_B1_C5_o554880:d);

[0056] In the first pin pair, pin A1_B1_C1_D12_o534273:q belongs to layout cell A1_B1_C1_D12_o534273, with a horizontal offset of 0.905µm and a vertical offset of 0.865µm relative to the center of its respective layout cell; pin A1_B1_C1_D12_o134359:a belongs to layout cell A1_B1_C1_D12_o134359, with a horizontal offset of 1.393µm and a vertical offset of 0.600µm relative to the center of its respective layout cell. Layout cell A1_B1_C1_D12_o534273 has a width of 9.500µm and a height of 1.710µm, therefore, the drive strength factor corresponding to this layout cell is... Therefore, the timing cost corresponding to the first pin pair is: The timing costs of all 59 pin pairs are summed to obtain the first critical path. Corresponding time series cost ;

[0057] In this embodiment, preset parameters The range of values ​​for is: ,here The value is 12; preset parameter The range of values ​​for is: ,here The value is 45. For example, the first critical path Timing margin The set of critical paths All paths in minimum value Therefore, the path Corresponding time-series cost weights ;

[0058] A5. Determine if convergence has occurred: If the line length and density meet the convergence conditions, proceed to step A6; otherwise, proceed to step A1-3.

[0059] In this embodiment, the convergence condition is that the line length of the current iteration is greater than the minimum line length before the current iteration and the density overflow rate of the current iteration is less than the threshold. The threshold range is 0.05~0.15, and in this embodiment it is set to 0.1. The density overflow rate is the ratio of the total excess area of ​​all instances in the cell that exceeds the cell capacity to the total area of ​​the layout unit.

[0060] A6. Legalization: By moving components, the component positions are transformed into a legal layout that meets physical constraints such as no overlap, row alignment, grid alignment, and power connection, and the final layout result is output.

[0061] In this embodiment, the DREAMPlace 4.0 method is used to convert the component positions into a legal layout that meets physical constraints such as no overlap, row alignment, grid alignment, and power connection. The final output is a .def file, which stores the global layout result for the current input circuit.

[0062] To evaluate the performance of the method of this invention, this invention was compared with DREAMPlace 4.0. Three indicators were used: total negative timing margin (TNS), worst negative timing margin (WNS), and half-cycle length (HPWL). The test circuits included the smaller-scale circuit Superblue4, the medium-scale circuit Superblue1, and the larger-scale circuit Superblue7 in ICCAD2015. The test results are shown in Table 1.

[0063] Table 1 Layout Performance Comparison

[0064]

[0065] As shown in Table 1, compared with DREAMPlace 4.0, the performance of TNS and WNS of the present invention is significantly improved, while HPWL remains unchanged. This indicates that the timing-driven global layout method based on the two-layer delay model proposed in this invention can effectively improve the timing performance of the circuit while the control line length increases.

[0066] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A timing-driven global placement method based on a two-layer delay model, characterized in that, Includes the following steps: A1. Gradient descent optimization layout: A1-1. Construct the objective function: Let the vector coordinates of the center of the layout unit be... , , ,in, and The first The x and y coordinates of each layout unit, , Define the number of layout cells; define the line length based on the layout cell coordinates. ,density and timing Three cost functions; , and The objective function is obtained by weighted summation of the three functions. : ， in, and These are the weighting coefficients for density and time series terms, respectively; This is a binary time-series enable variable, with an initial value of 0; A1-2. Set the iteration counter to an initial value of 0. ; A1-3. Single-step gradient descent: Minimizing the objective function using gradient descent. Currently, a single-step update is being performed, and the iteration counter is being updated. This yields the updated vector coordinates of the layout units; A2. Determine whether to perform a time series evaluation: Let... and These are the preset number of preheating steps and the timing evaluation interval, respectively. Exceeding the number of preheating steps And the time-series evaluation interval If divisible, then set a binary timing enable variable. If the result is 1, proceed to step A3; otherwise, proceed to step A1-3. A3. Critical Path Extraction: Use static timing analysis tools to perform timing analysis, identify all path endpoint pins with timing margin slack < 0, and for each endpoint pin, construct the path from the starting pin to that endpoint pin. Define the path with the smallest slack as the critical path and add it to the critical path set. In the middle; let's assume that the final set of critical paths is generated. The CCP includes The critical path, namely ,in, For the first Critical path ; A4. Constructing the temporal cost function: Define the temporal cost as the set of critical paths. The weighted sum of the temporal costs of all paths in the process is expressed as: ， in, For path The corresponding time series cost is expressed as: ， in, For path upper connected pins With pins The pin pair formed; As the driving intensity factor, , set pin Belongs to layout unit pin Belongs to layout unit ,but and They are layout units Width and height, and Pins Relative to layout unit The horizontal and vertical offsets of the center and Pins Relative to layout unit The horizontal and vertical offsets of the center; For path The corresponding time-series cost weights are expressed as: ， in, For path Timing margin, set of critical paths All paths in The minimum value, and These are preset parameters; A5. Determine if convergence has occurred: If the line length and density meet the convergence conditions, proceed to step A6; otherwise, proceed to step A1-3. A6. Legalization: By moving the components, the component positions are transformed into legal layouts that satisfy physical constraints, and the final layout result is output.

2. The timing-driven global layout method based on a two-layer delay model according to claim 1, characterized in that, In step A1, the line length Using a weighted average line length model, density An electrostatic field model is used.

3. The timing-driven global layout method based on a two-layer delay model according to claim 1, characterized in that, In step A4, preset parameters The range of values ​​for is: .

4. The timing-driven global layout method based on a two-layer delay model according to claim 1, characterized in that, In step A4, preset parameters The range of values ​​for is: .

5. The timing-driven global layout method based on a two-layer delay model according to claim 1, characterized in that, In step A5, the convergence condition is that the line length of the current iteration is greater than the minimum line length before the current iteration and the density overflow rate of the current iteration is less than the threshold.

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