Time sequence driven global layout-oriented delay sensing line network weighting method

Abstract

The invention discloses a time sequence driven global layout-oriented delay sensing line network weighting method, which comprises the following steps of: in a layout preprocessing stage, quantizing unit driving capability based on a standard unit delay lookup table, and calculating a reference line length; in the global layout process, key paths and net criticality are extracted; performing weight reconstruction modeling and updating on each line network; solving a layout objective function, and executing standard unit legalization operation after layout convergence; time sequence analysis is dynamically triggered in optimization iteration, and the network weight is adjusted in a self-adaptive mode according to path changes. According to the method, while the wiring length and the operation efficiency are maintained, the time sequence margin on a critical path is remarkably improved, setup and hold violations are effectively relieved, and the performance requirement of the time sequence driving layout of a super-large-scale integrated circuit under the advanced technology is met.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit physical design automation, and specifically relates to a delay-aware wire net weighting method for timing-driven global placement. BACKGROUND

[0002] With the design of very large scale integrated circuits (VLSI) entering the nanometer scale, the number of standard cells in a chip continues to grow, and the timing constraints continue to become more stringent, making it a key challenge in physical design to achieve effective timing convergence. As the initial stage in the physical design process, global placement is responsible for determining a reasonable physical location for each standard cell, and its optimization results have a direct and far-reaching impact on the subsequent resource distribution, congestion control and timing performance of wiring.

[0003] During the placement process, different wire nets have obvious differences in function in the circuit, and their sensitivity to timing also varies. Some wire nets are located on the critical path, and their propagation delay needs to be strictly controlled. Non-critical path wire nets have relatively small impact on timing. At the same time, there are differences in driving ability between different driving cells, which are affected by factors such as load capacitance, process parameters and fanout structure. If these differences are not fully considered during the placement stage, it may lead to an increase in the wiring length of the wire net on the critical path, uneven load or insufficient driving, thereby causing serious timing violations.

[0004] The quality of placement not only affects timing convergence itself, but also directly restricts the optimization space of subsequent physical implementation stages. For example, unreasonable initial placement will increase the congestion density and wiring length in the wiring stage, reducing the timing optimization margin. In the buffer insertion and gate sizing stages, if the critical path offset is too large, it may also lead to buffer insertion failure or limited gate sizing space, affecting the timing closure and power consumption of the entire design. Therefore, if the placement stage lacks modeling and guidance of the propagation characteristics of critical wire nets, it will form a bottleneck effect in the entire physical design process.

[0005] In addition, placement is a highly dynamic optimization process. As the positions of standard cells change, the topology and physical properties of wire nets also change, which in turn causes the delay characteristics of wire nets to fluctuate significantly. Especially in the early stage of optimization, the placement state is not yet stable, and the real-time and robustness of timing response is particularly important. If there is a lack of effective modeling and awareness of such dynamic changes, it may limit the timing guidance capability of the placement optimization, and affect the optimization convergence efficiency and quality of the entire design. SUMMARY

[0006] Inventive purpose: In order to solve the problems of lack of timing sensitivity modeling in global placement stage, poor consideration of driving capability difference and weak delay dynamic change perception ability, the application proposes a delay perception wire net weighting method for timing driven global placement, which is used to dynamically guide the optimization direction of key path related wire net in the layout process, so as to improve the timing convergence of layout result and the optimization space of subsequent physical implementation process.

[0007] Technical scheme: A delay perception wire net weighting method for timing driven global placement, comprising the following steps:

[0008] Step 1: According to the delay lookup table of each standard cell, the driving capability of the wire net of the standard cell is quantified as a capacitive reference load, and further combined with the topological structure of the wire net driven by the standard cell, the reference line length of the driven wire net is estimated;

[0009] Step 2: Determine whether the current layout state meets the static timing analysis trigger condition, only when it meets, execute the static timing analysis operation, and extract the incremental criticality factor of each wire net in the critical path, the critical path refers to the path in the timing path obtained by static timing analysis, from the register clock trigger edge to the register signal port or chip main output port, the signal change time exceeds the current clock cycle limit;

[0010] Step 3: According to the reference line length and the wire net half perimeter in the current layout state, the cell delay balancing factor is constructed;

[0011] Step 4: Based on the Elmore delay model, the equivalent RC delay model of each wire net is constructed, the delay of each wire net is calculated and normalized to obtain the wire net delay balancing factor;

[0012] Step 5: Fuse the cell delay balancing factor, the wire net delay balancing factor and the incremental criticality factor, construct the wire net weighting objective function, and dynamically update the wire net weight;

[0013] Step 6: Taking the wire net weighting objective function in step 5 as the optimization object, repeating steps 2 to 6 for iterative optimization until the preset convergence condition is reached, and the position of the optimized standard cell is obtained; in each iteration, the position of the standard cell is updated based on the gradient change trend of the current position of the standard cell and the position of the standard cell in the last step to predict the next update direction;

[0014] Step 7: The position of the optimized standard cell is legalized to make the layout result meet the physical design rule constraint.

[0015] Further, the driving capability of the wire net of the standard cell is quantified as a capacitive reference load according to the delay lookup table of each standard cell, and the specific operation includes:

[0016] The delay lookup table of each standard cell is obtained, which is defined as LUT(C, S), wherein C represents an output load capacitance feature point, and S represents an input flip time feature point;

[0017] A certain delay lookup table is selected as a reference delay lookup table LUT base ;

[0018] For the delay lookup table LUT cur of any standard cell to be evaluated, a loss function Loss(g) is established to fit the driving multiple g of the reference delay lookup table LUT base ;

[0019]

[0020] In the formula, N and M are respectively the number of output load capacitance feature points and input flip time feature points, C i and S j represent the i-th output load capacitance feature point and the j-th input flip time feature point, respectively, LUT cur (g·C i , S j ) and LUT base (C i , S j ) represent the delay value corresponding to LUT cur (g·C i , S j ) under the feature point C i and S j , and the delay value corresponding to the reference delay lookup table LUT base (C i , S j ), and g represents the driving intensity multiple of the delay lookup table LUT cur of the standard cell to be evaluated relative to the reference delay lookup table LUT base ;

[0021] The partial derivative of the loss function Loss(g) with respect to g is obtained, and the gradient expression of the driving multiple g is obtained:

[0022]

[0023] The loss function Loss(g) is minimized to obtain the driving multiple that minimizes the loss function Loss(g);

[0024] The reference load corresponding to the driving intensity of the reference delay lookup table LUT base is set as L baseThe delay look-up table LUT of the standard cell to be evaluated cur The reference load corresponding to the driving strength of the standard cell is:

[0025] L ref = g·L base .

[0026] Further, the reference line length of the driven line net is estimated based on the topology of the line net driven by the standard cell, and the specific operation comprises:

[0027] For a line net connected to the output pin and a plurality of receiving pins of the standard cell, the parasitic capacitance generated by the line net interconnection segment and the connection pin capacitance together constitute the load of the standard cell;

[0028] Based on the topology of the line net driven by the standard cell, let the sink pin set of the line net be S e , the input capacitance corresponding to one pin s is C s , the unit interconnection capacitance is denoted as cap_unit, and the calculation formula of the reference line length WL e,ref of the line net is:

[0029]

[0030] In the formula, L e,ref represents the reference capacitance of the type of the driven cell corresponding to the line net e.

[0031] Further, the static timing analysis trigger condition is that when the density overflow under the current layout state is lower than a first threshold value and the iteration number is an integer multiple of a set value, the static timing analysis is triggered once;

[0032] The density overflow under the current layout state is calculated according to the following steps:

[0033] First, the layout area is divided into a plurality of grids, the unit area density in each grid is counted and compared with the preset target density, let the grid set be B, and the movable unit set be V mov , the unit area density in the grid b under the current position is D b (x, y), x and y are respectively the coordinate vectors of the unit in the horizontal and vertical positions, the grid area is A b , the preset target density is d target , and the area of any movable unit is A c , then the density overflow calculation formula under the current layout state is:

[0034]

[0035] Further, the static timing analysis operation is performed, and an incremental criticality factor of each wire net in the critical path is extracted, and the specific operation includes:

[0036] For the wire net e, define its setup time margin as:

[0037]

[0038] Wherein, S e represents all sink pin sets of the wire net e, represents the setup timing margin of the pin s;

[0039] According to the wire net criticality index is constructed:

[0040]

[0041] Wherein, wns setup represents the worst negative setup time margin of the wire net e;

[0042] The incremental criticality factor is updated in an exponential weighted moving average manner:

[0043]

[0044] Wherein, ε is a adjustable proportion coefficient, is the last incremental criticality factor of the wire net e, and is initialized as 1, η e is a weight dynamically adjusted according to the slack fluctuation, and is defined as:

[0045]

[0046] In the formula, represents the setup timing margin value of the wire net e in the last timing iteration.

[0047] Further, the unit delay balancing factor is constructed according to the reference line length and the wire net half circumference in the current layout state, and the specific operation includes:

[0048] For the wire net e, in the mth iteration, the normalized line length offset rate is calculated, and the definition is as follows:

[0049]

[0050] Wherein, represents the actual line length of the wire net e in the current iteration, WL e,ref represents the reference line length of the wire net e;

[0051] Based on the normalized line length offset rate the unit delay balancing factor It is defined as follows:

[0052]

[0053] Among them, the parameter α is the control factor that adjusts the steepness of the curve;

[0054] The initial value of parameter α is set to 1. When the density overflow of the current layout state is lower than the second threshold, and the second threshold is greater than the first threshold, a dynamic update is triggered. The update formula is:

[0055] α=b·β

[0056] Where β is the scaling factor set by the user, and b is the exponential average of the offset rate of the network set E, which is calculated as follows:

[0057]

[0058] Furthermore, the equivalent RC delay model of each line network is constructed based on the Elmore delay model, the delay of each line network is calculated and normalized, and the line network delay equalization factor is obtained. The specific operations include:

[0059] For line net e, match the sink pin set S according to the source pin D e Perform horizontal and vertical RC interconnection to generate interconnection tree, and use Elmore delay model to calculate the delay of a receiving end S i The delay of the horizontal and vertical interconnection trees is estimated, which are expressed as D(S i ) P1 and D(S i ) P2 , define the receiving end S i The delay is:

[0060] D(S i )=max(D(S i ) P1 ,D(S i ) P2 )

[0061] Define the receiving end S i The attention weight i s , construct the weighted maximum delay of the network at the mth iteration:

[0062]

[0063] Finally, the network delay equalization factor is constructed It is defined as follows:

[0064]

[0065] in, The largest weighted maximum delay in each net.

[0066] Further, the dynamic updating of the weights of the nets is specifically performed as follows:

[0067] The weight updating method of the net e in the mth iteration is defined as follows:

[0068]

[0069] wherein, is a unit delay balancing factor, is a net delay balancing factor, f e,cri is an incremental criticality factor, and k is a constant term.

[0070] Further, the preset convergence condition is:

[0071] (1) When the density overflow in the layout process drops to below a third threshold, it is considered that the current layout has reached an acceptable physical density balancing state, and the iteration is terminated; the third threshold is less than the first threshold;

[0072] or (2) the iteration is terminated in advance under the condition that other auxiliary conditions are met.

[0073] Further, the Abacus legalization algorithm is used to legalize the positions of the optimized standard cells, so as to satisfy: (1) the standard cells must be aligned to the standard cell rows, and the row boundary restrictions are met; (2) the standard cells cannot overlap.

[0074] Beneficial effects: Compared with the prior art, the method can significantly improve the timing margin on the critical path while maintaining the wiring length and running efficiency, effectively alleviates the setup and hold violations, and meets the performance requirements of timing-driven layout of super-large scale integrated circuits under advanced processes. BRIEF DESCRIPTION OF DRAWINGS

[0075] Figure 1 The flowchart of the delay-aware net weighting method for timing-driven global layout proposed by the present application is shown. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical scheme and advantages of the present application clearer, the delay-aware net weighting method for timing-driven global layout proposed by the present application will be further described below in combination with the drawings and examples.

[0077] Example 1:

[0078] The embodiment proposes a delay-aware wire-net weighting method for timing-driven global placement. The method introduces a comprehensive delay-aware wire-net weighting mechanism, and comprehensively considers the driving capability of standard cells, wire-net RC delay and critical path information, to guide the placement process to improve timing convergence capability and subsequent design quality. As shown in FIG. 8, the method mainly includes the following steps: Figure 1

[0079] Step 1: In the layout preprocessing stage, based on the delay lookup table (LUT) of the standard cell, the driving capability of the standard cell is quantified in an analytical way, and the reference line length of the driven wire-net is further estimated in combination with the topological structure. The specific operation includes the following two sub-processes:

[0080] (1) According to the driving capability of the standard cell, it is quantified as a capacitive reference load;

[0081] For the standard cell cell, in order to evaluate the driving capability of the standard cell, first, according to the process characteristic library file (.lib file) of the standard cell, the delay lookup table (LUT) of each standard cell is extracted as LUT(C,S), wherein C represents the output load capacitance characteristic point, and S represents the input transition time characteristic point. And select a certain delay lookup table LUT base as the reference reference lookup table.

[0082] For any standard cell lookup table LUT cur to be evaluated, the following loss function is established to fit its driving multiple g relative to LUT base :

[0083]

[0084] In the formula, N and M are the number of output load capacitance and input transition time characteristic points, respectively, C i and S j represent the i-th output load capacitance characteristic point and the j-th input transition time characteristic point, respectively, LUT cur (g·C i ,S j ) and LUT base (C i ,S j ) represent the delay value corresponding to LUT cur (g·C i ,S j ) under the characteristic point C i and S j , and the reference reference delay lookup table LUT base (C i ,S j ​) corresponding to the delay value, g represents the driving strength multiple of the current standard cell relative to the reference cell. LUT base The rising delay table (cell_rise) of the INV_X1 cell is preferred.

[0085] The partial derivative of the loss function Loss(g) with respect to g is obtained, and the gradient expression with respect to the driving multiple g is obtained:

[0086]

[0087] The partial derivative of the LUT cur can be obtained by interpolation fitting. The driving multiple g can be solved by minimizing the above loss function through a numerical optimizer (such as the Adam optimizer), so as to obtain the driving multiple that minimizes Loss(g).

[0088] The LUT base is set to be base The reference load corresponding to the driving strength of the LUT cur is:

[0089] L ref = g·L base

[0090] (2) After obtaining the reference load L ref corresponding to the driving line net capability of the standard cell, the reference line length matching the driving strength can be further calculated in combination with the topology of the line net driven thereby.

[0091] For a line net connected to the output pin and a plurality of receiving pins of a standard cell, the parasitic capacitance generated by the line net interconnection line segment and the connection pin capacitance together constitute the load of the standard cell. In combination with the topology of the line net driven by the current standard cell, the reference line length of the line net is estimated. Let the sink pin set of the line net be S e , the input capacitance corresponding to each pin s is C s , the unit interconnection capacitance is denoted as cap_unit, and the calculation formula of the reference line length WL e,ref of the line net is:

[0092]

[0093] In the formula, L e,ref represents the reference capacitance of the driving cell type corresponding to the line net e.

[0094] Step 2: To optimize the timing of the dynamic routing process, a trigger condition for static timing analysis (STA) is set. The trigger condition is used to determine whether the current layout state meets the trigger condition for static timing analysis (STA). If the trigger condition is met, the STA operation is performed and the incremental criticality factor of each net in the critical path is extracted. The critical path refers to a path in the timing path obtained by static timing analysis, in which the signal change time from the register clock trigger edge to the register signal port or chip main output port exceeds the current clock cycle limit due to excessive delay of the combinational logic and the wire delay on the path. The specific operation includes:

[0095] In this embodiment, the trigger condition for static timing analysis (STA) is that when the density overflow of the current layout state is less than a threshold value (set to 0.2) and the design iteration number is an integer multiple of 30, static timing analysis (STA) is triggered once.

[0096] The density overflow under the current layout state is calculated as follows:

[0097] First, the layout area is divided into a plurality of grids, and the area density of each grid is calculated and compared with the preset target density. Let the grid set be B, and the movable cell set be V mov The area density of the cell in grid b at the current position is D b (x, y), where x and y are the coordinate vectors of the cell in the horizontal and vertical positions, the grid area is A b , the preset target density is d target , and the area of any movable cell is A c The density overflow calculation formula under the current layout state is:

[0098]

[0099] For a net e, the setup slack is defined as:

[0100]

[0101] where S e represents the set of all sink pins of net e, represents the setup timing slack of pin s.

[0102] According to the net criticality index is constructed as:

[0103]

[0104] where wns setup represents the worst negative setup slack of net e.

[0105] The incremental criticality factor is updated in an exponentially weighted moving average manner:

[0106]

[0107] where ε is a tunable proportionality coefficient, is the last incremental criticality factor of the net e, initialized as 1, η e is the weight dynamically adjusted according to slack fluctuation, which is defined as:

[0108]

[0109] where, denotes the setup slack value of the net e at the last timing iteration.

[0110] Step 3: According to the reference wire length calculated in step 1 and the half perimeter wire length (HPWL) in the current layout state, the unit delay balancing factor is constructed to measure the coordination between the standard cell driving capability and the physical properties of the net. The specific operation includes:

[0111] To quantify the matching between the standard cell driving capability and the topology of the net it drives, for each net e, in the mth iteration, the normalized wire length offset rate is calculated which is defined as follows:

[0112]

[0113] where, denotes the actual wire length of the net in the current iteration, WL e,ref denotes the reference wire length of the net.

[0114] Based on the wire length offset rate the unit delay balancing factor is constructed which is defined as follows:

[0115]

[0116] where the parameter α is a control factor that adjusts the steepness of the curve.

[0117] The initial value of the parameter α is set to 1, and a dynamic update is triggered once the layout density overflow is less than 0.5, and its update formula is:

[0118] α = b·β

[0119] where β is a scaling factor set by the user, and b is the exponential average of the offset rate of the net set E, which is calculated as follows:

[0120]

[0121] Step 4: Based on the Elmore delay model, an equivalent RC delay model of each line network is constructed, the delay of each line network is calculated and normalized, and the line network delay balancing factor is obtained. The specific operation includes:

[0122] To reflect the delay characteristics of the line network under the conditions of topology and load, for each line network e, according to the source pin D and the sink pin set S e , the horizontal and vertical RC interconnection generation is performed, and the Elmore delay model is used to estimate the delay of the horizontal and vertical interconnection tree of a receiving end S i , which is D(S i ) P1 and D(S i ) P2 , and the delay of the receiving end S i is defined as:

[0123] D(S i )=max(D(S i ) P1 ,D(S i ) P2 )

[0124] Considering the attention weight i s of the receiving end, the weighted maximum delay of the line network in the mth iteration is constructed:

[0125]

[0126] Finally, the line network delay balancing factor is constructed, and its definition is as follows:

[0127]

[0128] Where, is the maximum weighted maximum delay in each line network.

[0129] Step 5: To consider three types of timing factors embodied by driving capability, RC delay and critical path information, the unit delay balancing factor, the line network delay balancing factor and the incremental criticality factor of the line network are fused, the line network weighted function is constructed, and the line network weight is dynamically updated. The specific operation includes:

[0130] The unit delay balancing factor, the line network delay balancing factor and the incremental criticality factor of the line network are integrated, and the weight updating method of the line network e in the mth iteration is defined as follows:

[0131]

[0132] Where, is the unit delay balancing factor, is the line network delay balancing factor, and fe,cri For increment key factor, k is constant term, used to introduce the basic line network weight to maintain line length quality.

[0133] Step 6: In order to optimize the physical position of standard cells efficiently, Nesterov accelerated gradient descent method is used to optimize the current layout objective function, and the optimization process includes: taking the line network weighted objective function as the optimization object, wherein the line network weight is dynamically calculated according to the unit delay equalization factor, the line network delay equalization factor and the critical path factor; in each iteration, the next step update direction is predicted based on the current position and the last gradient change trend; the position variable of the standard cell is updated, the layout optimization process is iteratively promoted, and the convergence speed and timing guiding ability are improved.

[0134] The line network weighted objective function is represented as:

[0135]

[0136] Where x and y are the coordinate vectors of the cell in the horizontal and vertical positions, w e is the line network weight calculated in step 5, WL e (x, y) is the line network length of the line network e under the current layout, D(x, y) is the density penalty value representing each grid area under the current layout, and λ is an important adjustment parameter for balancing wirelength optimization and density constraint.

[0137] Step 7: In order to ensure that the layout process stably converges to a high-quality solution, a convergence judgment mechanism is set for the optimization iteration process in this step, and when the convergence condition is not met, the optimization loop composed of steps 2 to 6 is repeatedly executed. Specifically, the following convergence criteria are set: (1) when the density overflow in the layout process drops to 0.05 or below, it is considered that the current layout has reached an acceptable physical density equalization state; or (2) under the condition of meeting other auxiliary conditions (such as maximum iteration number limit), the iteration is terminated in advance.

[0138] Step 8: After the global layout optimization process meets the preset convergence condition, in order to ensure that the layout result meets the physical design rule constraints, the standard cell position needs to be legalized. The legalization operation uses Abacus legalization algorithm. The algorithm projects the optimized cell position back to the legal cell row area with the standard cell behavior aligned to the unit, ensuring that the following constraint conditions are met: (1) the cell must be aligned to the standard cell row, meeting the row boundary limit; (2) the cells must not overlap.

Claims

1. A delay-aware net weighting method for timing-driven global layout, characterized by: The following steps are involved: Step 1: Based on the delay lookup table of each standard cell, the capability of the driving line net of the standard cell is quantified as a capacitive reference load. The reference line length of the driven line net is estimated based on the topology of the line net driven by the standard cell. Step 2: Determine whether the current layout state meets the static timing analysis trigger condition. Only if it meets the condition, perform the static timing analysis operation and extract the incremental criticality factor of each line net in the critical path. The critical path refers to the path in the timing path obtained by static timing analysis where the signal change time from the register clock trigger edge to the register signal port or the chip main output port exceeds the current clock cycle limit; Step 3: Construct the cell delay equalization factor based on the reference line length and the half-circumference of the line in the current layout state; Step 4: Construct an equivalent RC delay model for each line net based on the Elmore delay model, calculate the delay of each line net and perform normalization to obtain the line net delay equalization factor; Step 5: Integrate the unit delay equalization factor, the line network delay equalization factor, and the incremental criticality factor to construct the line network weighted objective function and dynamically update the line network weight; Step 6: Using the net weighted objective function in step 5 as the optimization object, repeat steps 2 to 6 for iterative optimization until the preset convergence condition is reached, and the optimized standard cell position is obtained; In each iteration, the next update direction is predicted based on the gradient change trend of the current position of the standard cell and the position of the previous step, and the position of the standard cell is updated accordingly; Step 7: Legalize the positions of the optimized standard cells so that the layout results meet the physical design rule constraints.

2. The delay-aware net weighting method for timing-driven global layout according to claim 1, characterized in that: The aforementioned operation of quantifying the driving line network capability of the standard cell into a capacitive reference load according to the delay lookup table of each standard cell includes: Obtain the delay lookup table of each standard cell, defined as LUT(C,S), where C represents the output load capacitance characteristic point and S represents the input flip time characteristic point; Select a delay lookup table as the reference delay lookup table LUT base ; For any standard cell to be evaluated, the delay lookup table LUT cur , establish the following loss function Loss(g) to fit its delay lookup table LUT relative to the reference base Drive multiple g: Where N and M are the number of characteristic points of output load capacitance and input flip time, respectively. i and S j Respectively represent the i-th output load capacitance characteristic point and the j-th input flip time characteristic point, LUT cur (g·C i ,S j ) and LUTs base (C i ,S j ) represent the feature points C i and S j Next, LUT cur (g·C i ,S j ) corresponding to the delay value under g times the capacitance, and the reference delay lookup table LUT base (C i ,S j ) corresponds to the delay value, g represents the delay lookup table LUT of the standard unit to be evaluated cur Relative reference delay lookup table LUT base The driving strength multiple of By taking the partial derivative of the loss function Loss(g) with respect to g, we can get the gradient expression of the driving factor g: Minimize the loss function Loss\g) to obtain the driving factor that minimizes the loss function Loss\g); Setting the reference delay lookup table (LUT) base The reference load corresponding to the driving strength is L base , then the delay lookup table LUT of the standard cell to be evaluated cur The reference load corresponding to the driving strength is: L ref =g·L base 。 3. The delay-aware net weighting method for timing-driven global layout according to claim 2, characterized in that: The above-mentioned operation of estimating the reference line length of the driven line net based on the topological structure of the line net driven by the standard cell specifically includes: For a wire net, it is connected to the output pins and several receiving pins of the standard unit. The parasitic capacitance generated by the interconnection line segments of the wire net and the connection pin capacitance together constitute the load of the standard unit; Based on the topology of the network driven by the standard cell, the network sink pin set is S e For one of the pins s, the corresponding input capacitance is C s , the unit interconnect capacitance is recorded as cap_unit, then the reference line length WL of the line network e,ref The calculation formula is: Where, L e,ref Indicates the reference capacitance of the drive unit type corresponding to the line e.

4. The delay-aware net weighting method for timing-driven global layout according to claim 3, characterized in that: The static timing analysis triggering condition is: when the density overflow in the current layout state is lower than the first threshold and the number of iterations is an integer multiple of the set value, a static timing analysis is triggered; Follow these steps to calculate density overflow in the current layout state: First, the layout area is divided into several grids. The cell area density in each grid is counted and compared with the preset target density. Let the grid set be B and the movable cell set be V. mov , the unit area density in the grid b at the current position is D b (x,y), x and y are the coordinate vectors of the unit in the horizontal and vertical positions respectively, and the grid area is A b , the preset target density is d target , the area of ​​any movable unit is A c , the density overflow calculation formula in the current layout state is:

5. The delay-aware net weighting method for timing-driven global layout according to claim 4, characterized in that: The aforementioned static timing analysis operation is performed and the incremental criticality factor of each net in the critical path is extracted. Specifically, the operations include: For the line e, its setup time margin is defined as: Among them, S e Represented as the set of all sink pins of the net e, Indicates the setup timing margin of pin s; according to Construct network criticality indicators: Among them, wns setup It represents the worst negative setup time margin of the line net e; Update the incremental criticality factor using an exponentially weighted moving average: Among them, ε is the adjustable proportional coefficient, is the last incremental criticality factor of the network e, initialized to 1, η e The weight is dynamically adjusted according to the fluctuation of slack, which is defined as: Where, Indicates the setup timing margin value of net e in the last timing iteration.

6. The delay-aware net weighting method for timing-driven global layout according to claim 5, characterized in that: The unit delay equalization factor is constructed based on the reference line length and the half-circumference of the line net in the current layout state. The specific operations include: For the line network e, in the mth iteration, calculate its normalized line length deviation rate It is defined as follows: in, Indicates the actual length of the wire mesh e in the current iteration, WL e,ref Indicates the reference line length of the line network e; Based on the normalized line length deviation rate Constructing unit delay equalization factor It is defined as follows: Among them, the parameter α is the control factor that adjusts the steepness of the curve; The initial value of parameter α is set to 1. When the density overflow of the current layout state is lower than the second threshold, and the second threshold is greater than the first threshold, a dynamic update is triggered. The update formula is: α＝b·β Where β is the scaling factor set by the user, and b is the exponential average of the offset rate of the network set E, which is calculated as follows:

7. The delay-aware net weighting method for timing-driven global layout according to claim 6, characterized in that: The equivalent RC delay model of each line network is constructed based on the Elmore delay model, the delay of each line network is calculated and normalized, and the line network delay equalization factor is obtained. The specific operations include: For line net e, match the sink pin set S according to the source pin D e Perform horizontal and vertical RC interconnection to generate interconnection tree, and use Elmore delay model to calculate the delay of a receiving end S i The delay of the horizontal and vertical interconnection trees is estimated, which are expressed as D(S i ) P1 and D(S i ) P2 , define the receiving end S i The delay is: D(S i )=max(D(S i ) P1 ,D(S i ) P2 ) Define the receiving end S i The attention weight i s , construct the weighted maximum delay of the network at the mth iteration: Finally, the network delay equalization factor is constructed It is defined as follows: in, It is the largest weighted maximum delay among all network lines.

8. The delay-aware net weighting method for timing-driven global layout according to claim 7, characterized in that: The dynamic update of the line network weights includes the following specific operations: The weight update method of the network e in the mth iteration is defined as follows: in, is the unit delay equalization factor, is the network delay equalization factor, f e,cri is the incremental criticality factor, and k is a constant term.

9. The delay-aware net weighting method for timing-driven global layout according to claim 8, characterized in that: The preset convergence conditions are: (1) When the density overflow during the layout process drops below a third threshold, it is considered that the current layout has reached an acceptable physical density balance state and the iteration is terminated; the third threshold is less than the first threshold; Or (2) terminate the iteration early if other auxiliary conditions are met.

10. The delay-aware net weighting method for timing-driven global layout according to claim 9, characterized in that: The Abacus legalization algorithm is used to legalize the positions of the optimized standard cells so that: (1) the standard cells must be aligned to the standard cell rows and meet the row boundary restrictions; (2) the standard cells must not overlap.

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