A method for integrating asymmetric stress-distributed vertical channel nanowire transistors

Abstract

This invention discloses an integration method for asymmetric stress-distributed vertical-channel nanowire transistors, belonging to the field of very large-scale integrated circuit manufacturing technology. This invention designs the source / drain materials and channel materials separately, effectively applying uniaxial stress in the channel. By adjusting the magnitude and distribution of this stress, complementary drive currents are achieved for N / P type devices. Simultaneously, this invention effectively improves the hole mobility and on-state current of P-type MOSFETs. The vertical nanowire devices can achieve discrete source / drain fabrication in the manufacturing process, providing greater flexibility for adjusting device characteristics.

Description

Technical Field

[0001] This invention belongs to the field of very large-scale integrated circuit manufacturing technology and relates to a vertical channel nanowire / nanosheet transistor with asymmetric stress distribution. Background Technology

[0002] As semiconductor devices entered the 5nm technology era, horizontal channel devices, represented by FinFETs, faced challenges in further scaling down, such as reaching the limits of photolithography in terms of device size and density. Therefore, vertical channel nanowire / nanofasheet devices have attracted attention due to their advantage of being able to scale down their physical gate length and contact hole spacing independently of the channel projection area, thereby increasing integration density.

[0003] In CMOS circuits, to achieve complementarity between N / P type devices, the on-state currents of N-type and P-type devices must be matched. In silicon, the mobility of holes is much lower than that of electrons, but they are more sensitive to strain changes. Therefore, in horizontal CMOS device integration processes, stress engineering, such as stressed silicon channels and source / drain stress engineering, is used to increase the drive current of P-type devices.

[0004] Currently, the reported integration schemes for vertical channel nanowire / nanofasheet devices mainly employ anisotropic etching to form the vertical channels. During the etching process, the stress evolves according to the pattern size, and both the magnitude and direction of the stress are redistributed. Moreover, due to the channel orientation, vertical channel devices cannot apply stress to the channel through conventional stress engineering.

[0005] Therefore, in order to realize vertical channel CMOS devices with complementary drive currents, the industry urgently needs an integrated solution for stress application and control. Summary of the Invention

[0006] To address the above problems, this invention provides an integration method for asymmetric stress-distributed vertical channel nanowire transistors, which is beneficial for achieving complementary on-state currents between N-type and P-type devices.

[0007] The technical solution of the present invention is as follows:

[0008] An integration method for asymmetric stress distribution vertical channel nanowire transistors, characterized by comprising the following steps:

[0009] A. Epitaxially forming a single crystal material on the substrate. For NMOS, the lattice constant of the heavily doped active region material is required to be greater than that of the lightly doped channel layer. For PMOS, the lattice constant of the heavily doped active region material is required to be less than that of the lightly doped channel layer. A stack of bottom source / drain materials and channel materials is formed. Uniaxial stress in the vertical direction is generated in the lightly doped channel layer through lattice adaptation.

[0010] B. Forming device isolation in the active layer;

[0011] C. Vertical channels are formed through graphical representation;

[0012] D. Deposit a layer of medium to form a bottom barrier isolation;

[0013] E. Deposit a layer of dummy gate material and pattern it to form a dummy gate pattern;

[0014] F. Deposit a layer of dielectric material to form the top barrier isolation layer;

[0015] G. The top gate isolation dielectric is patterned and the top source drain is formed by epitaxy. For NMOS, the lattice constant of the top source drain material is required to be greater than that of the lightly doped channel layer. For PMOS, the lattice constant of the top source drain material is required to be less than that of the lightly doped channel layer. At the same time, in order to achieve the asymmetric distribution of stress in the device channel and the control of channel stress, the lattice constant of the top source drain material is different from that of the bottom source drain material, so as to ensure that uniaxial stress in the vertical direction is generated in the channel layer through lattice mismatch.

[0016] H. Dummy gate removal and formation of gate oxide layer and metal gate.

[0017] I. Forming metal contacts at each end of the device;

[0018] J. The device integration will then be completed using the publicly available back-end process.

[0019] Furthermore, step A specifically includes:

[0020] A1. By covering the PMOS region with a hard mask material, a layer of semiconductor material is selectively epitaxially grown to form an N-type heavily doped active region, which is the source or drain terminal below the vertical transistor.

[0021] A2. An epitaxial layer of semiconductor material is grown to form a lightly doped P-type region, the thickness of which defines the channel length of the N-type device;

[0022] A3. Remove the hard mask from the PMOS region and cover the NMOS region with the hard mask material;

[0023] A4. Selectively epitaxially grow a layer of semiconductor material to form a heavily doped P-type active region, which is the source or drain terminal below the vertical transistor.

[0024] A5. An epitaxial layer of semiconductor material is grown to form a lightly doped N-type region, the thickness of which defines the channel length of the P-type device;

[0025] Among them, the semiconductor materials described in steps A1, A2, A4, and A5 should maintain a perfect single-crystal structure.

[0026] Furthermore, step C specifically includes the following implementation steps:

[0027] C1. Deposit a dielectric layer as a hard mask material for etching, used to protect the channel pattern during multiple etching processes;

[0028] C2. The channel is defined by photolithography, and its size and shape determine the size and shape of the device channel cross-section;

[0029] C3. A hard mask pattern is formed by anisotropic etching, exposing a lightly doped layer in the area not protected by the photoresist.

[0030] C4. Vertical channels are formed by anisotropic etching, exposing the heavily doped active region at the bottom of the unprotected area of ​​the photoresist, and the etching depth includes the entire lightly doped region.

[0031] Furthermore, step D specifically includes:

[0032] D1. Deposition medium material;

[0033] D2. Achieving dielectric surface planarization through CMP;

[0034] D3. The dielectric is etched back below the channel layer by anisotropic etching, but it should not be too far below the lower surface of the channel layer. The size below the lower surface of the channel layer is the size of the over-coverage area of ​​the device gate to the source and drain.

[0035] Furthermore, step E specifically includes:

[0036] E1. Deposit a layer of pseudo-gate material;

[0037] E2. Surface planarization is achieved through CMP;

[0038] E3. The material is etched back to below the hard mask surface and above the lightly doped channel layer surface through anisotropic etching. The remaining thickness of the dummy gate layer defines the gate length of the device.

[0039] E4. Remove hard mask;

[0040] E5. A dummy gate pattern is formed by photolithography, and the pattern determines the gate lead-out pattern of the device;

[0041] E6. Anisotropic etching is used to remove the dummy gate material that is not protected by photoresist, exposing the underlying gate isolation dielectric.

[0042] Furthermore, step F specifically includes:

[0043] F1. Deposition medium material, which is the same material as the bottom gate isolation medium described in step D, and its thickness is greater than the height of the dummy gate pattern;

[0044] F2. Achieving dielectric surface planarization through CMP;

[0045] F3. The dielectric thickness is reduced by anisotropic etching, and its thickness should meet the requirements of the isolation gate and source / drain.

[0046] Furthermore, step G specifically includes:

[0047] G1. Define the top-level source / drain epitaxial window using photolithography; the photolithographic pattern should be aligned with the underlying channel pattern.

[0048] G2. Anisotropic etching is used to form the top-level source / drain epitaxial windows, exposing the underlying lightly doped channel layer;

[0049] G3. Selective epitaxial growth to form a top heavily doped source / drain layer, wherein the top source / drain material should maintain a single crystal structure and its lattice constant should be greater than or less than that of the lightly doped channel layer material.

[0050] Furthermore, step H specifically includes:

[0051] H1. Deposit a dielectric layer with a thickness greater than the epitaxial height of the top source / drain layer;

[0052] H2. The underlying dummy gate layer is exposed by defining a window through photolithography and anisotropic etching;

[0053] H3. Removal of dummy gate material through isotropic corrosion;

[0054] H4. By sequentially filling the gate oxide layer material and the metal gate material with isotropic conformal properties, the voids formed after the removal of the dummy gate in step H3 are completely filled.

[0055] H5. Remove the metal and gate dielectric material grown on top of the dielectric in step H1 by anisotropic etching.

[0056] Furthermore, step I specifically includes:

[0057] I1. Deposit a layer of dielectric material for interlayer isolation and achieve planarization through CMP;

[0058] I2. Contact holes at each end of the device are formed by photolithography and anisotropic etching;

[0059] I3. Each contact hole is filled with Metal 0;

[0060] I4. By performing CMP on the metal 0, the conductive layers between devices are separated, achieving the effect of device isolation.

[0061] Furthermore, the substrate is a bulk silicon substrate, an SOI substrate, a bulk germanium substrate, or a GOI substrate.

[0062] Furthermore, the filler metal Metal 0, which serves as the conductive layer, is required to have low resistivity, and can be selected from materials such as W and Cu.

[0063] The advantages and positive effects of this invention are as follows:

[0064] 1) Compared with existing methods that form vertical nanowire channels by etching, the source / drain material and channel material design proposed in this invention can effectively apply uniaxial stress in the channel; by adjusting the magnitude and distribution of the stress, complementary drive currents of N / P type devices can be achieved.

[0065] 2) This invention can flexibly realize the hybrid integration of multiple material channels or source / drain, can realize the asymmetric stress distribution in the device channel, and can realize the magnitude and distribution of stress in the channel by adjusting the material parameters. It can simultaneously optimize and control the on-state current and subthreshold characteristics of the device. Attached Figure Description

[0066] Figures 1 to 21 These are schematic diagrams illustrating the key processes involved in fabricating a vertical-channel CMOS device in a specific embodiment of the present invention. In each figure, (a) is a top view, and (b) is a cross-sectional view along A-A' in (a), wherein:

[0067] Figure 1 The heavily doped active region and the lightly doped channel layer of the bottom source and drain of the N-type device are formed by in-situ doping epitaxy on the substrate.

[0068] Figure 2 The heavily doped active region of the bottom source / drain and the lightly doped channel layer of the P-type device are formed by in-situ doping epitaxy on the substrate.

[0069] Figure 3 Deposit a hard mask, and use photolithography to define the active region;

[0070] Figure 4 Etching creates active regions;

[0071] Figure 5 STI isolation is formed between active regions;

[0072] Figure 6 Deposit a hard mask, then use photolithography and etching to form vertical channels;

[0073] Figure 7 Deposit and etch back to form the bottom gate isolation medium;

[0074] Figure 8 A pseudo-gate material layer is formed by deposition and etchback.

[0075] Figure 9 Hard mask removal and dummy grid patterning;

[0076] Figure 10Deposit and etch back to form the top gate isolation medium;

[0077] Figure 11 Photolithography etching defines the top source / drain epitaxial window of the NMOS transistor;

[0078] Figure 12 NMOS top source / drain is formed by in-situ doping and epitaxy;

[0079] Figure 13 Photolithography defines the top source / drain epitaxial window of the PMOS transistor;

[0080] Figure 14 PMOS top source / drain is formed by in-situ doping and epitaxy;

[0081] Figure 15 Interlayer isolation medium;

[0082] Figure 16 The window is removed by exposing the dummy gate through photolithography etching.

[0083] Figure 17 The dummy gate material was removed by isotropic corrosion.

[0084] Figure 18 Fill with HKMG material sequentially;

[0085] Figure 19 Interlayer media isolation;

[0086] Figure 20 Contact hole V0 is formed by photolithography etching;

[0087] Figure 21 The contact holes are filled with metal (Metal 0) and CMP is used to isolate the conductive layer of the device.

[0088] Figure 22 for Figures 1 to 21 Legend of the diagram. Detailed Implementation

[0089] The present invention will now be described in detail with reference to the accompanying drawings and specific examples.

[0090] In a specific embodiment of this invention, the bottom source / drain material of the NMOS is SiGe, and the channel material is Si; the bottom source / drain material of the PMOS is Si, and the channel material is SiGe. In the Si / SiGe superlattice structure, SiGe experiences compressive stress in the biaxial direction and tensile stress in the uniaxial direction; Si experiences tensile stress in the biaxial direction and compressive stress in the uniaxial direction. After dry etching, the stress at the edge of the pattern is released, and the uniaxial tensile stress in SiGe evolves into uniaxial compressive stress, while the uniaxial compressive stress in Si evolves into uniaxial tensile stress. Therefore, the NMOS uses a SiGe source / drain / Si channel structure, and the channel experiences uniaxial tensile stress after etching; the PMOS uses a Si source / drain / SiGe channel structure, and the channel experiences uniaxial compressive stress after etching. Since the hole mobility in SiGe is much higher than that in Si, the hole mobility is increased by using SiGe material, which, while ensuring the improvement of carrier stress, achieves complementarity in the drive current of NMOS and PMOS.

[0091] The following specific steps can be used to achieve CMOS integration of a 6nm diameter bulk silicon vertical nanowire device (its structural parameters are set according to the "11 / 10nm" technology generation High-Performance device in ITRS-2013):

[0092] 1) A hard mask material is deposited on a bulk silicon substrate, and the NMOS region is exposed by photolithography and etching. 100nm N+Si is then formed in the NMOS region using an in-situ doped epitaxial process. 1-x Ge x A heavily doped active region (serving as the source / drain of the NMOS) is formed, and a 20nm lightly doped PSi layer (serving as the channel of the NMOS) is formed on the N+ heavily doped active region, such as... Figure 1 As shown;

[0093] 2) Remove the existing hard mask, redeposit the hard mask material, and use photolithography to etch and expose the PMOS region and the 100nm P+ region.

[0094] A heavily doped Si active region (serving as the source / drain of the PMOS) is formed on the P+ heavily doped active region, with a 20nm N Si layer. 1- x Ge x A lightly doped layer (as the channel of the NMOS), such as Figure 2 As shown;

[0095] 3) LPCVD deposition of 20nm Si3N4 was used as the etching hard mask material. The shape and size of the active region were defined through photolithography and anisotropic etching, such as... Figure 3 As shown;

[0096] 4) Active regions are formed through anisotropic etching, such as... Figure 4 As shown;

[0097] 5) Shallow Trench Isolation (STI) of SiO2 is formed using a disclosed process, such as... Figure 5 As shown;

[0098] 6) A 20nm Si3N4 layer is deposited using LPCVD as a hard mask material. Vertical channels (6nm diameter cylinders) are formed through photolithography and anisotropic etching, exposing the heavily doped active region of the N / PMOS transistor in the unprotected areas of the photoresist. Figure 6 As shown;

[0099] 7) 300nm SiO2 was deposited via PECVD, planarized by CMP, and then etched back to form a 20nm thick bottom gate isolation dielectric, such as... Figure 7 As shown;

[0100] 8) Amorphous Si is deposited via PECVD, planarized by CMP, and then etched back to form a 25nm dummy gate layer, such as... Figure 8 As shown

[0101] 9) Remove the Si3N4 hard mask by etching with concentrated phosphoric acid;

[0102] 10) The dummy gate is patterned by photolithography etching, exposing the underlying gate isolation dielectric in the unprotected areas of the photoresist. Figure 9 As shown;

[0103] 11) SiO2 is deposited by PECVD, planarized by CMP, and then etched back to form the top gate isolation dielectric, such as... Figure 10 As shown;

[0104] 12) Define the top-level source / drain epitaxial window of the NMOS through photolithography etching, such as... Figure 11 As shown;

[0105] 13) Epitaxial growth of Si through in-situ doping 1-x Ge x The heavily doped top-layer source / drain forms the NMOS, wherein the Ge content of the top-layer source / drain is...

[0106] It can be inconsistent with the underlying source and drain to achieve asymmetric stress distribution in the device, such as... Figure 12 As shown;

[0107] 14) Deposit Si3N4 and pattern it to form a mask to protect the top layer source and drain of the NMOS;

[0108] 15) Define the top-level source / drain epitaxial window of the PMOS through photolithography etching, such as... Figure 13 As shown

[0109] 16) Forming heavily doped top-layer source / drain PMOS through in-situ doping of epitaxial Si, such as... Figure 14 As shown;

[0110] 17) 100 nm SiO2 is deposited by PECVD, and then planarized by CMP to form an interlayer dielectric, such as... Figure 15 As shown;

[0111] 18) Define the window for dummy gate removal through photolithographic etching, such as... Figure 16 As shown;

[0112] 19) Selective removal of amorphous silicon dummy gates via TMAH, such as... Figure 17 As shown;

[0113] 20) HfO2, NMOS WFM, and PMOS WFM are deposited sequentially via ALD, such as... Figure 18 As shown;

[0114] 21) 200 nm SiO2 was deposited by PECVD, and then planarized by CMP to form an interlayer dielectric, such as... Figure 19 As shown;

[0115] 22) Contact holes at the gate, source, drain, and body ends of the device are formed by photolithography and anisotropic etching, such as... Figure 20 As shown;

[0116] 23) Metal 0 is filled into each contact hole by sputtering;

[0117] 24) By performing CMP on the metal 0, the conductive layers between devices can be separated, achieving device isolation. Figure 21 As shown;

[0118] 25) The device integration will be completed according to the publicly available back-end process.

[0119] The embodiments of this invention are not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this invention, or modify them into equivalent embodiments, without departing from the scope of the invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this invention, without departing from the scope of the invention, shall still fall within the protection scope of this invention.

Claims

1. A method for integrating asymmetric stress-distributed vertical channel nanowire transistors, characterized in that, Includes the following steps: A. NMOS and PMOS single crystal materials are epitaxially formed on a substrate, including a stack of NMOS and PMOS bottom source / drain materials and lightly doped channel materials; the heavily doped active region is the source or drain end below the vertical channel nanowire transistor; the lattice constant of the heavily doped active region material in NMOS is greater than that of the lightly doped channel layer, and the lattice constant of the heavily doped active region material in PMOS is less than that of the lightly doped channel layer; uniaxial stress in the vertical direction is generated in the lightly doped channel layer through lattice mismatch; B. Isolation is formed between NMOS and PMOS devices in the active layer; C. Vertical channels are formed through graphical representation; D. Deposit a layer of medium to form a bottom barrier isolation medium; E. Deposit a layer of dummy gate material and pattern it to form a dummy gate pattern; F. Deposit a layer of dielectric material to form the top layer of barrier dielectric material; G. The top gate isolation dielectric is patterned and the top source drain is formed by epitaxy. In NMOS, the lattice constant of the top source drain material is greater than that of the lightly doped channel layer, while in PMOS, the lattice constant of the top source drain material is less than that of the lightly doped channel layer. At the same time, in order to achieve the asymmetric distribution of stress in the device channel and the control of channel stress, the lattice constant of the top source drain material is different from that of the bottom source drain material, so as to ensure that uniaxial stress in the vertical direction is generated in the channel layer through lattice mismatch. H. The dummy gate is removed and a gate oxide layer and a metal gate are formed; I. Forming metal contacts at each end of the device; J. Complete device integration according to back-end processes.

2. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 1, characterized in that, Step A specifically includes: A1. By covering the PMOS region with a hard mask material, a layer of semiconductor material is selectively epitaxially grown to form an N-type heavily doped active region; A2. An epitaxial layer of semiconductor material is grown to form a lightly doped P-type region, the thickness of which defines the channel length of the N-type device; A3. Remove the hard mask from the PMOS region and cover the NMOS region with the hard mask material; A4. Selectively epitaxially grow a layer of semiconductor material to form a heavily doped P-type active region; A5. An epitaxial layer of semiconductor material is grown to form a lightly doped N-type region, the thickness of which defines the channel length of the P-type device; The semiconductor material mentioned in steps A1, A2, A4, and A5 has a single-crystal structure.

3. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 2, characterized in that, Step C specifically includes the following steps: C1. Deposit a layer of dielectric material as a hard mask material for etching, to protect the channel pattern during multiple etching processes; C2. The channel is defined by photolithography, and its size and shape determine the size and shape of the device channel cross-section; C3. Hard mask patterns are formed by anisotropic etching, exposing lightly doped regions in areas not protected by photoresist. C4. Vertical channels are formed by anisotropic etching, exposing the heavily doped active region at the bottom of the unprotected area of ​​the photoresist.

4. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 1, characterized in that, Step D specifically includes: D1. Deposition medium material; D2. Achieving dielectric surface planarization through CMP; D3. The dielectric is etched back below the channel layer through anisotropic etching. The size below the lower surface of the channel layer is the size of the over-coverage area of ​​the device gate to the source and drain.

5. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 1, characterized in that, Step E specifically includes: E1. Deposit a layer of pseudogate material; E2. Surface planarization is achieved through CMP; E3. The material is etched back below the hard mask surface through anisotropic etching, while above the lightly doped channel layer surface. The remaining thickness of the dummy gate layer defines the device gate length. E4. Remove hard mask; E5. A dummy gate pattern is formed by photolithography, and the pattern determines the gate lead-out pattern of the device; E6. The dummy gate material not protected by photoresist is removed by anisotropic etching, exposing the bottom gate isolation medium.

6. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 1, characterized in that, Step F specifically includes: F1. A dielectric layer is formed by depositing a dielectric material, which is the same material as the bottom gate isolation medium described in step D, and its thickness is greater than the height of the dummy gate pattern; F2. Achieving surface planarization of the dielectric layer through CMP; F3. The thickness of the dielectric layer is reduced by anisotropic etching, and its thickness meets the requirements of the isolation gate and source / drain.

7. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 1, characterized in that, Step G specifically includes: G1. Define the top-level source / drain epitaxial window using photolithography, and align the photolithographic pattern with the underlying channel pattern; G2. Anisotropic etching is used to form the top-level source / drain epitaxial windows, exposing the underlying lightly doped channel layer; G3. Selective epitaxial growth forms a top heavily doped source / drain, wherein the top source / drain material is a single crystal structure.

8. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 1, characterized in that, Step H specifically includes: H1. Deposit a dielectric layer with a thickness greater than the epitaxial height of the top source / drain layer; H2. A window is defined using photolithography and anisotropic etching to expose the underlying dummy gate layer; H3. Removal of dummy gate material by isotropic etching; H4. By isotropically conformally filling the gate oxide layer material and the metal gate material, the voids formed after the removal of the dummy gate in step H3 are completely filled. H5. Remove the metal gate material and gate oxide layer material grown on top of the dielectric in step H1 by anisotropic etching.

9. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 1, characterized in that, Step I specifically includes: I1. Deposit a dielectric layer as an interlayer isolation layer and achieve planarization through CMP; I2. Contact holes at each end of the device are formed by photolithography and anisotropic etching; I3. Each contact hole is filled with Metal 0; I4. By performing CMP on the metal 0, the conductive layers between devices can be separated, achieving the effect of device isolation.

10. The integration method of the asymmetric stress distribution vertical channel nanowire transistor as described in claim 1, characterized in that, The substrate is a bulk silicon substrate, an SOI substrate, a bulk germanium substrate, or a GOI substrate.

Images