Silicon carbide MOSFET devices and their fabrication methods

Abstract

This application discloses a silicon carbide MOSFET device and its fabrication method. The silicon carbide MOSFET has a first withstand voltage masking structure and a second withstand voltage masking structure, which improves the withstand voltage performance of the device, avoids the problem of gate insulating dielectric layer breakdown, improves the device's resistance to electrostatic effects in harsh environments and high voltage spikes in the circuit, and improves the device's surge voltage resistance and overvoltage protection capability. Furthermore, the first withstand voltage masking structure can be formed by ion implantation based on the first trench, and the second withstand voltage masking structure can be formed by ion implantation through the second trench. A large depth of ion implantation region in the silicon carbide epitaxial layer can be achieved without high-dose, high-energy ion implantation. The fabrication process is simple and the fabrication cost is low.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a silicon carbide MOSFET device and its fabrication method. Background Technology

[0002] Due to its excellent properties, SiC material is highly attractive for high-power applications, making it one of the ideal materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFETs and UMOSFETs with vertical gate trench structures.

[0003] like Figure 1 As shown, Figure 1 This is a schematic diagram of a DMOSFET structure, including: an N+ (heavily N-type doped) substrate 2; an N- (lightly N-type doped) drift region 3 disposed on the surface of the substrate 2; a P-type well region 4 located within the drift region 3; and a source region 5 located within the P-type well region. The source region 5 includes an N+ doped region 51 and a P+ (heavily P-type doped) doped region 52, with source electrodes 6 disposed on the surfaces of the N+ doped region 51 and the P+ doped region 52. A gate dielectric layer 7 is disposed on the surface of the drift region 3, and a gate electrode 8 is disposed on the surface of the gate dielectric layer 7. A drain electrode 1 is disposed on the surface of the substrate 2 opposite to the drift region 3.

[0004] The DMOSFET structure employs planar diffusion technology, using a refractory material, such as a polysilicon gate, as a mask. The edges of the polysilicon gate define the P-type base region and the N+ source region. The name DMOS originates from this double-diffusion process. The surface channel region is formed by utilizing the lateral diffusion difference between the P-type base region and the N+ source region.

[0005] like Figure 2 As shown, Figure 2 This is a schematic diagram of a UMOSFET structure, and Figure 1 The difference in the structure shown is that the UMOSFET has a U-shaped trench, the surface of which is covered by a gate dielectric layer 7, and the gate 8 is filled within the U-shaped trench. The vertical gate trench structure of the UMOSFET derives its name from the U-shaped trench structure. This U-shaped trench structure is formed in the gate region using reactive ion etching. The U-shaped trench structure has a high channel density (channel density is defined as the active region channel width), which significantly reduces the on-state characteristic resistance of the device.

[0006] After years of research in the industry, some manufacturers have already launched commercial products of planar SiC MOSFETs. For the conventional lateral DMOSFET structure, modern technological advancements have reached a point where shrinking the MOSFET cell size no longer reduces the on-resistance. This is mainly due to the limitation of the JFET neck resistance; even with smaller photolithography dimensions, it is difficult to reduce the on-resistance per unit area to 2 mΩ·cm.2 A trench structure can effectively solve this problem. A U-shaped trench structure, such as... Figure 2 As shown, it employs trench etching technology in the manufacturing process of memory storage capacitors, changing the conductive channel from horizontal to vertical. Compared with the ordinary structure, it eliminates the neck resistance of JFET, greatly increases the cell density, and improves the current handling capability of power semiconductors.

[0007] However, several problems still exist in the actual fabrication and application of SiC UMOSFETs:

[0008] 1) The high electric field in the SiC drift region leads to a very high electric field on the gate insulating dielectric layer. This problem is exacerbated at the slot corner, resulting in rapid breakdown of the gate insulating dielectric layer under high drain voltage. It also has poor electrostatic effects in harsh environments and poor tolerance to high voltage spikes in the circuit.

[0009] 2) Since SiC power MOSFETs are mainly used in high-voltage, high-frequency, and high-current applications, parasitic parameters in the circuit can cause spikes and glitches during high-frequency switching, such as... Figure 3 As shown, Figure 3 The waveforms show the voltage overshoot and oscillation phenomena during MOSFET switching, based on... Figure 3 It is known that instantaneous overvoltage in the current path of a device increases the losses during the switching process; or large surge voltages are generated due to changes in power load, etc. Therefore, the surge voltage resistance and overvoltage protection of MOSFETs are also very important.

[0010] Because conventional MOSFET devices do not inherently possess surge voltage suppression or overvoltage protection capabilities, complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits are often required in practical applications. However, these externally matched suppression and overvoltage protection circuits often have a time delay; the high-frequency spike voltage surges during actual switching processes are still absorbed by the device itself. This can sometimes lead to breakdown failure in the device's channel region, as well as gradual failure of the gate structure and electrode ohmic contact areas, causing device reliability issues.

[0011] 3) Limited ion implantation depth makes it difficult to implement many targeted trench gate protection structures and surge protection designs from a manufacturing process perspective. Generally, the trench depth used to form the gate is 1μm-2μm or more, because protecting the gate structure within the trench is crucial. The actual fabrication process for buried protection structures cannot be directly completed using ion implantation, as the ion implantation depth in silicon carbide processes is difficult to exceed 1μm. Existing technologies typically involve first forming the desired doped region within a pre-formed epitaxial layer through etching and ion implantation, and then forming two P-type epitaxial layers with specific structures. This results in a complex manufacturing process and high manufacturing costs. Summary of the Invention

[0012] In view of this, this application provides a silicon carbide MOSFET device and a method for fabricating the same, as follows:

[0013] A silicon carbide MOSFET device, comprising:

[0014] A silicon carbide epitaxial layer having a first surface and a second surface opposite to each other, with a buried layer between the first surface and the second surface; the first surface includes a gate region and source regions located on both sides of the gate region;

[0015] A first trench located in the gate region and a trench gate located in the first trench; the first trench is located on the side of the buried layer opposite to the second surface and has a gap with the buried layer;

[0016] A second trench located within the source region and a trench source located within the second trench;

[0017] The first pressure-resistant shielding structure is located within the silicon carbide epitaxial layer at the bottom of the first trench and is spaced apart from the buried layer.

[0018] The second pressure-resistant shielding structure is located within the silicon carbide epitaxial layer on the surface of the second trench and is in contact with the buried layer.

[0019] Preferably, in the silicon carbide MOSFET device described above, the buried layer has a first ion implantation region formed based on the first trench; the first ion implantation region penetrates the buried layer and has a gap with the first voltage-resistant shielding structure.

[0020] Preferably, in the above-mentioned silicon carbide MOSFET device, the first trench is a single-level trench, and the width of the first ion implantation region is smaller than the width of the single-level trench;

[0021] The width of the first pressure-resistant shielding structure is smaller than the width of the single-stage trench.

[0022] Preferably, in the above-described silicon carbide MOSFET device, the depth of the first trench is less than the depth of the second trench;

[0023] There is a well region between the first trench and the second pressure-resistant shielding structure, and the depth of the well region is less than the depth of the first trench;

[0024] The silicon carbide epitaxial layer on the side of the well region away from the second surface is a second ion implantation region with a doping type opposite to that of the well region.

[0025] Preferably, in the above-mentioned silicon carbide MOSFET device, the second trench is a multi-level stepped trench;

[0026] The second pressure-resistant masking structure is a third ion implantation region formed based on the multi-level stepped trenches. The third ion implantation region is located at the bottom of the multi-level stepped trenches, on the sidewalls of each level of trenches, and in the silicon carbide epitaxial layer of the steps between adjacent trenches.

[0027] Preferably, in the above-described silicon carbide MOSFET device, the bottom of the second trench is located on the side of the buried layer away from the second surface, and has a gap with the buried layer;

[0028] At least a portion of the second pressure-resistant shielding structure is located within the buried layer.

[0029] Preferably, in the silicon carbide MOSFET device described above, at least a portion of the second trench is located within the buried layer.

[0030] Preferably, in the above-described silicon carbide MOSFET device, the trench gate comprises polysilicon filling the first trench, and a metal gate is disposed on the surface of the polysilicon.

[0031] The trench source includes polysilicon filled in the second trench, and a metal source electrode is disposed on the surface of the polysilicon.

[0032] An insulating dielectric layer is provided between the first trench and the polysilicon filled therein, and between the second trench and the polysilicon filled therein, and the insulating dielectric layer also covers the first surface;

[0033] The insulating dielectric layer covering the first surface has an opening that exposes a portion of the first surface for providing an ohmic contact layer, and the metal source electrode covers the ohmic contact layer.

[0034] Preferably, in the above-described silicon carbide MOSFET device, a silicon carbide substrate is disposed opposite to the second surface, and a metal drain is disposed on the side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0035] This application also provides a method for fabricating the silicon carbide MOSFET device described in any one of the above claims, comprising:

[0036] An epitaxial wafer is provided, the epitaxial wafer including a silicon carbide epitaxial layer having a first surface and a second surface opposite to each other, and a buried layer between the first surface and the second surface; the first surface includes a gate region and source regions located on both sides of the gate region;

[0037] A first trench is formed in the gate region, and a second trench is formed in the source region; the first trench is located on the side of the buried layer opposite to the second surface and has a gap with the buried layer;

[0038] Based on the first trench, a first voltage-resistant masking structure is formed within the silicon carbide epitaxial layer; based on the second trench, a second voltage-resistant masking structure is formed within the silicon carbide epitaxial layer; the first voltage-resistant masking structure has a gap with the buried layer; the second voltage-resistant masking structure is in contact with the buried layer.

[0039] A trench gate is formed in the first trench, and a trench source is formed in the second trench.

[0040] Preferably, in the above manufacturing method, before forming the first voltage-resistant shielding structure and the second voltage-resistant shielding structure, the method further includes:

[0041] Ion implantation is performed on the buried layer based on the first trench, forming a first ion implantation region in the region of the buried layer corresponding to the first trench;

[0042] The first ion implantation region penetrates the buried layer and has a gap between it and the first pressure-resistant shielding structure.

[0043] Preferably, in the above manufacturing method, forming a first trench in the gate region and forming a second trench in the source region includes:

[0044] A first-stage trench is formed in the source region by the first etching process;

[0045] A single-level trench is formed in the gate region by a second etching, and a second-level trench is formed based on the first-level trench.

[0046] The etching window of the second etching is larger than that of the first etching. While increasing the depth of the first-level trench, a second-level trench is formed based on the first trench. The first trench includes the single-level trench. The second trench is a double-step trench, including the first-level trench and the second-level trench.

[0047] Preferably, the above manufacturing method further includes:

[0048] A well region and a second ion implantation region with the opposite doping type to the well region are formed within the first surface;

[0049] The well region is located between the first trench and the second pressure-resistant shielding structure; the depth of the well region is less than the depth of the first trench.

[0050] Preferably, in the above manufacturing method, the first surface has an electric field buffer surrounding the second trench;

[0051] Based on the first trench, a first voltage-resistant masking structure is formed within the silicon carbide epitaxial layer; based on the second trench, a second voltage-resistant masking structure is formed within the silicon carbide epitaxial layer, including:

[0052] A mask layer is formed, which covers the first surface and the sidewalls of the first trench;

[0053] Based on the mask layer, ion implantation is performed to form the first voltage-resistant masking structure in the silicon carbide mask layer at the bottom of the first trench, and the second voltage-resistant masking structure is formed on the sidewall and bottom of the second trench.

[0054] The electric field buffer region surrounds the second voltage-resistant shielding structure.

[0055] Preferably, in the above manufacturing method, forming a trench gate in the first trench and forming a trench source in the second trench includes:

[0056] An insulating dielectric layer is formed, which covers the first surface and the surface of the first trench and the surface of the second trench;

[0057] The first trench and the second trench are filled with polysilicon; the trench gate includes polysilicon filled in the first trench, and a metal gate is disposed on the surface of the polysilicon; the trench source includes polysilicon filled in the second trench, and a metal source is disposed on the surface of the polysilicon.

[0058] As described above, the silicon carbide MOSFET device and its fabrication method provided in this application have a first withstand voltage masking structure and a second withstand voltage masking structure, which improves the withstand voltage performance of the device, avoids the breakdown problem of the gate insulating dielectric layer, improves the device's resistance to electrostatic effects in harsh environments and high voltage spikes in the circuit, and improves the device's surge voltage resistance and overvoltage protection capability. Furthermore, the first withstand voltage masking structure can be formed by ion implantation based on the first trench, and the second withstand voltage masking structure can be formed by ion implantation through the second trench. A large depth of ion implantation region in the silicon carbide epitaxial layer can be achieved without high-dose, high-energy ion implantation, resulting in a simple fabrication process and low manufacturing cost. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0060] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0061] Figure 1 This is a schematic diagram of a DMOSFET structure;

[0062] Figure 2 This is a schematic diagram of a UMOSFET structure;

[0063] Figure 3 Waveforms showing voltage overshoot and oscillation during MOSFET switching;

[0064] Figure 4 This is a schematic diagram of the structure of a silicon carbide MOSFET device provided in an embodiment of this application;

[0065] Figure 5 This is a schematic diagram of another silicon carbide MOSFET device provided in an embodiment of this application;

[0066] Figures 6-27 This is a process flow diagram of a method for fabricating a silicon carbide MOSFET device provided in an embodiment of this application. Detailed Implementation

[0067] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0068] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0069] refer to Figure 4 As shown, Figure 4 This application provides a schematic diagram of the structure of a silicon carbide MOSFET device, which includes:

[0070] A silicon carbide epitaxial layer 11 has a first surface and a second surface opposite to each other, and a buried layer 12 is provided between the first surface and the second surface; the first surface includes a gate region and source regions located on both sides of the gate region.

[0071] A first trench 13 located in the gate region and a trench gate g located in the first trench 13; the first trench 13 is located on the side of the buried layer 12 away from the second surface and has a gap with the buried layer 12;

[0072] The second trench 14 located in the source region and the trench source s located in the second trench 14;

[0073] The first pressure-resistant shielding structure 15 is located within the silicon carbide epitaxial layer 11 at the bottom of the first trench 13 and has a distance from the buried layer 12;

[0074] The second pressure-resistant shielding structure 16 is located within the silicon carbide epitaxial layer 11 on the surface of the second trench 14 and is in contact with the buried layer 12.

[0075] An insulating dielectric layer 17 is provided between the trench gate g and the first trench 13. The first withstand voltage shielding structure 15 is located within the surface of the bottom of the first trench 13 and has no gap with the bottom of the first trench 13, so as to achieve a better protection effect for the insulating dielectric layer 17 on the surface of the first trench 13.

[0076] The silicon carbide MOSFET has a first withstand voltage masking structure 15 and a second withstand voltage masking structure 16, which improves the withstand voltage performance of the device, avoids the breakdown problem of the gate insulating dielectric layer 17, improves the device's resistance to electrostatic effects in harsh environments and high voltage spikes in the circuit, and improves the device's surge voltage resistance and overvoltage protection capability. The first withstand voltage masking structure 15 can be formed by ion implantation based on the first trench 13, and the second withstand voltage masking structure 16 can be formed by ion implantation through the second trench 14. A large depth of ion implantation region in the silicon carbide epitaxial layer can be achieved without high-dose, high-energy ion implantation, which simplifies the fabrication process and reduces the manufacturing cost.

[0077] The silicon carbide epitaxial layer 11 includes a first epitaxial layer 111 and a second epitaxial layer 112 disposed opposite to each other, and the buried layer 12 is located between the first epitaxial layer 111 and the second epitaxial layer 112. The surface of the first epitaxial layer 111 facing away from the second epitaxial layer 112 is the second surface. The surface of the second epitaxial layer 112 facing away from the first epitaxial layer 111 is the first surface.

[0078] The silicon carbide MOSFET device has a silicon carbide substrate 10 disposed opposite to the second surface, and a metal drain D is disposed on the side of the silicon carbide substrate 10 away from the silicon carbide epitaxial layer 11.

[0079] The buried layer 12 has a first ion implantation region 21 formed based on the first trench 13; the first ion implantation region 21 penetrates the buried layer 12 and has a gap with the first pressure-resistant shielding structure 15.

[0080] In the silicon carbide MOSFET device, a first ion implantation region 21 is formed in the buried layer 12, and the first ion implantation region 21 is spaced from the first breakdown voltage masking structure 15 below the trench gate g. The first ion implantation region 21 penetrates the entire buried layer 12, forming the main current path of the device. This introduces a JFET structure into the drain current path of the device, and the conduction characteristics of the JFET structure are optimized and adjusted by the pattern design of the first ion implantation region 21 and the ion implantation concentration and pattern contour. This design and process flexibility results in good manufacturability.

[0081] In the silicon carbide MOSFET device, the depth of the first trench 13 is less than the depth of the second trench 14, so as to realize a second breakdown voltage masking structure 16 with deeper ion implantation. Furthermore, the second breakdown voltage masking structure 16 and the buried layer 12 can be connected to form reverse breakdown voltage protection for the bottom and corners of the trench gate, thereby achieving a highly reliable trench-type MOSFET device. A well region W is formed between the first trench 13 and the second breakdown voltage masking structure 16, and the depth of the well region W is less than the depth of the first trench 13. The silicon carbide epitaxial layer 11 on the side of the well region W facing away from the second surface is a second ion implantation region 18 with a doping type opposite to that of the well region W. The well region W is located on both sides of the first trench 13 and is in contact with the sidewalls of the first trench 13.

[0082] In this embodiment, the silicon carbide substrate 10 can be an N+ doped silicon carbide substrate; the silicon carbide epitaxial layer 11 can be an N- doped epitaxial layer, that is, both the first epitaxial layer 111 and the second epitaxial layer 112 are N- doped epitaxial layers; the first breakdown voltage masking structure 15 and the second breakdown voltage masking structure 16 are both P+ doped ion implantation regions; the well region W can be a P-doped ion implantation region; and the second ion implantation region 18 can be an N+ doped ion implantation region. It should be noted that in this embodiment, the doping type of each region of the device is not limited to that described in the embodiments, and its doping type can be set according to requirements to form a PMOS or NMOS structure.

[0083] In this design, the first trench 13 is a single-level trench, and the width of the first ion implantation region 21 is smaller than the width of the single-level trench; the width of the first voltage-resistant masking structure 15 is also smaller than the width of the single-level trench. The first voltage-resistant masking structure 15 needs to be positioned between the trench gate and the buried layer 12, with a gap between the first voltage-resistant masking structure 15 and the buried layer 12 to form a JFET structure in the silicon carbide MOSFET device. Therefore, the implantation depth of the first voltage-resistant masking structure 15 does not need to be large; a single-level trench with a smaller depth as the first trench 13 is sufficient to meet the implantation depth requirement of the first voltage-resistant masking structure 15. This results in a simple fabrication process and lower manufacturing costs.

[0084] The second trench 14 is a multi-level stepped trench; wherein, the second pressure-resistant masking structure 16 is a third ion implantation region formed based on the multi-level stepped trench, which is located at the bottom of the multi-level stepped trench, on the sidewalls of each level of the trench, and within the silicon carbide epitaxial layer of the steps between adjacent trenches. To achieve the connection between the second pressure-resistant masking structure 16 and the buried layer 12, a second pressure-resistant masking structure 16 with a relatively large depth is required. Using a multi-level stepped trench as the second trench 14 eliminates the need for high-dose, high-energy ion implantation, thus allowing the fabrication of a relatively deep second pressure-resistant masking structure 16 within the silicon carbide epitaxial layer 11.

[0085] Optionally, the multi-level stepped trench is a double-level stepped trench. Generally, for a silicon carbide epitaxial wafer including a silicon carbide substrate 10 and a silicon carbide epitaxial layer 11, the depth of the buried layer 12 is generally around 2 μm, and the depth of the first trench 12 used to prepare the trench gate is generally around 1 μm. By using a double-level stepped trench as the second trench 14, the ion implantation depth requirement of the second breakdown voltage masking structure 16 can be met without high-dose, high-energy ion implantation, and the lattice structure of silicon carbide will not be damaged.

[0086] exist Figure 4 In the illustrated configuration, the bottom of the second trench 14 is located on the side of the buried layer 12 opposite to the second surface and is spaced from the buried layer 12; at least a portion of the second voltage-resistant shielding structure 16 is located within the buried layer 12, such that the second voltage-resistant shielding structure 16 is connected to the buried layer, thereby achieving a better protection effect for the trench gate. In this case, it can be done as follows: Figure 4 As shown, the bottom of the second pressure-resistant shielding structure 16 is located inside the buried layer 12, or the bottom of the second pressure-resistant shielding structure 16 is located below the buried layer 12.

[0087] refer to Figure 5 As shown, Figure 5This is a schematic diagram of another silicon carbide MOSFET device provided in an embodiment of this application, and... Figure 4 The difference in the device shown is that, Figure 5 In the illustrated configuration, at least a portion of the second trench 14 is located within the burial layer 12. At this time, as... Figure 5 As shown, the bottom of the second pressure-resistant shielding structure 16 is located within the buried layer 12.

[0088] Ion implantation is performed based on the second trench 14 to form the second pressure-resistant masking structure 16, and the bottom of the second pressure-resistant masking structure 16 can be as follows: Figure 4 As shown, it is located within the buried layer 12, or as... Figure 5 As shown, it is located below the burial layer 12. The depth of the bottom of the second trench 14 relative to the burial layer 12 can be set according to requirements, such as... Figure 4 As shown, the bottom of the second trench 14 is positioned above the burial layer 12, or as shown in the diagram. Figure 5 As shown, the bottom of the second trench 14 is located inside the burial layer 12. In other configurations, the bottom of the second trench 14 may be located below the burial layer 12.

[0089] In the silicon carbide MOSFET device described in this application embodiment, the trench gate g includes polysilicon filled in the first trench 13, and a metal gate G is disposed on the surface of the polysilicon; the trench source s includes polysilicon filled in the second trench 14, and a metal source S is disposed on the surface of the polysilicon; an insulating dielectric layer 17 is provided between the first trench 13 and the polysilicon filled therein, and between the second trench 14 and the polysilicon filled therein, and the insulating dielectric layer 17 also covers the first surface; the insulating dielectric layer 17 covering the first surface has an opening exposing a portion of the first surface for disposing of an ohmic contact layer 20, and the metal source S covers the ohmic contact layer 20.

[0090] An electric field buffer zone 19 is disposed within the first surface, and the electric field buffer zone 19 surrounds the second trench 14. The electric field buffer zone 19 and the second breakdown voltage masking structure 16 can both be P+ doped regions. The electric field buffer zone 19 can solve the leakage and breakdown problems caused by the thinness of the second breakdown voltage masking structure 16 at the opening of the second trench 14, thereby enhancing the manufacturability and reliability of the device.

[0091] As described above, in the silicon carbide MOSFET device provided in this application embodiment, trench sources s are simultaneously integrated and constructed on both sides of the trench gate g through process design. The second trench 14 can be a two-stage stepped trench to form a dual-stage trench source. A second breakdown voltage masking structure 16 is formed by ion implantation in the silicon carbide epitaxial layer 11 at the bottom of the two-stage stepped trench, the sidewalls of each stage of the trench, and the steps of adjacent two-stage trenches. The bottom of the second withstand voltage masking structure 16 is located inside the buried layer 12, or the second withstand voltage masking structure 16 penetrates the buried layer 12, that is, the bottom of the second withstand voltage masking structure 16 is located below the buried layer 12, so that the second withstand voltage masking structure 16 contacts the buried layer 12, thereby grounding the second withstand voltage masking structure 16 (connecting the source), so that the JFET structure is introduced into the drain current path of the device. The second withstand voltage masking structure 16 constituting the JFET structure is not floating, but fully connected to the source, which can better perform the electric field masking of the bottom of the trench gate and enhance the surge self-suppression capability.

[0092] Furthermore, a first breakdown voltage masking structure 15 can be formed based on the first trench 13, and a second breakdown voltage masking structure 16 can be formed based on the second trench 14. This solves the problems of difficulty in forming deep P+ masking structures in silicon carbide materials and the damage and reliability issues caused by high-dose, high-energy P+ ion implantation. At the same time, it can better shield and protect the trench gate g. For the second breakdown voltage masking structure 16, if high-energy and high-dose ion implantation to a depth of 1um-2um or more is simply used, it is easy to cause severe ion implantation damage to the silicon carbide material, causing reliability problems in the long-term operation of subsequent devices. In this embodiment, the second breakdown voltage masking structure 16 can be formed based on the second trench 14, which can easily achieve the implantation of a P+ electric field masking structure with a depth of 1um-2um or more, forming the second breakdown voltage masking structure 16. This can effectively shield and protect the sidewalls and bottom of the trench gate g, enhancing the gate reliability of the silicon carbide trench MOSFET device.

[0093] The silicon carbide MOSFET device utilizes a design that forms a first ion implantation region 21 in the buried layer 12 of the epitaxial wafer. A dual-level trench-grounded JFET structure, modulated by the first ion implantation region 21, is intentionally introduced into the drain current path of the device. Under large surge voltages, it can automatically expand the depletion regions on both sides, thereby increasing the on-resistance of the JFET region, effectively acting as a buffer circuit to suppress surge spikes. Simultaneously, when the surge voltage is excessive, the depletion regions on both sides continue to expand and overlap, creating a blocking effect that protects the insulating dielectric layer 17 in the internal trench gate, providing a certain degree of overvoltage protection. Although the introduction of the JFET increases the on-resistance, it provides switching buffering and surge voltage self-suppression effects, increasing the device's self-suppression resistance to surge voltages and overvoltages. This avoids device damage and reliability reduction caused by time delays in the actual operation of overvoltage and overcurrent protection circuits. Furthermore, it can buffer spikes during circuit switching, reduce switching losses, reduce the number of buffer circuits / buffer circuits in circuit design, reduce discrete components, thereby reducing costs, reducing the actual module size, and enhancing reliability.

[0094] Based on the above embodiments, another embodiment of this application also provides a method for fabricating the silicon carbide MOSFET device described in the above embodiments, the fabrication method as follows: Figures 6-27 As shown.

[0095] refer to Figures 6-27 , Figures 6-27 A process flow diagram of a silicon carbide MOSFET device fabrication method provided in this application embodiment is shown. The fabrication method includes:

[0096] Step S11: As Figure 6 As shown, an epitaxial wafer is provided.

[0097] The epitaxial wafer includes a silicon carbide epitaxial layer 11, the silicon carbide epitaxial layer 11 having a first surface and a second surface opposite to each other, and a buried layer 12 between the first surface and the second surface; the first surface includes a gate region and source regions located on both sides of the gate region.

[0098] In this embodiment, a SiC epitaxial wafer with an N-type epitaxial layer is used. Specifically, the epitaxial wafer further includes a silicon carbide substrate 10, which is disposed opposite to the second surface. The silicon carbide epitaxial layer 11 includes a first epitaxial layer 111 and a second epitaxial layer 112 disposed opposite to each other, and the buried layer 12 is located between the first epitaxial layer 111 and the second epitaxial layer 112. The surface of the first epitaxial layer 111 facing away from the second epitaxial layer 112 is the second surface. The surface of the second epitaxial layer 112 facing away from the first epitaxial layer 111 is the first surface.

[0099] Step S12: As Figures 7-12 As shown, a first trench 13 is formed in the gate region and a second trench 14 is formed in the source region; the first trench 14 is located on the side of the buried layer 12 away from the second surface and has a gap with the buried layer 12.

[0100] Plasma dry etching processes, such as RIE or ICP etching, can be used to form the first trench 13 and the second trench 14. The etching principle of silicon carbide material is as follows: Figures 7-9 As shown. First, as Figure 7 As shown, SiO2 is deposited on silicon carbide material as a mask layer using deposition processes such as CVD. Photoresist (PR) is then spin-coated onto the mask layer surface. The desired pattern of the photoresist is formed through exposure and development. Then, as shown... Figure 8 As shown, based on the patterned photoresist PR, the mask layer is etched to form a patterned mask layer, and finally as... Figure 9 As shown, based on a patterned mask layer, silicon carbide material is etched to form trenches on its surface. Subsequent processes will not describe in detail the common semiconductor processes such as photolithography and etching.

[0101] In step S12, forming a first trench in the gate region and a second trench in the source region includes:

[0102] Step S121: As Figure 10 As shown, a first-stage trench 41 is formed in the source region through the first etching.

[0103] The first surface can be etched based on the mask layer 36 on the first surface to form the first-level trench 41. After the epitaxial wafer enters the production line, alignment marks need to be made for position alignment in subsequent photolithography processes. The technical solution of this application prepares the first-level trench 41 at the same time as the alignment marks are made, without the need to add a separate etching process. The etching process of the alignment marks is reused to prepare the first-level trench 41, which reduces the manufacturing cost.

[0104] CVD deposition of silicon dioxide can be used as a mask layer 36. Gases containing F groups such as CF4 and SF6, or gases containing Cl groups such as chlorine, or a mixture of Ar and oxygen can be used. ICP or RIE equipment is employed to etch the underlying SiC material in the areas of the epitaxial wafer requiring alignment markings and the source region, thus forming alignment marks. Figure 10 (The alignment mark is not shown in the image) and the first-stage trench 41. The depth of the first-stage trench 41 is 200nm-2um, which is determined according to the type of lithography machine and the requirements of the alignment mark type. Optionally, the depth of the first-stage trench 41 is 800nm.

[0105] Step S122: As Figure 11 and Figure 12 As shown, a single-level trench is formed in the gate region by a second etching, and a second-level trench is formed based on the first-level trench.

[0106] The etching window of the second etching is larger than that of the first etching. While increasing the depth of the first-level trench, a second-level trench is formed based on the first trench. The first trench 13 includes the single-level trench. The second trench 14 is a double-step trench, including the first-level trench and the second-level trench.

[0107] Before the second etching, the process includes: forming a well region W within the first surface and a second ion implantation region 18 with a doping type opposite to that of the well region W. The second ion implantation region 18 is located on the side of the well region W facing the first surface. An electric field buffer zone 19 surrounding a second trench 14 is also formed within the first surface by ion implantation. The well region W is located between the first trench 13 and the second breakdown voltage masking structure 16; the depth of the well region W is less than the depth of the first trench 13.

[0108] In step S122, first as Figure 11 As shown, after removing the mask layer 36, ion implantation is performed on the first surface to form the required electric field buffer zone 19, the second ion implantation region 18, and the well region W. High-temperature ion implantation equipment at 500℃-600℃ is generally used for SiC materials to reduce damage to the silicon carbide lattice structure caused by ion implantation. Then, as... Figure 12 As shown, a second etching is performed based on mask layer 25.

[0109] During the second etching, CVD deposition of silicon dioxide can be used as the etching mask 35. Gases containing F groups, such as CF4 and SF6, or gases containing Cl groups, such as chlorine, and a mixture of Ar and oxygen can be used. Plasma etching equipment such as ICP or RIE is employed to etch the underlying SiC material in the gate region and the source regions on both sides, forming a layer such as... Figure 12 The first trench 13 and the second trench 14 are shown. A single-level trench is formed in the gate region as the first trench 13; the depth of the first trench 13 is 300nm-2um, or optionally, the depth of the first trench 13 is 800nm-1um.

[0110] The etching mask 35 has a first opening in the region corresponding to the first trench 13 for forming the first trench 13, so as to etch the gate region based on the first opening to form the first trench 13. The etching mask 35 has a second opening in the region corresponding to the second trench for forming the second trench, so as to etch the source region based on the second opening to form the second trench 14 on the basis of the first trench.

[0111] During the second etching, in the source region, the second opening is larger than the opening of the first-stage trench 41, thus forming a two-stage stepped trench as the second trench 14. During this process, the bottom of the first-stage trench 41 will continue to be etched downwards, forming a total depth that is approximately equal to the sum of the depths of the two etchings. The end of the first-stage trench 41 facing the first surface is enlarged due to the second opening, forming a two-stage stepped trench.

[0112] In one approach, such as Figure 12 As shown, in the source region, the sum of the depths of the two etching operations can be set to be less than the distance between the buried layer 12 and the first surface, in order to fabricate materials such as... Figure 4 The silicon carbide MOSFET device shown is illustrated. The distance d1 between the bottom of the second trench 14 and the buried layer 12 is < 600 nm. In this method, during subsequent ion implantation to form the second breakdown voltage masking structure 16, the implantation energy and dose need to be sufficient to reach the buried layer 12 so that the second breakdown voltage masking structure 16 and the buried layer 12 are connected. This method is used to fabricate devices such as... Figure 4 The silicon carbide MOSFET device shown has a relatively uniform distribution of the highest electric field region in the buried layer 12 when the device is operating in reverse, and the device has good reverse withstand voltage performance.

[0113] Other methods include, for example Figure 13 As shown, in the source region, the sum of the depths of the two etching operations can be set to be greater than the distance between the lower surface of the buried layer 12 and the first surface, for fabrication such as... Figure 5 The silicon carbide MOSFET device shown is an example. Silicon dioxide can be deposited using CVD as the etching mask 35. Using F-based gases such as CF4 and SF6, or Cl-based gases such as chlorine, or a mixture of Ar and oxygen, plasma etching equipment such as ICP or RIE is employed to etch the SiC material in the gate region and the source regions on both sides, forming a structure as shown. Figure 13 The structure is shown. A single-level trench is formed in the gate region as the first trench 13, with a depth of 300 nm to 2 μm, optionally 800 nm to 1 μm. At this time, the second trench 14 penetrates the buried layer 12. The distance d2 between the bottom of the second trench 14 and the buried layer 12 is < 600 nm. In this method, during subsequent ion implantation to form the second withstand voltage masking structure 16, since the second trench 16 penetrates the buried layer 12, relative to... Figure 12 As shown, the connection between the second pressure-resistant masking structure 16 and the buried layer 12 requires only a relatively low injection dose and injection energy. This method is used to fabricate materials such as... Figure 5 The silicon carbide MOSFET device shown has its highest electric field strength region in the second breakdown voltage shielding structure 16 at the bottom of the second trench 14 when the device is operating in reverse. The area of ​​the region that withstands the highest electric field is determined by the width of the bottom of the second trench 14, relative to... Figure 4 As shown, the reverse withstand voltage performance is relatively low.

[0114] Step S13: As Figures 14-19 As shown, based on the first trench, a first voltage-resistant masking structure 15 is formed in the silicon carbide epitaxial layer 11, and based on the second trench, a second voltage-resistant masking structure 16 is formed in the silicon carbide epitaxial layer 11; the first voltage-resistant masking structure 15 has a gap with the buried layer 12; the second voltage-resistant masking structure 16 is in contact with the buried layer 12.

[0115] Before forming the first withstand voltage shielding structure 15 and the second withstand voltage shielding structure 16, the method further includes: Figure 14 As shown, ion implantation is performed on the buried layer 12 based on the first trench 13, forming a first ion implantation region 21 in the region of the buried layer 12 corresponding to the first trench 13. This first ion implantation region 21 penetrates the buried layer 12, and after the first pressure-resistant masking structure 15 is subsequently formed, there is a gap between the first ion implantation region 21 and the first pressure-resistant masking structure 15. A mask 34 is used to expose the first trench 13 and shield other areas of the first surface. The first ion implantation region 21 can be formed using a nitrogen ion source.

[0116] Ion implantation can be performed using a photoresist mask or a sampling silica-assisted hard mask. When using a photoresist mask, the photoresist can be directly spin-coated onto the first surface, and then implanted through a process such as... Figure 14 The mask 34 shown is used for photolithographic development of the bottom of the first trench 13. In the layout design of the mask 34, the opening of the mask 34 corresponding to the first trench 13 is smaller than the first trench 13.

[0117] The first surface has an electric field buffer 19 surrounding the second trench; based on the first trench 13, a first voltage-resistant masking structure 15 is formed within the silicon carbide epitaxial layer 11, and based on the second trench 14, a second voltage-resistant masking structure 16 is formed within the silicon carbide epitaxial layer 11, including:

[0118] Step S131: As Figures 15-17 As shown, a mask layer 32 is formed, which covers the first surface and the sidewalls of the first trench.

[0119] In step S131, firstly as follows Figure 15 As shown, a mask layer 32 is formed covering the first surface and filling the first trench 13 and the second trench 14. SiO2 can be deposited as the mask layer 32 via CVD. For example... Figure 16 As shown, a photolithography mask layer 33 is provided. The opening 331 of the photolithography mask layer 33 corresponding to the first trench 13 is smaller than the opening of the first trench 13, and the opening 332 of the photolithography mask layer 33 corresponding to the second trench 14 is larger than the opening of the second trench 14. Then as... Figure 17 As shown, photolithography is performed based on the photolithography mask layer 33. Dry etching can be used, and the mask layer 32 is etched based on the high selectivity of the SiO2:SiC etching gas.

[0120] Since the opening 331 is smaller than the opening of the first trench 13, a portion of the mask layer 32 can be reserved on the sidewall of the first trench 13. When ion implantation is performed to form the first breakdown voltage masking structure 15, the reserved portion of the mask layer 32 on the sidewall of the first trench 13 can prevent ion implantation on the sidewall of the first trench 13 due to ion scattering during ion implantation. This allows the first breakdown voltage masking structure 15 to be located below the well region W, preventing the first breakdown voltage masking structure 15 from contacting the well region W. This avoids the abnormal opening of the semiconductor device channel caused by this and ensures the normal operation of the device.

[0121] Since the opening 332 is larger than the opening of the second trench 14, part of the first surface around the opening of the second trench 14 can be exposed. When ion implantation is performed to form the second withstand voltage masking structure 16, the ion implantation area can cover the entire second trench 16. Thus, ion implantation can be performed at the bottom of the second trench 14, on the sidewalls of each level of trench, and in the silicon carbide epitaxial layer 11 of the steps between adjacent trenches to form the required second withstand voltage masking structure 16. This allows the second withstand voltage masking structure 16 to completely mask and protect the trench source when the final device is operating in reverse, avoiding large reverse leakage current.

[0122] Step S132: As Figure 18 As shown, based on the mask layer 32, ion implantation is performed to form the first voltage-resistant masking structure 15 within the silicon carbide mask layer 11 at the bottom of the first trench 13, and the second voltage-resistant masking structure 16 is formed on the sidewalls and bottom of the second trench 14; then, as... Figure 19 As shown, the mask layer 32 can be removed by a buffered HF wet method.

[0123] The electric field buffer region 19 surrounds the second voltage-resistant masking structure 16; both structures are identically doped and integrally connected. P+ type ion implantation is performed at 500℃-600℃ using a high-temperature ion implantation device to form the first voltage-resistant masking structure 15 and the second voltage-resistant masking structure 16. During P+ type ion implantation, Al ions are implanted. Optionally, the ion implantation energy can be several hundred keV, and the dose can be 1E12 cm⁻¹. -2 -1E16 cm -2 The injection depth is 100nm-500nm.

[0124] like Figure 20 As shown, Figure 20 SEM images of the first voltage-resistant masking structure 15 and the second voltage-resistant masking structure 16 after fabrication according to the embodiment of this application. The buried layer 12 is a silicon carbide P-type buried layer; the region corresponding to the first trench has an N-Enrich (N-type doped) ion implantation region as the first ion implantation region 21; SiO2 is disposed on the first surface of the epitaxial wafer as a mask layer 32; the second voltage-resistant masking structure 16 and the buried layer 12 have an overlapping portion to achieve the connection between the two.

[0125] like Figure 21 As shown, Figure 21 The images show SEM images of the source region before and after P+ ion implantation, using the fabrication method described in this application. Taking the second trench 14 as a two-stage stepped trench as an example, the left image is the SEM image of the region corresponding to the second trench 14 before P+ ion implantation, and the right image is the SEM image of the region corresponding to the second trench 14 after P+ ion implantation. The area with lower grayscale in the right image is the SEM slice image formed after Al ion implantation.

[0126] Step S14: As Figures 22-26 As shown, a trench gate g is formed in the first trench 13, and a trench source s is formed in the second trench 14.

[0127] In step S14, a trench gate g is formed in the first trench 13, and a trench source s is formed in the second trench 14, including:

[0128] Step S141: As Figure 22 As shown, an insulating dielectric layer 17 is formed, which covers the first surface and the surface of the first trench 13 and the surface of the second trench 14.

[0129] A trench gate oxide layer is grown under a high-temperature furnace tube as an insulating dielectric layer 17. Oxygen is introduced into the high-temperature furnace tube at 1100℃-1350℃ to grow SiO2 on the surface. The thickness of SiO2 is 40 nm-70 nm.

[0130] Step S142: As Figure 23 As shown, polysilicon 31 is filled in the first trench 13 and the second trench 14; the trench gate g includes polysilicon 31 filled in the first trench 13, and a metal gate G is disposed on the surface of the polysilicon 31; the trench source s includes polysilicon 31 filled in the second trench 14, and a metal source S is disposed on the surface of the polysilicon 31.

[0131] Polycrystalline silicon layers can be deposited using LPCVD technology to fill the first trench 13 and the second trench 14. Specifically, at 540℃-800℃, silane or DCS gas and Ar, as well as doped gases such as phosphine or borane containing phosphorus or boron, are introduced into the LPCVD furnace tube. Polycrystalline silicon is generated through a chemical pyrolysis reaction, and the thickness of the polycrystalline silicon can range from 400 nm to several μm. To facilitate the subsequent fabrication of metal electrodes, the process also includes:

[0132] Step S143: As Figure 24 As shown, polysilicon 31 is etched to remove polysilicon 31 from the surface of the insulating dielectric layer 17 outside the first trench 13 and the second trench 14, such that the polysilicon filled in the first trench 13 is slightly lower than the opening of the first trench 13, and the polysilicon filled in the second trench 14 is slightly lower than the second trench 14, to facilitate the subsequent formation of the metal source S and the metal gate G. A mixed gas of HBr, chlorine and oxygen can be used to etch the polysilicon.

[0133] Step S144: As Figure 25 As shown, an opening is formed on the insulating dielectric layer 17 outside the first trench 13 and the second trench 14. The opening can be formed by etching the insulating dielectric layer 17 using F-based gases such as CHF3 and CF4, or chlorine-based gases containing Cl, for subsequent fabrication of the ohmic contact layer 20.

[0134] Step S145: As Figure 26 As shown, an ohmic contact layer 20 is formed in the opening of the insulating dielectric layer 17. Specifically, a single layer of Ni or a Ti / Ni / Al stack is deposited by PVD in the opening of the insulating dielectric layer 17, and the metal except for the opening is stripped or etched away. Then, rapid thermal annealing is performed at 900℃-1100℃ for 30 seconds to 5 minutes to form the ohmic contact layer 20.

[0135] Finally, a metal gate G is formed on the surface of the trench gate g, a metal source S is formed on the surface of the trench source s, and a metal drain D is formed on the side of the silicon carbide substrate 10 facing away from the silicon carbide epitaxial layer 11, forming a structure as shown below. Figure 4The silicon carbide MOSFET device shown has a source metal S located on the polysilicon surface filling the second trench 14 and covered by a connecting ohmic contact layer 20. The metal drain D can be a stacked structure formed of one or more of Ni, Ti, Al, and Ag.

[0136] The subsequent metal processes for the gate and source, the passivation layer and polyimide (PI) adhesive, and the metal processes for the back drain are all conventional processes and will not be described in detail here.

[0137] like Figure 27 As shown, Figure 27 This application provides a layout of a silicon carbide MOSFET device in terms of trench design and ion implantation area in the doped region. The implantation window of the first ion implantation region 21 is located within the first trench 13. The channel characteristics of the JFET structure can be adjusted by the pattern design, ion implantation concentration, and pattern contour design of the first ion implantation region 21. The implantation window area of ​​the first ion implantation region 21 can be less than or equal to the area of ​​the first trench 13.

[0138] The above process flow is used to prepare Figure 4 The silicon carbide MOSFET device shown is used as an example for illustration. Based on this method, in other methods, as described above, by setting the depth of the second trench 14 after two etchings, its bottom is located within or through the buried layer 12. In this case, it is possible to fabricate a device like... Figure 5 The silicon carbide MOSFET device is shown. In this way, lower-energy P-type ion implantation can be used to connect the second breakdown voltage masking structure 16 to the buried layer 12, achieving modulation of the parasitic JFET structure in the current path; thus further reducing the requirements for device parameter design and fabrication.

[0139] As can be seen, the technical solution described in this application embodiment, through a clever process integration design, forms a second withstand voltage shielding structure 16 based on the second trench 14, connecting the second withstand voltage shielding structure 16 and the buried layer 12, grounding the second withstand voltage shielding structure 16, and combining the structural design of the epitaxial wafer and the first ion implantation region 21, solves the problems of shielding the gate insulating dielectric layer 17 in silicon carbide trench MOSFET devices and the P-type deep implantation process in silicon carbide materials. At the same time, a JFET structure can be introduced into the drain current path of the device, forming a two-stage trench-grounded JFET structure modulated by the first ion implantation region 21. While automatically adjusting the on-resistance and self-locking protection effect of the device, it can also maintain a small device cell size.

[0140] Based on the fabrication method described in this application, P+ ion implantation can be performed at a lower energy of less than 1 MeV, with an implantation depth not exceeding 1 μm. However, the buried layer 12, which is more than 1 μm deep from the first surface, can be grounded to the source. This application's technical solution, through a clever dual-trench dual-buried structure grounding process integration, and by forming a first ion implantation region 21 in the buried layer 12 of the epitaxial wafer, solves the challenges of shielding the gate insulating dielectric layer in SiC trench MOSFETs and deep P-type implantation in silicon carbide materials. Simultaneously, a dual-trench grounded JFET structure, modulated by the first ion implantation region 21, is deliberately introduced into the drain current path of the device. This automatically adjusts the device's on-resistance and self-locking protection effect while maintaining a small device cell size.

[0141] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0142] It should be noted that, in the description of this application, the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0143] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0144] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0145] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A silicon carbide MOSFET device, characterized in that, include: A silicon carbide epitaxial layer having a first surface and a second surface opposite to each other, with a buried layer between the first surface and the second surface; the first surface includes a gate region and source regions located on both sides of the gate region; A first trench located in the gate region and a trench gate located within the first trench; The first trench is located on the side of the buried layer away from the second surface and has a gap between it and the buried layer; A second trench located within the source region and a trench source located within the second trench; The first pressure-resistant shielding structure is located within the silicon carbide epitaxial layer at the bottom of the first trench and is spaced apart from the buried layer. The second pressure-resistant masking structure is located within the silicon carbide epitaxial layer on the surface of the second trench, and at least a portion of the second pressure-resistant masking structure is located within the buried layer; The buried layer has a first ion implantation region formed based on the first trench; The first ion implantation region penetrates the buried layer and has a gap between it and the first pressure-resistant shielding structure; The first trench is a single-stage trench, and the width of the first ion implantation region is smaller than the width of the single-stage trench; the width of the first pressure-resistant masking structure is smaller than the width of the single-stage trench.

2. The silicon carbide MOSFET device according to claim 1, characterized in that, The depth of the first trench is less than the depth of the second trench; There is a well region between the first trench and the second pressure-resistant shielding structure, and the depth of the well region is less than the depth of the first trench; The silicon carbide epitaxial layer on the side of the well region away from the second surface is a second ion implantation region with a doping type opposite to that of the well region.

3. The silicon carbide MOSFET device according to claim 1, characterized in that, The second trench is a multi-stage stepped trench; The second pressure-resistant masking structure is a third ion implantation region formed based on the multi-level stepped trenches. The third ion implantation region is located at the bottom of the multi-level stepped trenches, on the sidewalls of each level of trenches, and in the silicon carbide epitaxial layer of the steps between adjacent trenches.

4. The silicon carbide MOSFET device according to claim 1, characterized in that, The bottom of the second trench is located on the side of the buried layer away from the second surface and is spaced apart from the buried layer.

5. The silicon carbide MOSFET device according to claim 1, characterized in that, At least a portion of the second trench is located within the burial layer.

6. The silicon carbide MOSFET device according to claim 1, characterized in that, The trench gate includes polysilicon filled in the first trench, and a metal gate is disposed on the surface of the polysilicon. The trench source includes polysilicon filled in the second trench, and a metal source electrode is disposed on the surface of the polysilicon. An insulating dielectric layer is provided between the first trench and the polysilicon filled therein, and between the second trench and the polysilicon filled therein, and the insulating dielectric layer also covers the first surface; The insulating dielectric layer covering the first surface has an opening that exposes a portion of the first surface for providing an ohmic contact layer, and the metal source electrode covers the ohmic contact layer.

7. The silicon carbide MOSFET device according to claim 1, characterized in that, The silicon carbide substrate is disposed opposite to the second surface, and a metal drain is disposed on the side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

8. A method for fabricating a silicon carbide MOSFET device as described in any one of claims 1-7, characterized in that, include: An epitaxial wafer is provided, the epitaxial wafer including a silicon carbide epitaxial layer having a first surface and a second surface opposite to each other, and a buried layer between the first surface and the second surface; the first surface includes a gate region and source regions located on both sides of the gate region; A first trench is formed in the gate region, and a second trench is formed in the source region; The first trench is located on the side of the buried layer away from the second surface and has a gap between it and the buried layer; Based on the first trench, the first voltage-resistant masking structure is formed in the silicon carbide epitaxial layer, and based on the second trench, the second voltage-resistant masking structure is formed in the silicon carbide epitaxial layer. The first pressure-resistant shielding structure has a gap with the buried layer; At least a portion of the second pressure-resistant shielding structure is located within the buried layer; A trench gate is formed in the first trench, and a trench source is formed in the second trench; Before forming the first and second withstand voltage shielding structures, the method further includes: Ion implantation is performed on the buried layer based on the first trench, forming a first ion implantation region in the region of the buried layer corresponding to the first trench; The first ion implantation region penetrates the buried layer and has a gap with the first pressure-resistant shielding structure. The first trench is a single-stage trench, and the width of the first ion implantation region is smaller than the width of the single-stage trench; the width of the first pressure-resistant masking structure is smaller than the width of the single-stage trench.

9. The manufacturing method according to claim 8, characterized in that, A first trench is formed in the gate region, and a second trench is formed in the source region, including: A first-stage trench is formed in the source region by the first etching process; A single-level trench is formed in the gate region by a second etching, and a second-level trench is formed based on the first-level trench. The etching window of the second etching is larger than that of the first etching. While increasing the depth of the first-level trench, a second-level trench is formed based on the first trench. The first trench includes the single-level trench. The second trench is a double-step trench, including the first-level trench and the second-level trench.

10. The manufacturing method according to claim 8, characterized in that, Also includes: A well region and a second ion implantation region with the opposite doping type to the well region are formed within the first surface; The well region is located between the first trench and the second pressure-resistant shielding structure; the depth of the well region is less than the depth of the first trench.

11. The manufacturing method according to claim 8, characterized in that, The first surface has an electric field buffer surrounding the second trench; Based on the first trench, a first voltage-resistant masking structure is formed within the silicon carbide epitaxial layer; based on the second trench, a second voltage-resistant masking structure is formed within the silicon carbide epitaxial layer, including: A mask layer is formed, which covers the first surface and the sidewalls of the first trench; Based on the mask layer, ion implantation is performed to form the first voltage-resistant masking structure in the silicon carbide mask layer at the bottom of the first trench, and the second voltage-resistant masking structure is formed on the sidewall and bottom of the second trench. The electric field buffer region surrounds the second voltage-resistant shielding structure.

12. The manufacturing method according to claim 8, characterized in that, A trench gate is formed in the first trench, and a trench source is formed in the second trench, including: An insulating dielectric layer is formed, which covers the first surface and the surface of the first trench and the surface of the second trench; The first trench and the second trench are filled with polysilicon; the trench gate includes polysilicon filled in the first trench, and a metal gate is disposed on the surface of the polysilicon; the trench source includes polysilicon filled in the second trench, and a metal source is disposed on the surface of the polysilicon.

Images