System and Method for Verification and Characterization of VLSI Devices

Abstract

Test networks implemented using BEOL and / or MOL devices provide on-chip test probes that enable direct access to selected test points within the circuitry on a VLSI integrated circuit. The test network allows for direct application of inputs to the target test point and direct observation of outputs at the target test point, significantly improving the observability and controllability of the integrated circuit. Multiple test networks can be employed in the integrated circuit to enable independent and / or parallel testing of circuitry and / or functional blocks of the chip. Because the test circuits and networks are implemented using BEOL and / or MOL devices, they can be manufactured on layers of the integrated circuit stacked on top of the main circuitry, thus avoiding a significant increase in the chip's die area.

Description

[Technical Field]

[0001] The present invention relates to a system and method for testing semiconductor devices. More specifically, the present invention relates to a system and method for verifying and characterizing semiconductor devices such as VLSI circuits using one or more on-chip test probe networks. [Background technology]

[0002] Semiconductor device manufacturers refer to Moore's Law to explain the continuous decrease in the size of semiconductor components such as transistors and interconnects on integrated circuits, and the resulting increase in density. Moore's Law states that the number of transistors on an integrated circuit die (i.e., chip) doubles approximately every two years.

[0003] To achieve this increase in scale, many technological efforts are being made to reduce the size of the components that make up integrated circuits. For example, very large-scale integrated circuits ("VLSI") now have feature sizes of 7 nanometers or less. However, despite the significant reduction in component size, the overall size (i.e., die area) of many integrated circuits has still increased significantly, and the die size is growing as more features and performance are added to the chip.

[0004] For example, the Apple M1 processor currently used in some Apple devices reportedly has 11.8 billion transistors and a die size of approximately 120 square mm, while the Apple M1 Max processor reportedly has 57 billion transistors and a die size of approximately 490 square mm. Other advanced integrated circuits also have a similar or greater number of transistors and die size.

[0005] This combination of smaller components on larger dies presents numerous challenges for integrated circuit designers and manufacturers. In fact, a significant percentage of manufactured integrated circuits either fail to function properly or operate at the desired speed due to a variety of factors, including slight undesirable variations in the processes used to manufacture them, faulty designs, overly optimistic design rules employed in the software used to design the circuits, and errors by the circuit designers.

[0006] Consequently, the yield for manufacturing these integrated circuits (the percentage of manufactured integrated circuits that operate within specific acceptable parameters, determined by post-manufacturing testing) is typically lower than desired. For integrated circuits where the design is the limit of manufacturing technology, the yield can be far lower than desired. Lower yields mean reduced profits for manufacturers, and the supply of such advanced devices may fall below demand. As Moore's Law continues to push the limits of VLSI design further, inadequate testing and / or bottlenecks can hinder further practical improvements in chip density and performance.

[0007] To ensure they function correctly, all integrated circuits must be tested after manufacturing, and the basic purpose of this testing is to distinguish between good (functioning correctly) and defective (having one or more defects) integrated circuits.

[0008] There is a need for practical systems and methods for verifying and characterizing integrated circuits such as VLSI devices. [Overview of the project] [Problems that the invention aims to solve]

[0009] The object of the present invention is to provide a novel system and method for verifying and characterizing semiconductor devices, thereby eliminating or mitigating at least one drawback of the prior art. [Means for solving the problem]

[0010] A very large-scale integrated circuit (VLSI) semiconductor integrated circuit, comprising a main circuit (circuitry) designed to perform the required functions of the integrated circuit, at least one test network comprising transistors manufactured on a plane above the main circuit and manufactured by BEOL and / or MOL processes, wherein the transistors are selectively connectable by the test network to each selected node of the main circuit, and the test network connects each transistor to the corresponding node of the main circuit to form an on-chip test probe that is operable to enable the application of inputs and / or observation of outputs at the selected nodes.

[0011] Preferably, the semiconductor integrated circuit includes multiple test networks, each capable of operating to test different parts of the main circuit network.

[0012] A method for designing a VLSI semiconductor integrated circuit is provided, comprising: (i) designing a main network of the integrated circuit; (ii) determining a plurality of nodes corresponding to points in the main network to which it is desirable to apply test values ​​and / or read test outputs to verify the precise operation of each main network; and (iii) designing at least one test network to be manufactured on a plane above the main network to selectively connect to one of the determined nodes of the main network to enable the application of test signals to each node and / or receive test outputs from each node.

[0013] According to yet another aspect of the present invention, there is provided a VLSI semiconductor integrated circuit including a main circuit network implementing a desired function of an integrated circuit, and a test network fabricated on a plane above the main circuit network, the test network being operable to provide test probes to selected nodes of the main circuit network, apply test values thereto, and / or read test outputs therefrom. The present invention provides test networks and methods implemented using BEOL and / or MOL devices, which enable direct access to selected test points within circuits on an integrated circuit such as a VLSI chip when active, or provide on-chip test probes that are effectively removed from the circuit under test when inactive. The test network enables direct application of inputs to a target (of interest) test point and / or direct observation of outputs at the target test point, significantly improving the observability and controllability of the chip. A plurality of test networks can be employed on the chip to enable testing of circuits on the chip independently and / or in parallel. Since the test circuits and networks are implemented using BEOL and / or MOL devices, they can be fabricated on one or more layers of the chip laminated above the implemented main circuit network, on separate planes of the chip, and thus do not need to significantly increase the die area of the chip.

Brief Description of the Drawings

[0014] Here, preferred embodiments of the present invention will be described by way of example only with reference to the accompanying drawings.

[0015] [Figure 1] A plot showing the historical trend of the increase in the average number of transistors per pin in VLSI integrated circuits. [Figure 2] A schematic diagram of a cross-point array test network for testing main circuit network nodes, according to one aspect of the present invention. [Figure 3]It is a schematic diagram of a conventional test flow. [Figure 4] It is a block-level diagram of a test flow according to one aspect of the present invention. [Figure 5] It is a schematic diagram of a 32-bit counter. [Figure 6] It is a block diagram of the 32-bit counter of FIG. 5 when implemented according to one aspect of the present invention. [Figure 7] A block diagram of a built-in self-test (Built In Self-Test) system according to one aspect of the present invention is shown. [Figure 8] A block diagram of another configuration of a built-in self-test system according to one aspect of the present invention is shown.

Mode for Carrying Out the Invention

[0016] Prior to the integrated circuit not being relatively complex, functional tests were used to evaluate the characteristics of the integrated circuit and verify its operation. Since functional tests are closely related to the functions of the integrated circuit, when these tests can be used, they are relatively simple and straightforward. For example, a 4-bit binary counter can be comprehensively tested by applying 2 4 = 16 test vectors, where each "test vector" corresponds to one of the 16 possible inputs and the corresponding exact output, and by applying each test vector in order, the generated output is compared with the corresponding one of the expected "exact" outputs. However, as the complexity of the integrated circuit increases, the entire set of possible inputs and corresponding exact outputs increases exponentially, so such functional tests quickly become impractical.

[0017] For example, an integrated circuit having 32 inputs has a design complexity that is not so high by today's VLSI standards, but a comprehensive functional test requires 2 32This requires 4,294,967,296 test vectors. Even if these test vectors were applied at a rate of over one million test vectors per second, testing a single instance of this part of the integrated circuit would take well over an hour. Furthermore, as the integrated circuit includes sequential logic and / or as the amount of circuitry directly or indirectly connected to the input or output pins increases, the time required for testing becomes significantly longer and the complexity increases significantly. Therefore, due to their complexity, functional testing of VLSI circuits is clearly impractical.

[0018] Figure 1, taken from the International Technology Roadmap for Semiconductors, illustrates this complexity from a testing perspective. The figure shows that, on average, the number of transistors per input and output (IO) pins is increasing for microprocessors (MPUs) and application-specific integrated circuits (ASICs). The number of input and output pins (or pads) is not keeping pace with the increasing integration density and circuit complexity, and this packaging limitation imposes significant additional constraints on testing complex ICs such as VLSI devices.

[0019] Specifically, as mentioned above, the number of transistors on a chip continues to double approximately every two years. However, according to the International Semiconductor Technology Roadmap, the number of pins on a package is increasing at a rate of approximately 11% per year. Further exacerbating this problem is the fact that, typically, such larger, more complex integrated circuits require an increased number of pins to enable data flow to and from the integrated circuit. In addition, more pins are needed to provide sufficient power and electrical grounding to the chip, as power supply and power supply noise are critical and limiting factors for the normal operation of high-performance integrated circuits.

[0020] Therefore, approximately 50% of all pins in many modern VLSI circuits are dedicated to providing power and electrical grounding to supply over 100 watts of power to the billions of transistors within the VLSI chip. This rapid increase in the number of transistors per pin and the corresponding decrease in the number of pins available for other purposes, such as testing, exacerbates the difficulty of testing these chips.

[0021] Further complicating the issue is the widely accepted "rule of thumb" regarding testing: for every dollar spent testing at the chip level, it costs $10 at the board level and $100 at the system level to test, diagnose, and replace the same defective integrated circuit. Therefore, chip manufacturers are well motivated to produce tested, high-quality devices at the lowest possible cost.

[0022] In a typical digital test scenario, a functional block (such as a counter, shift register, or register) is tested by providing a set of Boolean inputs to the block and observing the output from the block. As a figure of performance (FOM), the concept of "controllability" is defined as the difficulty of controlling a particular input signal to the block, while "observability" is defined as the difficulty of observing a particular output signal from the block.

[0023] In many cases, the difficulty of controllability and observability is measured in terms of the number of clock or data cycles required for a test sequence to run until certain desired conditions are met in order to control or observe the nodes within a block. These cycles, along with defined inputs and expected outputs, form the test vector used to test the chip.

[0024] For example, if the output terminal of counter "A" is supplied to shift register "R", the input to shift register "R" can only be controlled through the counting sequence of counter "A". Similarly, the output of shift register "R" can only become visible at the output of the integrated circuit after passing through another complex logic block that may require another sequence of events or test vectors. Thus, modern VLSI circuits can have a very large number of required test vectors, and these many test vector counts result in lower controllability and observability scores in the aforementioned FOM, significantly increasing the cost of testing.

[0025] To address these challenges, semiconductor manufacturers have developed Design for Testability (DfT) strategies such as Scan Chain and Built-in Self Test (BIST), which are employed in attempts to reduce the high test costs associated with testing and debugging at the subsystem and / or system level.

[0026] For example, a scan chain includes additional pins and circuits on a VLSI chip to provide an alternative path for test vectors applied to control and observe nodes on the chip, thereby reducing the test vector count and thus the test cost.

[0027] On the other hand, the conventional BIST scheme employs a dedicated additional network of circuitry on the chip to provide the test sequence and expected response, thus reducing the number of test vectors that need to be applied from outside the chip via the chip's I / O. However, even the BIST scheme may still require a large number of test vectors to test all potential defects or imperfections.

[0028] Furthermore, both scan chain and BIST implementations require dedicated circuitry added to the chip die, undesirably increasing the die area. It is well known that the probability of manufacturing defects increases exponentially as die size increases, and therefore, increasing die area / size to improve test capability involves a difficult trade-off.

[0029] The concept of structural testing became popular alongside DfT (Device-for-Test) technology. Structural testing differs from functional testing in that it may not verify the functionality of the Device Under Test ("DUT"). Instead, structural testing assumes that the manufacturing process can cause defects or failures, and that these need to be tested in an efficient manner. Thus, structural testing employs a failure model that underlies the generation and application of the test.

[0030] For example, the logic-level degenerate fault (stuck-at-fault) ("SAF") model is one of the most popular fault models for structural testing. All SAFs are mapped onto the interconnections (or nets) between logic gates on the DUT, and therefore they are also called stack-line ("SL") faults. Under fault conditions, it is assumed that the affected line has a permanent (stuck-at) logic "0" or "1" value that cannot be changed by an input stimulus.

[0031] However, despite the use of these DfT technologies, the cost of testing and verifying VLSI circuits continues to rise. Furthermore, most DfT technologies are intrusive and have a significant impact on the complexity, performance, power requirements, and die area of ​​integrated circuit designs.

[0032] The inventors determined that new technology was needed to provide improved controllability and observability of particularly critical and hard-to-reach nodes in VLSI circuits, while ensuring that the impact on the intrinsic operation and die size of the integrated circuit is minimized as much as possible.

[0033] International Application 2023 / 285936, a published PCT patent application by Barlage et al., assigned to the assignee of the present invention, teaches thin-film transistors ("TFTs") that can be manufactured in back-end-of-line (BEOL) and / or middle-of-line ("MOL") processes. International Application 2023 / 285951, a published PCT patent application by Barlage and Shoute, also assigned to the assignee of the present invention, teaches active vias, which are vias that can include vertical mounting of one or more TFTs that can be formed within a trans-silicon via ("TSV") in a BEOL or MOL process. The contents of these two published applications are incorporated herein by reference in their entirety. Since these BEOL and / or MOL devices can be formed in planar layers on a conventional CMOS network, they do not utilize die area that would be useful for a conventional network in the absence of these devices, and therefore do not result in an increase in the die area of ​​the integrated circuit.

[0034] Figure 2 shows a DfT scheme according to one aspect of the present invention, which employs an interconnected test network 100 of the aforementioned BEOL and / or MOL TFTs and / or active vias 104 as a test network that functions as an on-chip test probe, enabling access to internal nodes of the VLSI main network for test purposes.

[0035] In the example shown in Figure 2, the main circuit network is a digital circuit (i.e., logic, memory, etc.), but as will be further explained below, the present invention is also intended to be applicable to analog main circuit networks.

[0036] In the illustrated embodiment, the test network 100 includes N rows and M columns of a crosspoint array. The network 100 includes M × N BEOL and / or MOL devices 104 as shown. 1,1 From 104 n,m It also includes.

[0037] As used herein, the network of VLSI chips, such as logic, memory, and / or analog circuits, implemented in a front-end-of-line manufacturing process using CMOS devices, is referred to as the "main network," while additional networks implemented in the aforementioned BEOL and / or MOL compatible processes are referred to as the "test network" and / or collectively as the "test network."

[0038] As shown in Figure 2, each BEOL and / or MOL device 104 in the test network is connected to a selected node 108 of the main network, thereby enabling controllability and / or observability to those nodes 108. As described below, the BEOL and / or MOL devices 104 and nodes 108 function as "on-chip test probes" to the circuitry on the VLSI chip.

[0039] In Figure 2, the source terminal of each BEOL and / or MOL device 104 in the test network 100 corresponds to the corresponding node 108 in the main network of the integrated circuit being tested. 1,1 from 108 n,m The gate terminals of each BEOL and / or MOL device 104 are connected to the respective column lines 1121 to 112 of the network 100. m The drain terminals are connected to the respective row lines 1161 to 116.n is connected to. In the illustrated embodiment, the control signal for the column line 112 is provided by the register 120, but the column line 112 can also be controlled in various other ways, if desired and as will be apparent to those skilled in the art.

[0040] The row line 116 is connected to at least one register 124 and, in the illustrated embodiment, also to a second register 128. By having two registers (or equivalents), as will be described below, the application of inputs to one or more nodes 108 n,m and / or the reading of outputs from one or more nodes 108 n,m are made possible by the network 100.

[0041] In use, one or more nodes 108 can be selected for test inputs (controllability) and / or reads (observability) by the register 120 asserting the appropriate column line 112 and the register 124 placing the desired test data on the corresponding row line 116. For example, by asserting column line 1122 and asserting row line 1162, a logic high can be applied to node 108 2,2 .

[0042] Similarly, the values of the nodes 108 within the main circuit network of the circuit under test can be read by asserting the corresponding column line 112 and reading the value on the corresponding row line 116. For example, the value of node 108 1,2 can be read from row line 1161 by the register 128 after asserting column line 1122. As will be apparent to those skilled in the art, the registers 120, 124, and 128 can be implemented within the main circuit network, if desired, or using BEOL and / or MOL devices.

[0043] Nodes, such as 108 1,1In an exemplary scenario where we need to observe the operation, register 120 asserts column line 1121 high, and all BEOL and / or MOL devices 104 connected to line 1121 n,1 Enable (enable). Node 108 1,1 The data above drives line 1161, and register 128 captures its Boolean value.

[0044] As is clear, the test network(s) 100 allows for the simultaneous application of inputs to selected nodes 108 and the reading of outputs from other nodes 108, but with some limitations. Specifically, the crosspoint array of network 100 cannot simultaneously read from and write to nodes 108 on the same row line 116, nor can it write different values ​​to nodes on the same row line 116, nor can it read values ​​from two or more nodes 108 on the same row line.

[0045] Alternatively, a value (controllability) can be written to the main circuit under test using the first test network 100, and an output value can be read from the same main circuit under test using the second network 100, thus avoiding the problem of simultaneous access to several rows and / or columns.

[0046] As is evident here, the network 100 could not otherwise directly access selected nodes 108 for verification and / or characterization of integrated circuits. n,m This enables direct controllability and / or observability.

[0047] Although not shown in Figure 2, if nodes are sampled, register 120 may also include a column line with the system clock to provide precise timing control of the instances. Furthermore, the network used to write test values ​​and read test results (registers 124 and 128 in the illustrated embodiment) may be programmed to drive row lines or independently sense data on row lines. In one scenario, a number of row lines may be configured to sense data on corresponding rows, while another number of row lines may be configured to drive or assert specific data values ​​on rows. The remaining number of row lines may be placed in a high-impedance state to effectively remove them from the circuit under test, if desired.

[0048] Therefore, although the example in Figure 2 shows network 100 implemented as a crosspoint array, it is intended that a higher-performance control network can be implemented within network 100 if desired, and the present invention is not limited to the use of a crosspoint array.

[0049] Furthermore, as described above, in order to enable the simultaneous or independent testing of multiple circuit components and / or functions, the VLSI circuit under test is intended to have multiple instances of the network 100 implemented on the circuit. For example, an arithmetic logic unit (ALU) may have a dedicated first network 100 for testing it, while a part of the output network of an integrated circuit may have a dedicated second network 100 for testing it, and / or a network 100 that implements only writing to or reading from a target node may be employed. In fact, VLSI circuits employing the present invention are intended to have tens or even hundreds of instances of the network 100 employed on them, which is possible mainly because the test network 100 is implemented using BEOL and / or MOL devices on a plane above the main network, and therefore does not significantly increase the die area.

[0050] If the main network is analog, the input from test network 100 to node 108 may be provided from a digital-to-analog converter or from an analog network, and the output from node 108 may be applied to an analog-to-digital converter or an analog network, if desired.

[0051] As will be apparent to those skilled in the art, the present invention provides an on-chip test network that implements test probes that provide observability and / or controllability of selected nodes of a main network.

[0052] As described above, the network 100 is implemented using BEOL and / or MOL devices. Thus, the network 100 can be formed in a stacked manner, with one or more networks 100 being formed on top of one or more other networks 100, all of which are further formed on top of the main network of the chip without increasing the die area of ​​the chip. In such a case, the devices 104 in the layer are connected to each node 108 of the main network through vias that can penetrate the layer of the main network as well as the layer of intervening test networks.

[0053] In the currently preferred embodiment, only n-type BEOL and / or MOL devices 104 are used in network 100, which may affect the propagation of logic high signals through BEOL and / or MOL devices 104. As a mitigation function, row line 116 n These can be precharged to logic high from registers 124 and 128. Once the desired test output data is captured in register 124 or 128, it can be scanned out through I / O pins or pads on the chip under test.

[0054] Similarly, the values ​​of one or more nodes in the main network of the DUT can be controlled through network 100. For example, row line 116 n When activated, data can be asserted from register 124. After a defined delay, a specific column line, e.g., line 1121, is activated, and under these circumstances, test data is driven to the appropriate node in the DUT. The controlled DUT node 108 should be designed to accept data through network 100 without causing logical inconsistencies.

[0055] As described above, in typical situations, the network 100 can be manufactured in a BEOL and / or MOL process on top of any other type of main logic on a conventional CMOS or VLSI chip, requiring only a subset of additional masks to facilitate testing of the VLSI chip or device under test (DUT). While it may be desirable in some cases to implement a portion of the network 100's control circuitry within the chip's main circuitry, the majority of the network(s) 100 is in the plane of an additional layer formed on top of the main circuitry, so generally the network 100 does not significantly increase the die area.

[0056] Therefore, the present invention is intended to offer a significant advantage in that direct test access is provided to and from nodes in the circuit design, enabling chip designers to achieve significantly improved controllability and observability of their designs without affecting their design processes or procedures.

[0057] Figure 3 shows a schematic diagram of the test flow of the conventional technology. A series of test vectors 200 are applied to the DUT 204 to obtain a series of test results 208, which are then compared to the expected set of outputs. If the DUT 204 contains sequential logic such as a 16-bit counter as input and a 24-bit counter as output, then the application of the test vectors 200 is to verify 2 16 (65,536) × 2 24 (16,777,216) = 1,099,511,627,776 test steps are required.

[0058] Figure 4 shows a schematic diagram of a test flow according to one aspect of the present invention. In Figure 4, the DUT 300 comprises a main circuit network 304 implemented in CMOS or the like, and one or more test networks 308 implemented using BEOL and / or MOL devices 104 according to the present invention as described above. A series of test vectors 312 are applied to the test network 308, which applies the corresponding test values ​​to appropriate nodes in the main circuit network 304, reads the corresponding output values ​​from the appropriate nodes in the main circuit network 304, and obtains a series of test results 316.

[0059] As will be apparent to those skilled in the art from the above description, the set of test vectors 312 can be much smaller (and therefore much faster) than the set of test vectors required to test a similar DUT in the prior art. This is because the test signals can be applied directly to the target node in the main network without going through the upstream network, which is necessary to apply the desired test input to the node under test. Specifically, in the above example, each of the 16-bit counter and the 24-bit counter can be tested individually, and if desired, in parallel, significantly reducing the time required to test the circuit. Furthermore, if two or more networks 100 are present on the DUT 300, the test vectors can be applied and the results read out in parallel, further reducing the test and verification time.

[0060] Figure 5 shows a block diagram of a 32-bit counter 400 having a clock input (CLK), an enable input 404, and a logic output 408, so that when the enable signal is high, the counter 400 increments with each clock cycle. In a conventional test regime, the counter 400 is 2 32 This requires 4,294,967,296 test vectors per clock cycle.

[0061] Figure 6 shows a block diagram of a counter 400 implemented according to one aspect of the present invention. The circuit designer of the counter 400 implements the counter 400 as a set of three series-connected logic blocks, which include a first 12-bit counter 425, a second 12-bit counter 427, and a third 8-bit counter 429 to form a 32-bit counter.

[0062] In this example, by using network 100, the output of counter logic block 425 is sent to node 108. 1,1 It can be observed, and the output of counter block 427 is at node 108 2,1 It can be observed at node 108, and the output of counter logic block 429 is displayed at node 108. 3,1 It can be observed.

[0063] Similarly, by using network 100, the input to counter logic block 425 is connected to node 108 1,2 It can be applied to the logical counter block 427, and the input to node 108 2,2 It can be applied to the input to the counter logic block 429, and the input to node 108 3,2 It can be applied to.

[0064] Therefore, test 2 32 Instead of requiring 4,294,967,296 test vectors / clock cycles, the counter 400 can test 2 12 +2 12 +2 8 = 4096 + 4096 + 256 = 8,448 test vectors / clock cycles are required. Furthermore, Node 108 1,1 , 108 1,2 and 108 1,3 If they are connected to separate networks 100, counter 400 will be 2 12 = It can be tested in parallel with 4096 clock cycles.

[0065] In the example in Figure 6, multiplexers (mux) 431, 433, and 435 are employed to prevent logic input inconsistencies when inputs are applied from network 100 to nodes of the main network. Each of the multiplexers 431, 433, and 435 is a 2-to-1 multiplexer, and has multiplexer control lines 437, 439, and 441, respectively, which are used to select whether an enable input from the main network or a test input from network 100 is applied to the respective circuit. Appropriate signals for the multiplexer control lines 437, 439, and 441 can be provided from network 100, from the main network, or a combination of both.

[0066] To prevent inconsistencies when applying test vector inputs via network 100, a 2:1 multiplexer can be omitted if the main circuit network employs tristate logic; however, the use of a multiplexer is now preferred because it allows for the parallel application of test vectors to circuit blocks. For example, as described above, each of the counters 425, 427, and 429 can be tested independently of each other, since their respective inputs and outputs can be directly controlled and observed.

[0067] As will be apparent here, the use of the present invention significantly improves both the controllability and observability of key circuits such as the counter 400. Circuit designers can significantly reduce test time and test vector complexity by including one or more test networks 100 on the designed semiconductor chip to provide direct control and observability at critical nodes in the chip's circuit network. By implementing the network 100 using BEOL and / or MOL devices, a significant increase in die area for the test circuit network is not required.

[0068] As explained, VLSI chip designers can employ multiple networks 100 to enable testing of various functions and circuit areas of the chip independently and / or in parallel. Network 100 can be employed to test the chip for manufacturing defects, but can also be employed in conjunction with a BIST strategy to enable periodic testing and verification as the device ages over its lifespan. Such a BIST function can provide an alarm or notification to the system on which the chip is installed if a failure is detected.

[0069] As is well known, in addition to post-manufacturing testing, BIST functionality can also be employed to test throughout the lifespan of the DUT, helping to take corrective action. For example, if a fault is detected in the circuitry on a chip while it is operating at its operating clock speed, but the fault does not occur at a lower clock speed, the system can reduce the operating clock speed to a speed at which the chip operates correctly. Similarly, if an error is determined in a core of a multi-core processor chip, the faulty core can be disabled by the system. Such BIST-type functionality can employ appropriate test vectors, executed at each power-up event of the integrated circuit, or at intervals separately specified by the circuit designer.

[0070] A first example of a BIST system 700 according to one aspect of the present invention is shown in Figure 7. Typically, the device under test (DUT) 704, formed on a conventional CMOS layer of an integrated circuit, may be a functional subset of the integrated circuit, such as an ALU, memory, or integer core, or it may be the entire integrated circuit.

[0071] The BIST system 700 primarily features a conventional BIST controller 708 that controls the entire test operation and generates a "Pass / Fail" output 712, which can be used by a system controller or other management device on an integrated circuit to take appropriate error mitigation steps or to disable a defective DUT 704 or a functional block (such as an arithmetic core) on the DUT 704.

[0072] The BIST controller 708 receives the system clock 716 and inputs from the integrated circuit's system controller or other systems, initiates the test process when deemed necessary, and outputs a "pass or fail" test response at the end of the test. A set of appropriate test vectors 720, including test inputs and corresponding expected outputs, are stored in a non-volatile read-on memory (ROM) in a typical scenario, or alternatively, the test vectors 720 can be provided using a linear feedback shift register (LFSR) capable of generating a pseudo-random test sequence. LFSRs are typically composed of digital logic and can be implemented using CMOS transistors, and the design of such functional blocks is well known.

[0073] The test vector 720 is applied to the DUT 704 via network 724, which is a test network such as network 100 described above, in order to achieve controllability of the DUT 704. In the example shown, network 724 also provides observability of the DUT 704 by providing the corresponding results of the applied test vectors to a response analyzer 728, which compares the results with the expected output for the corresponding test vectors 720 and provides the results of these comparisons to the BIST controller 708.

[0074] The test operation begins when the BIST controller 708 receives a signal 718 to start the test. The BIST controller 708 sets the DUT 704 to test mode so that the DUT 704 can accept the test vector 720, and enables the test vector 720 to be applied to the DUT 704 via the test network 724.

[0075] The test vectors 720 are sequentially applied to the DUT 704 via the test network 724, and the corresponding responses from the DUT 704 are compared with the expected responses by the response analyzer 728, and the results of the comparison are transmitted to the BIST controller 708. The BIST controller 708 then asserts an output 712 indicating whether the DUT 704 passed or failed the test(s).

[0076] Figure 8 shows another example of a BIST system 760 according to one aspect of the present invention. In Figure 8, components similar to those in system 700 of Figure 7 are indicated by the same reference numerals. In system 760, instead of the test network 724 which operated bidirectionally to both apply test vectors and acquire the corresponding results, the BIST system 760 employs a controllability test network 764 for applying test vectors 720 and an observability test network 768 for acquiring test results. Test networks 764 and 768 are networks such as the test network 100 described above, each implemented as a unidirectional network, with network 764 operating to apply test signals and network 768 operating to receive test results.

[0077] A method using one embodiment of the present invention may involve a chip designer designing the main network of a VLSI using substantially conventional methods. The designer then selects nodes, functional blocks, etc., within the main network that are desired to be controllable and / or observable for testing purposes. The designer then designs at least one test network to provide an on-chip test probe for each of the selected nodes within the main network. The completed design then yields a desired on-chip test probe, which is manufactured by first manufacturing the main logic and then forming at least one test network of BEOL and / or MOL transistors on top of the main logic using a BEOL and / or MOL process, and which has vias formed to connect the BEOL and / or MOL transistors of the test network to the corresponding selected nodes of the main logic, which can be used to perform initial testing for manufacturing defects and / or to function as BIST test points.

[0078] As will be apparent here, the present invention provides an on-chip test probe that enables direct access to selected node test points within a major network on a VLSI chip. One or more test networks implemented using BEOL and / or MOL devices provide an on-chip test probe that enables inputs to be applied directly to a desired selected node in the major network and outputs to be observed directly at that node, thereby significantly improving the observability and controllability of the major network on the chip. Multiple test networks can be employed on the chip to enable different circuits of the major network on the chip to be tested independently, and / or in parallel, and / or in a continuous BIST-type manner.

[0079] Since the test circuits and networks are implemented using BEOL and / or MOL devices, they can be manufactured on a plane of chip layers stacked on top of the main circuitry, and therefore do not require any significant increase in the chip die area.

[0080] The above embodiments of the present invention are intended to be examples of the present invention, and those skilled in the art can modify and alter them without departing from the scope of the invention as defined solely by the appended claims.

Claims

1. A VLSI semiconductor integrated circuit comprising a main circuit network designed to perform a required function of an integrated circuit, at least one test network including transistors manufactured on a plane above the main circuit network and manufactured by BEOL and / or MOL processes, wherein the transistors are selectively connectable by the test network to each selected node of the main circuit network, and the test network operates to connect each transistor to the corresponding node of the main circuit network to form an on-chip test probe that enables the application of inputs and / or observation of outputs at the selected nodes.

2. The VLSI semiconductor integrated circuit according to claim 1, wherein the at least one test network includes at least one shift register for selecting transistors to connect to corresponding selected nodes.

3. The VLSI semiconductor integrated circuit according to claim 2, wherein the at least one test network includes at least a second shift register for applying a test input to the selected transistor connected to the corresponding selected node.

4. The VLSI semiconductor integrated circuit according to claim 1, wherein the test network includes a crosspoint array.

5. The VLSI semiconductor integrated circuit according to claim 2, further comprising an analog-to-digital converter for converting an analog test signal received from an on-chip test probe into a digital value.

6. The VLSI semiconductor integrated circuit according to claim 1, wherein the transistors of the test network are connected via vias to the selected nodes of the main circuit network.

7. The VLSI semiconductor integrated circuit according to claim 1, further comprising multiple test networks, each test network operable to test different parts of the main circuit network.

8. The VLSI semiconductor integrated circuit according to claim 7, wherein the plurality of test networks are operable to test different parts of the main circuit network in parallel.

9. The VLSI semiconductor integrated circuit according to claim 1, wherein the at least one test network tests the main circuit network at each power-up of the main circuit network.

10. A VLSI semiconductor integrated circuit according to claim 1, further comprising a built-in self-test controller, a source of test vectors for the main circuit, and a source of expected test vector results, wherein the built-in self-test controller operates to apply test vectors from the test vector sources to the main circuit, to obtain and compare corresponding results from the main circuit for the applied test vectors, and to determine and output corresponding signals representing the pass or fail of the execution of the main circuit for the applied test vectors.

11. The VLSI semiconductor integrated circuit according to claim 10, wherein the built-in self-test controller tests the integrated circuit each time the circuit is energized.

12. The VLSI semiconductor integrated circuit according to claim 10, wherein the built-in self-test controller tests the integrated circuit when it receives a command to perform a test from the main circuit network.

13. The VLSI semiconductor integrated circuit according to claim 7, wherein different test networks test different functional blocks of the semiconductor integrated circuit.

14. A method for designing a VLSI semiconductor integrated circuit, (i) The step of designing the main circuit network of the integrated circuit, (ii) The step of determining a number of nodes corresponding to points in the main circuit network where it is desirable to apply test values ​​and / or read test outputs to verify the precise operation of each of the main circuit networks, (iii) The step of designing at least one test network to be manufactured on a plane above the main circuit network to be selectively connected to one of the determined nodes of the main circuit network to enable the application of test signals to each node and / or receive test outputs from each node. Methods that include...

15. The method according to claim 14, wherein the at least one test network is a crosspoint array.

16. The method according to claim 14, wherein the main circuit network includes a plurality of functional blocks, each functional block having a corresponding test network.

17. A VLSI semiconductor integrated circuit comprising a main circuit network for implementing desired functions of an integrated circuit, and a test network manufactured on a plane above the main circuit network, wherein the test network is operable to provide test probes to selected nodes of the main circuit network, enabling the application of test values ​​thereto and / or the reading of test outputs therefrom.

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