Dag and congestion-aware chip-oriented global routing method

Abstract

The present application belongs to the technical field of electronic design automation physical design in integrated circuits, and relates to a chip-oriented global routing method based on directed acyclic graph and congestion awareness, which can be used for global routing in chip physical design. The present application innovatively introduces a wire mesh routing sequence strategy based on internal pin density and average congestion density, dynamically gives the most difficult-to-route wire mesh the highest routing priority by scientifically quantifying the internal topology of the wire mesh and the congestion degree of the external environment; a dynamic via punishment mechanism with congestion awareness is proposed, which can obtain the congestion gradient of the underlying grid in real time, and intelligently apply nonlinear vertical layer transition resistance in the congestion hotspot area; an enhanced directed acyclic graph mode routing space is constructed in the underlying engine, and combined with a node cost fast updating algorithm based on dynamic programming, the iteration number of wire breaking and rerouting is reduced, and the time overhead of the super large scale integrated circuit routing link is saved.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation and physical design technology in integrated circuits, and relates to a chip-oriented global routing method based on directed acyclic graphs and congestion awareness, which can be used for global routing in chip physical design. Background Technology

[0002] In the physical design flow of Electronic Design Automation (EDA), routing serves as the bridge between layout and manufacturing, and is a core step determining the convergence of chip power, performance, and area metrics. Its core task is to plan physical wire paths for all signal connections in the netlist while satisfying extremely complex electrical rules (such as crosstalk and electromigration) and design constraints. Routing is not only the most computationally resource-intensive and time-consuming step in the back-end process, but its quality directly determines the final area utilization, timing performance, power consumption, and reliability of the chip. In short, the success or failure of routing directly affects whether the chip can be successfully fabricated.

[0003] Essentially, chip routing is a multi-objective optimization problem of solving large-scale Steiner trees under extremely complex constraints. Its optimization objective is not only to achieve full logical connectivity but also to optimize physical performance indicators. This is achieved by minimizing bus length to reduce interconnect latency and dynamic power consumption, reducing the number of vias to improve manufacturing yield and reduce parasitic resistance, and strictly controlling congestion to ensure wired availability. However, as semiconductor process nodes evolve towards the nanometer scale, the design scale of integrated circuits is growing exponentially, and the explosive growth in device density has intensified competition for routing resources.

[0004] Under such extremely complex constraints, traditional routing algorithms—such as classic maze routing and teardown / rerouting strategies—often face problems of search space explosion and convergence difficulties when solving the routing feasibility of large-scale netlists. They struggle to find satisfactory solutions within a limited time and expose several problems. Poor micro-routing quality, lacking fine-grained control over via resources in three-dimensional space, leads to a large number of meaningless vias in congested areas, causing an overabundance of invalid vias. Inadequate macro-resource scheduling, with routing sequences often using static or random allocation, causes long nets to prematurely occupy local bottom-layer hotspots, leaving subsequent short nets in a deadlock state with no way to proceed, resulting in numerous design rule violations. Huge computational overhead, due to numerous nets congesting and deadlocking, forces the algorithm to perform massive teardown / rerouting iterations, significantly slowing down the operation in both single-threaded and multi-threaded environments and reducing the quality of the routing solution. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a chip-oriented global routing method based on directed acyclic graphs (DAGs) and congestion awareness. This method extracts netlist information, pin locations, and physical constraints from the chip design data to be routed through input parsing and data initialization. It then constructs a three-dimensional global routing cell mesh and initializes its capacity and requirements to solve the fundamental modeling problem of underlying spatial resources, thereby providing an accurate physical spatial view for subsequent pathfinding. Simultaneously, a pre-introduced net routing order strategy scientifically assigns routing priorities to nets by quantifying their inherent topological characteristics and external environmental congestion. This provides clear guidance to prevent improper macro-level resource allocation, reducing the disorderly preemption of local hotspots by long nets and resolving local congestion deadlock problems. In the initial routing stage, by combining the extracted net information with the underlying mesh, a pattern routing pathfinding space based on a DAG is constructed. A node cost update algorithm based on dynamic programming is used to quickly solve for paths, significantly reducing redundant search space and improving routing efficiency in complex meshes. To further control 3D spatial resources and suppress via flooding, a congestion-aware dynamic via penalty mechanism is introduced. This mechanism diversifies the cost of the generated underlying mesh and, combined with an enhanced directed acyclic graph (DAG) model, perceives congestion gradients in real time and intelligently applies vertical via penalties to generate 3D routing with lower via costs. Furthermore, during the overall routing optimization process, a congestion-driven iterative teardown and rerouting mechanism is employed to optimize the routing results. By globally monitoring mesh congestion overflow, it guides the teardown of meshes passing through hotspots and updates penalty costs for rerouting, thereby gradually eliminating local congestion and improving overall connectivity. Finally, in the output stage, valid topology paths are generated. Through multi-layered collaborative scheduling, this invention not only significantly reduces routing time overhead in large-scale chip design but also greatly reduces implicit resource waste such as design rule violations and invalid via flooding, comprehensively improving the quality and robustness of global routing.

[0006] The technical solution of the present invention: A chip-oriented global routing method based on directed acyclic graphs and congestion awareness is proposed, with the following specific steps: Step (1) Obtain initial chip design data and initialize the three-dimensional routing space. The set of nets to be routed is obtained through parsing the initial data. and physical design constraints Simultaneously, the chip layout space is discretized into a three-dimensional global routing mesh. Each node in the mesh diagram is called a global wiring mesh cell. To achieve this through a 3D global wiring mesh diagram It collects public information computing resource capacity and demand information, and at the same time constructs a dynamic through-hole penalty mechanism.

[0007] Step (2) Calculate the net set Internal pin density of each net and external space congestion value And perform net routing sorting. Synthesize and quantize the net set. The inherent topological characteristics and external environmental congestion of each network to be wired are used to generate corresponding network priorities. According to this priority Assign routing priorities to all nets to be routed, thus obtaining a net priority queue. This determines the overall cabling sequence strategy, prioritizing the cabling of high-priority networks.

[0008] Step (3) combines the information calculated in step (1) with the net priority queue from step (2). Construct an enhanced directed acyclic graph model and perform initial pattern routing. For the net priority queue obtained in step (2)... ,according to Net priority The corresponding directed acyclic graphs are constructed sequentially for routing. At the same time, the congestion status of the routing space is acquired in real time and dynamic via penalties are applied intelligently. Then, a minimum cost three-dimensional topology path from the source pin to the target pin is solved in the directed acyclic graph space using a node cost update algorithm based on dynamic programming. The generated net path is recorded in the current routing scheme.

[0009] Step (4) performs congestion-driven iterative teardown and rerouting. First, a congestion overflow threshold and a maximum number of iterations are set, then all net paths generated in step (3) are globally evaluated. First, the net set is detected. If any unrouted nets exist, perform time-consuming but effective maze routing on them; otherwise, check the 3D global routing mesh. Check if there is a congestion overflow in the routing path; if there is no congestion overflow, end the routing; if there is a congestion overflow, dismantle and reroute the network where the congestion overflow occurred, update the historical penalty cost of the area, and send the dismantled network back to step (2) for the next round of sorting and routing iteration until the iteration termination condition is met.

[0010] Step (5) Output and save the final global routing result. Obtain the valid 3D topology paths of all nets after the complete unraveling and re-iteration in step (4), and perform a routing integrity check. Traverse the connectivity integrity of each routed net using a breadth-first search to ensure that all pins pass through continuous paths. The paths are physically connected and there are no suspended segments or loops, ultimately generating a rectangular guide area that can be used in the subsequent detailed routing stage.

[0011] Furthermore, step (1) specifically includes the following steps: 1-1) Read the standard cell library file (Library Exchange Format, LEF) and design netlist file (Design Exchange Format, DEF) for integrated circuit design. Extract all sets of nets to be routed from the input files. This process involves obtaining the physical coordinates of the source and target pins contained in each net. Simultaneously, physical design constraints are extracted. This includes the default routing direction of each metal layer (usually horizontal for odd-numbered layers and vertical for even-numbered layers), minimum line width, minimum line spacing, and via size limitations.

[0012] 1-2) Based on the preset global wiring mesh cells The dimensions of the chip are used to uniformly divide the continuous three-dimensional physical space of the entire chip into a three-dimensional global wiring mesh. Each one All can use a unique three-dimensional coordinate system To identify, among which and These represent the number of columns and rows in a horizontal two-dimensional plane, respectively. This represents the total number of metal layers available for wiring on the chip.

[0013] 1-3) Each Abstracted as a 3D global wiring mesh diagram One of the vertices, adjacent to They are connected by edges. Edges are divided into two categories: those adjacent within the same metal layer... Two-dimensional edges with horizontal or vertical orientations between them; another type is the same between adjacent metal layers. coordinates The edge of the vertical through hole.

[0014] 1-4) Calculate the 3D global wiring mesh. The physical capacity information within the data represents the upper limit of available physical cabling resources within a specific area. For connecting two adjacent... grid edges Based on the physical width of the metal layer and the minimum allowable linewidth of that layer, the maximum number of available wiring tracks that can pass through the edge is calculated, and this number is denoted as the physical capacity of that edge. For Its physical capacity is defined as the average of the capacities of two adjacent grid edges in the preferred routing direction.

[0015] 1-5) By introducing a dynamic via penalty mechanism, the 3D global routing mesh is calculated. The requirement information in the data represents the actual resource usage of the current cabling scheme. The requirement information consists of two parts: wiring requirements and via requirements. The requirement information for traditional global cabling methods is calculated as follows: side demand The number of metal wires passing through this side and the adjacent The additional overhead caused by the through-hole consists of the following components. The calculation formula is as follows: in, Indicates crossing the edge The number of wires, Represents a node The number of through holes containing metal connections. Represents a node The number of through holes containing metal connections. This represents a fixed, constant value. To accurately reflect the resource consumption of vertical interconnects, for those passing through... The stacked through-holes (i.e., those that enter from below and exit from above, or those that enter from above and exit from below) are weighted 2 when counting.

[0016] Similarly, demand It is also the sum of wiring requirements and via requirements. The difference is that wiring requirements are taken as the average of two adjacent values, while via requirements only consider vias within the unit. Let... and For nodes Two adjacent lines in the preferred wiring direction The calculation formula is as follows: in, Indicates crossing the edge The number of wires, Indicates crossing the edge The number of wires, Represents a node The number of through holes containing metal connections. It represents a fixed constant value.

[0017] Traditional global routing algorithms typically use a fixed constant coefficient to estimate the implicit resource consumption of vias. This static approach ignores the spatial heterogeneity of the chip layout. This invention proposes a congestion-aware adaptive penalty mechanism. By introducing a dynamic coefficient... This coefficient is based on the current Connection resource utilization rate Adaptive adjustments were made. The improved requirement model was restructured as follows: in, Indicates the current connection or the current Resource utilization rate, which is the ratio of occupied resources to total capacity.

[0018] This is a non-linear growth function used to represent the dynamic cost of the via. When regional resources are abundant, Maintain a low baseline value. This encourages more direct inter-layer connections using vias in non-congested areas, thereby optimizing line length and timing. When resource utilization approaches or exceeds a threshold, The load increases exponentially or linearly. This constraint mechanism significantly increases the cost of punching holes in hotspot areas, forcing non-critical wirelines to bypass these areas, thereby achieving global load balancing and reducing overflow. The specific form is as follows: in, , , and It is a parameter. Indicates the basic penalty. This indicates the highest punishment. Indicates the center threshold. This indicates the steepness of the function.

[0019] Furthermore, step (2) specifically includes the following steps: 2-1) For the set of wire meshes obtained in step (1) For multi-pin nets containing two or more pins, in order to reduce the difficulty of subsequent routing, the Steiner minimum tree algorithm and FLUTE algorithm are used to decompose them into multiple two-pin subnets. In subsequent processes, the subnets will inherit the priority of the parent net.

[0020] 2-2) Regarding the set of wire meshes obtained in step (1) Each wire mesh Obtain the smallest bounding rectangle formed by its internal pins, i.e., the bounding box. Calculate the semi-perimeter of the bounding box and the total number of pins of the net. Define the net. Internal pin density for: in, It is a wire mesh The number of pins, It is a wire mesh The half perimeter of the bounding box, It is a very small positive constant (such as 10). -5 This is used to prevent division by zero errors when a degenerate mesh causes the bounding box half-perimeter to be zero.

[0021] 2-3) Obtain the net The degree of congestion in the external environment is used to characterize the severity of congestion at the physical location of the network, defining the network. average congestion density for: in, Represents the underlying grid. It is a enclosure for the wire mesh. For the underlying mesh The estimated cabling congestion value. It refers to the total number of grids covered by the mesh bounding box.

[0022] 2-4) Due to the wire mesh Internal pin density and average congestion density Belonging to different physical dimensions, their numerical distribution ranges differ significantly. To prevent the absolute value of one dimension from being too large and thus overshadowing the features of another dimension, a strict normalization process was performed to ensure that the two dimensions are on an equivalent scoring scale in subsequent fusion. The wire sequence priority score of the net is then evaluated. : in, and It is the value after normalization. and The weighted parameter for the line order.

[0023] 2-5) Establish a global net priority queue based on the line order priority. All decomposed subnets to be routed are sorted from highest to lowest priority. Under this mechanism, nets with a large number of pins, a very small span, and located in a severely congested area in the center of the chip will be placed at the front of the queue and given priority for routing.

[0024] Furthermore, step (3) specifically includes the following steps: 3-1) Constructing the topology of the enhanced directed acyclic graph: from the wire priority queue of step (2) The net with the highest priority is selected. Starting from the source pin and ending at the target pin, the net is expanded outwards from its bounding box to form a local 3D search sub-mesh. Within this 3D search sub-mesh, a directed acyclic graph (DAG) topology is constructed strictly according to the physical direction from the source pin to the target pin. Based on this DAG, a pattern routing method is selected to perform initial pattern routing for the net.

[0025] 3-2) Before routing search, the congestion information of each vertex in the sub-mesh of the directed acyclic graph topology is obtained in real time. For each vertical via edge, the congestion status of the underlying layer at its two-dimensional location is determined. When regional resources are sufficient, the vertical via resistance remains at a low base value, which encourages more direct inter-layer connections using vias in non-congested areas, thereby optimizing line length and timing. When resource utilization approaches or exceeds the threshold, the vertical via resistance increases exponentially or linearly. This means that in congested hotspot areas, extremely high resistance is applied to the via generation action, forcing the mesh to find more open areas in the horizontal layer before performing inter-layer jumps, effectively suppressing via flooding.

[0026] 3-3) To obtain the optimal path for the network routing, perform fast updates of node costs based on dynamic programming. This is done in the 3D global routing mesh diagram. In the middle, the nodes represent Each layer represents a wiring metal layer, with multiple parallel wiring tracks between layers. The connection points between adjacent layers represent vias. Define the minimum node cost. This indicates that all relevant upstream pins are connected to the pin located at the first... Layer nodes Minimum required cabling cost. Assuming a total number of layers... The root node is Then the minimum cabling cost for the entire network is For any node and the current layer The state transition equation is as follows: The state transition equation recursively calculates the cost, which consists of three core parts. The first part is the substructure cost, which recursively includes the selected predecessor nodes. minimum cost The second part of the cost is the connection cost, which represents the cost from the predecessor node. To the current node Plane connection cost The third part of the cost is the via cost, which is represented at the node. In order to connect all the different layers that converge. and the current output layer A cost is required for vertical through-holes. The external minimum expression selects each stream. The nodes to be connected The internal minimum value expression determines the selected node. Connect to node conductor layer The equation assumes nodes There are no pins at this point, so only the cost of a via connecting the lowest and highest layers is added.

[0027] 3-4) For wire mesh Run the node cost update algorithm based on dynamic programming in step 3-3) to find the optimal routing path with the minimum routing cost. Map the routing path back to the 3D global routing mesh. Simultaneously, the resource requirements of all two-dimensional horizontal and vertical edges and three-dimensional via edges along this path are increased to provide the latest environmental data for subsequent network congestion sensing.

[0028] Furthermore, step (4) specifically includes the following steps: 4-1) After all nets have completed the initial routing in step (3), the first round of iteration detection begins. First, it checks if there are any unrouted nets. If there are unrouted nets, it performs time-consuming but effective maze routing on them. If there are no unrouted nets, it further checks if there are any overflow nets. The 3D mesh is scanned globally, and the overflow amount of each edge is calculated. At the same time, it checks if there are any congested overflow routing paths in the 3D mesh.

[0029] 4-2) If no overflow is found after scanning, or if the current iteration count has reached the preset maximum iteration threshold, the routing process is determined to have converged, and the process is directly skipped to step (5) for output. Otherwise, an iterative teardown and rerouting mechanism is started.

[0030] 4-3) For all detected congested edges, reverse the process to find all sets of nets occupying that edge. Using a specific disconnection strategy, remove these nets from the current cabling scheme. At the same time, the edge resource requirements originally occupied by the disconnected nets will be reduced accordingly, thereby freeing up physical resources in the congested area.

[0031] 4-4) To prevent the wire network from falling into the same congestion hotspot again in the next iteration, the repulsion force of the region must be increased. For each edge that overflows, a historical penalty cost constant is set. When an edge overflows, the historical penalty cost of the edge is updated and added to the resource occupation of the edge, forcing the edge to actively avoid these extremely congested regions in subsequent rounds.

[0032] 4-5) Re-label the removed nets as pending cabling. Then re-enter these nets into step (2), recalculate their priorities based on the updated global congestion environment, reorder them, and re-enter the global cabling space for rerouting.

[0033] Furthermore, step (5) specifically includes the following steps: 5-1) Convert the array of predecessor node pointers of all nets residing in memory into a standard set of physical segments. Explicitly mark the metal layer, start coordinates, end coordinates, and three-dimensional coordinate set of each segment as a via for interlayer passages.

[0034] 5-2) Format the valid 3D coordinate set data from 5-1) accordingly and export it as a global routing result guide file commonly used in the field of electronic design automation. This file will be directly used as input to the detailed routing tools in the physical design backend for precise track assignment and physical connections.

[0035] Compared with the prior art, the present invention has the following advantages and beneficial effects: Existing technologies typically employ static allocation or random sorting when determining network routing order. This can easily lead to long networks prematurely preempting local congestion hotspots, forcing shorter networks to enter a deadlock state with no way to proceed, resulting in numerous design rule violations. This invention innovatively introduces a network routing order strategy based on internal pin density and average congestion density. By scientifically quantifying the network's internal topology and external environmental congestion, it dynamically assigns the highest routing priority to difficult-to-route networks. This mechanism fundamentally eliminates the disorderly preemption of underlying hotspots by long networks, completely breaking the deadlock caused by resource depletion.

[0036] Meanwhile, traditional global routing algorithms often use fixed, static inter-layer costs when handling cross-layer routing, failing to detect real-time changes in 3D spatial congestion. This leads to nets frequently zigzagging up and down in congested areas, generating numerous meaningless redundant vias and severely impacting chip manufacturing yield. This invention proposes a congestion-aware dynamic via penalty mechanism that can acquire the congestion gradient of the underlying mesh in real time and intelligently apply nonlinear vertical layer transition resistance in congested hotspot areas. This mechanism effectively suppresses ineffective net traversal behavior and significantly optimizes the routing quality in 3D space.

[0037] Finally, addressing the technical pain points of traditional 3D maze pathfinding algorithms, such as space explosion and extremely slow computation in complex meshes, this invention constructs an enhanced directed acyclic graph pattern routing space in the underlying engine and combines it with a dynamic programming-based node cost fast update algorithm, reducing the number of iterations for wire teardown and rerouting, and saving time overhead in the routing process of VLSI. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the chip-oriented global routing method based on directed acyclic graphs and congestion awareness, as proposed in this invention.

[0039] Figure 2 This is the input file parsing process for the chip-oriented global routing method based on directed acyclic graphs and congestion awareness, as described in this invention.

[0040] Figure 3 This is a schematic diagram of the 3D mesh space and net routing of the chip-oriented global routing method based on directed acyclic graphs and congestion awareness, which is the subject of this invention.

[0041] Figure 4 This is a schematic diagram of the L-shaped pattern routing-based directed acyclic graph of the global routing method for chips based on directed acyclic graphs and congestion awareness, as described in this invention.

[0042] Figure 5 This is a schematic diagram of an initial routing method for a chip-oriented global routing method based on directed acyclic graphs and congestion awareness, according to the present invention. Detailed Implementation

[0043] The method of the present invention will be described in detail below with reference to the accompanying drawings, technical solutions, and embodiments.

[0044] like Figure 1 As shown, the present invention provides a chip-oriented global routing method based on directed acyclic graphs and congestion awareness. The overall method framework can be divided into five core stages, and the specific execution flow is as follows: The first stage is the input parsing and data initialization stage. First, the underlying files provided by the front-end design are parsed. Physical constraint data from the standard cell library (LEF file) is extracted from these files. and the set of nets to be wired in the design exchange format (DEF file). Based on the above physical constraints With net sets The three-dimensional physical continuous space is discretized to construct a three-dimensional global wiring mesh. Subsequently, the 3D global routing mesh is traversed. Initialize and calculate each global wiring mesh cell for each resource in the dataset. The physical capacity, cabling requirements, and basic costs of each edge are used to establish a data foundation for subsequent resource scheduling.

[0045] The second phase is the net routing sequence strategy phase. Since the order of net routing directly affects the global congestion distribution, this phase uses a 3D global routing mesh diagram... Get the current set of nets Based on capacity and demand data, network priority characteristics are evaluated. Specifically, the internal pin density of each network is calculated to characterize its topology, while the external congestion value of its region is calculated to characterize environmental severity. Combining these two factors, a comprehensive priority score is generated for each network, and a global network priority queue is constructed accordingly. The queue is arranged from highest to lowest priority, ensuring that vulnerable networks prone to deadlock are routed first.

[0046] The third phase is the initial routing phase. This involves establishing a global net priority queue based on the structure built in the second phase. The network is extracted one by one and fed into the underlying routing engine. At this stage, a local directed acyclic graph (DAG) search space is constructed for the current network. During routing, congestion conditions are considered in real time, and a node cost update algorithm based on dynamic programming is used to quickly calculate the minimum cost path from the source node to the target node, thus efficiently completing the pattern routing based on the DAG.

[0047] The fourth stage is the congestion-driven iterative teardown and rerouting optimization stage. After the initial routing is completed, a closed-loop detection and iterative optimization process begins. First, it checks whether there are any unrouted nets in the current routing space (including nets that failed in the initial routing or were forcibly removed in subsequent iterations). If so, a maze routing engine with a larger search space and stronger detour capabilities is invoked to reroute these nets. Then, a global overflow assessment is performed to determine whether the current state satisfies the condition of no overflowing nets or whether the current loop has reached the preset maximum number of iterations. If not, a loop teardown mechanism is triggered (as shown by the loop arrow in the diagram), forcibly removing conflicting nets that pass through congestion hotspots, turning them back into unrouted nets, and updating the penalty cost of congestion edges. Then, the process returns to the state detection step above for the next iteration.

[0048] The fifth stage is the output stage. When the convergence judgment in stage four is positive (i.e., there are no more congested overflow nets in the entire graph, or the maximum iteration limit has been forcibly reached), the iteration loop is terminated, and a valid global routing result is generated and output. This result is then directly delivered to the downstream detailed router for precise physical track allocation. Finally, a comprehensive evaluation result of various core performance indicators is output, and the process ends.

[0049] The following example illustrates the implementation details of each process. The specific implementation method is as follows: Step 1, as follows Figure 2 As shown, the LEF and DEF input files are first read, parsed, and loaded into the OpenDB design database to extract process rules, unit abstraction information, instance layout positions, and netlist connection relationships. Then, the 3D global routing mesh is generated. During the construction phase, the underlying resources are initialized through mesh generation, obstacle mapping, and metal layer constraint resolution. Finally, a computer-processable 3D global wiring mesh is generated. The model consists of mesh cells representing global wiring. The vertices, the edges representing the routing path, and the capacity, demand, and cost attributes associated with the edges together form the basic data support for subsequent global routing.

[0050] 1.1 First, the chip design data is read through the input data parsing module. Specifically, the LEF file, which contains the physical dimensions of standard cells and macrocells, the routing of each metal layer, minimum linewidth, and minimum spacing constraints, is parsed. At the same time, the DEF netlist file, which contains the coordinates of component instances and the pin coordinates of the nets to be routed, is also parsed.

[0051] 1.2 Constructing a 3D Global Wiring Mesh : a) The 3D global routing mesh modeling module divides the entire chip space into sections based on the density of the routing tracks. Three-dimensional global cabling unit Using mathematical graph theory, it is abstracted into a three-dimensional mesh graph. Each As a vertex Connect adjacent edge There are two categories: horizontal / vertical trace edges between adjacent nodes on the same floor, and trace edges across floors. Through-hole edges between coordinate nodes.

[0052] b) As Figure 3 The image shows a simple routing example. It illustrates the routing result of a four-pin net within a three-layer routing space. The routing method shown is just one possible connection scheme. The pins can be seen... , , , Although on the same layer, because the preferred routing direction of the first layer is horizontal, connecting all pins requires going through vias to the second layer. Vertical routing is then performed on the second layer to connect all pins and complete the net routing. However, in real-world chips, the number of nets requiring routing can reach millions.

[0053] c) Calculate the capacity, requirements, and costs needed for subsequent routing. These metrics apply to both mesh edges and global routing mesh cells. Capacity represents the upper limit of physical cabling resources available within a specific area. For connecting two adjacent global cabling mesh cells... The capacity of a grid edge is defined as the number of available routing tracks passing through that edge, which also approximates the maximum number of nets that the edge can theoretically accommodate. Demand quantifies the actual resource consumption of the current routing scheme. It consists of two parts: wiring demand and via demand. Edge demand is determined by the number of metal wires passing through that edge and the adjacent global routing grid cells. The additional overhead caused by vias is comprised of the following components. The cost represents the overhead of trace length and vias during routing. The cost of trace length is related to the number of edges crossing the net in the graph, while the cost of vias is related to the congestion level of the metal layer region. Furthermore, to address the erroneous cost assessment caused by traditional global routing algorithms using fixed constant coefficients to estimate the implicit consumption of routing resources by vias, this invention introduces a dynamic via penalty mechanism, dynamically adjusting the via cost based on resource availability.

[0054] Step 2: Complete the 3D global wiring mesh. After construction, in order to solve the problem of disorderly contention for local hotspots in existing technologies, which leads to deadlocks caused by subsequent re-running of wires after disconnection, this invention introduces a wire priority evaluation mechanism to determine the wiring order of the wire network.

[0055] 2.1 Calculate the priority order of the wire mesh: a) The global routing algorithm first targets the set of nets to be routed. Each net in the dataset is decomposed using the Steiner minimum tree algorithm and the FLUTE algorithm. Simultaneously, for the set of nets to be routed... Each wire network Calculate the internal pin density based on the number of pins and the half-perimeter of the outer bounding box. When a net has a large number of pins and a very small half-perimeter of its bounding box, the net will achieve extremely high performance. Score. From a physical routing perspective, this means that the net must achieve highly complex topological connectivity within an extremely small and confined local space. Such nets have almost no physical redundancy for outward detours. If such nets are delayed during the dismantling and rewiring phase, their few legal routing paths are easily preempted by previously routed nets, inevitably leading to severe local short circuits or spacing violations. Conversely, nets with few pins and a large bounding box semi-perimeter have extremely high pathfinding flexibility, easily finding alternative paths with minimal penalty even in the face of local congestion. Therefore, through The metrics and algorithms can accurately identify the most vulnerable and deadlock-prone local critical networks and give them an absolute first-mover advantage, thereby cutting off the chain reaction of resource squeeze at the source.

[0056] b) To assess the congestion level of the external environment, this invention introduces a fast congestion prediction mechanism to extract network data. The external environmental congestion situation is considered. The average congestion density is calculated using the estimated cabling congestion value and the area of ​​the outer boundary frame. To obtain the congestion distribution in the global space without significantly increasing computational overhead, this invention introduces a fast probabilistic congestion prediction model. This model avoids the extremely time-consuming initial maze pathfinding, instead macroscopically fitting congestion hotspots through the spatial superposition of net bounding boxes. Specifically, for any net in the ideal condition of no obstructions, the minimum wiring length of the net is half its perimeter. Assuming that a net has an equal wiring probability on all feasible shortest paths within its bounding box, the expected wiring demand contributed by the net to any grid within the bounding box can be defined as the wiring length consumption per unit area, i.e., the minimum wiring length divided by the area of ​​the net bounding box. After traversing all nets to be wired, the total estimated wiring demand capacity of any bottom-level grid in the global space is the linear superposition of the demand densities of all nets covering that grid.

[0057] When assessing the external spatial congestion pressure faced by a wire mesh, the algorithm not only simply sums up the estimated congestion demand of all bottom-level meshes within the wire mesh bounding box, but also introduces the bounding box area as the denominator to obtain the average congestion density of the bounding box region. This formula enables the algorithm to accurately identify high-risk wire meshes that must traverse high-density congestion hotspots before maze pathfinding begins.

[0058] 2.2. The priority score of the wire sequence in the comprehensive evaluation network. At that time, due to the internal pin density of the wire mesh and average congestion density Belonging to different physical dimensions, their numerical distribution ranges differ significantly. To prevent the absolute value of one dimension from being too large and causing features of another dimension to be overwhelmed, this invention performs strict min-max normalization processing before weighting, ensuring that topological features and congestion features have equivalent scoring scales in the subsequent fusion. For linear weighting parameters... and Essentially, it controls the router's decision preferences in different environments. Experimental tests and extensive empirical evaluations show that in most high-density chip designs, the objective congestion environment in which the net is located has a slightly greater limiting effect on its routing success rate than its own pin density. When setting and At that time, the algorithm achieved the optimal balance between bus length and design rule violations, and performed best across all evaluation metrics. This was achieved after calculating the wire priority score of the net. Then, put the wire mesh The score is assigned to the subnets it decomposes, and then all subnets are sorted by priority. Sort and build wire mesh priority queue .

[0059] Step 3 Figure 4 It is a five-pin , , , , The network is generated using a directed acyclic graph with L-shaped single-inflection-point routing as the sole routing pattern. For This type of geometrically shared same coordinates or Point pairs of coordinates The routing pattern degenerates into a straight line, therefore in a directed acyclic graph they appear as a single directed edge connecting two nodes, and the solution space is unique. For These pairs of points, located diagonally, form a rectangular bounding box. The pattern-based routing allows for two routing methods ("horizontal then vertical" or "vertical then horizontal"). To encompass both possibilities, a new intermediate node (representing...) needs to be introduced. The inflection point of the pattern routing allows each end subnet to be expanded into two parallel directed paths. This means that in the subsequent dynamic programming phase, the algorithm can freely choose to take the upper or lower path based on congestion cost.

[0060] 3.1 Construct a directed acyclic graph for pattern routing: a) Constructing a directed acyclic graph (DAG) is a mapping process from physical topology to logical flow graph, specifically involving the following four steps. The first step is topology decomposition. Given a net with multiple pins, the first step is to construct a right-angled Steiner minimum tree for the multi-pin net to determine the basic topological skeleton of the net. For multi-pin nets, this is typically achieved by generating Steiner points, decomposing the multi-pin net tree into multiple independent sets of two-end nets. Steiner points are geometrically virtual convergence points designed to minimize bus length.

[0061] b) Establish the flow direction. To implement dynamic programming, the undirected tree must be transformed into a directed acyclic graph to determine the order of computation, i.e., the subproblem dependencies. Randomly select a pin as the sink ( Figure 4 Select node a), and traverse the entire Steiner minimum tree using depth-first search. Depth-first search establishes a parent-child hierarchy, where signals are considered to flow from leaf nodes to the root node. For each end subnet, the direction is defined as from child node to parent node.

[0062] c) Select the routing pattern type to construct a directed acyclic graph (DAG), thereby performing a 3D solution for the routing path. A complete routing solution requires assigning each edge in the DAG to a specific metal layer. A possible routing method is as follows: Figure 5As shown in the diagram, there are assumed to be three metal layers, and all pins are located at the bottom layer, i.e., the pins are located at the nodes. , , , , The lowest level. It's important to note that each node in a directed acyclic graph (DAG) implicitly possesses vertical connectivity. That is, when a path changes the layer assignment at a node, it represents the insertion of a via, and different line segments and vias have different costs. The routing objective based on a DAG is to find a subgraph from all leaf nodes to the root node that minimizes the total routing cost.

[0063] 3.2. Minimum cost solution based on dynamic programming: a) To address the topology merging issue in multi-terminal wire networks, predecessor node set Divide into several mutually exclusive subsets These subsets are called flows, and nodes within the same flow have the same upstream node. Figure 4 Taking a directed acyclic graph as an example, the nodes There are three predecessor nodes , , ,Right now . The nodes in the stream can be divided into two streams. Because of the node and nodes All connected to upstream pins , , Therefore, they belong to the same flow. In the compute node... At the cost of this, a node needs to be selected from each of the two streams to converge all signals. A stream represents a logical branch of the signal source, and different nodes within the same stream represent different path choices connecting the same set of upstream pins. Therefore, to connect the entire network, at least one node needs to be selected from each stream for connection.

[0064] b) Based on the minimum node cost defined above The goal is to find the minimum node cost of the root node. To overcome the time complexity bottleneck of traditional enumeration methods, the traditional approach of allocating layers separately for each flow must be abandoned. This invention proposes a novel node cost update strategy, the core idea of ​​which lies in the shift in perspective, no longer independently enumerating each input flow. The layer used Instead, it enumerates the current node. At this point, the lowest level traversed by all convergence paths. and the highest level Due to the node All connections at that location must be included. Within this vertical interval, a high-dimensional combinatorial problem is cleverly transformed into a two-dimensional interval scanning problem.

[0065] Step 4: This stage is essentially a closed-loop adaptive optimization based on congestion feedback memory. In the initial routing, a strongly constrained routing pattern based on a directed acyclic graph was used to pursue extremely high computational speed. This inevitably led to congestion on several local critical paths. This stage uses global scanning to accurately locate these congestion hotspots, forcibly dismantles the congested networks, and imposes a very high historical penalty cost on these areas. When the dismantled networks seek a path again, the underlying cost evaluation function forces them to avoid these areas, actively utilizing a maze routing engine with stronger detour capabilities to explore farther and wider free spaces. Ultimately, through multiple cycles of "dismantle-penalize-reroute," congestion is eliminated as much as possible, achieving the legal allocation of resources across the entire graph.

[0066] 4.1 Execute a congestion-aware iterative disconnect and restep process: a) Upon entering the loop start point of this phase, a global scan of the state of all nets is performed first. This will generate a set of unwired nets. This set mainly includes networks that failed to be routed in the previous round of initial routing due to the inability to find a legal path, as well as networks that were forcibly removed and stripped due to their route through congested hotspots.

[0067] b) Considering that the local environments of the nets entering this set are often extremely harsh, the originally limited pattern routing can no longer provide sufficient detour space. Therefore, a maze routing engine with stronger search capabilities is adopted for these nets. The pathfinding bounding box of the net will be appropriately enlarged, allowing it to be routed within the 3D global routing mesh. It can freely diverge in four directions (front, back, left, right) and above and below. Combined with a dynamic via penalty mechanism, a connection path that can successfully bypass the original congestion area is solved in a wider space.

[0068] c) When the unwired network assembly After all unrouted nets in the map have undergone one pass of maze routing, the results are not output immediately; instead, a very strict overflow check is performed. This involves traversing the 3D global routing mesh. For each physical edge in the graph, calculate its resource overflow. If there is no overflow at any edge in the entire graph or the current number of edge splitting and restepping iterations has reached the preset maximum number of iterations, the algorithm is considered to have converged and exits the edge splitting and restepping stage, and the final result is output.

[0069] d) If overflowing congestion edges still exist, a teardown and restep mechanism will be triggered. These congestion hotspot edges will be precisely located, and all nets passing through them will be traced. To free up these over-crowded physical channels, the topology connections of these conflicting nets will be forcibly removed, clearing the cabling resources they occupy within the cabling space. Their status will then be remarked as unrouted and added to the unrouted net set. Inside.

[0070] e) While dismantling the mesh, a crucial historical cost accumulation update is performed on mesh edges that experience overflow. The more times an edge becomes congested, the greater its historical penalty cost becomes. Subsequently, a new round of iterations is initiated along the dismantling and re-stepping process. In the next round of maze routing solution node accumulation cost calculation, because these hotspot edges have accumulated high historical costs, the underlying routing algorithm will determine that the cost of passing through this area is too expensive, thus intelligently guiding the new round of meshes to detour to areas with lower costs and more abundant resources.

[0071] Step 5: When no congestion is detected across the entire map, the teardown re-step loop will be exited, and the final output result stage will be executed. The global routing result module converts the legal routing paths residing in system memory into a set of 3D physical traces and vias. The final output conforms to industry standards and is directly imported into the downstream EDA toolchain to guide the precise allocation of metal tracks to complete the detailed routing stage. Finally, the industry-standard official evaluation tool CadenceInnovus is used to comprehensively evaluate the routing results, check for design rule violations, and export the final score. The method of this invention is compared with two advanced global routers, CUGR and SPRoute 2.0. Table 1 details the final comprehensive score of each global routing method after evaluation by Innovus under different test sets. In this scoring system, the smaller the value, the higher the overall quality of the routing scheme.

[0072] Table 1

[0073] The quantitative presentation of the above data verifies the significant technical advantages of this invention in the field of global routing of chips.

Claims

1. A chip-oriented global routing method based on directed acyclic graphs and congestion awareness, characterized in that, The specific steps are as follows: Step (1) Obtain initial chip design data and initialize the three-dimensional routing space; obtain the set of nets to be routed through parsing the initial data. and physical design constraints Simultaneously, the chip layout space is discretized into a three-dimensional global routing mesh. Each node in the mesh diagram is called a global wiring mesh cell. To achieve this through a 3D global wiring mesh diagram The public information computing resource capacity and demand information are used to construct a dynamic through-hole penalty mechanism. Step (2) Calculate the net set Internal pin density of each net and external space congestion value And sort the nets; comprehensively quantify the net set. The inherent topological characteristics and external environmental congestion of each network to be wired are used to generate corresponding network priorities. According to this priority Assign routing priorities to all nets to be routed, thus obtaining a net priority queue. This determines the overall network routing sequence strategy, prioritizing the routing of high-priority networks. Step (3) combines the information calculated in step (1) with the net priority queue from step (2). Construct an enhanced directed acyclic graph model and perform initial pattern routing; for the net priority queue obtained in step (2) ,according to Net priority Construct the corresponding directed acyclic graphs sequentially for routing; simultaneously acquire the congestion status of the routing space in real time and intelligently apply dynamic via penalties; then use a node cost update algorithm based on dynamic programming to solve for a minimum cost three-dimensional topology path from the source pin to the target pin in the directed acyclic graph space, and record the generated net path in the current routing scheme. Step (4) Perform congestion-driven iterative teardown and rerouting; first, set the congestion overflow threshold and the maximum number of iterations, and then perform a global evaluation of all net paths generated in step (3); first, detect the net set. If any unrouted nets exist, perform time-consuming but effective maze routing on them; otherwise, check the 3D global routing mesh. If there is a congestion overflow in the routing path; if there is no congestion overflow, the routing ends; if there is a congestion overflow, the network where the congestion overflow occurred is dismantled and rerouted, the historical penalty cost of the area is updated, and the dismantled network is sent back to step (2) for the next round of sorting and routing iteration until the iteration termination condition is met. Step (5) Output and save the final global routing result; Obtain the valid 3D topology paths of all nets after complete unraveling and re-iteration in step (4), and perform a routing integrity check; traverse the connectivity integrity of each routed net using breadth-first search to ensure that all pins pass through continuous paths. The paths are physically connected and there are no suspended segments or loops, ultimately generating a rectangular guide area that can be used in the subsequent detailed routing stage.

2. The chip-oriented global routing method based on directed acyclic graphs and congestion awareness according to claim 1, characterized in that, Step (1) specifically includes the following steps: 1-1) Read the standard cell library file LEF and the design netlist file DEF for integrated circuit design; extract all sets of nets to be routed from the input files. Obtain the physical coordinates of the source and target pins contained in each net; simultaneously, extract the physical design constraints. This includes the default routing direction, minimum line width, minimum line spacing, and via size limitations for each metal layer; 1-2) Based on the preset global wiring mesh cells The dimensions of the chip are used to uniformly divide the continuous three-dimensional physical space of the entire chip into a three-dimensional global wiring mesh. ; each They all use a unique three-dimensional coordinate system. To identify, among which and These represent the number of columns and rows in a horizontal two-dimensional plane, respectively. This represents the total number of metal layers available for wiring in the chip; 1-3) Each Abstracted as a 3D global wiring mesh diagram One of the vertices, adjacent to They are connected by edges; edges are divided into two categories, one of which is adjacent edges within the same metal layer. Two-dimensional edges with horizontal or vertical orientations between them; another type is the same between adjacent metal layers. coordinates The edge of the vertical through hole; 1-4) Calculate the 3D global wiring mesh. The physical capacity information in the data represents the upper limit of available physical cabling resources within a specific area; for connecting two adjacent... grid edges Based on the physical width of the metal layer and the minimum allowable linewidth of that layer, calculate the maximum number of available wiring tracks that the edge can pass through, denoted as the physical capacity of that edge; for Its physical capacity is defined as the average of the capacities of two adjacent grid edges in the preferred routing direction; 1-5) By introducing a dynamic via penalty mechanism, the 3D global routing mesh is calculated. The requirement information in the data represents the actual resource usage of the current cabling scheme; the requirement information consists of two parts: wiring requirements and via requirements. A congestion-aware adaptive penalty mechanism is proposed; this is achieved by introducing a dynamic coefficient. This coefficient is based on the current Connection resource utilization rate Adaptive adjustments were made; the improved requirement model was restructured as follows: in, Indicates the current connection or the current Resource utilization rate, which is the ratio of occupied resources to total capacity; It is a non-linear growth function used to represent the dynamic cost of the via; as follows: in, , , and It is a parameter; Indicates the basic penalty. This indicates the highest punishment. Indicates the center threshold. This indicates the steepness of the function.

3. The chip-oriented global routing method based on directed acyclic graphs and congestion awareness according to claim 1, characterized in that, Step (2) specifically includes the following steps: 2-1) For the set of wire meshes obtained in step (1) For multi-pin nets containing two or more pins, the Steiner minimum tree algorithm and the FLUTE algorithm are used to decompose them into multiple two-pin subnets. In subsequent processes, the subnets will inherit the priority of the parent net. 2-2) Regarding the set of wire meshes obtained in step (1) Each wire mesh Obtain the smallest circumscribed rectangle (boundary box) formed by its internal pins; calculate the semi-perimeter of the bounding box and the total number of pins of the net; define the net. Internal pin density for: in, It is a wire mesh Number of pins, It is a wire mesh The half perimeter of the bounding box, It is a positive constant used to prevent division by zero errors when degenerate meshes cause the bounding box half-perimeter to be zero; 2-3) Obtain the net The degree of congestion in the external environment is used to characterize the severity of congestion at the physical location of the network, defining the network. average congestion density for: in, Represents the underlying grid. It is a enclosure for the wire mesh. For the underlying mesh The estimated cabling congestion value; It refers to the total number of grids covered by the mesh enclosure box; 2-4) Due to the wire mesh Internal pin density and average congestion density Different physical dimensions are normalized; the wire sequence priority score of the wire mesh is evaluated. : in, and It is the value after normalization. and For line order weighting parameters; 2-5) Establish a global net priority queue based on the line order priority. Sort all the decomposed subnets to be wired in descending order of their corresponding priorities.

4. The chip-oriented global routing method based on directed acyclic graphs and congestion awareness according to claim 1, characterized in that, Step (3) specifically includes the following steps: 3-1) Constructing the topology of the enhanced directed acyclic graph: from the wire priority queue of step (2) The net with the highest priority is selected. Starting from the source pin and ending at the target pin, the net is expanded outward from its bounding box to form a local three-dimensional search sub-mesh. Within the three-dimensional search sub-mesh, a directed acyclic graph topology is constructed strictly according to the physical direction from the source pin to the target pin. Based on this directed acyclic graph, a pattern routing method is selected to perform the initial pattern routing of the net. 3-2) Before the routing search, the congestion information of each vertex in the sub-mesh of the directed acyclic graph topology is obtained in real time; for each vertical via edge, the congestion status of the bottom layer at its two-dimensional position is determined; when the regional resources are sufficient, more direct inter-layer connections are encouraged to be made using vias in non-congested areas, thereby optimizing line length and timing; when the resource utilization rate is close to or exceeds the threshold, resistance is applied to the via generation action in congested hotspot areas, forcing the mesh to find a more open area in the horizontal layer before performing inter-layer jumps, thus suppressing via flooding; 3-3) To obtain the optimal path for the network routing, perform fast updates of node costs based on dynamic programming; in the 3D global routing mesh graph In the middle, the nodes represent Each layer represents a wiring metal layer, with multiple parallel wiring tracks between layers. The connection points between adjacent layers represent vias; the minimum node cost is defined. This indicates that all relevant upstream pins are connected to the pin located at the first... Layer nodes Minimum required cabling cost; assuming a total number of layers. The root node is Then the minimum cabling cost for the entire network is For any node and the current layer The state transition equation is as follows: The state transition equation recursively calculates the cost, which consists of three parts; the first part is the substructure cost, which recursively includes the selected predecessor node. minimum cost The second part of the cost is the connection cost, which represents the cost from the predecessor node. To the current node Plane connection cost The third part of the cost is the via cost, which is represented at the node. In order to connect all the different layers that converge. and the current output layer A cost is required for vertical through-holes. The external minimum expression selects each stream. The nodes to be connected The internal minimum value expression determines the selected node. Connect to node conductor layer The equation assumes nodes There are no pins at this point, so only the cost of vias connecting the lowest and highest layers is added; 3-4) For wire mesh Run the node cost update algorithm based on dynamic programming in step 3-3) to find the optimal routing path with the minimum routing cost; map the routing path back to the 3D global routing mesh. Simultaneously, the resource requirements of all two-dimensional horizontal and vertical edges and three-dimensional via edges along this path are increased to provide the latest environmental data for subsequent network congestion sensing.

5. The chip-oriented global routing method based on directed acyclic graphs and congestion awareness according to claim 1, characterized in that, Step (4) specifically includes the following steps: 4-1) After all the nets have completed the initial routing in step (3), the first round of iteration detection is entered; firstly, it is detected whether there are unrouted nets. If there are unrouted nets, time-consuming but effective maze routing is performed on the unrouted nets. If there are no unrouted nets, it is further detected whether there are overflow nets; the three-dimensional mesh is scanned globally and the overflow amount of each edge is calculated; at the same time, it is detected whether there are congested overflow routing paths in the three-dimensional mesh. 4-2) If no overflow is found after scanning, or the current iteration number has reached the preset maximum iteration threshold, the wiring process is determined to have converged, and the process is directly jumped to step (5) for output; otherwise, the iterative wire tearing and rewiring mechanism is started. 4-3) For all detected congested edges, reverse the search to find all sets of nets occupying that edge; use a specific disconnection strategy to remove these nets from the current cabling scheme; at the same time, the edge resource requirements originally occupied by the disconnected nets will be reduced accordingly, thereby releasing the physical resources of the congested area; 4-4) To prevent the wire network from falling into the same congestion hotspot again in the next iteration, the repulsion force of the region is increased; for each edge that overflows, a historical penalty cost constant is set. When an edge overflows, the historical penalty cost of the edge is updated and added to the resource occupation of the edge, forcing the edge to actively avoid these extremely congested regions in subsequent rounds. 4-5) Re-label the removed nets with the "to be re-routed" label; and re-enter these nets into step (2), recalculate their priorities according to the updated global congestion environment, reorder them, and re-enter the global cabling space for re-routing.

6. The chip-oriented global routing method based on directed acyclic graphs and congestion awareness according to claim 1, characterized in that, Step (5) specifically includes the following steps: 5-1) Convert the array of predecessor node pointers of all nets residing in memory into a standard set of physical line segments; explicitly mark the metal layer, start coordinates, end coordinates, and three-dimensional coordinate set of each line segment as an interlayer channel via; 5-2) Format the valid three-dimensional coordinate set data in 5-1) and export it as a global routing result guide file commonly used in the field of electronic design automation. This file will be directly used as input to the detailed routing tool in the physical design backend for precise track assignment and physical connection.

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