A chip routing detailed layout optimization method based on dynamic programming

Abstract

This invention discloses a dynamic programming-based method for detailed chip circuit layout optimization. In the timing-driven detailed layout process of chip circuit routing, the method includes the following steps: static timing analysis of initial transistor positions to identify negative slack regions on critical paths, and heuristic optimization targeting these regions; adaptive search window definition: dynamically adjusting the movable range of cells based on their impact on path timing, focusing optimization on critical regions and avoiding unnecessary disturbances to non-critical regions; fine-grained cell movement based on dynamic programming: enumerating all legal cell arrangements within a local window, and accurately solving for the optimal layout scheme by combining timing cost and legality constraints. This invention ensures sufficient generalization ability under different target densities and layout resources, considering the interactions between different cells within the local area generated during the global layout stage.

Description

Technical Field

[0001] This invention belongs to the field of circuit layout technology, and in particular relates to a method for optimizing the detailed layout of chip circuits based on dynamic programming. Background Technology

[0002] In digital chip design, timing convergence is a crucial step that directly determines whether the chip can achieve its intended function after tape-out.

[0003] To improve the success rate of timing convergence, timing-driven design methods have been introduced into the placement phase. The core idea is to use timing information as a guiding factor for placement optimization, thereby providing greater optimization space for subsequent processes. However, most existing timing-driven placement methods are limited to independent adjustments of single-type cells, which has significant limitations. First, when the design scale is large, the solution space of the placement expands dramatically, and complex constraints mean that fine-grained optimization of cell positions can only rely on computationally expensive exhaustive searches, which undoubtedly slows down the design progress and increases development costs. Second, traditional optimization methods (such as Lagrange relaxation) tend to pursue local optima at each step. This "short-sighted" strategy often fails to approach the global optimum in complex circuit designs, resulting in less than ideal final results. Furthermore, existing methods often ignore the orientation information of the initial placement when optimizing timing. This lack of information may lead to inefficient iterative optimization, wasting computational resources and extending the design cycle.

[0004] While the size of the search window is a critical parameter, controlling both runtime and solution quality, its design typically requires extensive trial and error and is heavily influenced by subjective factors. Therefore, it is difficult to ensure sufficient generalization capability under varying target densities and layout resources.

[0005] Existing time-driven detailed placement methods only consider the relationship between the current target cell and the cells connected to it in the abstract time sequence diagram, without considering the interaction between different cells within the local scope generated during the global placement phase. Summary of the Invention

[0006] To address the aforementioned issues, this invention proposes a chip circuit detailed layout optimization method based on dynamic programming, which ensures sufficient generalization capability under different target densities and layout resources, taking into account the interactions between different units within the local area generated during the global layout stage.

[0007] To achieve the above objectives, the technical solution adopted by this invention is: a chip circuit detailed layout optimization method based on dynamic programming, which includes the following steps in the timing-driven detailed layout process of chip circuit routing:

[0008] Static timing analysis of the initial transistor positions identifies negative slack regions on the critical path, and heuristic optimization is carried out targeting these regions.

[0009] Adaptive search window definition: Dynamically adjust the movable range of a cell based on its impact on the path timing, so that optimization focuses on key areas and avoids unnecessary disturbances to non-critical areas;

[0010] Fine-grained cell movement based on dynamic programming: Enumerate all legal cell arrangements in a local window, and combine time cost and legality constraints to accurately solve the optimal layout scheme.

[0011] Furthermore, the input consists of the initial cell coordinates and their network connection information after global layout, and the negative slack path and key units under the current layout are identified through static timing analysis.

[0012] Furthermore, during the adaptive search window definition process, when performing local optimization on a certain region or certain units in the circuit, a spatial range is defined; within this range, the algorithm allows a selected set of cells to move, exchange, or rearrange between legal positions to optimize timing, line length, and congestion metrics.

[0013] Furthermore, the determination criteria in the adaptive search window definition process are as follows:

[0014]

[0015] For the cells that have been moved by the previous stage, n cells are selected in sequence according to the importance of the pins to construct a rectangle that completely surrounds these cells.

[0016] Furthermore, during the adaptive search window definition process,

[0017] Tail insertion is used to sequentially read the coordinate data generated in the initial black-box process into the initial doubly linked list. Starting from the head of the initial doubly linked list, each time a cell is added to the current rectangle, it is necessary to calculate whether the distance from the cell to the center of the rectangle exceeds the Manhattan distance limit. The distance constraint formula is as follows:

[0018]

[0019] lim x With lim y These represent the displacement limits of the current transistor along the horizontal and vertical axes of the entire layout, respectively. Max.Disp is a hyperparameter that constrains the detailed layout to avoid excessive perturbation of the global layout.

[0020] If the limit is exceeded, the cells are temporarily stored in an auxiliary list; once n cells are queued and a rectangle is constructed, the cells in the auxiliary list are reinserted in order to the head of the initial doubly linked list; this process is repeated until no more rectangles can be constructed in the original doubly linked list.

[0021] Furthermore, a dynamic programming unit movement method based on trigger position reconstruction is established, including:

[0022] By moving triggers within a reasonable range, the propagation delay between adjacent paths can be dynamically adjusted, thereby fixing setup and hold violations and optimizing the overall slack distribution without introducing illegal layouts.

[0023] Furthermore, the relocation problem of triggers in a local region is modeled as a minimum cost permutation problem with blocking constraints, and a dynamic programming strategy is introduced to solve it.

[0024] Furthermore, dynamic programming strategies include:

[0025] Static timing analysis is used to extract adjacent paths with violations. Taking the final logic unit c1 of path A and the first logic unit c2 of path B as reference points, two feasible placement regions centered on c1 and c2 are calculated using the slack value. The Manhattan distance d is determined by subtracting the timing cost difference calculated based on the Elmore delay model formula from the initial distance between the current position of the trigger and the reference point. If the two rectangular regions overlap, the intersection is the target region where the trigger can legally move. Optimization is performed within this region, reducing the propagation delay of path A and increasing the delay of path B to achieve a balance between setup and hold violations.

[0026] Furthermore, to find the optimal trigger placement location within the feasible placement region, the feasible placement region is discretized into an r×c two-dimensional grid, and all blocked regions are marked as unavailable regions. Subsequently, a three-dimensional dynamic programming table dp[n+1][r+1][c+1] is constructed, where dp[i][j][k] represents the minimum cost of placing the i-th trigger at position (j,k). The cost function comprehensively considers factors including path slack, wiring cost, and congestion factors. During the state transition process, all illegal positions are skipped, and the optimal predecessor position is recorded. Finally, the complete trigger placement path is reconstructed through backtracking.

[0027] Furthermore, in each local flip-flop adjustment, the clock network and path delay of the entire circuit are not immediately updated. Instead, it is assumed that the current combinational logic structure is fixed and the delay change is locally effective. Subsequently, the global timing correction is performed through the proposed LCB reallocation strategy.

[0028] The beneficial effects of adopting this technical solution are:

[0029] This invention designs an adaptive window size determination mechanism, which solves the problem of difficulty in determining the window size in existing search window algorithms, achieving a trade-off between running speed and quality. The efficient and adaptive determination of the search window size solves the problem of window design relying on extensive trial and error and subjective factors. Sufficient generalization ability is achieved under different target densities and layout resources.

[0030] By solving the problem of determining the search window size, the problem of determining the search space size is solved. For cell movements with a defined search space, an intuitive approach is to decompose them into subproblems and solve them sequentially. Clearly, the solutions to these subproblems are interdependent and can contribute to solving a larger problem. To leverage the interrelationships between cells, a dynamic programming-based cell movement is used, treating all rows and stations within the layout area occupied by each rectangle as the input grid. Cells within rectangles that move during the current black-box process are considered movable cells. Macros and cells that do not move within the grid are considered blocks, representing areas where placement is not possible. The final output is a set of positional solutions enhanced by local dynamic programming.

[0031] This invention utilizes dynamic programming-based layout optimization to efficiently determine the optimal placement of elements. By constructing a three-dimensional dynamic programming state space, it comprehensively considers layout costs, temporal constraints, and mesh feasibility, avoiding the reliance on local or brute-force searches found in traditional methods. Leveraging the global optimization characteristics of dynamic programming, we can ensure the convergence of optimal solutions in complex layout environments and efficiently determine the optimal placement path through a backtracking mechanism, thereby improving layout quality and reducing computational costs. Attached Figure Description

[0032] Figure 1 This is a schematic flowchart of a chip circuit detailed layout optimization method based on dynamic programming according to the present invention.

[0033] Figure 2 This is a circuit arrangement diagram under extreme conditions in an embodiment of the present invention;

[0034] Figure 3 The diagram shows the traditional search window definition in an embodiment of the present invention. (a) shows the dynamically planned movement range when a search window is constructed with two consecutive transistors, and (b) shows the dynamically planned movement range when a search window is constructed with ten consecutive transistors.

[0035] Figure 4The diagram shows the size of the optional region in the embodiment of the present invention. (c) is a search window constructed with two consecutive transistors, and (d) is the dynamically planned movement range when a search window is constructed with ten consecutive transistors.

[0036] Figure 5 This is an example diagram of trigger movement in an embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below with reference to the accompanying drawings.

[0038] In this embodiment, see Figure 1 As shown, this invention proposes a chip circuit detailed layout optimization method based on dynamic programming, which includes the following steps in the timing-driven detailed layout process of chip circuit routing:

[0039] Static timing analysis of the initial transistor positions identifies negative slack regions on the critical path, and heuristic optimization is carried out targeting these regions.

[0040] However, traditional black-box optimization algorithms such as simulated annealing (SA) and particle swarm optimization (PSO) are prone to getting trapped in local optima or generating a large number of invalid perturbations due to their strong randomness and slow convergence, which seriously affects the optimization quality and efficiency. To overcome this deficiency, we introduce two key enhancement strategies: adaptive search window determination and dynamic programming-based cell movement.

[0041] Adaptive search window definition: The movable range of a cell is dynamically adjusted according to its impact on the path timing, so that optimization focuses on key areas and avoids unnecessary disturbances to non-critical areas.

[0042] Fine-grained cell movement based on dynamic programming: Enumerate all legal cell arrangements in a local window, combine time-series cost and legality constraints to accurately solve the optimal layout scheme, significantly improving the quality and stability of the solution.

[0043] Through these two enhancement measures, the process not only effectively avoids the inherent disadvantages of black-box algorithms, but also significantly improves the convergence speed and final timing performance of layout optimization.

[0044] As an optimization scheme in the above embodiment, the input consists of the initial cell coordinates and their network connection information after global layout, and negative slack paths and key units under the current layout are identified through static timing analysis. These key units constitute the core region of optimization and will serve as candidate perturbation objects in the heuristic optimization stage.

[0045] As an optimization scheme of the above embodiment, in the process of defining the adaptive search window, when performing local optimization on a certain region or some units in the circuit, a spatial range is defined; within this range, the algorithm allows a selected group of cells to move, exchange, or rearrange between legal positions to optimize timing, line length, and congestion indicators.

[0046] Traditional search window algorithms brute-force search for the optimal location within a local area. However, due to the large scale and complex structure of circuits, fixed-size windows are difficult to adapt to different scenarios, especially given the significant trade-off between area and computational cost. Furthermore, window size, as a key hyperparameter, often requires extensive experimental tuning and is highly dependent on human experience.

[0047] A key observation based on static timing analysis is that in VLSI static timing analysis, timing propagates from the main input layer to the main output layer. Therefore, the relaxation of the main input is always greater than or equal to the relaxation of the main output. Furthermore, for timing-critical paths, the most critical cells tend to physically cluster (not strictly). Figure 2 As shown, an extreme case arises when cells on the critical path (from PI to PO) are all in the same row. Clearly, cells with similar temporal criticality are usually closer to each other. Therefore, we introduce the concept of importance:

[0048] The determination criteria in the adaptive search window definition process are as follows:

[0049]

[0050] For the cells that have been moved by the previous stage, n cells are selected sequentially according to their pin importance to construct a rectangle that completely surrounds these cells, such as... Figure 3 As shown:

[0051] Figure 3 In a design with millions of gates, the initial layout for the first iteration is obtained based on a heuristic algorithm, where red nodes represent each transistor unit. Substituting the n units into a clustering algorithm yields a rectangular representation (the size of the solution space during subsequent moves), with green rectangles indicating areas less than or equal to... 2×li m x ×2×lim y (The meanings of the variables are shown in Formula 4), while the purple rectangle represents the area greater than that in this equation.

[0052] It is worth noting that there is a positive correlation (not strictly) between the size of n and the area of ​​the constructed rectangle. This "not strictly" refers to the fact that even when constructing a rectangle with two units per cluster (n=2), the rectangle area can still be excessively large (similar temporal critical values, but with significant differences), as... Figure 3 (a) shows the purple rectangle in the neutron. This is unacceptable for the search window algorithm. The above problem is solved by the following method.

[0053] Tail insertion is used to sequentially read the coordinate data generated in the initial black-box process into the initial doubly linked list. Starting from the head of the initial doubly linked list, each time a cell is added to the current rectangle, it is necessary to calculate whether the distance from the cell to the center of the rectangle exceeds the Manhattan distance limit. The distance constraint formula is as follows:

[0054]

[0055] lim x With lim y These represent the displacement limits of the current transistor along the horizontal and vertical axes of the entire layout, respectively. Max.Disp is a hyperparameter that constrains the detailed layout to avoid excessive perturbation of the global layout.

[0056] If the limit is exceeded, the cells are temporarily stored in an auxiliary list; once n cells are queued and a rectangle is constructed, the cells in the auxiliary list are re-inserted in order at the head of the initial doubly linked list (the earlier cell in the temporary list is inserted closer to the head of the original list); this process is repeated until no more rectangles can be constructed in the original doubly linked list (no pair of nodes is within the Manhattan distance limit). The intuitive result is as follows: Figure 4 As shown, with Figure 3 A comparison shows that the embodiments of the present invention can still maintain a good balance of the moving range even when the moving range is constructed in groups of 10 consecutive transistors.

[0057] By employing the aforementioned adaptive search window construction strategy, we effectively overcome three major problems faced by traditional fixed-window methods in large-scale circuit layout: first, the window size does not match the circuit structure, resulting in some key areas being uncovered or causing redundant searches; second, parameters are highly dependent on manual tuning, making it difficult to adapt to different design scenarios; and third, when the physical distribution of key units is discrete, a fixed window may lead to solution space expansion, severely impacting optimization efficiency. Based on temporal importance and physical adjacency, we dynamically construct a set of compact, temporally relevant, and controllable local rectangular regions. These regions not only effectively focus on critical path units, significantly reducing invalid disturbances, but also provide structurally clear and boundary-defined inputs for subsequent dynamic programming-based unit movements, thereby significantly improving optimization quality, operational efficiency, and the overall scalability of the algorithm. The final output is a series of range coordinates of search sub-regions satisfying adaptive constraints, which can be directly used for high-quality layout optimization in the next stage.

[0058] As an optimization of the above embodiments, after limiting the search window range, in order to improve the effect of timing optimization, a dynamic programming unit movement method based on trigger position reconstruction is established, including:

[0059] like Figure 5 As shown, the core idea of ​​this method is to dynamically adjust the propagation delay between adjacent paths by moving triggers within a reasonable range, thereby fixing setup and hold violations and optimizing the overall slack distribution without introducing illegal layouts.

[0060] To efficiently execute the movement operation of the trigger, the relocation problem of the trigger in the local region is modeled as a minimum cost permutation problem with blocking constraints, and a dynamic programming strategy is introduced to solve it.

[0061] Dynamic programming strategies include:

[0062] Static timing analysis is used to extract adjacent paths with violations. Taking the final logic unit c1 of path A and the first logic unit c2 of path B as reference points, two feasible placement regions centered on c1 and c2 are calculated using the slack value. The Manhattan distance d is determined by subtracting the timing cost difference calculated based on the Elmore delay model formula from the initial distance between the current position of the trigger and the reference point. If the two rectangular regions overlap, the intersection is the target region where the trigger can legally move. Optimization is performed within this region, reducing the propagation delay of path A and increasing the delay of path B to achieve a balance between setup and hold violations.

[0063] To find the optimal trigger placement location within the feasible placement region, the feasible placement region is discretized into an r×c two-dimensional grid, and all blocking regions (such as macrocells, unplaceable cells, etc.) are marked as unusable regions. Then, a three-dimensional dynamic programming table dp[n+1][r+1][c+1] is constructed, where dp[i][j][k] represents the minimum cost of placing the i-th trigger at position (j,k). The cost function comprehensively considers factors including path slack, wiring cost, and congestion. During state transitions, all illegal positions are skipped, and the optimal predecessor position is recorded. Finally, the complete trigger placement path is reconstructed through backtracking. This method effectively transforms the trigger reconstruction problem into a well-structured and efficiently solvable dynamic optimization problem, significantly improving the quality of the solution and the convergence speed.

[0064] In the actual process, to avoid resource waste caused by excessive iteration, the concept of delayed update from deep learning was adopted. During each local trigger adjustment, the clock network and path delay of the entire circuit are not immediately updated. Instead, it is assumed that the current combinational logic structure is fixed, and the delay change is locally effective. Subsequently, a global timing correction is performed using the proposed LCB reallocation strategy. This approach avoids redundant calculations, improves system efficiency, and ensures the timing convergence and global consistency of the final layout.

[0065] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A chip circuit detailed layout optimization method based on dynamic programming, characterized in that, The timing-driven detailed layout process for chip circuit routing includes the following steps: Static timing analysis of the initial transistor positions identifies negative slack regions on the critical path, and heuristic optimization is carried out targeting these regions. Adaptive search window definition: Dynamically adjust the movable range of a cell based on its impact on the path timing, so that optimization focuses on key areas and avoids unnecessary disturbances to non-critical areas; Fine-grained cell movement based on dynamic programming: Enumerate all legal cell arrangements in a local window, and combine time-series cost and legality constraints to accurately solve the optimal layout scheme; In the process of defining the adaptive search window, when performing local optimization on a certain region or certain units in the circuit, a spatial range is defined; within this range, the algorithm allows a selected group of cells to move, exchange, or rearrange between legal positions to optimize timing, line length, and congestion metrics. The determination criteria in the adaptive search window definition process are as follows: ； ； For the cells that have been moved by the previous stage, n cells are selected in sequence according to the importance of the pins to construct a rectangle that completely surrounds these cells; During the adaptive search window definition process, Tail insertion is used to sequentially read the coordinate data generated in the initial black-box process into the initial doubly linked list. Starting from the head of the initial doubly linked list, each time a cell is added to the current rectangle, it is necessary to calculate whether the distance from the cell to the center of the rectangle exceeds the Manhattan distance limit. The distance constraint formula is as follows: ； lim x With lim y These are the displacement limits of the current transistor in the horizontal and vertical directions of the entire layout, respectively; Max.Disp is a hyperparameter that constrains the detailed layout to avoid excessive disturbance to the global layout. If the limit is exceeded, the cells are temporarily stored in an auxiliary list; once n cells are queued and a rectangle is constructed, the cells in the auxiliary list are reinserted in order to the head of the initial doubly linked list; this process is repeated until no more rectangles can be constructed in the original doubly linked list.

2. The chip circuit detailed layout optimization method based on dynamic programming according to claim 1, characterized in that, The input consists of the initial cell coordinates and network connection information after global layout, and the negative slack path and key cells under the current layout are identified through static timing analysis.

3. The chip circuit detailed layout optimization method based on dynamic programming according to claim 1, characterized in that, A dynamic programming cell movement method based on trigger position reconstruction is established, including: By moving triggers within a reasonable range, the propagation delay between adjacent paths can be dynamically adjusted, thereby fixing setup and hold violations and optimizing the overall slack distribution without introducing illegal layouts.

4. The chip circuit detailed layout optimization method based on dynamic programming according to claim 3, characterized in that, The problem of relocating triggers within a local region is modeled as a minimum-cost permutation problem with blocking constraints, and a dynamic programming strategy is introduced to solve it.

5. The chip circuit detailed layout optimization method based on dynamic programming according to claim 4, characterized in that, Dynamic programming strategies include: Static timing analysis is used to extract adjacent paths with violations. Taking the final logic unit c1 of path A and the first logic unit c2 of path B as reference points, two feasible placement regions centered on c1 and c2 are calculated using the slack value. The Manhattan distance d is determined by subtracting the timing cost difference calculated based on the Elmore delay model formula from the initial distance between the current position of the trigger and the reference point. If these two rectangular regions overlap, the intersection is the target region where the trigger can legally move. Optimization is performed within this region, reducing the propagation delay of path A and increasing the delay of path B to achieve a balance between setup and hold violations.

6. The chip circuit detailed layout optimization method based on dynamic programming according to claim 5, characterized in that, To find the optimal trigger placement location within the feasible placement area, the feasible placement area is discretized into an r×c two-dimensional grid, and all blocked areas are marked as unusable areas; Subsequently, a three-dimensional dynamic programming table dp[n+1][r+1][c+1] is constructed, where dp[i][j][k] represents the minimum cost of placing the i-th trigger at position (j,k). The cost function comprehensively considers factors including path slack, wiring cost, and congestion. During the state transition process, all illegal positions are skipped, and the optimal predecessor position is recorded. Finally, the complete trigger placement path is restored by backtracking.

7. The chip circuit detailed layout optimization method based on dynamic programming according to claim 6, characterized in that, In each local flip-flop adjustment, the clock network and path delay of the entire circuit are not updated immediately. Instead, it is assumed that the current combinational logic structure is fixed and the delay change is locally effective. Subsequently, the global timing correction is performed through the proposed LCB reallocation strategy.

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