A method and apparatus for VLSI global layout timing optimization
By representing the area to be laid out as a target mesh and utilizing static temporal analysis and virtual mesh optimization methods, the problem of insufficient temporal constraints in global layout is solved, thereby improving the layout quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI LIXIN SOFTWARE TECH CO LTD
- Filing Date
- 2022-11-02
- Publication Date
- 2026-05-29
AI Technical Summary
Existing layout algorithms cannot fully consider complex timing constraints during the global layout process, resulting in a decrease in the overall quality of the global layout solution.
The area to be laid out is represented as multiple non-overlapping target meshes by unconstrained optimization based on line length and density. The critical path is obtained by static temporal analysis, and the delay on the critical path is optimized by the temporal path optimization method based on virtual mesh. The objective function is optimized by preprocessing by inverting the Jacobi matrix.
It improves the optimization of timing and line length, enhances the overall quality of the global layout solution, and solves the problem that complex timing constraints cannot be fully considered during the global layout process.
Smart Images
Figure CN115618781B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, and specifically to a VLSI global layout timing optimization method, apparatus, computer device, and computer-readable storage medium. Background Technology
[0002] With the continuous increase in the scale of integrated circuit design and the increasingly complex timing constraints, achieving timing closure has become increasingly challenging for Very Large Scale Integration (VLSI) design flows. Current placement algorithms are mainly divided into three types: simulated annealing, partitioning-based methods, and analytical placement methods. Compared with simulated annealing and partitioning-based methods, analytical placement methods have been recognized by both industry and academia for their superior solution quality and efficiency. Analytical placement methods are divided into three main optimization stages: Global Placement (GP), Legalization (LG), and Detailed Placement (DP). Global Placement ignores overlaps between cells, finding the optimal position for each cell, and the quality of the global placement solution largely determines the quality of the final placement solution. Legalization removes all design rule violations while preserving the global placement solution as much as possible. Detailed Placement further optimizes the quality of the solution after legalization.
[0003] Timing optimization techniques in the global layout process are mainly divided into two types: wire-net based methods and path-based methods. Among them, wire-net based methods convert timing information into wire weights or constraints; path-based methods directly optimize the delay on the critical path through mathematical programming problems; compared with wire-net based methods, path-based methods are more likely to obtain high-quality solutions.
[0004] Existing placement algorithms typically use bus length as the primary optimization target, which may cause the overall design process to fail to meet timing constraints, thereby reducing the quality of the overall global placement solution.
[0005] Currently, no effective solution has been proposed to address the problem that existing layout algorithms cannot fully consider complex timing constraints during the global layout process. Summary of the Invention
[0006] In view of this, embodiments of this specification provide a VLSI global layout timing optimization method, apparatus, computer device, and computer-readable storage medium to solve the problem that existing layout algorithms cannot fully consider complex timing constraints during the global layout process.
[0007] To address the aforementioned technical problems, a first aspect of the present invention provides a VLSI global layout timing optimization method, comprising:
[0008] Unconstrained optimization based on line length and density represents the region to be laid out as multiple non-overlapping target meshes;
[0009] All critical paths in the target mesh are obtained through static time series analysis;
[0010] A timing path optimization method based on virtual nets optimizes the latency on the critical path.
[0011] In some embodiments, the timing path optimization method based on virtual nets optimizes the latency on the critical path by including:
[0012] A plurality of first timing arcs are generated based on the critical path, wherein the first timing arc is a line connecting two adjacent first units on the critical path;
[0013] The first timing arc, which has a higher importance than a first preset level, is used as the first initial timing arc in the next optimization process to optimize the delay on the critical path.
[0014] In some embodiments, using the first timing arc, which has a higher importance than a first preset level, as the first initial timing arc for the next optimization process includes:
[0015] Obtain several attributes corresponding to each first time arc, wherein the several attributes include at least times, pSlack, pDis and aLength, times represents the number of times the first time arc occurs, pSlack represents the worst delay in the critical path containing the first time arc, pDis represents the worst Manhattan distance in the critical path containing the first time arc, and aLength represents the length of the first time arc.
[0016] The importance of each of the first time-series arcs is calculated based on the aforementioned attributes, using the following formula:
[0017]
[0018]
[0019] in, Represents the weighted weight corresponding to the first time-series arc of the i-th order, criticality(arc i The significance of the first time-series arc is represented by .
[0020] In some embodiments, a line length function and a density function are used as the objective function to represent the region to be laid out as multiple non-overlapping target meshes using unconstrained optimization based on line length and density. The objective function includes:
[0021]
[0022] in, For smooth lines, For a smooth density function, This represents the density weight.
[0023] In some embodiments, the VLSI global layout timing optimization method further includes:
[0024] When optimizing the objective function using gradient descent, the objective function is preprocessed and optimized using the inversion of the Jacobi matrix. Specifically, the gradient of each second unit during gradient descent optimization is:
[0025] .
[0026] In some embodiments, the VLSI global layout timing optimization method further includes:
[0027] Obtain several non-critical paths in the target grid;
[0028] A plurality of second timing arcs are generated based on a plurality of non-critical paths, wherein the second timing arc is a line connecting two adjacent third units on the non-critical path;
[0029] Select several target time arcs from the plurality of second time arcs, wherein the target time arcs are second time arcs with a length greater than a preset length and a level lower than a preset level;
[0030] The target timing arc is assigned a new weight, and the target timing arc with a higher importance than the second preset level is used as the second initial timing arc in the next optimization process to optimize the delay on the non-critical path.
[0031] In some of these embodiments, assigning new weights to the target temporal arc includes:
[0032] A specified weight is assigned to the target time series arc, wherein the formula for calculating the specified weight is as follows:
[0033]
[0034] Where, weight factor Here are the preset weighting factors, base is the preset baseline value, remain is the preset retention value, and level is the preset weighting factor. arc For level, level max For the maximum level, length arc For length, length max This is the maximum length.
[0035] A second aspect of the present invention provides a VLSI global layout timing optimization apparatus, comprising:
[0036] A representation unit is used to represent the region to be laid out as multiple non-overlapping target meshes based on unconstrained optimization of line length and density;
[0037] The acquisition unit is used to acquire all critical paths in the target mesh through static time series analysis;
[0038] An optimization unit is used to optimize the latency on the critical path using a timing path optimization method based on a virtual net.
[0039] A third aspect of the present invention provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the VLSI global layout timing optimization method as described in the first aspect.
[0040] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the VLSI global layout timing optimization method as described in the first aspect.
[0041] Compared with existing technologies, the VLSI global layout timing optimization method of the present invention represents the region to be laid out as multiple non-overlapping target meshes through unconstrained optimization based on line length and density; obtains all critical paths in the target meshes through static timing analysis; and optimizes the delay on the critical paths based on the timing path optimization method of virtual wire mesh. This solves the problem that existing technologies cannot fully consider complex timing constraints in the global layout process, further improves the optimization of timing and line length, and improves the quality of the overall solution of global layout. Attached Figure Description
[0042] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 This is a flowchart of the VLSI global layout timing optimization method according to an embodiment of the present invention;
[0044] Figure 2 This is a schematic diagram of the target unit and the area to be laid out in an embodiment of the present invention;
[0045] Figure 3 This is a schematic diagram of the critical path in an embodiment of the present invention;
[0046] Figure 4 This is a flowchart illustrating the optimization of the critical path in an embodiment of the present invention;
[0047] Figure 5 This is a schematic diagram of the first timing arc (first-level timing arc) according to an embodiment of the present invention;
[0048] Figure 6 This is a schematic diagram of the extended algorithm for the first temporal arc according to an embodiment of the present invention;
[0049] Figure 7 This is a flowchart illustrating the determination of ARC importance on the critical path in an embodiment of the present invention;
[0050] Figure 8 This is a flowchart illustrating the construction and optimization of the objective function in an embodiment of the present invention;
[0051] Figure 9 This is a flowchart of timing optimization for non-critical paths in an embodiment of the present invention;
[0052] Figure 10 This is a structural block diagram (I) of the VLSI global layout timing optimization device according to an embodiment of the present invention;
[0053] Figure 11 This is a structural block diagram (II) of the VLSI global layout timing optimization device according to an embodiment of the present invention;
[0054] Figure 12 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention;
[0055] Figure 13 This is a flowchart illustrating the global layout of an embodiment of the present invention;
[0056] Figure 14 This is a flowchart illustrating the critical path optimization process in an embodiment of the present invention. Detailed Implementation
[0057] The embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0058] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0059] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0060] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0061] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.
[0062] To address the issue that existing timing optimization techniques in global layout processes cannot adequately consider complex timing constraints, this invention provides a VLSI global layout timing optimization method. This method transforms the VLSI global layout problem into a mathematical model that simultaneously considers line length and density. Based on this, a preprocessing technique different from existing technologies is used to improve the convergence of the global layout. At the same time, a virtual path optimization method is used to optimize the delay on the timing critical path, thereby improving the optimization of timing and line length and enhancing the overall solution quality in the global layout process.
[0063] Example 1
[0064] Figure 1 This is a flowchart of the VLSI global layout timing optimization method according to an embodiment of the present invention, as follows: Figure 1 As shown, the VLSI global layout timing optimization method includes:
[0065] Step S102: Based on the unconstrained representation of line length and density, the area to be laid out is represented as multiple non-overlapping target meshes;
[0066] Step S104: Obtain all critical paths in the target mesh through static time series analysis;
[0067] Step S106: Optimize the latency on the critical path using a timing path optimization method based on virtual wire mesh.
[0068] Before step S102, critical paths and non-critical paths need to be divided into the target grid to facilitate the acquisition of critical paths or non-critical paths.
[0069] In step S102, the line length is the bus length of the area to be laid out, and the density is the component density of the area to be laid out in the global layout.
[0070] In some of these embodiments, the number of target grids can be set according to the size of the area to be laid out, the number of components in the area to be laid out, or a combination of both.
[0071] like Figure 2 As shown, Figure 2 The diagram illustrates how the area to be laid out is represented as multiple non-overlapping target grids.
[0072] In step S104, during each timing iteration, all critical paths are obtained through the Static Timing Analysis (STA) engine to facilitate subsequent optimization of critical path delays, enabling timely intervention in timing optimization of the global layout so that the global layout results meet timing constraints.
[0073] like Figure 3 As shown, Figure 3 The diagram illustrates the critical paths between target grids.
[0074] in, Figure 3 The diagram only illustrates one critical path and does not represent all critical paths in the embodiments of the present invention.
[0075] Step S106 is used to optimize the delay on the critical path and reduce the latency on the critical path so as to make the solution of the global layout more reasonable and thus improve the quality of the global layout solution.
[0076] Through steps S102 to S106, the global layout problem is transformed into an unconstrained optimization model that simultaneously considers line length and density. By optimizing the critical path, the problem that complex temporal constraints cannot be fully considered in the global layout process in the prior art is solved, further improving the optimization of temporal and line length and improving the overall quality of the global layout solution.
[0077] Figure 4 This is a flowchart illustrating the optimization of the critical path in an embodiment of the present invention, such as... Figure 4 As shown, this specification provides an embodiment of a method using virtual nets to optimize the selected time arc (ARC) on the critical path. Specifically, the timing path optimization method based on virtual nets to optimize the latency on the critical path may include:
[0078] Step S202: Generate several first time arcs based on the critical path, wherein the first time arc is the line connecting two adjacent first units on the critical path;
[0079] Step S204: Use the first timing arc with an importance level higher than the first preset level as the first initial timing arc for the next optimization process to optimize the delay on the critical path.
[0080] For step S202, in each timing iteration, all critical paths are first obtained through the static timing analysis (STA) engine, and then all first timing arcs are generated.
[0081] like Figure 5 As shown, Figure 5 The diagram illustrates the first-order arc (first-order arc) on the critical path.
[0082] Figure 6 This is an illustrative algorithm of an embodiment of the present invention, used for the extension of the first timing arc.
[0083] In some of these embodiments, each critical path can generate at least one first temporal arc.
[0084] The first unit is a component unit on the critical path.
[0085] Step 204 includes the following steps:
[0086] Step 204a: Obtain the importance of all first-sequence arcs;
[0087] Step 204b: Sort all the first time-series arcs according to their importance, that is, sort all the first time-series arcs from most important to least important, and set a first preset level;
[0088] Step 204c: Use the first timing arc with an importance level higher than the first preset level as the first initial timing arc in the next optimization process to optimize the delay on the critical path.
[0089] In step 204b, the first preset degree is a preset importance level. The first preset degree can be flexibly set. Generally speaking, the first preset degree is a higher level of importance.
[0090] For example, if all first time arcs are divided into 1 to 10 levels from important to unimportant, the first preset level can be set to level 2. Thus, after generating several first time arcs, the first time arc with a higher importance level than level 2 can be used as the first initial time arc for the next optimization process to optimize the delay on the critical path.
[0091] In some of these embodiments, there is at least one first initial timing arc.
[0092] By taking steps S202 to S204, and obtaining each timing arc on the critical path, and sorting and optimizing the timing arcs, the delay on the critical path can be optimized to improve the quality of the global layout solution.
[0093] Figure 7 This is a flowchart illustrating the determination of ARC importance on the critical path in an embodiment of the present invention, such as... Figure 7 As shown, the importance of obtaining the first time arc includes:
[0094] Step S302: Obtain several attributes corresponding to each first time arc, wherein the several attributes include at least times, pSlack, pDis and aLength;
[0095] Step S304: Calculate the importance of each first time arc based on several attributes.
[0096] In step S302, times represents the number of occurrences of each first time arc, pSlack represents the worst delay in the critical path containing the first time arc, pDis represents the worst Manhattan distance in the critical path containing the first time arc, and aLength represents the length of the first time arc.
[0097] In step S304, the formula for calculating the importance of the first timing arc is as follows:
[0098]
[0099]
[0100] in, Represents the weighted weight corresponding to the first time-series arc of the i-th order, criticality(arc i The significance of the first time-series arc is represented by .
[0101] Through steps S302 to S304, several attributes of the first time arc are obtained, and the importance of the first time arc is calculated based on these attributes. This allows the first time arcs to be sorted according to their importance, so that the corresponding first time arc can be selected as the first initial time arc for the next optimization process.
[0102] Figure 8 This is a flowchart of the objective function processing in an embodiment of the present invention, such as... Figure 8 As shown, in unconstrained optimization based on line length and density, where the region to be laid out is represented as multiple non-overlapping target meshes, the objective function used in temporal optimization can be set through the following steps:
[0103] Step S402: Construct the objective function from the line length function and the density function, and represent the area to be laid out as multiple non-overlapping target meshes using unconstrained optimization based on line length and density.
[0104] In step S402, the objective function includes:
[0105]
[0106] in, For smooth lines, For a smooth density function, This represents the density weight.
[0107] In step S402, the objective function is constructed based on the line length function and the density function. The density function is then added to the objective function after weighting coefficients. This not only takes into account the line length and density of the global layout, but also the influence of density in the global layout, thus making it easier to obtain the optimal solution of the global layout.
[0108] Furthermore, when optimizing the objective function, traditional layouts typically use Hessian matrix inversion for preprocessing. However, considering that the aforementioned objective equation is nonlinear, computational efficiency decreases and convergence speed may be slow. Therefore, this specification also provides a more advanced preprocessing technique to replace the traditional preprocessing technique.
[0109] like Figure 8 As shown, the preprocessing for gradient descent on the objective function can include the following steps:
[0110] Step S404: When optimizing the objective function using gradient descent, preprocess and optimize the objective function by inverting the Jacobi matrix.
[0111] For step S404, during the global layout process, when using gradient descent to optimize the objective function, the gradient of each second unit is:
[0112] .
[0113] By replacing the Hessian matrix with the Jacobi matrix in step S404, computational efficiency is improved, while the stability and convergence of the global layout process are also enhanced.
[0114] Figure 9 This is a flowchart of timing optimization for non-critical paths in an embodiment of the present invention, such as... Figure 9 As shown, the selected time arc (ARC) on non-critical paths can be optimized by using virtual nets. Specifically, the VLSI global layout timing optimization method can also include:
[0115] Step S502: Obtain several non-critical paths in the target mesh;
[0116] Step S504: Generate several second time arcs based on non-critical paths, wherein the second time arc is the line connecting two adjacent third units on the non-critical path;
[0117] Step S506: Select a number of target time arcs from a number of second time arcs, wherein the target time arcs are second time arcs with a length greater than a preset length and a level lower than a preset level;
[0118] Step S508: Assign new weights to the target timing arcs, so that the target timing arcs with a higher importance than the second preset level are used as the second initial timing arcs in the next optimization process, so as to optimize the delay on non-critical paths.
[0119] In step S504, at least one second timing arc is generated on each non-critical path.
[0120] The third unit is a component unit on a non-critical path.
[0121] In step S506, when selecting a number of target timing arcs, priority should be given to selecting second timing arcs that are longer (i.e., longer than the preset length) and have a lower level (i.e., lower than the preset level), so as to optimize the second timing arcs to avoid delay degradation on non-critical paths during the optimization of critical paths.
[0122] In the case of optimizing the target timing arc, a 2-pin virtual net can be created to optimize the target timing arc.
[0123] In step S506, the preset length can be the second timing arc with a length ratio of the top 50% as the target timing arc.
[0124] In step S506, when a preset level is set, since the second timing arc may appear in different critical paths, and the level of the same second timing arc is different in different critical paths during the timing arc expansion process, multiple levels will be generated. The lower the level, the closer the relationship between the second timing arc and the corresponding critical path.
[0125] In step S508, a specified weight is set for the target time arc, wherein the calculation formula for the specified weight is as follows:
[0126]
[0127] Where, weight factor Here are the preset weighting factors, base is the preset baseline value, remain is the preset retention value, and level is the preset weighting factor. arc For level, level max For the maximum level, length arc For length, length max This is the maximum length.
[0128] Among them, when a specified weight is set for the target time arc, a higher weight should be set for the target time arc, that is, the importance of the target time arc should reach the second preset level.
[0129] Figure 10 This is a structural block diagram (I) of the VLSI global layout timing optimization device according to an embodiment of the present invention, as shown below. Figure 10 As shown, a VLSI global layout timing optimization device 90 of the present invention includes:
[0130] Representation element 91 is used for unconstrained optimization based on line length and density to represent the region to be laid out as multiple non-overlapping target meshes;
[0131] Acquisition unit 92 is used to acquire all critical paths in the target mesh through static time series analysis;
[0132] Optimization unit 93 is used to optimize the latency on the critical path using a timing path optimization method based on virtual wire mesh.
[0133] In some embodiments, representation unit 91 is further configured to construct a new objective function from the line length function and density function, so as to represent the region to be laid out as multiple non-overlapping target meshes based on unconstrained optimization of line length and density. The new objective function includes:
[0134]
[0135] in, For smooth lines, For a smooth density function, This represents the density weight.
[0136] In some embodiments, the optimization unit 93 is further configured to: generate a plurality of first timing arcs based on the critical path, wherein the first timing arc is a line connecting two adjacent first units on the critical path; and use the first timing arc with an importance higher than a first preset level as the first initial timing arc for the next optimization process to optimize the delay on the critical path.
[0137] In some embodiments, the optimization unit 93 is further configured to: obtain several attributes corresponding to each first time arc, wherein the several attributes include at least the following attributes: times, pSlack, pDis, and aLength, where times represents the number of times the first time arc occurs, pSlack represents the worst latency in the critical path containing the first time arc, pDis represents the worst Manhattan distance in the critical path containing the first time arc, and aLength represents the length of the first time arc; and calculate the importance corresponding to each first time arc based on the several attributes.
[0138] In some embodiments, the optimization unit 93 is further configured to: calculate the importance of each first timing arc based on the following formula.
[0139]
[0140]
[0141] in, Represents the weighted weight corresponding to the first time-series arc of the i-th order, criticality(arc i The significance of the first time-series arc is represented by .
[0142] In some embodiments, the optimization unit 93 is further configured to: optimize the objective function using gradient descent, and preprocess the objective function using the inversion of the Jacobi matrix, wherein, when optimizing the objective function using gradient descent, the gradient of each second unit is:
[0143] .
[0144] Figure 11 This is a structural block diagram (II) of the VLSI global layout timing optimization device according to an embodiment of the present invention, as shown below. Figure 11 As shown, the VLSI global layout timing optimization device 90 also includes:
[0145] The generation unit 94 is used to generate a number of second timing arcs based on non-critical paths, wherein the second timing arc is the line connecting two adjacent third units on the non-critical path.
[0146] Selection unit 95 is used to select a number of target timing arcs from a number of second timing arcs, wherein the target timing arcs are second timing arcs with a length greater than a first preset length and a level lower than a first preset level;
[0147] Assignment unit 96 is used to assign new weights to the target timing arc, so that the target timing arc with a higher importance than the second preset level is used as the second initial timing arc for the next optimization process, so as to optimize the delay on the non-critical path.
[0148] The acquisition of non-critical paths can be performed by the acquisition unit 92 in the aforementioned embodiment. That is, the acquisition unit 92 is also used to acquire several non-critical paths in the target mesh so that other processing units can perform corresponding processing based on the non-critical paths given by the acquisition unit 92.
[0149] In some embodiments, the assigning unit 96 is further configured to set a specified weight for the target time arc, wherein the formula for setting the specified weight is as follows:
[0150]
[0151] Where, weight factor Here are the preset weighting factors, base is the preset baseline value, remain is the preset retention value, and level is the preset weighting factor. arc For level, level max For the maximum level, length arc For length, length max This is the maximum length.
[0152] By recalculating the weights of each virtual net using the above formula, higher weights can be assigned to ARCs that are longer and have lower levels, thereby optimizing their timing and obtaining a better global layout solution.
[0153] In one example, weight factor Set it to 0.1, base to 1, and remain to 4.
[0154] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can reside in the same processor; or the above modules can be located in different processors in any combination.
[0155] like Figure 12 As shown in the illustration, this application also provides a computer device 100. The computer device 100 may include one or more processors 101 and memory 102.
[0156] The processor 101 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions.
[0157] The memory 102 may include one or more computer programs, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer programs may be stored on the computer-readable storage medium, and the processor 101 may execute the program instructions to implement the VLSI global layout timing optimization and / or other desired functions described above.
[0158] In addition, depending on the specific application, electronic devices may include any other suitable components such as buses, input / output interfaces, etc.
[0159] In addition to the methods and devices described above, embodiments of this disclosure may also be computer program products, including computer program instructions that, when executed by processor 101, cause processor 101 to perform the VLSI global layout timing optimization steps described above in this specification.
[0160] The computer program product can be written in any combination of one or more programming languages to perform the operations of the embodiments of this application. The programming languages include object-oriented programming languages such as Java and C++, as well as conventional procedural programming languages such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.
[0161] Furthermore, the embodiments disclosed in this invention may also be computer-readable storage media storing computer program instructions thereon, which, when executed by processor 101, cause processor 101 to perform the steps in the VLSI global layout timing optimization described above in this specification.
[0162] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0163] Example 2
[0164] This embodiment is a specific implementation of the present invention.
[0165] like Figure 13 As shown, the VLSI global layout process of the present invention includes the following steps.
[0166] Step S1301: Input the netlist and constraints;
[0167] Step S1302, Line length driven layout;
[0168] Step S1303: Determine whether timing optimization should be performed. If timing optimization is performed, proceed to step S1304. If timing optimization is not performed, proceed to step S1305.
[0169] Step S1304: Critical path optimization;
[0170] Step S1305: Determine whether the convergence is successful. If the convergence is unsuccessful, proceed to step S1302. If the convergence is successful, proceed to step S1306.
[0171] Step S1306: Output the global layout result.
[0172] Step S1302 includes gradient calculation and cell position optimization.
[0173] Step S1301 basically corresponds to step S102.
[0174] Step S1302 basically corresponds to steps S402 to S404.
[0175] Among them, steps S1303 to S1304 basically correspond to steps S204 to S206.
[0176] Among them, steps S1305 to S1302 basically correspond to steps S402 to S404.
[0177] like Figure 14 As shown, the critical path optimization of the present invention includes the following steps:
[0178] Step S1401: Timing path analysis;
[0179] Step S1402, timing arc extension;
[0180] Step S1403: Virtual net generation.
[0181] Among them, steps S1401 to S1403 correspond to steps S202 to S204.
[0182] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.
[0183] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A VLSI global layout timing optimization method, characterized in that, include: Unconstrained optimization based on line length and density represents the region to be laid out as multiple non-overlapping target meshes; All critical paths in the target mesh are obtained through static time series analysis; The timing path optimization method based on virtual nets optimizes the latency on the critical path; The timing path optimization method based on virtual nets optimizes the latency on the critical path, including: A plurality of first timing arcs are generated based on the critical path, wherein the first timing arc is a line connecting two adjacent first units on the critical path. The first timing arc, which has a higher importance than a first preset level, is used as the first initial timing arc for the next optimization process to optimize the delay on the critical path.
2. The VLSI global layout timing optimization method according to claim 1, characterized in that, The first time arc whose importance is higher than the first preset level is used as the first initial time arc in the next optimization process, including: Obtain several attributes corresponding to each first time arc, wherein the several attributes include at least times, pSlack, pDis and aLength, times represents the number of times the first time arc occurs, pSlack represents the worst delay in the critical path containing the first time arc, pDis represents the worst Manhattan distance in the critical path containing the first time arc, and aLength represents the length of the first time arc. The importance of each of the first time-series arcs is calculated based on the aforementioned attributes, using the following formula: in, Represents the weighted weight corresponding to the first time-series arc of the i-th order, criticality(arc i The significance of the first time-series arc is represented by .
3. The VLSI global layout timing optimization method according to claim 1, characterized in that, The objective function is constructed using a line length function and a density function. Unconstrained optimization based on line length and density represents the region to be laid out as multiple non-overlapping target meshes. The objective function includes: in, For smooth lines, For a smooth density function, This represents the density weight.
4. The VLSI global layout timing optimization method according to claim 3, characterized in that, The VLSI global layout timing optimization method also includes: When optimizing the objective function using gradient descent, the objective function is preprocessed and optimized using the inversion of the Jacobi matrix. Specifically, the gradient of each second unit during gradient descent optimization is: 。 5. The VLSI global layout timing optimization method according to claim 1, characterized in that, The VLSI global layout timing optimization method also includes: Obtain several non-critical paths in the target grid; A plurality of second timing arcs are generated based on a plurality of non-critical paths, wherein the second timing arc is a line connecting two adjacent third units on the non-critical path; Select a plurality of target time arcs from the plurality of second time arcs, wherein the target time arcs are second time arcs with a length greater than a preset length and a level lower than a preset level; The target timing arc is assigned a new weight, and the target timing arc with a higher importance than the second preset level is used as the second initial timing arc in the next optimization process to optimize the delay on the non-critical path.
6. The VLSI global layout timing optimization method according to claim 5, characterized in that, Assigning new weights to the target time arc includes: A specified weight is assigned to the target time series arc, wherein the formula for calculating the specified weight is as follows: Where, weight factor Here are the preset weighting factors, base is the preset baseline value, remain is the preset retention value, and level is the preset weighting factor. arc For level, level max For the maximum level, length arc For length, length max This is the maximum length.
7. A VLSI global layout timing optimization device, characterized in that, include: A representation unit is used to represent the region to be laid out as multiple non-overlapping target meshes based on unconstrained optimization of line length and density; The acquisition unit is used to acquire all critical paths in the target mesh through static time series analysis; An optimization unit is used to optimize the delay on the critical path based on a timing path optimization method using a virtual net, including generating a plurality of first timing arcs according to the critical path, wherein the first timing arc is a line connecting two adjacent first units on the critical path. The first timing arc, which has a higher importance than a first preset level, is used as the first initial timing arc for the next optimization process to optimize the delay on the critical path.
8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the VLSI global layout timing optimization method as described in any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the VLSI global layout timing optimization method as described in any one of claims 1 to 6.