Static timing analysis method and static timing analysis system
By performing circuit structure analysis and logic testing on standard component libraries, redundant timing constraints are identified and removed, thus solving the problems caused by redundant timing in integrated circuits, improving the efficiency and reliability of circuit design, and reducing correction costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2022-08-03
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies struggle to effectively identify and remove redundant timing constraints in integrated circuit mass production, leading to decreased chip design performance, power consumption, and area, and incurring high correction costs.
By performing circuit structure analysis on the standard component library, redundant timing constraints are identified and removed. Logic test programs are used to find non-mutually controllable pin combinations, and static timing analysis is performed based on the optimized standard component library to reduce redundant timing constraints.
It effectively identifies and removes redundant timing constraints, reduces the number of circuit design modifications and costs, improves development efficiency, avoids performance and area degradation, and provides a reusable optimized component library.
Smart Images
Figure CN117556755B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a static timing analysis method and a static timing analysis system, and particularly to a static timing analysis method and a static timing analysis system that can reduce redundant timing limitations. Background Technology
[0002] Static Timing Analysis (STA) is used in integrated circuit (IC) mass production to evaluate the correct chip operating speed and confirm whether the chip is usable and ready for mass production. However, incorrect STA will affect chip operation.
[0003] For example, when a chip design is modified to meet incorrect timing constraints in a standard operating system (STA), the chip's performance, power consumption, and area (PPA) will decrease, affecting its competitiveness and wasting the cost of correcting the chip design.
[0004] Furthermore, regardless of whether computer-aided or manual debugging methods are used, it is only possible to determine from the circuit architecture of the input STA whether there are any pin relationships that cause redundant timing constraints. This is very time-consuming and difficult to detect for standard component library files with thousands of circuits. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a static timing analysis method and a static timing analysis system that can reduce redundant timing limitations, in order to address the shortcomings of the prior art.
[0006] To address the aforementioned technical problems, one technical solution adopted by this invention is to provide a static timing analysis method, comprising: obtaining a standard cell library file describing multiple standard cells, wherein the standard cell library file defines multiple timing constraints associated with the standard cells; performing topology mapping on the standard cell library file to identify at least one target ordered element from the standard cells, wherein each of the at least one target ordered element includes a logic gate, a selection circuit, and a register circuit connected in sequence, the logic gate having multiple first input terminals, and the selection circuit having a selection terminal; and executing a logic test program for each of the at least one target ordered element to identify a non-mutual (mutual) relationship between the first input terminals and the selection terminal. At least one pin combination with a non-controllable relationship; based on the obtained at least one pin combination, the timing constraints associated with the at least one pin combination in the standard component library file are regarded as redundant timing constraints and removed from the standard component library file to generate an optimized standard component library file; and a static timing analysis is performed on a target circuit design based on the optimized standard component library file to obtain data of a critical path of the target circuit design.
[0007] To address the aforementioned technical problems, another technical solution adopted by the present invention is to provide a static timing analysis system for integrated circuit layout, including a memory and a processor. The memory is configured to store a plurality of computer-executable instructions. The processor is electrically coupled to the memory and configured to acquire and execute the computer-executable instructions to perform a static timing analysis method. This static timing analysis method includes: acquiring a standard cell library file describing a plurality of standard cells, wherein the standard cell library file defines a plurality of timing constraints associated with the standard cells; performing topology mapping on the standard cell library file to identify at least one target ordered element from the standard cells, wherein each of the at least one target ordered element includes a logic gate, a selection circuit, and a register circuit connected in sequence, the logic gate having a plurality of first input terminals, and the selection circuit having a selection terminal; and executing a logic test program for each of the at least one target ordered element to identify a non-mutual (mutual) relationship between the first input terminals and the selection terminal. At least one pin combination with a non-controllable relationship; based on the obtained at least one pin combination, the timing constraints associated with the at least one pin combination in the standard component library file are regarded as redundant timing constraints and removed from the standard component library file to generate an optimized standard component library file; and a static timing analysis is performed on a target circuit design based on the optimized standard component library file to obtain data of a critical path of the target circuit design.
[0008] One of the beneficial effects of the present invention is that the static timing analysis method and static timing analysis system provided by the present invention can effectively identify circuit components in the previous circuit design that need to be corrected due to redundant timing constraints, thereby reducing the time required for error detection and repeated circuit modifications, thus accelerating the development time and achieving both high reliability and high efficiency.
[0009] In addition, it avoids the performance-power-area (PPA) degradation caused by corrections for redundancy timing constraints, and also avoids wasting the cost of correcting chip designs.
[0010] On the other hand, the optimized standard component library obtained after removing redundant timing constraints can be reused by all circuit designs that use the same standard component library, making the data reusable.
[0011] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description
[0012] Figure 1 This is a functional block diagram of the static timing analysis system according to an embodiment of the present invention.
[0013] Figure 2 This is a flowchart of the static timing analysis method according to an embodiment of the present invention.
[0014] Figure 3 This is a functional block diagram of a target sequence element according to an embodiment of the present invention.
[0015] Figure 4 This is a flowchart of a logic test procedure according to an embodiment of the present invention.
[0016] Symbol Explanation
[0017] 1: Static timing analysis system
[0018] 10: Memory
[0019] 100: Computer-readable instructions
[0020] 101: Standard Component Library Archive
[0021] 102: Logic Test Program
[0022] 103: Static Time Series Analysis Tools
[0023] 104: Time Series Analysis Results
[0024] 105: Circuit Design Description File
[0025] 11: Processor
[0026] 12: Network Unit
[0027] 13: Storage unit
[0028] 14: Input / output interfaces
[0029] 3: Target sequence element
[0030] 30: Logic gates (logic switches)
[0031] 300: First output terminal
[0032] 301, 302, ..., 30n: First input terminals
[0033] 32: Selection Circuit
[0034] 321: Second input terminal
[0035] 322: Third input terminal
[0036] 323: Second output terminal
[0037] 324: Selection end
[0038] 34: Temporary Register Circuit
[0039] 341: Fourth input terminal
[0040] 342: Clock terminal
[0041] out: Output terminal
[0042] CK: Clock signal
[0043] SE: Selection Signal
[0044] SI: Scan signal
[0045] Q: Output signal Detailed Implementation
[0046] The following specific embodiments illustrate the implementation of the "static timing analysis method and static timing analysis system" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" used herein should be interpreted to include, depending on the actual situation, any combination of any one or more of the associated listed items.
[0047] Figure 1 This is a functional block diagram of a static timing analysis system according to an embodiment of the present invention. (See also...) Figure 1 As shown, an embodiment of the present invention provides a static timing analysis system 1, which includes a memory 10, a processor 11, a network unit 12, a storage unit 13, and an input / output interface 14. The aforementioned components can communicate with each other via, for example, but not limited to, a bus 15.
[0048] The memory 10 can be any storage device that can be used to store data, such as, but not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk, or other storage devices that can be used to store data. The memory 10 is configured to store at least a plurality of computer-readable instructions 100. In one embodiment, the memory 10 can also be used to store temporary data generated by the processor 11 during computation.
[0049] The processor 11 is electrically coupled to the memory 10 and configured to access computer-readable instructions 100 from the memory 10 to perform the various steps of the static timing analysis method described below.
[0050] The network unit 12 is configured to access the network under the control of the processor 11. The storage unit 13 may be, for example, but is not limited to, a disk or optical disk, for storing data or instructions under the control of the processor 11. The input / output unit 14 is operable by a user to communicate with the processor 11 and input and output data.
[0051] Figure 2 This is a flowchart of a static timing analysis method according to an embodiment of the present invention. Figure 2 This paper provides a static time series analysis method that can be applied to... Figure 1 The static timing analysis system 1 shown may be implemented using other hardware components such as a database, general-purpose processor, computer, server, or other unique hardware devices with specific logic circuits or functions, such as integrating program code and processor / chip into unique hardware. More specifically, the static timing analysis method can be implemented using a computer program to control the components of the static timing analysis system 1. The computer program can be stored on a non-transitory computer-readable recording medium, such as a read-only memory, flash memory, floppy disk, hard disk, optical disk, USB flash drive, magnetic tape, a network-accessible database, or any computer-readable recording medium with similar functionality that is easily conceived by a person skilled in the art.
[0052] See Figure 2 As shown, an embodiment of the present invention provides a margin correction method for static time series analysis, which includes the following steps:
[0053] Step S20: Obtain a standard cell library file describing multiple standard cells. The standard cell library file 101 can be stored in memory 10 and is used to define multiple timing constraints associated with these standard cells.
[0054] In detail, standard components in a standard component library can be divided into two main categories: one category is used to build circuits (such as AND and OR components), and the other category provides auxiliary functions during chip physical layout. In the circuit design flow, the standard component library provides users and integrated circuit design automation software with necessary information. Generally, a standard component library includes information such as physical layout, logic, timing, and power. The timing information in the standard component library further includes cell delay and timing constraints.
[0055] To ensure correct operation of components, the input signal of a sequential cell must remain stable for a certain period of time. This stability period is defined by timing constraints, which play a crucial role in static timing analysis.
[0056] Step S21: Perform topology mapping on the standard component library archive to identify at least one target sequence component from these standard components.
[0057] In detail, this step involves using circuit inspection and structural analysis to identify target sequential components with specific characteristics, such as register circuits with multiple inputs. The reason for choosing such register circuits is that some pins in their circuit architecture may have mutually non-controllable relationships, and these pins correspond to potential redundant timing constraints.
[0058] Further reference is available. Figure 3 This is a functional block diagram of the target sequence element in an embodiment of the present invention. For example... Figure 3 As shown, the target sequential element 3 mentioned in this embodiment includes a logic gate 30, a selection circuit 32, and a temporary register circuit 34 connected in sequence. The logic gate 30 has first input terminals 301 to 30n and a first output terminal 300. The selection circuit 32 has a second input terminal 321, a third input terminal 322, a second output terminal 323, and a selection terminal 324. The temporary register circuit 34 has a fourth input terminal 341, a clock terminal 342, and an output terminal out.
[0059] like Figure 3As shown, the first output terminal 300 is connected to the second input terminal 321, the third input terminal 322 is connected to the scan signal SI, the selection terminal 324 of the selection circuit 32 is connected to a selection signal SE, and the clock terminal 342 of the temporary register circuit 34 is connected to the clock signal CK.
[0060] exist Figure 3 In this embodiment, the temporary register circuit 34 is a flip-flop (FF), the selection circuit 32 is a multiplexer (mux), and the logic gate 30 is a NAND gate. However, the above is only an example, and the present invention is not limited thereto. The logic gate 30 may also be, for example, an AND gate (AND gate), an OR gate (OR gate), a NOT gate (NOT gate), a NOR gate (NOT OR gate), or an XOR NOT gate (EXNOR gate) to implement other digital logic.
[0061] Furthermore, the so-called circuit structure analysis (Topology Mapping) first finds the physical layout file of the components in the standard component library file. For example, it is a Verilog file that uses Verilog's netlist to describe the signal connection relationship between individual standard components. Then, it finds the names of the circuit components (or modules), the signals associated with the circuit components, the signal directions, and the relevant descriptions of the pins in the file. In order to identify the target sequential component 3 with logic gate 30, selection circuit 32, and register circuit 34 from the circuit architecture of these standard components.
[0062] Step S22: For each of the at least one target sequence element, execute a logic test procedure to identify at least one pin combination in which there is a mutual non-controllable relationship between the first inputs and the selection circuit. In some embodiments, the logic test procedure 102 may be implemented in software, for example by a computer program, and may be stored in memory 10.
[0063] Further reference is available. Figure 4 This is a flowchart of a logic test procedure according to an embodiment of the present invention. The logic test procedure includes the following steps:
[0064] Step S220: Determine whether the logical relationship between each of the first input terminals and the selection terminal causes the output terminal of the temporary register circuit to be inactive.
[0065] In this step, for example, a set of test signals can be input analogically to the first input terminals 301 to 30n and the selection terminal 324, and it can be determined whether the output signal Q of the output terminal out of the temporary register circuit 34 changes. In an alternative embodiment, the determination can be made directly for the circuit architecture of at least one target sequence element, and the method of inputting a set of test signals analogically can be omitted. The present invention is not limited thereto.
[0066] It should be noted that, in Figure 3 In this embodiment, when the selection signal SE is the first level, for example, a high level, the selection circuit 32 can select the second input terminal 321 to output the signal received at the second input terminal 321 to the second output terminal 321. When the selection signal SE is the second level, for example, a low level, the selection circuit 32 selects the third input terminal 322 to output the scan signal SI received at the third input terminal 321 to the second output terminal 321. However, the present invention is not limited thereto; in other embodiments, the first level can also be a low level, and the second level can also be a high level.
[0067] Therefore, when the selection signal SE is at the second level, regardless of the signal combination input to the first input terminals 301 to 30n, it will not cause any change to the output signal Q at the output terminal OUT. The output signal Q will only be related to the scan signal SI. In other words, there is a non-controllable relationship between the first input terminals (301, 302, ..., or 30n) and the selection terminal 324.
[0068] In response to the determination that the output terminal OUT of the temporary register circuit 34 is inactive, the logic test program proceeds to step S221: determining that there is a non-controllable relationship between the corresponding first input terminal and the selection terminal, thus constituting one of at least one pin combination, and then returns to step S220 to determine the next input terminal. For example, when the selection signal SE of the selection terminal 324 is at the low level, the first input terminal 301 and the selection terminal 324 are a pin combination with a non-controllable relationship.
[0069] In response to the judgment causing a change in the output terminal out of the temporary register circuit 34, the logic test program enters step S222: it is determined that there is no non-controllable relationship between the corresponding input terminal and the selection terminal, and returns to step S220 to judge the next input terminal.
[0070] Step S23: Based on the obtained at least one pin combination, regard the timing constraints associated with the at least one pin combination in the standard component library file as redundant timing constraints and remove them from the standard component library file to generate an optimized standard component library file.
[0071] For example, when the selection signal SE of the selection terminal 324 is low level, the timing constraints associated with the first input terminal 301 and the selection terminal 324 are all considered as removable redundant timing constraints, and the standard component library file 101 can be modified accordingly.
[0072] Step S24: Perform static timing analysis on the target circuit design based on the optimized standard component library file to obtain the critical path data of the target circuit design.
[0073] Those skilled in the art will understand that static timing analysis is used in the circuit design process to calculate the timing of digital circuits, predict the workflow, measure the delay of the circuit at different operating stages, and test the circuit's ability to operate at a specified rate.
[0074] For example, in an embodiment of the present invention, the target circuit design can be described by a circuit design description file 105, and the target circuit design may include multiple signal transmission paths. After performing static timing analysis (e.g., executing a static timing analysis tool 103 on processor 11 and analyzing the target circuit based on an optimized standard component library file 101), the path among these signal transmission paths that causes the maximum signal transmission delay is considered the critical path. In this step, the relevant information of the critical path is obtained by simulation as the timing analysis result 104, and can be stored in memory 10.
[0075] [Beneficial Effects of the Examples]
[0076] One of the beneficial effects of the present invention is that the static timing analysis method and static timing analysis system provided by the present invention can effectively identify circuit components in the previous circuit design that need to be corrected due to redundant timing constraints, thereby reducing the time required for error detection and repeated circuit modifications, thus accelerating the development time and achieving both high reliability and high efficiency.
[0077] In addition, it avoids the performance-power-area (PPA) degradation caused by corrections for redundancy timing constraints, and also avoids wasting the cost of correcting chip designs.
[0078] On the other hand, the optimized standard component library obtained after removing redundant timing constraints can be reused by all circuit designs that use the same standard component library, making the data reusable.
[0079] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included within the scope of the claims of the present invention.
Claims
1. A static time series analysis method, comprising: Obtain a standard component library file describing multiple standard components, wherein the standard component library file defines multiple timing constraints associated with the multiple standard components; Circuit structure analysis is performed on the standard component library file to identify at least one target sequential component from the plurality of standard components. Each of the at least one target sequential component includes a logic gate, a selection circuit and a temporary register circuit connected in sequence. The logic gate has a plurality of first input terminals and the selection circuit has a selection terminal. For each of the at least one target sequence element, a logic test procedure is executed to identify at least one pin combination that is not mutually controllable between the plurality of first inputs and the selection terminal; Based on the obtained at least one pin combination, the plurality of timing constraints associated with the at least one pin combination in the standard component library file are considered redundant timing constraints and removed from the standard component library file to produce an optimized standard component library file; and A static timing analysis is performed on a target circuit design based on the optimized standard component library file to obtain data on a critical path of the target circuit design.
2. The static timing analysis method of claim 1, wherein, The logic test procedure includes determining whether the logical relationship between each of the plurality of first input terminals and the selection terminal causes one output terminal of the temporary register circuit to be inactive.
3. The static timing analysis method of claim 2, wherein, In response to the determination that the output terminal of the temporary register circuit is not activated, it is determined that there is a non-controllable relationship between the corresponding first input terminal and the selection terminal, and thus it is considered as one of the at least one pin combination.
4. The static time series analysis method as described in claim 2, wherein, The logic test procedure also includes inputting a test signal group into the plurality of first input terminals and the selection terminal, and determining whether an output signal of the output terminal of the temporary register circuit changes.
5. The static time series analysis method as described in claim 2, wherein, In the at least one target sequence element, the logic gate further has a first output terminal, the selection circuit further has a second input terminal, a third input terminal and a second output terminal, the register circuit has a fourth input terminal and a clock terminal, the first output terminal is connected to the second input terminal, the selection terminal is connected to a selection signal, the second output terminal is connected to the fourth input terminal, and the clock terminal is connected to a clock signal.
6. The static time series analysis method as described in claim 5, wherein, When the selection signal is a first bit timed, the selection circuit selects the second input terminal; when the selection signal is a second bit timed, the selection circuit selects the third input terminal.
7. The static time series analysis method as described in claim 6, wherein, When the selection signal is the second level, there is a non-controllable relationship between the plurality of first input terminals and the selection terminal.
8. The static time series analysis method as described in claim 1, wherein, The temporary register circuit is a flip-flop, and the selection circuit is a multiplexer.
9. A static timing analysis system for integrated circuit layout, comprising: A memory configured to store multiple computer-executable instructions; as well as A processor, electrically coupled to the memory, and configured to acquire and execute the plurality of computer-executable instructions to perform a static timing analysis method, the static timing analysis method comprising: Obtain a standard component library file describing multiple standard components, wherein the standard component library file defines multiple timing constraints associated with the multiple standard components; Circuit structure analysis is performed on the standard component library file to identify at least one target sequential component from the plurality of standard components. Each of the at least one target sequential component includes a logic gate, a selection circuit and a temporary register circuit connected in sequence. The logic gate has a plurality of first input terminals and the selection circuit has a selection terminal. For each of the at least one target sequence element, a logic test procedure is executed to identify at least one pin combination that is not mutually controllable between the plurality of first inputs and the selection terminal; Based on the obtained at least one pin combination, the plurality of timing constraints associated with the at least one pin combination in the standard component library file are considered redundant timing constraints and removed from the standard component library file to produce an optimized standard component library file; and A static timing analysis is performed on a target circuit design based on the optimized standard component library file to obtain data on a critical path of the target circuit design.
10. The static time series analysis system as described in claim 9, wherein, The logic test procedure includes determining whether the logical relationship between each of the plurality of first input terminals and the selection terminal causes one output terminal of the temporary register circuit to be inactive.