Margin correction method and margin correction system for static timing analysis
By using a margin correction method and system based on static timing analysis, and by optimizing the margin correction of chips using statistical models and fitting algorithms, the problem of decreased chip yield and increased cost caused by margin estimation errors in existing technologies is solved, thus achieving more efficient chip design and production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2022-01-13
- Publication Date
- 2026-07-07
AI Technical Summary
Existing static timing analysis methods have errors in estimating margins, leading to decreased chip yield or increased costs. They cannot accurately assess chip operating speed and yield, affecting chip performance, power consumption, and area.
By measuring the performance data of multiple dies on the chip under test, a statistical model is established, and the static timing analysis results are corrected using model fitting algorithms to obtain accurate margins. This includes the statistical analysis and fitting of measurement and simulation data, and the analysis results of the STA tool are optimized.
It achieves precise margin correction, improves chip yield, saves computing and measurement resources, shortens development time, and improves chip design efficiency and reliability.
Smart Images
Figure CN116484779B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a correction method and a correction system, and more particularly to a margin correction method and a margin correction system for static time series analysis. Background Technology
[0002] Generally speaking, static timing analysis (STA) is important for the mass production of integrated circuits (ICs) in the following ways:
[0003] (1) Chip operating speed: Only by evaluating the correct chip operating speed can we confirm whether it meets the application product specifications.
[0004] (2) Chip Yield: Increasing chip speed may cause a decrease in chip yield. Therefore, accurate static timing analysis results can monitor the actual yield when increasing chip speed to confirm whether the chip can be used normally and mass-produced. However, when the static timing analysis results are inaccurate, it cannot be guaranteed that the chip can be used normally and mass-produced after increasing the chip speed. This will lead to the conservative adoption of a lower chip speed during manufacturing. However, this will make the chip's performance, power consumption, and area (PPA) worse than it actually is, resulting in increased costs.
[0005] In existing STA methods, when estimating margins, wafer foundries provide margins to the design side based on the physical perturbation characteristics of transistors and the rules of thumb for mass production. This margin is used when performing STA for circuit design, with the aim of obtaining more accurate results when analyzing circuits.
[0006] Because the margin is obtained based on the transistor level, errors can occur when applying it to the logic level design due to different analysis and application conditions. This may result in analysis results that are either too optimistic or too pessimistic. When the analysis results are too optimistic, it will lead to a decrease in yield; conversely, it will make the PPA worse than it actually is, leading to an increase in cost. Summary of the Invention
[0007] The technical problem to be solved by the present invention is to provide a margin correction method and margin correction system that can obtain accurate margins for static time series analysis, in order to overcome the shortcomings of the prior art.
[0008] To address the aforementioned technical problems, one technical solution adopted by this invention is to provide a margin correction method for static timing analysis, comprising: measuring multiple dies on a chip under test having a target circuit to obtain multiple performance data of the critical paths of the dies; acquiring multiple simulation data for simulating the performance of the dies, each corresponding to one of the dies; and performing a static timing analysis. The method employs a Static Timing Analysis (STA) tool to perform static timing analysis on a target circuit based on multiple sets of simulated data to obtain multiple timing analysis results for the critical paths of the corresponding dies; statistically analyzes these timing analysis results to obtain a simulated process parameter; statistically analyzes multiple sets of performance data to obtain a measured process parameter; establishes a statistical model that defines a margin as the difference between the measured process parameter and the simulated process parameter; substitutes the timing analysis results and the measured process parameter into the statistical model and executes a model fitting algorithm to fit a target model to obtain the margin, wherein the target model defines a first function and a second function equal to each other, the first function being a function of the measured process parameter and the second function being a function of the timing analysis results; and executes the STA tool to perform static timing analysis on the target circuit based on multiple sets of simulated data and the margin to obtain multiple corrected timing analysis results for the corresponding dies.
[0009] To address the aforementioned technical problems, another technical solution adopted by the present invention is to provide a margin correction system for static timing analysis, comprising a memory and a processor. The memory is configured to store a plurality of computer-executable instructions. The processor is electrically coupled to the memory and configured to read and execute the plurality of computer-executable instructions to perform: measuring a plurality of dies on a chip under test having a target circuit to obtain multiple performance data; measuring a plurality of dies on a chip under test having a target circuit to obtain multiple performance data of the critical paths of the dies; acquiring multiple simulation data for simulating the performance of the dies; and performing a static timing analysis. The method employs a Static Timing Analysis (STA) tool to perform static timing analysis on a target circuit based on multiple sets of simulated data to obtain multiple timing analysis results for the critical paths of the corresponding dies; statistically analyzes these timing analysis results to obtain a simulated process parameter; statistically analyzes multiple sets of performance data to obtain a measured process parameter; establishes a statistical model that defines a margin as the difference between the measured process parameter and the simulated process parameter; substitutes the timing analysis results and the measured process parameter into the statistical model and executes a model fitting algorithm to fit a target model to obtain the margin, wherein the target model defines a first function and a second function equal to each other, the first function being a function of the measured process parameter and the second function being a function of the timing analysis results; and executes the STA tool to perform static timing analysis on the target circuit based on multiple sets of simulated data and the margin to obtain multiple corrected timing analysis results for the corresponding dies.
[0010] One of the beneficial effects of the present invention is that the margin correction method and margin correction system for static timing analysis provided by the present invention can estimate the optimal margin for STA through numerical optimization, which can save computing resources and measurement resources, improve yield and shorten development time.
[0011] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description
[0012] Figure 1 This is a functional block diagram of a margin correction system for static timing analysis according to an embodiment of the present invention.
[0013] Figure 2 This is a flowchart of a margin correction method for static timing analysis according to an embodiment of the present invention.
[0014] Figure 3A graph of the number of failures per grain versus frequency is plotted according to an embodiment of the present invention.
[0015] Figure 4 This is a schematic diagram of global statistics according to the present invention.
[0016] Figure 5 This is a schematic diagram of regional statistics according to the present invention.
[0017] Figure 6 This is a flowchart illustrating the dichotomy method according to an embodiment of the present invention. Detailed Implementation
[0018] The following specific embodiments illustrate the implementation of the "margin correction method and margin correction system for static time series analysis" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" used herein should be interpreted to include, depending on the actual situation, any combination of any one or more of the associated listed items.
[0019] [First Embodiment]
[0020] Figure 1 This is a functional block diagram of a margin correction system for static timing analysis according to an embodiment of the present invention. (See also...) Figure 1 As shown, an embodiment of the present invention provides a margin correction system 1 for static timing analysis, which includes a memory 10, a processor 11, a network unit 12, a storage unit 13, and an input / output interface 14. The above-mentioned components can communicate with each other via, for example, but not limited to, a bus 15.
[0021] The memory 10 can be any storage device that can be used to store data, such as, but not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk, or other storage devices that can be used to store data. The memory 10 is configured to store at least a plurality of computer-readable instructions 100. In one embodiment, the memory 10 can also be used to store temporary data generated by the processor 11 during computation.
[0022] The processor 11 is electrically coupled to the memory 10 and configured to access computer-readable instructions 100 from the memory 10 to control the components in the power rail design device 1 to perform the functions of the power rail design device 1.
[0023] The network unit 12 is configured to access the network under the control of the processor 11. The storage unit 13 may be, for example, but is not limited to, a magnetic disk or an optical disk, to store data or instructions under the control of the processor 11. The input / output unit 14 is operable by a user to communicate with the processor 11 and to input and output data.
[0024] Figure 2 This is a flowchart of a margin correction method for static timing analysis according to an embodiment of the present invention. Figure 2 A margin correction method is provided, which can be applied to Figure 1 The margin correction system 1 shown may be implemented by other hardware components such as a database, general-purpose processor, computer, server, or other unique hardware devices with specific logic circuits or specific functions, such as integrating program code and processor / chip into unique hardware. More specifically, the margin correction method can be implemented using a computer program to control the components of the margin correction system 1. The computer program can be stored in a non-transitory computer-readable recording medium, such as read-only memory, flash memory, floppy disk, hard disk, optical disk, USB flash drive, magnetic tape, a database accessible via a network, or any computer-readable recording medium with similar functionality that can be easily conceived by those skilled in the art.
[0025] See Figure 2 As shown, an embodiment of the present invention provides a margin correction method for static time series analysis, which includes the following steps:
[0026] Step S20: Measure multiple dies on the chip under test (Chip) with the target circuit to obtain multiple performance data of the critical paths of these dies.
[0027] For example, a network analyzer can be used to input signals from sources with different frequencies into the chip under test (DUT) to measure the operating frequencies of these chips, thereby obtaining multiple minimum pass frequencies for these chips as multiple sets of performance data. (See reference...) Figure 3 This plots the number of failures of different chips against frequency, as illustrated in the embodiments of the present invention. Specifically, the operating frequency of each chip (e.g., chip 1, chip 2) on the chip can be tested at different operating frequencies. When a certain frequency is reached, individual chips may become inoperable, such as... Figure 3As shown. A failure to operate is considered a failure, and the frequency prior to the failure is taken as the maximum passing frequency. Next, after obtaining multiple maximum passing frequencies for the die, the minimum value among these maximum passing frequencies is determined; this is the minimum passing frequency.
[0028] Step S21: Obtain multiple sets of simulation data for simulating the performance of these grains.
[0029] The simulated data represents the relevant data of the target circuit to which static timing analysis will be performed. It can be provided by the wafer foundry and can be, for example, transistor parameter model values, including parameters such as transistor length, width, oxide layer thickness, and conductivity.
[0030] Step S22: Execute the Static Timing Analysis (STA) tool to perform static timing analysis on the target circuit based on multiple sets of simulation data to obtain multiple timing analysis results for the critical paths of these dies.
[0031] Those skilled in the art will understand that static timing analysis is used in the circuit design process to calculate and predict the timing of digital circuits, measure the delay of the circuit at different operating stages, and test the circuit's ability to operate at a specified rate.
[0032] For example, in an embodiment of the present invention, the design of the target circuit may include multiple signal transmission paths. After performing static timing analysis (e.g., executing static timing analysis tool 102 with processor 11 and analyzing the target circuit based on simulation data 101), the path among these signal transmission paths that causes the maximum signal transmission delay is considered the critical path. In this step, the relevant information of the critical path is obtained through simulation as the timing analysis result 103, and can be stored in memory 10.
[0033] Step S23: Statistically analyze these timing analysis results to obtain simulated process parameters.
[0034] In this step, static timing analysis can be performed on the target circuit to obtain multiple setup times for the critical paths of these dies.
[0035] The set time represents the shortest time that the data signal must be stable before the rising edge of the input clock signal appears. This set time is determined by the clock period, the uncertainty of the clock signal, and the timing margin.
[0036] Timing margin is the difference between the actual time used and the time required by the circuit design. It is a term used to indicate whether the circuit design meets timing requirements. A positive timing margin indicates that the timing is met (timing margin), while a negative timing margin indicates that the timing is not met (timing deficiency).
[0037] After obtaining the set time, these set times can be converted into multiple simulated minimum pass frequencies according to the following formula (1).
[0038] Minimum pass frequency for simulation = [1 / (clock period – clock uncertainty – timing margin))]...Equation (1);
[0039] The processor 11 can then execute a statistical algorithm 104 to perform statistical analysis on the simulated process parameters and the measured process parameters. This analysis includes both global and local statistics. Please refer to [reference needed]. Figure 4 This is a schematic diagram of global statistics according to the present invention. Figure 4 As shown, the purpose of global statistics is to find common characteristics that can be used to represent all dies of all chips in a wafer 4. For example, wafer 4 may include chip 40 and chip 41. Chip 40 may include die 400, and chip 41 may include die 410. Specifically, if global statistics are performed on chip 40, a model can be found that can represent the characteristics of all transistors MA1 and MA2 in die 400 of chip 40, such as... Figure 4 As shown on the right. Similarly, if global statistics are performed on chip 41, a model can be found that can represent the characteristics of all transistors MB1 and MB2 in the die 410 of chip 41.
[0040] Therefore, global statistics can be represented, for example, by the following equation (2):
[0041] global corner = μ(die) i ...Equation (2);
[0042] Where global corner represents the global process parameter, μ(die i This means that the process parameters of i dies in the same chip are averaged, and the process parameters can be obtained by actual measurement (such as step S20) or simulation (such as steps S21 to S23).
[0043] Therefore, when it is necessary to extract simulated process parameters from the time series analysis results, the minimum pass frequency of these simulations can be averaged according to the above global statistical method to obtain the global simulated process parameters (simulating globalcorner).
[0044] Next, please refer to Figure 5 This is a schematic diagram of regional statistics according to the present invention. Figure 4 As shown, the purpose of regional statistics is to identify the degree of variation among dies with the same circuit design within a chip 50. For example, chip 50 may include dies 500 and dies 501. However, if global statistics are performed on chip 50, a model can be found to represent the degree of variation between dies 500 and 501 with the same circuit design within chip 50, such as... Figure 5 As shown on the right.
[0045] Therefore, regional statistics can be represented, for example, by the following equation (3):
[0046] local corner = σ(die) i )=σ(Die 1_i -Die 2_i ) / 2 0.5 …Equation (3);
[0047] Where local corner represents the global process parameter, σ(die i This indicates that in the same chip, the variation number of process parameters for i dies is calculated, and the process parameters can be obtained by actual measurement (such as step S20) or simulation (such as steps S21 to S23).
[0048] The statistical inference of equation (3) is as follows.
[0049] Let N(μ, σ) be a normal distribution function that conforms to the mean μ and the variance σ.
[0050] Let X 1_i Let be the first process parameter in the i-th grain, and satisfy the following equation (4):
[0051] X 1_i =N 1_i (μ global_1 , σ global_1 )+N 1_i (μ local_1 , σ local_1 ...Equation (4);
[0052] Let X 2_i Let be the second process parameter of the i-th grain, and satisfy the following equation (5):
[0053] X2_i =N 1_i (μ global_2 , σ global_2 )+N 2_i (μ local_2 , σ local_2 ...Equation (5);
[0054] The variance σ obtained by subtracting two random first process parameters and second process parameters is as shown in equation (6):
[0055] σ 2 (X 1_i -X 2_i )=σ 2 {[N 1_i (μ global_1 , σ global_1 )+N 1_i (μ local_1 , σ local_1 )]–[N 1_i (μ global_2 , σ global_2 )+N 2_i (μ local_2 , σ local_2 Equation (6)...
[0056] Because the global characteristics are the same within the same grain, therefore N 1_i (μ global_1 , σ global_1 ) = N 1_i (μ global_2 , σ global_2 ).
[0057] Next, equation (6) can be expressed as shown in equation (7):
[0058] σ 2 (X 1_i -X 2_i )=σ 2 local_1 +σ 2 local_2 –2Cov (local_1,local_2) …Equation (7);
[0059] Among them, the regional variable is always the same: σ 2 local_1 =σ 2 local_2 =σ 2 local ;
[0060] And 2Cov (local_1,local_2 ) = 0;
[0061] Therefore, σ can be obtained. 2local =σ 2 (X 1_i -X 2_i ) / 2, and thus σ local =σ(X) 1_i -X 2_i ) / 2 0.5 .
[0062] Therefore, taking the minimum transition simulation process parameters as an example, when it is necessary to extract the simulation process parameters from the timing analysis results, the above-mentioned regional statistical method can be used to extract the simulation minimum pass frequencies corresponding to the grains with paired design relationships. The variance is then calculated by subtracting each pair of those with paired design relationships and dividing by the statistical coefficient (which is the 2 obtained from the above deduction). 0.5 To obtain the regional simulation process parameters.
[0063] Step S24: Analyze multiple sets of the performance data to obtain the measurement process parameters.
[0064] In this step, the aforementioned global and regional statistical methods can be used to average multiple sets of performance data to obtain global measurement process parameters (global corner), and multiple sets of performance data corresponding to the dies with paired design relationships can be extracted, and the variance can be calculated by subtracting each pair of the multiple sets of performance data with paired designs, and then divided by a statistical coefficient to obtain regional measurement process parameters (local corner).
[0065] In an embodiment of the present invention, the performance data used to perform global and regional statistics is the minimum throughput obtained in step S20.
[0066] Step S25: Establish a statistical model, where the margin is defined as the difference between the measured process parameters and the simulated process parameters.
[0067] In this step, the statistical model may include a global statistical model and a regional statistical model.
[0068] The global statistical model is defined as follows:
[0069] Global margin = |Measured global process parameters - Simulated global process parameters|;
[0070] The regional statistical model is defined as follows:
[0071] Regional margin = |Measurement area process parameters - Regional global process parameters|.
[0072] Step S26: Substitute the time series analysis results and measurement process parameters into the statistical model, and execute the model fitting algorithm to fit the target model to obtain the margin. For example, the processor 11 can be configured to execute the model fitting algorithm 105, and the target model is defined as shown in the following equation (8):
[0073] f Measure =f Simulation …Equation (8);
[0074] Where f Measure f is a function for measuring process parameters. Simulation This is a function of the time series analysis results.
[0075] Therefore, the target model can be further obtained as f. Measure -f Simulation =0.
[0076] Therefore, the global statistical model and the regional statistical model can be fitted to this target model respectively to obtain the global residual and the regional residual respectively.
[0077] For example, measured global process parameters and simulated global process parameters can be substituted into a global statistical model to target f. Measure_global =f Simulation_global A fitting process is performed to obtain the global margin.
[0078] Among them, f Measure_global f is a function for measuring global process parameters. Simulation_global This is a function for simulating global process parameters.
[0079] Alternatively, the process parameters of the measurement area and the process parameters of the simulated area can be substituted into the regional statistical model to target f. Measure_local =f Simulation_local A fitting process is performed to obtain the regional margin.
[0080] Among them, f Measure_local f is a function of the process parameters in the measurement area. Simulation_local This is a function for simulating process parameters in the region.
[0081] For example, the model fitting algorithm could employ a bisection method, as shown in the reference. Figure 6 This is a flowchart illustrating the dichotomy method according to an embodiment of the present invention.
[0082] As shown in the figure, the bisection method can include:
[0083] Step S60: Randomly generate a first value and a second value between 0 and 1.
[0084] Step S61: Use the first value, the second value, and the median of the first value and the second value as the remainder, and substitute them into the statistical model. The first value is greater than the second value.
[0085] For example, the aforementioned statistical model can be simplified to a function f(margin) of the margin, where the first value, the second value, and the intermediate value are labeled STAP_h, STAP_l, and STAP_m, respectively, and STAP is the margin to be obtained and satisfies f(STAp) = 0.
[0086] At this point, STAP_h and STAP_l, which are between 0 and 1, are randomly generated and substituted into the calculation of the values of f(STAp_h), f(STAp_l), and f(STAp_m).
[0087] Step S62: Determine whether the fitting conditions are met, and then calculate the margin based on the first and second values when the fitting conditions are met.
[0088] For example, we can first determine whether f(STAp_h)*f(STAp_m) is less than 0. If it is, we replace STAP_l with STAP_m. If not, we replace STAP_h with STAP_m. At the same time, we use whether f(STAp_h)-f(STAp_l) is less than or equal to the 95% confidence interval as the fitting condition.
[0089] If f(STAp_h)-f(STAp_l) is greater than the 95% confidence interval, then return to step S60.
[0090] If f(STAp_h)-f(STAp_l) is less than or equal to the 95% confidence interval, then the margin is calculated based on STAP_h and STAP_l at this time.
[0091] Step S27: Execute the STA tool to perform static timing analysis on the target circuit based on multiple sets of simulation data and margins, so as to obtain multiple corrected timing analysis results for the corresponding chips.
[0092] The advantages of using the margin correction method and margin correction system for static time series analysis provided by this invention are as follows:
[0093] (1) High applicability: The margin correction method of the present invention can be used to correct margins according to different types of circuits and components. For example, it can be applied to the design of central processing units with ultra-high speed requirements or automotive chips with ultra-high yield requirements, or it can be applied to transistors with high, medium and low critical voltages.
[0094] (2) Save computing resources: The optimal STA parameters, which are calibrated by numerical optimization, can reduce the verification time using existing computationally intensive simulation programs (such as SPICE, Monte Carlo, etc.).
[0095] (3) Save measurement resources: By using statistical inference and regression analysis, the number of hardware measurements can be reduced, thus saving a lot of time and human resources.
[0096] (4) It can achieve a high yield, thus having high reliability.
[0097] (5) Shorten development time: Before the circuit is mass-produced, the corrected margin can be obtained, which can effectively shorten the development time and avoid the various resources consumed by repeatedly modifying the circuit.
[0098] [Beneficial Effects of the Examples]
[0099] One of the beneficial effects of the present invention is that the margin correction method and margin correction system for static timing analysis provided by the present invention can estimate the optimal margin for STA through numerical optimization, which can save computing resources and measurement resources, improve yield and shorten development time.
[0100] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.
[0101] [Symbol Explanation]
[0102] 1: Margin Correction System
[0103] 10: Memory
[0104] 100: Computer-readable instructions
[0105] 101: Simulated Data
[0106] 102: Static Time Series Analysis Tools
[0107] 103: Time Series Analysis Results
[0108] 104: Statistical Algorithm
[0109] 105: Model Fitting Algorithm
[0110] 11: Processor
[0111] 12: Network Unit
[0112] 13: Storage Unit
[0113] 14: Input / Output Interface
[0114] 4: Wafer
[0115] 40, 41, 50: Chips
[0116] 400, 410, 500, 501: Grain size
[0117] MA1, MA2, MB1, MB2: Transistors.
Claims
1. A margin correction method for static time series analysis, comprising: Measure multiple dies on a chip under test having a target circuit to obtain multiple performance data of the critical paths of the multiple dies; Obtain multiple sets of simulation data, each used to simulate the performance of multiple said grains; A static timing analysis tool is executed to perform static timing analysis on the target circuit based on multiple sets of simulation data to obtain multiple timing analysis results for the critical paths of the multiple dies; Statistical analysis of multiple time series results is used to obtain a simulated process parameter; Analyze multiple sets of the aforementioned performance data to obtain a measurement process parameter; Establish a statistical model, wherein the statistical model defines a margin as the difference between the measured process parameter and the simulated process parameter; Substitute multiple time-series analysis results and the measurement process parameters into the statistical model and execute a model fitting algorithm to fit a target model to obtain the margin. The target model defines a first function and a second function that are equal. The first function is a function of the measurement process parameters, and the second function is a function of the time-series analysis results. as well as The static timing analysis tool is executed to perform static timing analysis on the target circuit based on multiple sets of simulation data and the margin, so as to obtain multiple corrected timing analysis results corresponding to multiple chips.
2. The margin correction method according to claim 1, wherein, The step of measuring multiple of the said grains to obtain multiple sets of said performance data includes: The operating frequencies of the plurality of said grains are measured to obtain a plurality of minimum pass frequencies of the plurality of said grains as a plurality of said performance data.
3. The margin correction method according to claim 2, wherein, The steps for obtaining multiple time-series analysis results corresponding to multiple grains include: Static timing analysis was performed on the target circuit to obtain multiple set times for the multiple said dies; and The multiple set times are converted into multiple simulated minimum pass frequencies.
4. The margin correction method according to claim 3, wherein, The steps for calculating the measurement process parameters based on multiple sets of performance data include: The performance data from multiple datasets are averaged to obtain a global measurement process parameter; and Multiple sets of performance data corresponding to multiple grains with paired design relationships are extracted. The variance is calculated by subtracting each pair of the multiple sets of performance data with paired designs and then dividing by a statistical coefficient to obtain a region measurement process parameter.
5. The margin correction method according to claim 4, wherein, The statistical coefficient is 2. 0.5 .
6. The margin correction method according to claim 4, wherein, The steps for retrieving the simulated process parameter from multiple timing analysis results include: The average of the multiple simulation minimum pass frequencies is used to obtain a global simulation process parameter; and The minimum pass frequencies corresponding to the multiple grains with paired design relationships are taken out. The variance of the minimum pass frequencies with paired design relationships is calculated by subtracting each pair of the taken minimum pass frequencies from each pair and then dividing by the statistical coefficient to obtain a region simulation process parameter.
7. The margin correction method according to claim 6, wherein, The steps to establish this statistical model include: Establish a first statistical model, defining a global margin as the difference between the measured global process parameters and the simulated global process parameters; and A second statistical model is established, defining a regional margin as the difference between the process parameters of the measurement region and the global process parameters of the region.
8. The margin correction method according to claim 7, wherein, The model fitting algorithm includes: The measured global process parameters and simulated global process parameters are substituted into a first statistical model to fit a first target model, thereby obtaining the global margin. The first target model defines a third function and a fourth function that are equal, where the third function is a function of the measured global process parameters, and the fourth function is a function of the simulated global process parameters. The process parameters of the measured region and the process parameters of the simulated region are substituted into a second statistical model to fit a second target model in order to obtain the margin of the region. The second target model defines a fifth function and a sixth function that are equal. The fifth function is a function of the process parameters of the measured region, and the sixth function is a function of the process parameters of the simulated region.
9. The margin correction method according to claim 1, wherein, The model fitting algorithm also includes fitting the statistical model to the target model using a bisection method. This dichotomy includes: A first value and a second value between 0 and 1 are randomly generated multiple times, and an intermediate value between the first value and the second value is used as the remainder and substituted into the statistical model, wherein the first value is greater than the second value. To determine whether the fitting conditions are met, the first value and the second value when the fitting conditions are met are calculated as the margin.
10. A margin correction system for static time series analysis, comprising: A memory configured to store multiple computer-executable instructions; as well as A processor, electrically coupled to the memory, and configured to read and execute a plurality of said computer-executable instructions to perform: Measure multiple dies on a chip under test with a target circuit to obtain multiple sets of performance data; Measure multiple dies on a chip under test having a target circuit to obtain multiple performance data of the critical paths of the multiple dies; Obtain multiple sets of simulation data, each used to simulate the performance of multiple said grains; A static timing analysis tool is executed to perform static timing analysis on the target circuit based on multiple sets of simulation data to obtain multiple timing analysis results for the critical paths of the multiple dies; Statistical analysis of multiple time series results is used to obtain a simulated process parameter; Analyze multiple sets of the aforementioned performance data to obtain a measurement process parameter; Establish a statistical model, which defines a margin as the difference between the measured process parameter and the simulated process parameter; Substitute multiple time-series analysis results and the measurement process parameters into the statistical model and execute a model fitting algorithm to fit a target model to obtain the margin. The target model defines a first function and a second function that are equal. The first function is a function of the measurement process parameters, and the second function is a function of the time-series analysis results. as well as The static timing analysis tool is executed to perform static timing analysis on the target circuit based on multiple sets of simulation data and the margin, so as to obtain multiple corrected timing analysis results corresponding to multiple chips.