Computing method and system, terminal for topology-aware quantum circuit compilation

Abstract

This application discloses a computational method, system, terminal, and computer-readable storage medium for compiling topology-aware quantum circuits. The computational method for compiling topology-aware quantum circuits includes: parsing an abstract quantum circuit to obtain metadata of the abstract quantum circuit; obtaining a hardware topology graph based on the metadata; running a qubit mapping manifold constructor based on the metadata and the hardware topology graph to obtain an initialized differentiable manifold and its initial points; running a connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain an optimized embedding vector and discrete qubit mapping; and translating the abstract quantum circuit into a target quantum circuit based on the discrete qubit mapping. This application can optimize the topological connectivity of the target quantum circuit and minimize communication overhead.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, specifically to a computational method and system for compiling topologically sensed quantum circuits, a terminal, and a computer-readable storage medium. Background Technology

[0002] Quantum computing is a novel computing paradigm that utilizes quantum information units to perform calculations, governed by the laws of quantum mechanics. Unlike classical computers, which use bits (0 or 1), quantum computers use qubits for information processing. Qubits can exist in a superposition of 0 and 1 states, and multiple qubits exhibit quantum entanglement. This gives quantum computers computational potential unmatched by classical computers when dealing with specific complex problems. Currently, quantum computing is widely used in fields such as cryptography, materials simulation, drug development, and artificial intelligence.

[0003] Quantum algorithms are typically described in the form of abstract quantum circuits, which assume that two-qubit quantum gate operations (such as controlled-NOT gates, SWAP gates, etc.) can be directly performed between any two qubits. However, due to limitations in current quantum chip manufacturing processes and physical implementations, the qubits in actual quantum processors (QPUs) are usually arranged in specific topologies, such as one-dimensional chain structures, two-dimensional grid structures (such as Google's Sycamore processor), and heavy hexagonal structures (such as IBM's quantum processor). In these physical topologies, each qubit has direct physical connections only with a finite number of its neighboring qubits, allowing for the execution of two-qubit gate operations. For non-adjacent qubits, two-qubit gate operations cannot be directly performed.

[0004] To execute abstract quantum circuits on physically topologically constrained quantum hardware, computational work involving topology-aware quantum circuit compilation (also known as qubit mapping or layout synthesis) is necessary. The core task of this process is to map logical qubits in the circuit to physical qubits, inserting additional SWAP gates when needed. By exchanging quantum states, physically non-adjacent qubits that need to interact are temporarily moved to adjacent positions, thus indirectly enabling logic gate operations between them. However, SWAP gates themselves are one of the main sources of computational noise and significantly increase circuit depth and execution time, thereby reducing the overall circuit fidelity.

[0005] Existing computational methods for compiling topology-aware quantum circuits mainly include shortest path search methods based on Dijkstra's algorithm, heuristic algorithms based on A* search (such as the Sabre algorithm), and deterministic algorithms based on rules (such as move rules and swap rules). However, these methods essentially treat the qubit mapping problem as a discrete combinatorial optimization problem, traversing or heuristically exploring in a discrete search space. These methods have the following technical drawbacks: (1) They are prone to getting trapped in local optima, making it difficult to find the solution with the minimum mapping cost from a global perspective; (2) As the number of qubits increases, the search space explodes exponentially, leading to a sharp decrease in compilation efficiency; (3) They usually only aim to minimize the number of SWAP gates, making it difficult to comprehensively consider the geometric characteristics of the hardware topology, the communication distance between qubits, and the differences in physical gate fidelity, resulting in a disconnect between the compilation results and the actual hardware characteristics.

[0006] Furthermore, with the development of quantum computing technology, different hardware manufacturers adopt different qubit topologies. Existing compilation methods are often optimized for specific topologies, lacking universality and adaptability to different hardware platforms. When faced with quantum chips with different connectivity and fidelity distributions, existing methods need to readjust algorithm parameters or even redesign compilation strategies, resulting in high technical adaptation costs.

[0007] Therefore, there is an urgent need for a computational method for compiling topology-aware quantum circuits that can optimize topological connectivity and minimize communication overhead from a global geometric perspective. Summary of the Invention

[0008] In view of this, this application provides a computational method and system for compiling topology-aware quantum circuits, a terminal, and a computer-readable storage medium to optimize topology connectivity from a global geometric perspective, minimize communication overhead, and adapt to different hardware topologies.

[0009] This application provides a computational method for compiling topologically sensed quantum circuits, comprising the following steps: The abstract quantum circuit is parsed to obtain its metadata. Obtain the hardware topology diagram based on the aforementioned metadata; Run the qubit-mapped manifold builder based on the metadata and the hardware topology graph to obtain the initialized differentiable manifold and its initial point; Run the connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain the optimized embedding vector and discrete qubit mapping; The abstract quantum circuit is translated into the target quantum circuit based on the discrete qubit mapping.

[0010] Optionally, before running the connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain the optimized embedding vector and discrete qubit mapping, the computational method for compiling the topology-aware quantum circuit further includes: constructing a qubit mapping manifold constructor to execute the qubit mapping manifold constructor based on the metadata and hardware topology graph, establishing a differentiable search space, and outputting the initialized differentiable manifold and its initial points.

[0011] Optionally, the construction process of the bit-mapped manifold builder includes: extracting an interaction graph from the abstract quantum circuit, wherein the vertices in the interaction graph are logical qubits; assigning a continuous high-dimensional embedding vector in R^m space to each logical qubit of the abstract quantum circuit; and deriving a discrete hardware mapping based on the continuous high-dimensional embedding vector to obtain the bit-mapped manifold builder.

[0012] Optionally, after constructing the qubit mapping manifold builder, the computational method for compiling the topology-aware quantum circuit further includes: constructing a connectivity optimization engine, executing the connectivity optimization engine based on the initialized differentiable manifold and its initial points, to obtain the optimized embedding vector and discrete qubit mapping.

[0013] Optionally, the construction process of the connectivity optimization engine includes: S1061, defining a differentiable cost function on the manifold; S1062, calculating the standard gradient of the cost function in the environment space, and projecting the standard gradient onto the tangent space of the product spherical manifold; S1063, repeating iterative steps S1061 and S1062, in each iteration, updating the embedding vector on the product spherical manifold to gradually reduce the cost function until the cost function converges or reaches a fixed number of iterations, thereby obtaining the connectivity optimization engine.

[0014] Optionally, the computational method for compiling the topologically aware quantum circuit further includes: verifying whether the target quantum circuit conforms to physical hardware constraints.

[0015] Optionally, verifying whether the target quantum circuit complies with physical hardware constraints includes: traversing the target quantum circuit in chronological order, checking each quantum gate of the target quantum circuit one by one, and determining that the target quantum circuit complies with physical hardware constraints if all two qubit gates satisfy the connectivity check.

[0016] This application also provides a computing system for compiling topologically sensed quantum circuits, including: A parsing module is used to parse the abstract quantum circuit to obtain the metadata of the abstract quantum circuit; The acquisition module is used to acquire a hardware topology diagram based on the metadata; The first running module is used to run a qubit-mapping manifold constructor based on the metadata and the hardware topology graph to obtain an initialized differentiable manifold and its initial point; The second running module is used to run the connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain the optimized embedding vector and discrete qubit mapping; The translation module is used to translate the abstract quantum circuit into the target quantum circuit based on the discrete qubit mapping.

[0017] This application also provides a terminal, including: a memory and a processor, wherein the memory stores a computational program for compiling a topologically aware quantum circuit, and when the computational program for compiling the topologically aware quantum circuit is executed by the processor, it implements the steps of any of the above-mentioned computational methods for compiling a topologically aware quantum circuit.

[0018] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the computational method for compiling any of the above-described topological sensing quantum circuits.

[0019] The computational method, system, terminal, and computer-readable storage medium for compiling topology-aware quantum circuits described in this application obtain metadata of the abstract quantum circuit by parsing it. Based on the metadata, a hardware topology graph is obtained. A qubit mapping manifold constructor is run based on the metadata and the hardware topology graph to obtain an initialized differentiable manifold and its initial points. A connectivity optimization engine is run based on the initialized differentiable manifold and its initial points to obtain an optimized embedding vector and discrete qubit mapping. The abstract quantum circuit is translated into a target quantum circuit based on the discrete qubit mapping to optimize the topological connectivity of the target quantum circuit and minimize communication overhead, enabling the computational method for compiling topology-aware quantum circuits to adapt to different hardware topologies. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a topology optimization system for quantum compilation according to an embodiment of this application; Figure 2 This is a schematic flowchart of a computational method for compiling a topologically sensed quantum circuit according to an embodiment of this application; Figure 3This is a schematic diagram of the topology-aware compilation process according to an embodiment of this application; Figure 4 This is a schematic diagram of a manifold embedding optimization structure according to an embodiment of this application; Figure 5 This is a schematic diagram of an adaptive compilation framework according to an embodiment of this application; Figure 6 This is a schematic diagram of the computing system structure for topological sensing quantum circuit compilation according to an embodiment of this application; Figure 7 This is a schematic diagram of a terminal structure according to an embodiment of this application. Detailed Implementation

[0022] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0023] The first aspect of this application provides a computational method for compiling topology-aware quantum circuits, which can be executed by a terminal that needs to perform topology-aware quantum circuit compilation computation. Specifically, the terminal can provide a computational framework that guarantees optimal qubit mapping for topology-aware quantum compilation through manifold embedding optimization. This computational framework that guarantees optimal qubit mapping can also be referred to as a topology optimization system for quantum compilation, see reference. Figure 1 As shown, the topology optimization system for quantum compilation includes a topology compilation optimization core 104; wherein the topology compilation optimization core 104 may include a qubit mapping manifold constructor 105, a connectivity optimization engine 106, and a topology verification unit 107. The qubit mapping manifold constructor 105 is used to construct a differentiable manifold representing all possible qubit-to-hardware mappings. The connectivity optimization engine 106 is used to optimize the qubit layout to minimize communication distance and SWAP gate overhead. The topology verification unit 107 can verify that the compiled circuit maintains logical connectivity under physical topology constraints.

[0024] In some embodiments, reference Figure 2 As shown, the computational method for compiling topologically sensed quantum circuits includes the following steps S110 to S150.

[0025] S110, parse the abstract quantum circuit C to obtain the metadata of the abstract quantum circuit.

[0026] The aforementioned abstract quantum circuit may include quantum circuits that require compilation and / or related calculations. The corresponding terminal can receive the abstract quantum circuits that require compilation and / or calculations through relevant input devices and other components. Optionally, step S110 may also receive the physical hardware constraints and / or hardware topology specifications corresponding to the aforementioned abstract quantum circuit.

[0027] Optionally, the computational method for compiling the above-described topology-aware quantum circuit can also construct a topological manifold representing the hardware mapping of all possible qubits based on the abstract quantum circuit, optimize the qubit layout using geometric optimization on the topological manifold, generate a compiled circuit with minimized communication overhead based on the optimized qubit layout, and output a hardware-optimized circuit with certified topological efficiency. The compiled circuit with minimized communication overhead is a hardware-optimized circuit with certified topological efficiency. The geometric optimization minimizes the cost function of SWAP gate count, communication distance, and gate fidelity degradation. The topology verification guarantees that all multi-qubit gates in the compiled circuit are executable within hardware connectivity constraints.

[0028] Optionally, the computational method for compiling the above-described topology-aware quantum circuit can construct a topological manifold representing the hardware mapping of all possible qubits during the topology-aware compilation process. For example, this can be achieved by resolving the corresponding abstract quantum circuit to construct the topological manifold representing the hardware mapping of all possible qubits. (See reference) Figure 3 As shown, the topology-aware compilation process can begin with circuit topology analysis 201 and hardware mapping identification 202, followed by manifold embedding 203 and connectivity optimization 204.

[0029] S120, obtain hardware topology diagram and calibration data based on the metadata.

[0030] Optionally, step S120 may specifically include: resolving the abstract quantum circuit C, constructing the interaction graph I and gate dependency graph (DAG) of the abstract quantum circuit C; outputting the metadata of the abstract quantum circuit C, which may include edge weights and circuit depth analysis, and this information can be used to inform the weights of the cost function. The resolving mode used may include modes such as gate parallelism, critical path and / or qubit interaction frequency.

[0031] S130, based on the metadata and the hardware topology graph G(V, E), run the qubit-mapped manifold constructor to obtain the initialized differentiable manifold and its initial point.

[0032] Optionally, step S130 may specifically include: acquiring the hardware topology graph G(V, E) and calibration data based on the metadata of the abstract quantum circuit C, to prepare a processed hardware model for geometry optimization. It should be noted that acquiring the hardware topology graph G(V, E) here is not merely reading a file; the hardware topology graph G(V, E) can be pre-computed to efficiently optimize the required data structures. For example, the full-point-to-shortest-path matrix of the hardware topology graph G(V, E) can be used to quickly calculate the shortest-path distance d_G and create a lookup table for qubit / edge fidelity, etc. The shortest-path distance d_G is calculated from the soft-assignment matrix P using differentiable operations (such as weighted sums on the paths). The calibration data may include qubit fidelity and / or gate times, etc.

[0033] S140 runs a connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain optimized embedding vectors and discrete qubit mappings.

[0034] Optionally, step S140 may specifically include: executing a qubit mapping manifold constructor 105 based on the metadata of the abstract quantum circuit C and the hardware topology graph G(V,E) to establish a differentiable search space, and outputting an initialized differentiable manifold and its initial point, which includes an initial embedding vector.

[0035] Optionally, step S140 may specifically include: executing a connectivity optimization engine 106 based on the initialized differentiable manifold and its initial points to obtain an optimized embedding vector {e_i*}, which is then converted into the final, optimal discrete qubit mapping M* using the Hungarian algorithm.

[0036] S150, based on the discrete qubit mapping, the abstract quantum circuit is translated into the target quantum circuit.

[0037] Step S150 can use the discrete qubit mapping M* to translate the abstract quantum circuit C into the target quantum circuit C', so that the target quantum circuit C' can be inserted with the minimum necessary SWAP gates. The number of SWAP gates can be inferred from the minimized SWAP gate estimate F_swap cost.

[0038] Optionally, the target quantum circuit C' can also be input into the topology verification unit 107 to generate the final, certified, hardware-executable circuit.

[0039] The computational method for compiling topology-aware quantum circuits described above involves parsing an abstract quantum circuit to obtain its metadata, acquiring a hardware topology graph based on the metadata, running a qubit mapping manifold constructor based on the metadata and the hardware topology graph to obtain an initialized differentiable manifold and its initial points, and running a connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain an optimized embedding vector and discrete qubit mapping. Based on the discrete qubit mapping, the abstract quantum circuit is translated into a target quantum circuit to optimize the topological connectivity of the target quantum circuit and minimize communication overhead. This allows the computational method for compiling topology-aware quantum circuits to adapt to different hardware topologies.

[0040] In some embodiments, before running the connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain the optimized embedding vector and discrete qubit mapping, the computational method for compiling the topology-aware quantum circuit further includes: constructing a qubit mapping manifold constructor 105 to execute the qubit mapping manifold constructor 105 based on the metadata of the abstract quantum circuit C and the hardware topology graph G(V, E) in step S140 to establish a differentiable search space and output the initialized differentiable manifold and its initial points.

[0041] Optionally, the qubit mapping manifold constructor 105 is used to transform the abstract qubit mapping problem into a continuous geometric optimization space. The core idea is to represent each possible mapping from logical qubits (from the abstract quantum circuit C) to physical qubits (in hardware) as a unique point on a high-dimensional differentiable manifold. The qubit mapping manifold constructor 105 can be used to initialize the embedding vector {e_i} (e.g., randomly initialized on a sphere) to create the corresponding initial point on the product manifold.

[0042] In some examples, the construction process of the above-mentioned qubit mapping manifold builder 105 includes steps S1051 to S1053.

[0043] S1051, extract the interaction graph I from the abstract quantum circuit C. In the interaction graph I, the vertices are logical qubits. If there is at least one two-qubit quantum gate (such as CNOT) between two logical qubits in the abstract quantum circuit C, then there is an edge (l_i, l_j) between them. The weight of the edge can be the number of such gates or a key indicator. The abstract quantum circuit C has n logical qubits {l_0, l_1, ..., l_{n-1}}, and the hardware topology graph G(V, E) has m physical qubits {p_0, p_1, ..., p_{m-1}} (m ≥ n). The allowed connections of two-qubit quantum gates can be defined using E.

[0044] In step S1052, each logical qubit l_i of the abstract quantum circuit C is assigned a continuous high-dimensional embedding vector e_i in R^m space. The j-th component of e_i intuitively represents the "affinity" or "probability" of mapping the logical qubit l_i to the physical qubit p_j. Specifically, each continuous high-dimensional embedding vector e_i can be constrained on an (m-1)-dimensional sphere (||e_i||^2 = 1). The set of all these n vectors {e_0, e_1, ..., e_{n-1}} constitutes a point on the product manifold (S^{m-1})^n. This manifold is inherently differentiable. Step S1052 enables manifold parameterization.

[0045] S1053 derives a discrete, efficient hardware mapping M: {l_i} -> {p_j} based on the continuous high-dimensional embedding vector e_i. Specifically, step S1053 includes: we compute a soft assignment matrix P of size n x m, where P_{ij} = (e_i)_j^2 (squared to ensure non-negativity, and the sum of each row is 1 due to the spherical constraint). The discrete mapping is obtained by finding a one-to-one match between logical bits and physical bits that maximizes the total P_{ij} score. This can be optimally solved using the Hungarian algorithm (also known as the assignment problem). During the optimization phase, the Sinkhorn normalization / softmax relaxation technique can be used, and this process is fully differentiable.

[0046] In this example, the constructed product manifold (S^{m-1})^n is a differentiable search space. Moving a point on this manifold (through gradient-based optimization) smoothly changes the affinity vector e_i, and consequently alters the final discrete mapping M. This allows for the use of powerful continuous optimization techniques to solve the inherently discrete combinatorial qubit mapping problem.

[0047] In some embodiments, after constructing the qubit mapping manifold constructor, the computational method for compiling the topology-aware quantum circuit further includes: constructing a connectivity optimization engine 106, executing the connectivity optimization engine 106 based on an initialized differentiable manifold and its initial points, to obtain optimized embedding vectors and discrete qubit mappings. Optionally, the connectivity optimization engine 106 can perform geometric optimization on the constructed manifold to find a mapping that minimizes communication overhead; specifically, it can perform Riemann optimization on the manifold to minimize the cost function F, involving iterative processes of gradient calculation, projection, and manifold-aware updates.

[0048] In some examples, the construction process of the connectivity optimization engine 106 includes steps S1061 to S1063.

[0049] S1061, define a differentiable cost function F({e_i}) on the manifold to capture the compilation target. The cost function F({e_i}) may include the SWAP gate estimate F_swap, the communication distance F_distance, and the gate fidelity degradation F_fidelity. The formula for calculating the cost function F({e_i}) may include: F({e_i}) = α * F_swap + β * F_distance + γ * F_fidelity, where α represents the first weight corresponding to the SWAP gate estimate F_swap, β represents the second weight corresponding to the communication distance F_distance, and γ represents the third weight corresponding to the gate fidelity degradation F_fidelity.

[0050] The process of determining the SWAP gate estimate F_swap involves: for each edge (l_i, l_j) with weight w_ij in the interaction graph I, calculating the shortest path distance d_G(M(l_i), M(l_j)) of the currently mapped physical bits on the hardware topology graph G(V, E). F_swap is proportional to Σ w_ij * (d_G - 1) because (d_G - 1) SWAP gates are needed to make non-adjacent bits adjacent. d_G can be calculated from the soft allocation matrix P using differentiable operations (such as weighted sums on paths).

[0051] The process of determining the communication distance F_distance is similar to that of determining F_swap, but d_G can be used directly to minimize the total bit communication distance.

[0052] The gate fidelity degradation F_fidelity can contain hardware calibration data. Costs increase if logic gates are mapped to physical links with low fidelity.

[0053] S1062, Calculate the standard gradient of the cost function in the context space R^{n*m}. F, the standard gradient F is projected onto the tangent space of the product spherical manifold. This projected gradient is called the Riemann gradient, which indicates the steepest descent direction within the manifold constraints. The optimizer then moves forward one step along this direction on the manifold surface (using operations such as shrinkage).

[0054] This step S1062 can use a Riemann optimization algorithm, such as Riemann stochastic gradient descent (RSGD) or Riemann Adam. The optimizer does not treat the embedded vector e_i as a free vector in Euclidean space.

[0055] S1063, repeat iterative steps S1061 and S1062. In each iteration, the embedding vector {e_i} is updated on the product spherical manifold, gradually reducing the cost function F({e_i}) until the cost function F({e_i}) converges (the change in the cost function F({e_i}) is less than a small set value) or a fixed number of iterations is reached, thereby obtaining the connectivity optimization engine 106.

[0056] In this example, at the end of optimization, the final embedding {e_i*} yields an optimal soft allocation matrix P*. Applying the Hungarian algorithm to P* allows us to extract the final, discrete, hardware-optimized qubit map M*.

[0057] In some embodiments, the computational method for compiling the topology-aware quantum circuit further includes: verifying whether the target quantum circuit conforms to physical hardware constraints. Specifically, this embodiment may construct a topology verification unit 107 to verify whether the target quantum circuit conforms to physical hardware constraints.

[0058] In some examples, the process of verifying whether a target quantum circuit conforms to physical hardware constraints includes: Traverse the target quantum circuit chronologically, checking each quantum gate one by one. If all two-qubit gates satisfy the connectivity check, the target quantum circuit is determined to comply with the physical hardware constraints, and a verification certificate can be output. This certificate can be a simple Boolean flag (VALID) or a detailed log, confirming the executability of each gate on the target hardware. If any gate fails the check (i.e., (p_a, p_b)... If E), then an error can be marked.

[0059] Optionally, this example can provide diagnostic feedback, such as: "The gate between logical qubits l_i and l_j at time step t is mapped to physical bits p_x and p_y, which are not connected in the hardware topology G." This feedback is crucial for debugging the compilation process.

[0060] Optionally, for each single-qubit gate, the verification is trivial (valid for any physical bit), and for each two-qubit gate (including the original circuit gate and the inserted SWAP gate), the unit performs a constraint check: it retrieves the target physical bit (p_a, p_b) of the gate and checks whether the undirected edge (p_a, p_b) exists in the hardware connectivity set E.

[0061] In some embodiments, the translation of the abstract quantum circuit into the target quantum circuit based on the discrete qubit mapping can also be performed through a manifold embedding optimization structure. (See reference) Figure 4As shown, the manifold embedding optimization structure 300 includes topological manifold representation 301, connectivity optimization 302, and SWAP overhead minimization 303.

[0062] The topological manifold representation 301 can encode the hardware topology and the intrinsic structure of quantum circuits into a single computable geometric object. The specific operation of the topological manifold representation 301 includes steps S3011 to S3013.

[0063] S3011, Constructing the Graph Laplace: Based on the hardware topology graph G(V, E), construct its graph Laplace matrix L. For a graph with m physical bits, L is an m x m matrix, where L_{ii} is the degree of node i, and L_{ij} (i≠j) is -1 when i and j are adjacent, and 0 otherwise.

[0064] S3012, Eigenvalue Decomposition and Embedding: The eigenvalues ​​of the graph Laplacian matrix L are decomposed, and the eigenvectors corresponding to the k smallest non-zero eigenvalues ​​are selected to form an m x k ​​matrix. These k eigenvectors constitute the spectral embedding of the hardware topology in k-dimensional Euclidean space. Each physical bit p_j corresponds to a point in this space (i.e., the j-th row of the embedding matrix).

[0065] S3013, Circuit Structure Fusion: The logic nodes of the circuit interaction diagram I are weighted and allocated to the spectral embedding points of the aforementioned physical bits according to the current soft mapping probability P. In this way, the entire "logic circuit + hardware topology" system is represented as a point cloud in a high-dimensional space, whose geometric distribution reflects both the communication requirements of the circuit and the connection constraints of the hardware, together constituting the topological manifold representation.

[0066] Connectivity optimization 302 can directly optimize the effective connectivity between qubits through geometric operations on the above topological manifold representation. The specific operation process of connectivity optimization 302 includes steps S3021 to S3023.

[0067] S3021, Define geometric distance: In the spectral embedding space obtained from the topological manifold representation 301, calculate the expected geometric distance for each pair of logical bits (l_i, l_j). This is achieved by weighted averaging of their respective physical bit embedding vectors (with weights P_{i:} and P_{j:}).

[0068] S3022, Optimize target alignment: Design a loss function that minimizes the expected distance in the geometric space for frequently communicating logical bit pairs (high-weight edges in I) in the circuit interaction graph. This is achieved by directly optimizing the soft assignment matrix P (or the underlying embedding vector e_i) using gradient descent.

[0069] S3023, Constraint Preservation: The entire optimization process is performed on the product spherical manifold (S^{m-1})^n, ensuring the legality and differentiability of the soft assignment matrix P. The core of this step is to transform the objective of "minimizing logical communication distance" into the problem of point cloud clustering and arrangement in a geometric space that encodes the hardware topology.

[0070] The SWAP cost minimization 303 method can precisely quantify and transform the geometric results of connectivity optimization into the final SWAP gate insertion scheme. The specific operation process of SWAP cost minimization 303 includes steps S3031 to S3033.

[0071] S3031, Mapping from geometry to topology: After connectivity optimization 302, hard allocation M* is extracted from the optimal soft allocation matrix P* (using the Hungarian algorithm). At this point, for each two-bit gate in the abstract quantum circuit C, the source physical bit and target physical bit that need to communicate on the hardware topology graph G(V, E) can be determined.

[0072] S3032, Path Finding and SWAP Insertion: For each pair of physical bits (p_a, p_b) that need to communicate but are not adjacent, find the shortest path on the hardware topology graph G(V, E). Then, before executing the gate, insert a series of SWAP gates in reverse along this path from p_a to p_b, "swapping" the logical state of p_a to the adjacent position of p_b. After executing the gate, insert SWAP gates in forward along the original path, swapping the logical state back to its original position or restoring the layout for use by subsequent gates. The total number of inserted SWAP gates is equal to the sum of (d_G - 1) of all two-bit gates, where d_G has been minimized in the cost function F_swap.

[0073] S3033, Overhead Merging and Scheduling: Analyzes swap paths with different gate insertions, merges adjacent or identical swap operations, and performs global scheduling on all gates and swap gates to minimize the total circuit depth and the total number of swap gates. The output of SWAP Overhead Minimization 303 is a target quantum circuit C' that can be directly executed on the target hardware and satisfies all topological constraints.

[0074] In some embodiments, the computational method for topology-aware quantum circuit compilation can also construct a hardware adaptive compilation framework 400 to adapt to and verify different hardware topologies. Figure 5 The system demonstrates an adaptive compilation framework 400 for different hardware platforms, which includes three parts: cross-platform topology adaptation 401, adaptive mapping optimization 402, and performance guarantee 403.

[0075] Cross-platform topology adaptation 401 enables the compilation system to seamlessly access and process quantum hardware with different connection topologies. The specific operation process of cross-platform topology adaptation 401 includes steps S4011 to S4013.

[0076] S4011, Topology Description Standardization: Define a hardware description language or standardized data interface (such as JSON format) for describing the hardware topology G(V, E), number of qubits m, and calibration parameters of any quantum processor.

[0077] S4012, Automatic Feature Extraction: When new hardware is connected, the system automatically reads its description file and performs the topological manifold representation 301 operation (constructing graph Laplacian and calculating spectral embedding) to dynamically generate a topological manifold representation for that hardware. This process does not require modification of the core optimization algorithm.

[0078] S4013, Parameter Library Matching: Maintain a parameter library that pre-stores the optimal manifold dimension k, initialization strategy, and optimization hyperparameters (such as learning rate) for common topologies (linear, mesh, honeycomb, etc.) to achieve rapid adaptation.

[0079] Adaptive mapping optimization 402 can dynamically adjust the optimization strategy to obtain the best compilation result based on specific hardware performance and circuit characteristics. The specific operation process of adaptive mapping optimization 402 includes steps S4021 to S4023.

[0080] S4021, Adaptive Cost Function Weights: Based on the calibration data of the input hardware (such as significant differences in fidelity among links), the system automatically adjusts the weights α, β, and γ in the cost function F({e_i}). For example, on systems with large fidelity differences, the weight of γ is significantly increased, guiding the optimizer to preferentially avoid low-fidelity links.

[0081] S4022, Optimization Algorithm Selection: Based on the problem size (n, m) and topological complexity, the system automatically selects or combines algorithms such as Riemann stochastic gradient descent (suitable for large-scale problems) and Riemann L-BFGS (suitable for small-to-medium scale problems requiring high precision).

[0082] S4023, Multi-startpoint optimization: To avoid getting trapped in local optima, the system adopts a multi-startpoint strategy: starting from multiple different random initialization points, the position on the manifold is optimized independently, and finally the result with the minimum cost function F value is selected as the final mapping scheme.

[0083] Performance Guarantee 403 provides quantifiable performance metrics and theoretical boundaries for the compiled circuit, ensuring the quality of the compilation results. The specific operation of Performance Guarantee 403 includes steps S4031 to S4033.

[0084] S4031, Theoretical Boundary Calculation: Based on the expansion or diameter of the hardware topology graph G(V, E) and the cut width of the circuit interaction graph I, calculate the theoretical lower bound of the required number of SWAP gates. After compilation, compare the actual number of inserted SWAP gates with this theoretical lower bound to evaluate how close the compilation scheme is to the optimum.

[0085] S4032, Fidelity Prediction: The overall execution fidelity of the compiled target quantum circuit C' is estimated using hardware calibration data. This is achieved by multiplying or summing the fidelity (or error rate) of each gate in the target quantum circuit C' (including inserted SWAP gates), providing the user with an expected performance metric. The inventors conducted simulation analysis on the performance metrics corresponding to the guarantee of a target quantum circuit C' and found that the target quantum circuit C' obtained using the computational method for compiling topology-aware quantum circuits provided in this application can have its performance metrics corresponding to the guarantee effectively optimized compared to target quantum circuits obtained using other methods. For example, the target quantum circuit C' obtained using the computational method for compiling topology-aware quantum circuits provided in this application can be 20% better than other target quantum circuits in terms of the performance metrics corresponding to the guarantee.

[0086] S4033, Verification Certificate Generation: Output of the integrated topology verification unit 107. Along with the output of the final target quantum circuit C', a performance guarantee certificate is attached, containing: a) a topology verification pass flag; b) the ratio of the actual number of SWAP gates to the theoretical lower bound (i.e., optimization efficiency); and c) the estimated overall circuit fidelity. This provides users with a transparent and reliable assessment of compilation quality.

[0087] The computational method for compiling topology-aware quantum circuits described above obtains the metadata of the abstract quantum circuit by parsing it. Based on this metadata, a hardware topology graph is obtained. A qubit mapping manifold constructor is then run based on the metadata and the hardware topology graph to obtain an initialized differentiable manifold and its initial points. Finally, a connectivity optimization engine is run based on the initialized differentiable manifold and its initial points to obtain optimized embedding vectors and discrete qubit maps. The abstract quantum circuit is then translated into a target quantum circuit based on the discrete qubit maps to optimize the topological connectivity of the target quantum circuit and minimize communication overhead. This allows the computational method for compiling topology-aware quantum circuits to adapt to different hardware topologies. It can formulate the qubit mapping problem as a geometric optimization on a specifically constructed differentiable manifold, enabling efficient and global searching for the optimal mapping.

[0088] A second aspect of this application provides a computational system for compiling topologically-aware quantum circuits. This computational system can be located at the terminal where topologically-aware quantum circuit compilation computation is required. (Reference) Figure 6 As shown, the computational system for compiling the above-mentioned topologically sensed quantum circuits includes: The parsing module 110 is used to parse the abstract quantum circuit to obtain the metadata of the abstract quantum circuit; The acquisition module 120 is used to acquire a hardware topology diagram based on the metadata; The first running module 130 is used to run a qubit mapping manifold constructor based on the metadata and the hardware topology graph to obtain an initialized differentiable manifold and its initial point; The second running module 140 is used to run a connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain optimized embedding vectors and discrete qubit mappings; Translation module 150 is used to translate the abstract quantum circuit into a target quantum circuit based on the discrete qubit mapping.

[0089] Specific limitations on the computational system for compiling topologically-aware quantum circuits can be found in the limitations on the computational method for compiling topologically-aware quantum circuits described above, and will not be repeated here. Each module in the aforementioned computational system for compiling topologically-aware quantum circuits can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the computational modules in the relevant computer device, or they can be stored in software within the memory of the computer device, allowing the computational modules to call and execute the operations corresponding to each of the above units.

[0090] This application also provides a terminal, for reference. Figure 7 As shown, the terminal may include: a memory and a processor, wherein the memory stores a computational program for compiling a topology-aware quantum circuit, and when the computational program for compiling the topology-aware quantum circuit is executed by the processor, it implements the steps of the computational method for compiling the topology-aware quantum circuit as described in any of the above embodiments.

[0091] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the computational method for compiling a topologically sensed quantum circuit as described in any of the above embodiments.

[0092] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0093] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0094] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0095] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A computational method for compiling topologically sensed quantum circuits, characterized in that, The computational method for compiling the topologically sensed quantum circuit includes: The abstract quantum circuit is parsed to obtain its metadata. Obtain the hardware topology diagram based on the aforementioned metadata; Run the qubit-mapped manifold builder based on the metadata and the hardware topology graph to obtain the initialized differentiable manifold and its initial point; Run the connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain the optimized embedding vector and discrete qubit mapping; The abstract quantum circuit is translated into the target quantum circuit based on the discrete qubit mapping.

2. The computational method for compiling topologically sensed quantum circuits according to claim 1, characterized in that, The computational method for compiling the topology-aware quantum circuit, prior to running the connectivity optimization engine on the initialized differentiable manifold and its initial points to obtain the optimized embedding vector and discrete qubit mapping, further includes: Construct a qubit-mapped manifold constructor to execute the qubit-mapped manifold constructor based on the metadata and hardware topology graph, establish a differentiable search space, and output the initialized differentiable manifold and its initial points.

3. The computational method for compiling topologically sensed quantum circuits according to claim 2, characterized in that, The construction process of the bit-mapped manifold constructor includes: An interaction graph is extracted from the abstract quantum circuit, where the vertices are logical qubits; Assign a continuous high-dimensional embedding vector in R^m space to each logical qubit of the abstract quantum circuit; Based on the continuous high-dimensional embedding vector, a discrete hardware mapping is derived to obtain the bit-mapped manifold builder.

4. The computational method for compiling topologically sensed quantum circuits according to claim 2, characterized in that, The computational method for compiling the topologically-aware quantum circuit, following the construction of the qubit-mapping manifold builder, further includes: A connectivity optimization engine is constructed and executed based on an initialized differentiable manifold and its initial points to obtain optimized embedding vectors and discrete qubit mappings.

5. The computational method for compiling topologically sensed quantum circuits according to claim 4, characterized in that, The construction process of the connectivity optimization engine includes: S1061, define a differentiable cost function on the manifold; S1062, calculate the standard gradient of the cost function in the environment space, and project the standard gradient onto the tangent space of the product spherical manifold; S1063, repeating iterative steps S1061 and S1062, in each iteration the embedding vector is updated on the product spherical manifold to gradually reduce the cost function until the cost function converges or reaches a fixed number of iterations, thereby obtaining a connectivity optimization engine.

6. The computational method for compiling topologically sensed quantum circuits according to claim 1, characterized in that, The computational method for compiling the topologically sensed quantum circuit further includes: Verify whether the target quantum circuit follows physical hardware constraints.

7. The computational method for compiling topologically sensed quantum circuits according to claim 1, characterized in that, The verification of whether the target quantum circuit conforms to physical hardware constraints includes: Traverse the target quantum circuit in chronological order, check each quantum gate of the target quantum circuit one by one. If all two qubit gates satisfy the connectivity check, the target quantum circuit is determined to comply with physical hardware constraints.

8. A computing system for compiling topologically sensed quantum circuits, characterized in that, include: A parsing module is used to parse the abstract quantum circuit to obtain the metadata of the abstract quantum circuit; The acquisition module is used to acquire a hardware topology diagram based on the metadata; The first running module is used to run a qubit-mapping manifold constructor based on the metadata and the hardware topology graph to obtain an initialized differentiable manifold and its initial point; The second running module is used to run the connectivity optimization engine based on the initialized differentiable manifold and its initial points to obtain the optimized embedding vector and discrete qubit mapping; The translation module is used to translate the abstract quantum circuit into the target quantum circuit based on the discrete qubit mapping.

9. A terminal, characterized in that, The terminal includes a memory and a processor, wherein the memory stores a computational program for compiling a topologically aware quantum circuit, and when the computational program for compiling the topologically aware quantum circuit is executed by the processor, it implements the steps of the computational method for compiling a topologically aware quantum circuit as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the computational method for compiling a topologically sensed quantum circuit as described in any one of claims 1 to 7.

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