Quantum task execution method and apparatus, and device and storage medium

Abstract

A quantum task execution method and apparatus, and a device and a storage medium, relating to the technical field of quanta. The method comprises: acquiring a logic quantum circuit, wherein the logic quantum circuit is an abstract logic circuit for executing a quantum task (310); on the basis of topological information represented by a virtual quantum chip, and the logic quantum circuit, generating a virtual quantum circuit for the quantum task, wherein the virtual quantum chip corresponds to a partial structure of a physical quantum chip, and the topological information is used for representing a topological relationship between virtual quantum bits comprised in the virtual quantum chip (320); on the basis of the virtual quantum circuit and a bit mapping relationship between the virtual quantum chip and the physical quantum chip, generating a physical quantum circuit for the quantum task, wherein the bit mapping relationship is used for indicating physical quantum bits which are in the physical quantum chip and which correspond to the virtual quantum bits (330); and executing the physical quantum circuit by means of the partial structure in the physical quantum chip, so as to obtain an execution result of the quantum task (340).

Description

Quantum task execution method, device, equipment and storage medium This application claims priority to Chinese patent application No. 202310977711.3 filed on August 4, 2023, with invention name “Method, device, equipment and storage medium for executing quantum tasks”, the entire contents of which are incorporated by reference into this application. Technical Field The embodiments of the present application relate to the field of quantum technology, and in particular to a method, device, equipment and storage medium for executing a quantum task. Background Art The cloud platform can provide users with high-performance physical quantum chips, lowering the threshold for users to use physical quantum chips and expanding the application scenarios of physical quantum chips. In the related art, there is a topological relationship between the physical quantum bits included in the physical quantum chip. In order to avoid abnormalities in the state of the physical quantum bits, the physical quantum chip can only execute one quantum task at a time, that is, before the physical quantum chip generates the processing result corresponding to the quantum task, other quantum tasks cannot be executed synchronously. However, the utilization efficiency of computing resources when executing quantum tasks through physical quantum chips is low. Summary of the invention The embodiments of the present application provide a method, device, equipment and storage medium for executing quantum tasks, which can divide a physical quantum chip to obtain multiple virtual quantum chips, and the multiple virtual quantum chips can synchronously execute different quantum tasks, thereby improving the utilization efficiency of the physical quantum chip. The technical solution is as follows: According to one aspect of an embodiment of the present application, a method for executing a quantum task is provided, which is executed by a computer device, and the method includes: Acquire a logic quantum circuit, wherein the logic quantum circuit is an abstract logic circuit for performing a quantum task; Generate a virtual quantum circuit for the quantum task according to the topological information represented by the virtual quantum chip and the logical quantum circuit, wherein the virtual quantum chip corresponds to a partial structure of a physical quantum chip, the topological information is used to represent the topological relationship between virtual quantum bits included in the virtual quantum chip, and the virtual quantum circuit is a circuit constructed based on the virtual quantum bits; Generate a physical quantum circuit for the quantum task according to the virtual quantum circuit and a bit mapping relationship between the virtual quantum chip and the physical quantum chip, wherein the bit mapping relationship is used to indicate a physical quantum bit corresponding to the virtual quantum bit in the physical quantum chip; The physical quantum circuit is executed by the partial structure in the physical quantum chip to obtain an execution result of the quantum task. According to one aspect of an embodiment of the present application, a device for executing a quantum task is provided, the device comprising: A circuit generation module, used to obtain a logic quantum circuit, wherein the logic quantum circuit is an abstract logic circuit used to perform a quantum task; A first mapping module is used to generate a virtual quantum circuit for the quantum task based on the topological information represented by the virtual quantum chip and the logical quantum circuit, wherein the virtual quantum chip corresponds to a partial structure of the physical quantum chip, the topological information is used to represent the topological relationship between the virtual quantum bits included in the virtual quantum chip, and the virtual quantum circuit is a circuit constructed based on the virtual quantum bits; A second mapping module, configured to generate a physical quantum circuit for the quantum task according to the virtual quantum circuit and a bit mapping relationship between the virtual quantum chip and the physical quantum chip, wherein the bit mapping relationship is used to indicate a physical quantum bit corresponding to the virtual quantum bit in the physical quantum chip; A result generating module is used to execute the physical quantum circuit through the partial structure in the physical quantum chip to obtain the execution result of the quantum task. According to one aspect of an embodiment of the present application, a computer device is provided, the computer device comprising a processor and A memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement a method for executing a quantum task. According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement a method for executing a quantum task. According to one aspect of an embodiment of the present application, a computer program product is provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium, and a processor reading and executing the computer program from the computer-readable storage medium to implement a method for executing a quantum task. The technical solution provided in the embodiments of the present application can bring the following beneficial effects: Compared with the method of performing a quantum task once with a physical quantum chip in the related art, the present application divides the physical quantum chip so that the physical quantum chip corresponds to multiple virtual quantum chips that do not interfere with each other. After obtaining the quantum task to be executed, a virtual quantum chip is selected, and then according to the bit mapping relationship, part of the structure in the physical quantum chip corresponding to the virtual quantum chip participates in the execution process of the quantum task, ensuring that other structures in the physical quantum chip except for the part of the structure do not participate in the execution process of the quantum task, so that the physical quantum bits used in the execution of the quantum task are controllable, and other structures are allowed to execute other quantum tasks in the same period of time. This method can achieve the parallel execution of multiple quantum tasks, which helps improve the execution efficiency of quantum tasks, improve the response speed of feedback of the execution results of quantum tasks, and save computing resources. On the other hand, the above method allows one physical quantum chip to act as multiple quantum chips, which can flexibly adapt to the growing number of quantum tasks while helping to reduce the number of physical quantum chips that need to be maintained, thereby reducing the maintenance cost of physical quantum chips. BRIEF DESCRIPTION OF THE DRAWINGS FIG1 is a schematic diagram of a solution implementation environment provided by an exemplary embodiment of the present application; FIG2 is a schematic diagram of a method for executing a quantum task provided by an exemplary embodiment of the present application; FIG3 is a flow chart of a method for executing a quantum task provided by an exemplary embodiment of the present application; FIG4 is a schematic diagram of the structure of a physical quantum bit provided by an exemplary embodiment of the present application; FIG5 is a schematic diagram of the structure of a virtual quantum chip provided by an exemplary embodiment of the present application; FIG6 is a schematic diagram of a logic quantum circuit provided by an exemplary embodiment of the present application; FIG7 is a schematic diagram of a virtual quantum circuit provided by an exemplary embodiment of the present application; FIG8 is a schematic diagram of the correspondence between a virtual quantum chip and a physical quantum chip provided by an exemplary embodiment of the present application; FIG9 is a schematic diagram of a physical quantum chip provided by an exemplary embodiment of the present application; FIG10 is a schematic diagram of a virtual quantum chip mapping process provided by an exemplary embodiment of the present application; FIG11 is a schematic diagram of a virtual quantum chip mapping process provided by another exemplary embodiment of the present application; FIG12 is a block diagram of a device for executing a quantum task provided by an exemplary embodiment of the present application; FIG. 13 is a structural block diagram of a computer device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings. Before introducing the technical solution of the present application, some key terms involved in the present application are explained. Cloud technology refers to a hosting technology that unifies hardware, software, network and other resources within a wide area network or local area network to achieve data computing, storage, processing and sharing. Cloud technology is a general term for network technology, information technology, integration technology, management platform technology, application technology, etc. based on the cloud computing business model. It can form a resource pool and be used on demand, which is flexible and convenient. Cloud computing technology will become an important support. Cloud technology involves basic technologies such as cloud computing, cloud storage, database and big data. Cloud applications provided based on cloud technology include medical cloud, cloud Internet of Things, cloud security, cloud calling, private cloud, public cloud, hybrid cloud, cloud gaming, cloud education, cloud conferencing, cloud social networking, artificial intelligence cloud services, etc. With the development of cloud technology and its application in different fields, more and more cloud applications will appear. A quantum computer is a machine that uses the principles of quantum mechanics to perform calculations. Based on the superposition principle and quantum entanglement of quantum mechanics, quantum computers have strong parallel processing capabilities and can solve some problems that are difficult for classical computers to calculate. The zero resistance characteristics of superconducting quantum bits and the manufacturing process that is similar to that of integrated circuits make the quantum computing system built using superconducting quantum bits one of the most promising systems for realizing practical quantum computing. A quantum processor is a quantum-level computer processor, that is, a processor of a quantum computer. A quantum processor may include one or more quantum chips. A quantum chip (or superconducting quantum chip) is the central processing unit of a quantum computer and the core component of a quantum computer. A quantum chip integrates quantum circuits on a substrate to carry the function of quantum information processing. Drawing on the development history of traditional computers, after overcoming bottleneck technologies, research on quantum computers needs to take the path of integration in order to achieve commercialization and industrial upgrading. Superconducting systems, semiconductor quantum dot systems, micro-nano photonics systems, and even atomic and ion systems all want to take the path of chipization. From the perspective of development, superconducting quantum chip systems are technically ahead of other physical systems; traditional semiconductor quantum dot systems are also the goal of people's efforts to explore, because after all, the development of the traditional semiconductor industry is already very mature. For example, once semiconductor quantum chips break through the threshold of fault-tolerant quantum computing in terms of decoherence time and control accuracy, it is expected to integrate the existing achievements of the traditional semiconductor industry and save development costs. In the embodiment of this application, the physical quantum chip is referred to as a physical quantum chip. Given the advantages of quantum computers, quantum computers can be used in future systems built on cloud technology to perform some processing and calculations to provide better services. Quantum bit is a unit of measurement in quantum information science. Traditional computers use 0 and 1, and quantum computers also use 0 and 1 to represent information, but the difference is that quantum bits can be 0 and 1 at the same time. This effect is called quantum superposition, which is also a unique feature of quantum computers. Quantum circuit is an abstract concept that represents the circuit for operating quantum bits in a quantum computer, including the representation of quantum bit units, circuits (timelines), and the operations of various quantum logic gates. Finally, quantum measurements are usually required to read the results. Quantum gates are a basic quantum circuit in quantum computing that operates a small number of quantum bits. Unlike traditional logic gates, quantum gates are reversible and can be represented by unitary matrices. Quantum gates include Hadamard, Pauli-X, Pauli-Y, Pauli-Z, SWAP, CNOT, etc. Quantum gates include: single-bit gates, double-bit gates, and multi-bit gates: single-quantum gates refer to logic gates that act on a single quantum bit, double-quantum gates refer to logic gates that act on two quantum bits, and multi-quantum gates refer to logic gates that act on multiple quantum bits. Quantum Language is a research direction in quantum computing. Its fields include building a set of standard assembly instruction sets based on the logic gate capabilities of quantum computers, and can continue to abstractly build more advanced computer languages, and even mix the fields of classical computer languages ​​to create hybrid languages. Terminal symbols, non-terminal symbols and derivation rules: Terminal symbols are the basic symbols of formal languages. They can appear in the input or output strings of derivation rules, but cannot be decomposed into fewer units; non-terminal symbols are symbols that can be replaced. There is at least one starting symbol in a formal method, which must be a non-terminal symbol; derivation rules are the components that define grammar, and there are usually multiple rules. Each rule stipulates which word position can be rewritten as which other word position. Fidelity refers to the degree to which a model or simulation reproduces the conditions, characteristics, and states in the real world. It is an indicator of the authenticity of a model or simulation. In quantum mechanics and optics, the fidelity of a field is the overlap integral of the field of interest and the target field. Decoherence (also known as quantum decoherence) is the effect in quantum mechanics that the quantum coherence of an open quantum system is gradually lost over time due to quantum entanglement with the external environment. Decoherence will cause the interference phenomenon between quantum states to disappear, and the quantum behavior of the system will be transformed into classical behavior. Topology is a discipline that studies the properties of geometric figures or spaces that remain unchanged after continuous changes in shape. Topology only considers the positional relationship between objects without considering their shape and size. A mapping is a noun that refers to the "corresponding" relationship between two sets of elements. "Mapping" or "projection" is often equivalent to a function in mathematics and related fields. FIG1 is a schematic diagram of a solution implementation environment provided by an exemplary embodiment of the present application. The solution implementation environment may include: a terminal device 10 , a cloud server 20 , and a quantum computer 30 . The terminal device 10 may be an electronic device such as a personal computer, a tablet computer, a mobile phone, a wearable device, a smart home appliance, a vehicle-mounted terminal, etc. An application is running on the terminal device 10. The application is used to provide a quantum task execution function. The user provides the quantum task to be processed to the application, and the application returns the execution result corresponding to the quantum task to be processed to the user. The cloud server 20 is used to provide background services for the application in the terminal device 10. For example, the cloud server 20 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. The cloud server 20 can also provide cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content distribution networks, content delivery networks (CDN), and cloud servers for basic cloud computing services such as big data and artificial intelligence platforms, but is not limited to these. The cloud server 20 has a data receiving and sending function. In one example, the cloud server 20 obtains a quantum task to be executed from the terminal device 10, generates a physical quantum circuit corresponding to the quantum task to be executed, and instructs the quantum computer 30 to execute the quantum task through the physical quantum circuit, so as to obtain the execution result corresponding to the quantum task. The quantum computer 30 is provided with a physical quantum chip, which is used to perform quantum computing, execute quantum tasks, and generate execution results corresponding to quantum tasks. In this method, at least two virtual quantum chips (Virtual Quantum Processing Unit, VQPU for short, also called virtual quantum processor) are obtained based on the physical quantum chip division, that is, the physical quantum chip can be mapped into at least two virtual quantum chips, each of which corresponds to a partial structure in the physical quantum chip, and different virtual quantum chips correspond to partial structures that do not include overlapping physical quantum bits. The quantum computer 30 receives an instruction set corresponding to the physical quantum circuit from the cloud server 20, and the physical quantum bits included in the physical quantum circuit are all present in the partial structure corresponding to the virtual quantum chip in the physical quantum chip. After the quantum computer 30 obtains the execution result of the quantum task, it sends the execution result of the quantum task to the cloud server 20, and the cloud server 20 sends the execution result of the quantum task to the terminal device 10. With the continuous development of quantum computing, many companies have begun to release quantum cloud platforms. Quantum clouds are generally used to provide quantum computing services. However, since quantum chips are currently in the noisy intermediate-scale quantum (NISQ) era, the online maintenance cost of quantum chips is high, and the number of quantum chips online on each quantum cloud platform is limited. Moreover, quantum chips are limited by their own physical topology. When performing quantum tasks, no matter how big or small the quantum tasks are, they will occupy the entire chip, resulting in low computing resource utilization. According to the information disclosed by the existing quantum cloud platform, the cloud service platform uses the quantum processor (Quantum Processing Unit, QPU) in a mode where a single quantum task directly calls the entire hardware. When a large number of quantum tasks are simultaneously poured into the quantum cloud platform, a large number of quantum tasks need to be queued up and executed one by one using physical quantum chips. This results in a long task queue waiting time for users to obtain the execution results corresponding to the quantum tasks, resulting in a reduced user experience. In this quantum task execution mode, the response speed of user tasks can only be improved by putting more quantum chip resources online, but since maintaining a stable online physical quantum chip consumes a high cost. Moreover, a single quantum task often does not need to call the resources of the entire physical quantum chip. A single quantum task occupies the quantum task execution mode of the entire physical quantum chip, resulting in a large amount of quantum computing resources being idle and wasted. FIG. 2 is a schematic diagram of a method for executing a quantum task provided by an exemplary embodiment of the present application. In order to overcome the execution mode defects caused by a single quantum task monopolizing the physical quantum chip, this application is based on the idea of ​​virtualization and divides the physical quantum chip 210 into multiple virtual quantum chips 220 through the chip bit mapping method. The cloud server provides a virtualization management layer function to achieve multiple virtual quantum chips 220 with independent interfaces, that is, multiple virtual quantum chips 220 can perform different quantum tasks in the same period of time. This method removes the topological limitations of the physical quantum chip, allowing the same physical quantum chip to perform multiple quantum tasks at the same time, which helps to optimize the utilization of quantum computing resources and reduce idle resources. This method allows the quantum cloud platform to configure according to user needs. Different virtual quantum chips enable customized user services. FIG3 is a flow chart of a method for executing a quantum task provided by an exemplary embodiment of the present application. Exemplarily, the execution subject of the method may be the cloud server 20 in FIG1 . For the convenience of description, the following describes the method for executing a quantum task using a computer device as the execution subject. As shown in FIG3 , the method may include the following steps 310 to 340. Step 310: Obtain a logic quantum circuit, where the logic quantum circuit is an abstract logic circuit used to perform a quantum task. A quantum task is a task to be performed, and a quantum task refers to a circuit task that requires a physical quantum chip to perform. Optionally, the quantum task to be processed is a computing task in the fields of quantum chemistry simulation, quantum artificial intelligence and cryptographic analysis, weather forecasting, drug design, financial analysis, or oil exploration. In some implementations, the quantum task to be executed comes from a user of the quantum cloud service, for example, the user sends the quantum task to be executed to the computer device through a terminal device. Optionally, the quantum task to be executed is described by a quantum program, and the quantum program corresponding to the task to be executed includes the logical quantum bits required for the quantum task to be executed, and the gate units required to perform logical operations on the logical quantum bits. In one example, the computer device obtains the quantum program corresponding to the quantum task to be executed from the terminal device, and obtains the logical quantum circuit of the task to be executed according to the quantum program. In other embodiments, the computer device can directly obtain the logical quantum circuit of the quantum task to be executed. For example, the user transmits the logical quantum circuit to the computer device, so that the computer device obtains the logical quantum circuit. A logical quantum circuit belongs to a quantum circuit, and a logical quantum circuit refers to a quantum computing model. In some embodiments, a logical quantum circuit includes a logical quantum bit and a quantum gate for performing a logical operation on the state of the logical quantum bit. Optionally, there is a timing relationship between the quantum gates in the logical quantum circuit, and the execution process of the quantum task can be realized by performing corresponding gate unit operations on the state of the logical quantum bit of the logical quantum circuit according to the timing relationship. Optionally, there are no topological restrictions between logical qubits, that is, when performing quantum gate operations on more than one logical qubit, there is no need to consider whether the one or more logical qubits are connected. Step 320, generating a virtual quantum circuit for a quantum task based on the topological information and logical quantum circuit represented by the virtual quantum chip, wherein the virtual quantum chip corresponds to a partial structure of the physical quantum chip, and the topological information of the virtual quantum chip is used to represent the topological relationship between the virtual quantum bits included in the virtual quantum chip. The virtual quantum circuit is a circuit constructed based on virtual quantum bits. Schematically, the virtual quantum circuit is a circuit constructed based on virtual quantum bits for executing quantum tasks. A physical quantum chip refers to a physical quantum chip, and the execution of a quantum task is completed through a physical quantum chip. Schematically, a logical operation is performed on the physical quantum bits included in the physical quantum chip through a gate unit, and then the state quantity of the physical quantum bits is observed to obtain the execution result of the quantum task. As can be seen from the above background technology introduction, the related technology is limited by the topological information of the physical quantum chip. The physical quantum chip can only perform one quantum task at a time, resulting in a large waste of computing resources. In this method, the physical quantum chip is divided into multiple virtual quantum chips, each virtual quantum chip corresponds to a partial structure in the physical quantum chip, and there is no overlapping relationship between the partial structures corresponding to different virtual quantum chips in the physical quantum chip. "Dividing the physical quantum chip into multiple virtual quantum chips" can be understood as establishing a mapping relationship between the partial structure of the physical quantum chip and the virtual quantum chip. Optionally, the virtual quantum chip refers to a mapping of a partial structure of a physical chip. The virtual quantum chip includes virtual quantum bits, and there is a mapping between the virtual quantum bits and the physical quantum bits included in the partial structure of the physical quantum chip. In some embodiments, the number of virtual quantum bits included in the virtual quantum chip is related to the number of physical quantum bits included in the partial structure mapped by the virtual quantum chip. Exemplarily, the number of physical quantum bits included in the virtual quantum chip is less than or equal to the number of physical quantum bits included in the partial structure mapped by it. For example, a virtual quantum chip corresponds to partial structure 1 in a physical quantum chip, partial structure 1 includes 10 physical quantum bits, and the virtual quantum chip includes 10 virtual quantum bits. For another example, a virtual quantum chip corresponds to partial structure 2 in a physical quantum chip, partial structure 2 includes 6 physical quantum bits, and the virtual quantum chip includes 5 virtual quantum bits. Optionally, the topological information of the virtual quantum chip is consistent with the topological information of the corresponding partial structure of the virtual quantum chip in the physical quantum chip. That is, the arrangement of virtual quantum bits in the virtual quantum chip is the same as the arrangement of physical quantum bits in the partial structure of the corresponding physical quantum chip; the connectivity between virtual quantum bits in the virtual quantum chip is consistent with the connectivity between physical quantum bits in the partial structure of the physical quantum chip. For example, there is a mapping between virtual qubit 1 and physical qubit 1, and there is a mapping between virtual qubit 2 and physical qubit 2; if there is connectivity between physical qubit 1 and physical qubit 2, then there is connectivity between virtual qubit 1 and virtual qubit 2. Regarding the process of establishing the mapping relationship between the virtual quantum chip and the partial structure of the physical quantum chip, please refer to the following embodiment. In the field of quantum computing, topological information is used to characterize whether there is connectivity between quantum bits that is not affected by position and can interact with each other. Optionally, topological information is used to characterize that at least two quantum bits have a connection relationship, also known as connectivity. Schematically, for any two quantum bits that have connectivity, the states of the two quantum bits can interact with each other (for example, through quantum gate operations, so that the states of the two quantum bits affect each other); for any two quantum bits that do not have connectivity, the states of the two quantum bits cannot directly affect each other. Optionally, the above-mentioned quantum bits include virtual quantum bits and physical quantum bits. From the perspective of hardware structure, for two connected physical quantum bits in a physical quantum chip (ie, a physical quantum chip), elements such as a coupler are provided between the circuits of the two physical quantum bits, and the interaction between the states of the two physical quantum bits is achieved through these elements. In some embodiments, the topological information of the virtual quantum chip includes connectivity between any two virtual quantum bits in the virtual quantum chip. Optionally, the connectivity between the virtual quantum bits is represented by a 1-bit character, where "1" indicates that there is connectivity between the two virtual quantum bits, and "0" indicates that there is no connectivity between the two virtual quantum bits. For example, for virtual quantum bit 1 and virtual quantum bit 2 in a virtual quantum chip, if the bit character between virtual quantum bit 1 and virtual quantum bit 2 corresponds to "1" in the topological information of the virtual quantum chip, it means that there is connectivity between virtual quantum bit 1 and virtual quantum bit 2; if the bit character between virtual quantum bit 1 and virtual quantum bit 2 corresponds to "0", it means that there is no connectivity between virtual quantum bit 1 and virtual quantum bit 2. In some embodiments, a physical quantum chip corresponds to multiple virtual quantum chips. After the computer device obtains the logical quantum circuit corresponding to the quantum task to be performed, the computer device determines the virtual quantum chip that performs the above quantum task from at least one candidate virtual quantum chip, and determines the topological information of the virtual quantum chip, so as to generate the virtual quantum circuit of the quantum task according to the logical quantum circuit and the topological information of the virtual quantum chip. Optionally, the computer device determines the virtual quantum chip that performs the above-mentioned quantum task from at least one candidate virtual quantum chip, including: determining the virtual quantum chip for performing the quantum task from at least one candidate virtual quantum chip according to the topological information of the logical quantum circuit. Optionally, the selected virtual quantum chip refers to a virtual quantum chip that can perform the quantum task. Exemplarily, the topological relationship between the virtual quantum bits included in the selected virtual quantum chip is consistent with the logical quantum circuit, that is, when there are topological restrictions between the virtual quantum bits, the selected virtual quantum chip can realize the logical quantum circuit. For example, the logical quantum circuit only includes logical quantum bit 1 and logical quantum bit 2, and logical quantum bit 1 and logical quantum bit 2 require a quantum gate to perform a logical operation at the first moment. The virtual quantum bit 1 corresponding to the logical quantum bit 1 and the virtual quantum bit 2 corresponding to the logical quantum bit 2, and the virtual quantum bit 1 and the virtual quantum bit 2 have connectivity, which means that the topological relationship between the virtual quantum bits included in the virtual quantum chip is consistent with the logical circuit. Optionally, when the computer device determines the virtual quantum chip for performing the quantum task from at least one candidate virtual quantum chip, the computer device determines the virtual quantum chip for performing the quantum task according to the virtual quantum chip indication corresponding to the quantum task to be performed. For example, the virtual quantum chip indicates that it comes from the user who provides the quantum task, that is, the computer device supports the user to select the virtual quantum chip to perform the quantum task according to actual needs. Selecting different virtual quantum chips to perform quantum tasks means using different partial structures in the physical quantum chip to perform quantum tasks. Since the reliability of physical quantum bits at different positions in the physical quantum chip is different, the physical quantum chip is divided into multiple virtual quantum chips so that different virtual quantum chips can be used. The computing characteristics of the sub-chips are different, which makes it convenient for users to select the corresponding virtual quantum chip according to actual needs and realize customized user services. In some embodiments, the virtual quantum circuit is a quantum circuit. Optionally, the virtual quantum circuit includes virtual quantum bits and gate units for performing logical operations on the virtual quantum bits; wherein there is an execution sequence between the gate units. Optionally, the gate unit in the virtual quantum circuit conforms to the topological information of the virtual quantum circuit. Taking a double quantum gate for performing logical processing on two virtual quantum bits as an example, there should be connectivity between the two virtual quantum bits input into the double quantum gate. In some embodiments, in the step of generating a virtual quantum circuit for a quantum task based on the topological information of the virtual quantum chip and the logical quantum circuit, it is mainly necessary to convert the logical quantum bits in the logical quantum circuit into virtual quantum bits, and determine how to convert the gate units in the logical quantum circuit into gate units that conform to the topological relationship between the virtual quantum bits based on the topological information of the virtual quantum chip. For the implementation content of this step, please refer to the following embodiment. Step 330: Generate a physical quantum circuit for the quantum task based on the virtual quantum circuit and the bit mapping relationship between the virtual quantum chip and the physical quantum chip, where the bit mapping relationship is used to indicate the physical quantum bit corresponding to the virtual quantum bit in the physical quantum chip. Among them, the physical quantum circuit is a circuit constructed based on physical quantum bits. Schematically, the physical quantum circuit is a circuit constructed based on physical quantum bits for performing quantum tasks. In some embodiments, the physical quantum circuit includes physical quantum bits and gate units for performing logical processing on the physical quantum bits. The physical quantum chip operates according to the physical quantum circuit, which is equivalent to executing a quantum task and ultimately generates an execution result of the quantum task. In some embodiments, the bit mapping relationship is used to determine the physical quantum bit corresponding to the virtual quantum bit from the physical quantum chip. Optionally, the computer device generates a physical quantum circuit for the quantum task based on the virtual quantum circuit and the bit mapping relationship between the virtual quantum chip and the physical quantum chip, including: determining the physical quantum bit corresponding to the virtual quantum bit in the virtual quantum circuit based on the bit mapping relationship, and replacing the virtual quantum bit in the virtual quantum circuit with the physical quantum bit to obtain the physical quantum circuit. For relevant content of this process, please refer to the following embodiment. FIG4 is a schematic diagram 410 of the structural relationship between physical quantum bits provided by an exemplary embodiment of the present application, in which the bidirectional arrows in the figure indicate that two physical quantum bits have connectivity. For example, in FIG4 , there is connectivity between physical quantum bit q[0] and physical quantum bit q[1], but there is no connectivity between physical quantum bit q[0] and physical quantum bit q[6]. The topological relationship between physical quantum bits is related to the hardware structure of the physical quantum chip. Optionally, the topological relationship between physical quantum bits cannot be changed. Step 340: Execute the physical quantum circuit through a partial structure in the physical quantum chip to obtain the execution result of the quantum task. Optionally, after the computer device generates the physical quantum circuit of the physical quantum chip, it generates an instruction set corresponding to the physical quantum circuit and sends the instruction set to the physical quantum chip. The physical quantum chip executes according to the instructions of the instruction set and can generate the execution result of the quantum task. The physical quantum chip sends the execution result of the quantum task to the computer device. In some embodiments, the execution result of the quantum task refers to the result obtained by the physical quantum chip performing quantum calculations on the quantum task. In summary, compared to the related art where a physical quantum chip executes a method at a time, the present application divides the physical quantum chip so that the physical quantum chip corresponds to multiple virtual quantum chips that do not interfere with each other. After obtaining the quantum task to be executed, a virtual quantum chip is selected, and then according to the bit mapping relationship, part of the structure in the physical quantum chip corresponding to the selected virtual quantum chip participates in the execution process of the quantum task, ensuring that other structures in the physical quantum chip except for this part of the structure do not participate in the execution process of the quantum task, so that the physical quantum bits used in the execution of the quantum task are controllable, and other structures are allowed to execute other quantum tasks in the same period of time. This method can achieve the parallel execution of multiple quantum tasks, which helps improve the execution efficiency of quantum tasks, improve the response speed of feedback of quantum task execution results, and save computing resources. The above method enables one physical quantum chip to function as multiple quantum chips, which can flexibly adapt to the growing number of quantum tasks while helping to reduce the number of physical quantum chips that need to be maintained, thereby reducing the maintenance cost of physical quantum chips. The following describes the process of generating a logic quantum circuit through several embodiments, and the execution subject of this step is a computer device. In some embodiments, step 310, obtaining a logic quantum circuit, may also include the following sub-steps (not shown in the drawings of the specification). Sub-step 312, obtaining task indication information, where the task indication information is used to indicate the quantum task to be performed. Optionally, the task instruction information is used to indicate a logical quantum bit and a gate unit for operating the logical quantum bit. In some embodiments, the task instruction information is a quantum program, and the quantum program includes at least one line of program instructions, and the program instructions are used to indicate which virtual quantum bit to perform a logical operation on. Optionally, the computer device receives the task instruction information sent by the terminal device. Optionally, the computer device obtains the task instruction information through an external input device. Sub-step 314, for any step indication included in the task indication information, determine a first gate unit corresponding to the step indication, and at least one logical quantum bit logically processed by the first gate unit. In some embodiments, the step indication is used to indicate the operation of a first gate unit. The first gate unit refers to a quantum gate used to perform logical operations on logical quantum bits. The first gate unit can be a quantum gate or a combination of multiple quantum gates. For relevant content about the first gate unit, please refer to the embodiments below. In the case where the task instruction information is a quantum program, the step instruction refers to any program instruction in the quantum program, and the program instruction includes a first gate unit and a logical quantum bit used by the first gate unit to perform a logical operation. For example, a program instruction can be expressed as: H q[0], where q[0] represents a logical quantum bit 0, and H represents that the first gate unit is an H gate. Optionally, different first gate units have different functions, and the state of the logical quantum bit changes after being processed by the first gate unit. Exemplarily, different first gate units are used to perform logical operations on logical quantum bits at different times. There is a timing sequence between the first gate units. In the process of generating a logical quantum circuit, the first gate units need to be arranged according to the timing sequence of the first gate units. Sub-step 316, according to the timing information between the step instructions included in the task instruction information, the first gate units corresponding to the step instructions are time-sequentially associated to generate a logical quantum circuit of the quantum task. In some embodiments, the timing information is used to characterize the execution order of the first gate units corresponding to each step instruction. Exemplarily, when the task instruction information is a quantum program, the arrangement order of the execution of each program in the quantum program is used to characterize the timing information of each first gate unit. The timing of the program instructions arranged at the top in the quantum program takes precedence over the timing of the program instructions arranged at the bottom in the quantum program. For example, if the quantum program includes program instruction 1, program instruction 2, program instruction 3 and program instruction 4 from top to bottom, the execution order of the first gate unit 1 corresponding to program instruction 1 takes precedence over the execution order of the first gate unit 2 corresponding to program instruction 2, the execution order of the first gate unit 2 corresponding to program instruction 2 takes precedence over the execution order of the first gate unit 3 corresponding to program instruction 3, and the execution order of the first gate unit 3 corresponding to program instruction 3 takes precedence over the execution order of the first gate unit 4 corresponding to program instruction 4. In other words, the execution timings of the above four first gate units are: first gate unit 1, first gate unit 2, first gate unit 3, first gate unit 4. Based on this, after the logic operation of the first gate unit 1 is completed, the logic operation of the second gate unit 2 is performed, followed by the logic operation of the first gate unit 3 and the logic operation of the first gate unit 4. Optionally, the execution order of each first gate unit cannot be interactive. The computer device performs timing association with the first gate units corresponding to each step instruction, which can be understood as: setting the arrangement position of each first gate unit in the logic quantum circuit according to the timing information, ensuring that the first gate unit with a lagging timing occurs after the first gate unit with a priority timing. Optionally, the order of quantum circuits from left to right in the logic quantum circuit represents the timing, and the execution timing of the first gate unit on the left is earlier than the execution timing of the first gate unit on the right. In some embodiments, the first gate units corresponding to the respective step instructions are sequentially associated, and a logical quantum circuit of the quantum task is generated through logical quantum bits. Optionally, according to the timing information between the multiple first gate units, at least one logical quantum bit corresponding to the multiple first gate units is determined in sequence, and while the multiple first gate units are time-associated, at least one logical quantum bit corresponding to each first gate unit is associated, thereby generating a logical quantum circuit. The above content introduces the content of generating logical quantum circuits according to task instruction information. Task instruction information represents the logical quantum bits and gate units that need to be logically processed. By converting the task instruction information into logical quantum circuits, the purpose of automatically generating logical quantum circuits according to the timing relationship between step instructions is achieved, which helps to improve the generation efficiency of logical quantum circuits. At the same time, through this method, there is no need for users to provide logical quantum circuits. Only task instruction information with certain instruction information is needed to flexibly generate logical quantum circuits that are easier to be executed by computer devices, which helps to lower the threshold for users to obtain the execution results of quantum tasks, greatly avoiding the situation where users provide incorrect logical quantum circuits and cause deviations in the execution results, thereby indirectly improving the accuracy of the execution results. The following describes the process of generating a virtual quantum circuit through several embodiments, and the execution subject of this step is a computer device. Since the virtual quantum circuit includes virtual quantum bits and gate units for processing the virtual quantum bits, it is necessary to determine the gate units included in the virtual quantum circuit during the process of generating the virtual quantum circuit; and then arrange the gate units according to the time sequence relationship. In some embodiments, step 320, generating a virtual quantum circuit for a quantum task based on the topological information and logical quantum circuit represented by the virtual quantum chip, also includes the following sub-steps. Sub-step 322, according to the topological information of the virtual quantum chip, determining the second gate units corresponding to the first gate units in the logic quantum circuit, wherein the first gate unit is a quantum gate in the logic quantum circuit used to perform logical processing on the logic quantum bit, and the second gate unit is a quantum gate used to perform the same logical processing on the virtual quantum bit as the first gate unit. Wherein, sub-step 322 is mainly used to determine the second gate unit corresponding to the first gate unit in the logical quantum circuit in the virtual quantum circuit. Optionally, the first gate unit and the second gate unit have the same function, that is, the first gate unit and the second gate unit are used to implement the same logical operation. In some embodiments, the gate unit includes at least one quantum gate, for example, the gate unit refers to a single quantum gate, or the gate unit includes multiple quantum gates. For example, the gate unit includes multiple quantum gates that are executed sequentially. Optionally, the type of quantum gate includes but is not limited to at least one of the following: a single-bit gate, a two-bit gate, and a multi-bit gate. Among them, a single-bit gate refers to a quantum gate used to perform logical operations on a single quantum bit, and a two-bit gate refers to a quantum gate used to perform logical operations on two quantum bits. The two-bit gate requires the input of the state of two quantum bits, and the output is the state of the two quantum bits after logical processing. A multi-bit gate is a quantum gate used to operate multiple qubits. A multi-bit gate can be obtained by combining two-bit gates and / or single-bit gates. For example, a multi-bit gate can be decomposed into three single-bit gates, and another multi-bit gate can be decomposed into a two-bit gate and a single-bit gate. In some embodiments, the first gate unit refers to any gate unit included in the logic quantum circuit. Optionally, the first gate unit refers to a single-bit gate or a two-bit gate, for example, the first gate unit refers to an H (Hadamard) gate, which is used to convert the state of the quantum bit to a superposition state. For another example, the first gate unit is a CNOT (Controlled NOT) gate, which is used to convert two quantum bits into entangled quantum bits. In some embodiments, the second gate unit refers to a gate unit in the virtual quantum circuit that corresponds to the first gate unit. Optionally, the timing of the second gate unit in the virtual quantum circuit is the same as the timing of the first gate unit in the logical quantum circuit. Optionally, the second gate unit is used to implement the same logical operation as the first gate unit. Exemplarily, the state of the logical qubit input to the first gate unit is the same as the state of the virtual qubit input to the second gate unit, and the state of the logical qubit output by the first gate unit is the same as the state of the virtual qubit output by the second gate unit. The number of quantum gates included in the second gate unit is greater than or equal to the number of quantum gates included in the first gate unit. Exemplarily, the second gate unit is the same as the first gate unit, for example, when the first gate unit is a single-bit gate, the second gate unit is the same as the first gate unit. Assuming that the first gate unit is an H gate, the second gate unit is also an H gate. Exemplarily, the second gate unit is different from the first gate unit. From the above content, it can be seen that there is no topological relationship between logical quantum bits, which is equivalent to assuming that any two logical quantum bits have connectivity. Therefore, the first gate unit in the logical quantum circuit can perform logical operations on any one or more logical quantum bits. The virtual quantum chip has topological information, that is, some virtual quantum bits included in the virtual quantum chip have topological relationships, while other virtual quantum bits do not have topological relationships; if the virtual quantum bits corresponding to multiple (at least two) logical quantum bits used by the first gate unit for logical operations do not have connectivity, it is necessary to use a quantum gate to first exchange the state of the virtual quantum bit to other virtual quantum bits, and then perform the logical operation corresponding to the first gate unit on the other virtual quantum bits, so as to achieve the same effect as the first gate unit and the second gate unit. Since a quantum gate for state conversion is newly added in order to achieve the same effect as the first gate unit, in this case, the number of quantum gates included in the second gate unit is greater than the number of quantum gates included in the first gate unit. Exemplarily, the second gate unit includes at least one exchange gate unit and a gate unit of the same type as the first gate unit. In some embodiments, the computer device determines, according to the topological information of the virtual quantum chip, second gate units corresponding to the first gate units in the logic quantum circuit, including: determining a virtual quantum bit corresponding to the first gate unit; when the first gate unit corresponds to multiple virtual quantum bits, judging the topological relationship between the multiple virtual quantum bits (that is, whether the multiple virtual quantum bits are connected) according to the topological information of the virtual quantum chip; and determining the second gate unit corresponding to the first gate unit according to the judgment result. For relevant content of this step, please refer to the following embodiment. Sub-step 324, generating a virtual quantum circuit of the quantum task according to the second gate units corresponding to the first gate units and the timing relationship between the first gate units in the logical quantum circuit. In some embodiments, the timing relationship of each first gate unit in the logic quantum circuit is used to characterize the execution order of each first gate unit in the logic quantum circuit. Optionally, the timing relationship of each first gate unit in the logic quantum circuit is determined by a computer device according to the arrangement position of each first gate unit in the logic quantum circuit. For example, the logic quantum circuit arranges each first gate unit from left to right, and the execution timing of the first gate unit closer to the left is earlier, and the execution timing of the first gate unit closer to the right is later. After determining the second gate units corresponding to each first gate unit, it is equivalent to obtaining all the gate units that make up the virtual quantum circuit. The cloud server determines the timing relationship between each second gate unit based on the timing relationship of the first gate unit in the logical quantum circuit, arranges each second gate unit according to the timing relationship, and generates a virtual quantum circuit for the quantum task. Exemplarily, the execution timing of the second gate unit is the same as the execution timing of the first gate unit. For example, the logic quantum circuit includes three first gate units with adjacent execution timings, namely, the first gate unit 1, the first gate unit 2, and the first gate unit 3. The execution timing of the first gate unit 1 is the earliest, and the first gate unit 2 is executed between the first gate unit 1 and the first gate unit 3. Assuming that the computer device determines that the first gate unit 1 corresponds to the second gate unit 1, the first gate unit 2 corresponds to the second gate unit 2, and the first gate unit 3 corresponds to the second gate unit 3, then in the virtual quantum circuit, the second gate unit 1, the second gate unit 2, and the second gate unit 2 are three second gate units with adjacent execution timings; among which, the execution timing of the second gate unit 1 is the earliest, and the second gate unit 2 is executed between the second gate unit 1 and the second gate unit 3. The above process introduces the content of generating virtual quantum circuits according to the topological relationship represented by the virtual quantum chip. According to the topological relationship of the virtual quantum chip, the second gate units corresponding to each first gate unit are determined, and then according to the timing relationship of the first gate unit in the logical quantum circuit, the logical quantum circuit is converted into a virtual quantum circuit adapted to the topological information of the virtual quantum chip through the second gate unit, so as to avoid the incompatibility problem of directly executing quantum tasks through arbitrarily obtained logical quantum circuits. Under the condition that the logical quantum circuit corresponding to the quantum task is the basis, the virtual quantum circuit is generated layer by layer through the topological relationship of the virtual quantum chip, so that the virtual quantum circuit is executed by the virtual quantum information, that is, the purpose of controlling the partial structure in the physical quantum chip to smoothly execute the quantum task in the subsequent steps is achieved, and the pertinence of executing the quantum task through the partial structure in the physical quantum chip is improved. The generation process of the second gate unit is described below through several embodiments. The execution subject of this step is a computer device. In the process of determining the second door unit corresponding to the first door unit, the second door unit can be determined according to the type of the first door unit. The generation methods of the first gate units are classified, and the generation methods of the second gate units corresponding to different types of first gate units are not completely the same. Optionally, the type of the first gate unit is related to the number of logical qubits used by the first gate unit for logic processing. The following mainly introduces the case where the first gate unit is a single-bit gate and the case where the first gate unit is a two-bit gate through several embodiments. For the case where the first gate unit is a multi-bit gate, since the multi-bit gate can be implemented by at least one type of combination of a two-bit gate and a single-bit gate (such as the function of a three-quantum gate can be implemented by a combination of a two-bit gate and a single-bit gate), for the case where the first gate unit is a multi-bit gate, the multi-bit gate can be decomposed into a single-bit gate and a two-bit gate, that is, the first gate unit is decomposed into at least two first sub-units, and the first sub-unit is used as a new first gate unit, and the second gate unit corresponding to each first sub-unit is determined by the method of the following embodiment, and the second gate unit corresponding to each first sub-unit is generated by timing association. Optionally, the decomposition method of the multi-bit gate includes: predicting an equivalent gate combination of the multi-bit gate, testing the multi-bit gate and the equivalent gate combination, and when the test passes, the equivalent gate combination is used as a multi-bit gate. For the relevant content of the method, reference can be made to the relevant technology of multi-bit gate decomposition, and this application is not limited here. Example 1: When the first gate unit is a two-bit gate, the content of the second gate unit corresponding to the first gate unit is determined as shown. In some embodiments, sub-step 322, determining the second gate units corresponding to the first gate units in the logic quantum circuit according to the topological information of the virtual quantum chip, also includes the following sub-steps. Sub-step 322-a, for any first gate unit, when the first gate unit is used to perform logical processing on the first logical quantum bit and the second logical quantum bit, first information used to characterize the connection association relationship between the first virtual quantum bit and the second virtual quantum bit is determined according to the topological information of the virtual quantum chip; wherein the first virtual quantum bit corresponds to the first logical quantum bit, and the second virtual quantum bit corresponds to the second logical quantum bit. The connection association relationship is used to characterize the connectivity between the first virtual quantum bit and the second virtual quantum bit. Schematically, the connection association relationship includes: there is connectivity between the first virtual quantum bit and the second virtual quantum bit; or there is no connectivity between the first virtual quantum bit and the second virtual quantum bit. In some embodiments, the first logical qubit and the second logical qubit are two different logical qubits. The first qubit and the second qubit are used to represent two logical qubits used by the first gate unit in the logic quantum circuit for performing logical operations. The quantum logical qubits used by different first gate units for logical operations may be the same or different. For any first gate unit belonging to a two-bit gate in the logic quantum circuit, the first gate unit performs a logic operation on the state of the first logic quantum bit and the state of the second quantum bit at the same time. In some embodiments, the first virtual qubit refers to the virtual qubit corresponding to the first logical qubit in the virtual circuit, and the second virtual qubit refers to the virtual qubit corresponding to the second logical qubit in the virtual circuit. As can be seen from the above introduction, there is no topological restriction between logical qubits, but there is a topological restriction between virtual qubits. In other words, the first virtual qubit refers to the first logical qubit subject to topological restriction, and the second virtual qubit refers to the second logical qubit subject to topological restriction. The first gate unit can be set between the first logical qubit and the second logical qubit without considering the topological relationship between the first logical qubit and the second logical qubit, but it is necessary to determine whether the gate unit can be directly set between the first virtual qubit and the second virtual qubit according to the topological relationship between the first virtual qubit and the second virtual qubit. Therefore, it is necessary to determine the second gate unit corresponding to the first gate unit according to the topological information. In some embodiments, a logic quantum circuit includes multiple logic qubits. In order to identify different logic qubits, the logic qubit has identification information, and the identification information is used to uniquely identify the logic qubit. For example, the identification information is the number of the logic qubit. For example, if a certain logic qubit is numbered 0, the logic qubit can be represented as q[0], and if a certain logic qubit is numbered 1, the logic qubit can be represented as q[1]. And so on. Similarly, in order to identify the virtual quantum bit, the virtual quantum bit also has identification information, and the identification information can be the number of the virtual quantum bit. Optionally, the identification information of a certain logical quantum bit is consistent with the identification information of the virtual quantum bit corresponding to the logical quantum bit. There is a corresponding relationship between the information. Exemplarily, the logical quantum bit and its corresponding virtual quantum bit have the same number. For example, q[0] represents the logical quantum bit 0 in the logical quantum circuit, and q[0] represents the virtual quantum bit 0 in the virtual quantum circuit. In one example, a computer device determines a first virtual quantum bit corresponding to the first logical quantum bit based on identification information of the first logical quantum bit, and determines a second virtual quantum bit corresponding to the second logical quantum bit based on identification information of the second logical quantum bit; the computer device determines whether there is connectivity between the first virtual quantum bit and the second virtual quantum bit from topological information of the virtual quantum chip, and generates first information. Optionally, the first information is used to characterize the connection association relationship between the first virtual quantum bit and the second virtual quantum bit; based on the connection association relationship used to indicate the existence of connectivity, the first information can also be referred to as information used to characterize whether there is connectivity between the first virtual quantum bit and the second virtual quantum bit. Exemplarily, the first information can be represented by a 1-bit character, where "0" indicates that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, and "1" indicates that there is connectivity between the first virtual quantum bit and the second virtual quantum bit. The first information is used to determine the method for generating the second gate unit. Sub-step 322-b, determining a second gate unit corresponding to the first gate unit according to the first information. In the case where the first gate unit is a two-bit gate, the computer device determines a method for generating the second gate unit according to the first information. Exemplarily, when the first information represents connectivity between the first virtual qubit and the second virtual qubit, the computer device determines that a quantum gate can be directly set between the first virtual qubit and the second virtual qubit, and the quantum gate is of the same type as the first gate unit. Exemplarily, when the first information represents that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, the computer device determines that a quantum gate cannot be set directly between the first virtual quantum bit and the second virtual quantum bit. For relevant content of this process, please refer to the next embodiment. Through the above method, when the first gate unit is a two-bit gate, the generation method of the second gate unit is determined according to the topological information, so that the generated second gate unit meets the topological restrictions between virtual quantum bits. The above steps 322-a to 322-b introduce that when the logical quantum bits for logical processing in the first gate unit include the first logical quantum and the second logical quantum bits, it is necessary to determine the first information characterizing whether there is connectivity between the first virtual quantum bit and the second virtual quantum bit according to the topological relationship of the virtual quantum chip, and then determine the second gate unit corresponding to the first gate unit according to the first information according to the difference in connectivity represented by the first information. Considering that the second gate unit is used to generate a virtual quantum circuit executed by the virtual quantum chip, and the virtual quantum chip corresponds to a physical quantum chip used to perform quantum tasks, the second gate unit needs to be able to accurately characterize the logical processing process, and the first information characterizing the connectivity between different virtual quantum bits is used as a restriction condition for generating the second gate unit, which is conducive to obtaining a more accurate second gate unit, thereby helping to improve the accuracy of generating the virtual quantum circuit. Case 1: There is connectivity between the first virtual quantum bit and the second virtual quantum bit. The computer device determines the second gate unit corresponding to the first gate unit according to the first information, including: if the first information indicates that there is connectivity between the first virtual quantum bit and the second virtual quantum bit, determining the first gate unit as the second gate unit. If there is connectivity between the first virtual qubit and the second virtual qubit, it means that a quantum gate can be directly established between the first virtual qubit and the second virtual qubit, so the computer device determines the first gate unit as the second gate unit. For example, if the first gate unit is a CNOT gate, the computer device determines that the second gate unit is also a CNOT gate, the first gate unit is used to perform CONT logic processing on the first logical qubit and the second logical qubit, and the second gate unit is used to perform CONT logic processing on the first virtual qubit and the second virtual qubit. Case 2: There is no connectivity between the first virtual quantum bit and the second virtual quantum bit. The computer device determines, according to the first information, a second gate unit corresponding to the first gate unit, including: if the first information indicates that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, determining a state exchange link according to the topological information of the virtual quantum chip, the state exchange link being used to exchange the state of at least one virtual quantum bit of the first virtual quantum bit and the second virtual quantum bit; determining at least one exchange gate unit according to the state exchange link; determining an equivalent gate unit obtained by combining the at least one exchange gate unit and the first gate unit as the second gate unit, the exchange gate unit being used to input the exchange gate The states of the two quantum bits of the unit are exchanged, and in the equivalent gate unit, the operation timing of the exchange gate unit takes precedence over the operation timing of the first gate unit. In schematic form, if there is no connectivity between the first virtual qubit and the second virtual qubit, it means that there is no connectivity between the first physical qubit corresponding to the first virtual qubit and the second physical qubit corresponding to the second virtual qubit on the physical quantum chip. If the virtual quantum circuit includes a quantum gate between the first virtual qubit and the second virtual qubit, and a physical quantum circuit is generated based on the virtual quantum circuit, the physical quantum chip will be unable to perform the logic operation corresponding to the quantum gate between the first physical qubit and the second physical qubit, resulting in the failure of the quantum task execution. In this case, the computer device needs to exchange the state of the first virtual quantum bit (or the second virtual quantum bit) with the state of the other virtual quantum bits, and after completing the state exchange, perform logical operations on the other virtual quantum bits, and the quantum gates required to be used in the process are combined in a time sequence to obtain an equivalent gate unit. Optionally, the equivalent gate unit includes at least two quantum gates. In some embodiments, the state exchange link is used to exchange the state of the target virtual quantum bit with the state of other virtual quantum bits in the virtual quantum chip. After the state exchange is completed, the other virtual quantum bits obtain the state of the target virtual quantum bit; wherein the target virtual quantum bit refers to any one of the first virtual quantum bit and the second virtual quantum bit, and the other virtual quantum bits refer to the virtual quantum bits other than the first virtual quantum bit and the second virtual quantum bit in the multiple virtual quantum bits. For example, the target virtual quantum bit is the first virtual quantum bit q[0], and the other virtual quantum bits are represented as q[3]. After the state exchange is performed, the state quantity of q[3] is converted to the state of q[0] before the state exchange. Optionally, the state exchange link includes at least one virtual quantum bit including the target virtual quantum bit and a state exchange direction, and the state exchange direction is used to indicate the direction in which the at least one virtual quantum bit performs state exchange. Any two adjacent virtual quantum bits included in the state exchange link have connectivity. Exemplarily, when a state exchange link includes multiple virtual quantum bits, the target virtual quantum bit is located at the first position of the state exchange link, and the state exchange direction is used to indicate that the state exchange starts from the target virtual quantum bit, so that the state of the target virtual quantum bit is exchanged to the last virtual quantum bit at the state exchange link. For example, if a state exchange link is [target virtual qubit-virtual qubit 3-virtual qubit 5-virtual qubit 6], it means that the target virtual qubit is connected to virtual qubit 3, virtual qubit 3 is connected to virtual qubit 5, and virtual qubit 5 is connected to virtual qubit 7. That is, through four state exchanges, the state of the target virtual qubit before the state conversion is called the state of virtual qubit 7. It should be noted that the virtual quantum bits included in the state exchange link all belong to the virtual quantum chip used to perform quantum tasks. This method helps to perform quantum tasks using part of the structure of the physical quantum chip. In some embodiments, the computer device determines the state exchange link according to the topological information of the virtual quantum chip, including: determining the first link quantum bit with connectivity to the target virtual quantum chip according to the topological information of the virtual quantum chip, and determining the second link quantum bit with connectivity to the first link quantum bit according to the topological information of the virtual quantum chip; if the second link quantum bit is the second virtual quantum bit, then generating the state exchange circuit according to the first virtual quantum bit, at least one link quantum bit determined in the search process, and the second virtual quantum bit; if the second link quantum bit is not the second virtual quantum bit, then taking the second link quantum bit as the first link quantum bit, repeating the steps starting from determining the second link quantum bit with connectivity to the first link quantum bit according to the topological information of the virtual quantum chip; dividing the state exchange circuit to obtain a first state exchange link including the first virtual quantum bit and a second state exchange link including the second virtual quantum bit; wherein the last virtual quantum bit in the first state exchange link and the last virtual quantum bit in the second state exchange link have connectivity. The first link quantum bit and the second link quantum bit mentioned above are the virtual quantum bits included in the state exchange link. Exemplarily, the state exchange circuit determined by the computer device is [first virtual quantum bit, virtual quantum bit 1, virtual quantum bit 2, virtual quantum bit 3, virtual quantum bit 4, second virtual quantum bit], and the computer device divides between virtual quantum bit 2 and virtual quantum bit 3 in the state exchange circuit to obtain the first state exchange circuit is: [first virtual quantum bit, virtual quantum bit 1, virtual quantum bit 2], and the second state exchange link is: [second virtual quantum bit, virtual quantum bit 4, virtual quantum bit 3]. In the above example, the computer device can also be divided between virtual quantum bit 1 and virtual quantum bit 2 in the state exchange line, and the first state exchange link obtained is: [first virtual quantum bit, virtual quantum bit 1], and the second state exchange link is: [second virtual quantum bit, virtual quantum bit 4, virtual quantum bit 3, virtual quantum bit 2]. The above content introduces the difference in connectivity characterized by the first information, and the difference in determining the content of the second gate unit corresponding to the first gate unit. When the first information indicates that there is connectivity between the first virtual quantum bit and the second virtual quantum bit, the problem of additional processing of the physical quantum chip can be avoided, and the first gate unit is determined as the second gate unit; when the first information indicates that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, in order to avoid the problem of additional logical processing of the physical quantum chip, it is necessary to exchange the state of at least one virtual quantum bit with the device of other virtual quantum bits according to the state exchange link determined by the topological information, so as to avoid the problem of direct logical processing and improve the accuracy of logical processing. Since state exchange requires the use of exchange gate units, the process of adding gate units will affect the execution results of the quantum task. Optionally, the computer controls the number of virtual quantum bits included in the state exchange circuit in the process of determining the exchange circuit, so as to reduce the number of exchange gate units that need to be used. For example, when there are multiple state exchange circuits between the first virtual quantum bit and the second virtual quantum bit, the computer device selects the state exchange circuit with the least number of virtual quantum bits from the multiple state exchange circuits to divide them into the first state exchange link and the second state exchange link. This method helps to reduce the number of exchange gate units that need to be used and reduce the impact of this method on the execution results of the quantum task. In some implementations, the computer device determines at least one exchange gate unit based on the state exchange link, including: establishing an exchange gate unit between two adjacent virtual quantum bits in the state exchange link, and the exchange gate unit is used to realize state exchange between two connected virtual quantum bits. In some embodiments, the state exchange link includes at least one of the following: a first state exchange link and a second state exchange link, the first state exchange link has at least one virtual quantum bit including a first virtual quantum bit, the second state exchange link has at least one virtual quantum bit including a second virtual quantum bit, and there is connectivity between the last virtual quantum bit in the first state exchange link and the last virtual quantum bit in the second state exchange link; the computer device determines at least one exchange gate unit based on the state exchange link, including: for any one of the first state exchange link and the second state exchange link, when the state exchange link includes at least two virtual quantum bits, for any two adjacent virtual quantum bits in the state exchange link, an exchange gate unit is determined between the adjacent virtual quantum bits. When a state exchange link includes a virtual quantum bit, the virtual quantum bit is the target quantum bit. At this time, the target quantum bit is both the first virtual quantum bit and the last virtual quantum bit. At this time, there is no need to establish an exchange gate unit for the virtual quantum bit in the state transfer link. In some embodiments, the exchange gate unit is called a SWAP gate, which is used to exchange the state between virtual quantum bits. In the case of multiple adjacent virtual quantum bits in the state exchange link, there is an execution sequence between the exchange gate units corresponding to the multiple adjacent virtual quantum bits. Exemplarily, in the state exchange link, the closer the virtual quantum bit is to the target virtual quantum bit, the earlier the execution sequence of the exchange gate unit corresponding to the virtual bit is, and the farther the virtual quantum bit is from the target virtual quantum bit, the later the execution sequence of the exchange gate unit corresponding to the virtual bit is. For example, if a state exchange link is [second virtual quantum bit, virtual quantum bit a, virtual quantum bit b], the computer device determines the exchange gate unit 1 between the second virtual quantum bit and the virtual quantum bit a, and determines the exchange gate unit b between the virtual quantum bit a and the virtual quantum bit b, wherein the execution sequence of the exchange gate unit a takes precedence over the execution sequence of the exchange gate unit b. In this way, it is ensured that the state of the target virtual quantum bit can be exchanged to the virtual quantum bit at the end of the state exchange link, so that the virtual quantum bit at the end of the link is subsequently subjected to the same logical processing as the first gate unit, and the same effect as the first gate unit can be produced. Exemplarily, for the exchange gate units corresponding to the virtual quantum bits of the exchange links in different states, the exchange gate units The execution timing between them is not limited, for example, for the exchange gate unit 3 between the virtual quantum bit 1 and the virtual quantum bit 2 in the first state exchange link, and the exchange gate unit 4 between the virtual quantum bit 3 and the virtual quantum bit 4 in the second state exchange link, the execution timing of the exchange gate unit 3 and the exchange gate unit 4 is not limited. The exchange gate unit 3 can be executed in priority to the exchange gate unit 4 in timing, the exchange gate unit 3 can also be executed behind the exchange gate unit 4 in timing, or the exchange gate unit 3 and the exchange gate unit 4 can be executed in parallel. In some implementations, the equivalent gate unit includes at least one exchange gate unit and a first gate unit. The function of the exchange gate unit is introduced above, and the first gate unit is used to perform logical processing on the last virtual quantum bit of the first state exchange link and the last virtual quantum bit of the second state exchange link. The above process introduces the content of determining the exchange gate unit according to the state exchange link. According to the virtual quantum bits included in the state exchange link, an exchange gate unit is determined between any two adjacent virtual quantum bits. In addition, two state exchange links are introduced. Both of these state exchange circuits can determine the exchange gate unit according to the adjacent virtual quantum bits. Since the state of the first virtual quantum bit can be exchanged to the last virtual quantum bit of the first state exchange link, and the state of the second virtual quantum bit can be exchanged to the last virtual quantum bit of the second state exchange link, therefore, the first gate unit is set between the last virtual quantum bit of the first state exchange link and the last virtual quantum bit of the second state exchange link, which can achieve the same effect as the first gate unit in the logic quantum circuit processing the first logical quantum bit and the second logical quantum bit. Through this method, the logical operation equivalent to the first gate unit is realized between the virtual quantum bits that do not have connectivity, so that the quantum task can be smoothly executed. Since adding new quantum gates (such as the exchange gates designed above) on the basis of the original logical quantum circuit may have an impact on the operation process of the physical quantum chip and the execution results of the quantum task. For different quantum tasks, whether to add new quantum gates in the process of generating virtual quantum circuits has different effects on the execution results. In this scheme, whether to add new quantum gates in the process of generating virtual quantum circuits is determined by equivalent indication information. In some embodiments, before determining the state exchange link according to the topological information of the virtual quantum chip, the method further includes: obtaining equivalent indication information, the equivalent indication information being used to characterize the permission of at least one different gate unit between the logical quantum circuit and the virtual quantum circuit; when the equivalent indication information characterizes that at least one different gate unit is allowed between the logical quantum circuit and the virtual quantum circuit, determining the state exchange link according to the topological information of the virtual quantum chip; when the equivalent indication information characterizes that at least one different gate unit is not allowed between the logical quantum circuit and the virtual quantum circuit, returning an error prompt, the error prompt being used to characterize the failure of the execution of the quantum task. The permission condition is used to indicate the permission state of different gate units. That is, the equivalent indication information is used to characterize whether the logical quantum circuit and the virtual quantum circuit are allowed to have at least one different gate unit. The equivalent indication information includes: allowing the logical quantum circuit and the virtual quantum circuit to have at least one different gate unit; or not allowing the logical quantum circuit and the virtual quantum circuit to have at least one different gate unit. Illustratively, when the equivalent indication information representation does not allow the logical quantum circuit and the virtual quantum circuit to have at least one different gate unit, not only an error prompt is returned, but also the step of determining the state exchange link according to the topological relationship of the virtual quantum information is not performed. In some embodiments, the equivalent indication information is used to indicate whether a new gate unit can be added to the virtual quantum circuit during the process of generating the virtual quantum circuit. Optionally, the equivalent indication information and the task indication information are sent to the computer device at the same time. Or when the computer device determines that the virtual quantum circuit needs to have a gate unit different from the logical quantum circuit, the computer device sends equivalent query information to the terminal device, and the equivalent query information is used to inquire whether it is allowed to have at least one different gate unit between the logical quantum circuit and the virtual quantum circuit, and the computer device receives the equivalent indication information sent by the terminal device. Optionally, in the process of generating a virtual quantum circuit according to a logical quantum circuit by a computer device, if the first information indicates that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, the computer device obtains equivalent indication information; when the equivalent indication information allows at least one different gate unit between the logical quantum link and the virtual quantum link, the computer device starts executing from the step of determining a state exchange link according to the topological information of the virtual quantum chip. In other words, the computer device can generate a virtual quantum circuit according to a logical quantum circuit. In the case where the equivalent indication information is that at least one different gate unit is not allowed between the logical quantum circuit and the virtual quantum circuit, the computer does not perform the step of determining the state exchange link according to the topological information of the virtual quantum chip, and returns an error prompt for characterizing the failure of the quantum task execution. Optionally, the error prompt is used to indicate that the quantum task execution failed and the execution result of the quantum task cannot be obtained. The above process introduces the process of differentially determining whether to determine the content of the state exchange link according to whether at least one different gate unit is allowed to exist as represented by the equivalent indication information. When the equivalent indication information indicates that at least one different gate unit is allowed between the logical quantum circuit and the virtual quantum circuit, the state exchange link can be determined to determine the second gate unit; if the equivalent indication information indicates that at least one different gate unit is not allowed between the logical quantum circuit and the virtual quantum circuit, an error message will be fed back indicating that the content of the execution result cannot be obtained, thereby determining whether a new gate unit can be added to the virtual quantum circuit according to the needs of the user, which helps to avoid the unacceptable impact of adding gate units on the execution result of the quantum task through the interference of the equivalent indication information, and helps to improve the reliability of the execution result of the quantum task through the differential processing process. Example 2: A method for generating a second gate unit corresponding to a first gate unit when the first gate unit is a single-bit gate. In some embodiments, step 320, determining the second gate units corresponding to the first gate units in the logical quantum circuit according to the topological information of the virtual quantum chip, includes: for any first gate unit, when the first gate unit is used to perform logical processing on a logical quantum bit, the computer device determines the first gate unit corresponding to the logical quantum bit as the second gate unit. Determining the first gate unit corresponding to the logical quantum bit as the second gate unit means using a quantum gate of the same type as the first gate unit to perform logical processing on the virtual quantum bit corresponding to the logical quantum bit. For the relevant content of this step, please refer to the above embodiment, which will not be repeated here. The above process introduces that the first gate unit is used to determine the content of the second gate unit when performing logical processing on a logical qubit. When the first gate unit is used to perform logical processing on a logical qubit, it is possible to avoid additional consideration of other logical qubits, and determine the first gate unit corresponding to the logical qubit as the second gate unit, so that the virtual qubit corresponding to the logical qubit can be processed in a targeted manner through the second gate unit, which can improve the determination efficiency of the second gate unit without affecting the accuracy of the logical processing. In an example of generating a virtual quantum circuit, the computer device determines the second gate units corresponding to each first gate unit in the logical quantum circuit according to the topological information of the virtual quantum chip. In this process, the computer device determines the generation method of the second gate unit corresponding to the first gate unit according to the type of the first gate unit, which mainly includes several situations: In case 1.0, when the first gate unit is used to perform logic processing on a logical quantum bit, the first gate unit corresponding to the logical quantum bit is determined as the second gate unit. In case 2.0, when the first gate unit is used to perform logical processing on the first logical qubit and the second logical qubit, the computer device determines, based on the topological information of the virtual quantum chip, first information used to characterize whether there is connectivity between the first virtual qubit and the second virtual qubit; if the first information characterizes that there is connectivity between the first virtual qubit and the second virtual qubit, the first gate unit is determined as the second gate unit. Case 3.1: When the first gate unit is used to perform logical processing on the first logical quantum bit and the second logical quantum bit, the computer device determines the first information used to characterize whether there is connectivity between the first virtual quantum bit and the second virtual quantum bit according to the topological information of the virtual quantum chip; when the first information characterizes that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, the computer device obtains equivalent indication information; when the equivalent indication information is to allow at least one different gate unit between the logical quantum link and the virtual quantum link, the computer device determines the equivalent gate unit of the first unit and uses the equivalent gate unit as the second gate unit. For the relevant content of this step, please refer to the above embodiment, which will not be repeated here. Case 3.2: In the case where the first gate unit is used to perform logic processing on the first logical quantum bit and the second logical quantum bit, the computer device determines, based on the topological information of the virtual quantum chip, the first virtual quantum bit and the second virtual quantum bit. first information on whether there is connectivity between the quasi-quantum bits; when the first information represents that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, the computer device obtains equivalent indication information; when the equivalent indication information is that at least one different gate unit is not allowed between the logical quantum circuit and the virtual quantum circuit, the computer device does not generate an equivalent gate unit of the first gate unit, the quantum task cannot be executed, and an error prompt is returned, which means that the quantum task execution has failed. For situations 1.0, 2.0 and 3.1, the computer device generates a virtual quantum circuit for the quantum task according to the second gate units corresponding to the first gate units and the timing relationship of the first gate units in the logical quantum circuit. The following is an introduction to the method for generating a physical quantum circuit through an embodiment, and the execution subject of this step is a server. In some embodiments, step 330, generating a physical quantum circuit for a quantum task according to the virtual quantum circuit and the bit mapping relationship between the virtual quantum chip and the physical quantum chip, may include the following sub-steps: Sub-step 332: determining, according to the bit mapping relationship, physical quantum bits corresponding to at least one virtual quantum bit included in the virtual quantum chip. For the relevant contents of the bit mapping relationship, please refer to the above embodiment and no further description will be given here. Optionally, the bit mapping relationship refers to the mapping relationship between the identification information of the virtual quantum bit and the identification information of the physical quantum bit. Exemplarily, for any virtual quantum bit included in the virtual quantum circuit, the computer device determines the physical quantum bit corresponding to the virtual quantum bit according to the bit mapping relationship and the identification information of the virtual quantum bit. Sub-step 334, replacing each virtual quantum bit in the virtual quantum circuit with a physical quantum bit corresponding to the virtual quantum bit, to obtain a physical quantum circuit for the quantum task. Since the virtual quantum chip and its corresponding physical quantum chip have the same topological information, the logical operation on a virtual quantum bit can be performed in the physical quantum bit corresponding to the virtual quantum bit. In other words, the gate units included in the virtual quantum circuit and the physical quantum circuit are the same, and the computer device only needs to replace each virtual quantum bit in the virtual quantum circuit with the corresponding physical quantum bit to obtain the quantum circuit of the quantum task. The above steps 332 and 334 introduce the content of obtaining the physical quantum circuit according to the bit mapping relationship. Based on the bit mapping relationship, the correspondence between the virtual quantum bit and the physical quantum bit is characterized. Therefore, after determining the virtual quantum circuit and the virtual quantum bit therein, the physical quantum bits corresponding to the multiple virtual quantum bits can be determined according to the bit mapping relationship, thereby determining multiple physical quantum bits from the physical quantum chip, and constructing and generating a physical quantum circuit represented by multiple physical quantum bits by replacing the virtual quantum bits. In this way, after the physical quantum chip is divided into multiple virtual quantum chips, the partial structure corresponding to the virtual quantum chip can be located more quickly from the physical quantum chip according to the known bit mapping relationship, and the physical quantum circuit corresponding to the partial structure is generated. Not only will too many execution steps not be introduced in the process of generating the execution result of the quantum task, but it is also conducive to more targeted generation and construction of corresponding physical quantum circuits for different partial structures, thereby improving the utilization rate of quantum computing resources while helping to reduce the operating pressure of computer equipment, and facilitating the execution of different quantum tasks in parallel through different partial structures in the physical quantum chip. The generation process A of a physical quantum circuit is introduced and explained below through an example. FIG5 is a schematic diagram 510 of the structure of a virtual quantum chip provided by an exemplary embodiment of the present application. In this example, the virtual quantum chip is used to process a quantum task to be processed. The virtual quantum chip includes five virtual quantum bits, namely q[0], q[1], q[2], q[3], and q[4], wherein q[0] is connected to q[1], q[1] is connected to q[2], q[2] is connected to q[4], and q[3] is connected to q[4]. Step A10: The computer device obtains the logical quantum circuit of the quantum task to be executed. Optionally, step A10 may include the following sub-steps: Acquire task indication information, where the task indication information is used to indicate a quantum task to be performed; for any step indication included in the task indication information, determine a first gate unit corresponding to the step indication and at least one logical quantum bit logically processed by the first gate unit; and perform time-sequence association on the first gate units corresponding to the step indications according to the timing information between the step indications included in the task indication information, so as to generate a logical quantum circuit of the quantum task. In this example, the task instruction information refers to a quantum program consisting of program instructions implemented as follows. QREG q[4]; H q[0]; CX q[0],q[1]; CX q[1],q[2]; CX q[2],q[3]; MEASZ q[0]; MEASZ q[1]; MEASZ q[3]; MEASZ q[4]; Among them, QREG q[4] means that the quantum task to be executed requires 4 logical quantum bits, q[0], q[1], q[2], and q[4] represent 4 logical quantum bits; "H" represents an H gate, "H q[0]" represents the logical processing of the H gate on the logical quantum bit q[0], "CX" represents a CNOT gate, "CX q[i], q[j]" represents the logical processing of CNOT on q[i], q[j], where i=0, j=1, or i=1, j=2, or i=2, j=3, and "MEASZ" represents the observation of two quantum bits. Optionally, the order of each program instruction in the quantum program identifies the timing information between each gate unit in the logical quantum circuit. For example, in the above quantum program, the execution timing of H q[0] takes precedence over the execution timing of CX q[0], q[1], the execution timing of CX q[0], q[1] takes precedence over CX q[1], q[2], and so on. Since "MEASZ" does not involve logical operations on quantum bits and indicates the state of observed logical quantum bits, there is no limit on the execution timing between "MEASZ". Fig. 6 is a schematic diagram of a logic quantum circuit provided by an exemplary embodiment of the present application. The logic quantum circuit includes a plurality of logic quantum bits 610, namely q[0], q[1], q[2] and q[3], and logic gates acting on each logic quantum bit. In step A20, the computer device generates a virtual quantum circuit for the quantum task based on the topological information and logical quantum circuit of the virtual quantum chip. In this step, the computer device needs to determine the second gate units corresponding to each first gate unit in the logical quantum circuit according to the topological information of the virtual quantum chip; the computer device generates a virtual quantum circuit for the quantum task according to the second gate units corresponding to each first gate unit and the timing relationship between each first gate unit in the logical quantum circuit. 7 is a schematic diagram of a virtual quantum circuit provided by an exemplary embodiment of the present application. The virtual quantum circuit includes a plurality of virtual quantum bits 710, namely q[0], q[1], q[2], q[3] and q[4], and logic gates acting on each logical quantum bit. It can be seen from the above embodiments that in the process of generating a virtual quantum circuit, it is necessary to determine the second gate unit corresponding to each first gate unit in the logical quantum circuit according to the topological information of the virtual quantum chip. For the H gate on the logical quantum bit q[0] in the logical quantum circuit, since the H gate is a single-bit gate, the computer device determines to set the H gate on the line of the virtual quantum bit q[0]. For the CNOT gate between the logical quantum bits q[0] and q[1] in the logical quantum circuit, since there is connectivity between the virtual quantum bits q[0] and q[1] in the virtual quantum chip, a CNOT gate can be set between the virtual quantum bits q[0] and q[1]. That is, when the CNOT gate between the logical quantum bits q[0] and q[1] in the logical quantum circuit is used as the first gate unit, the computer device determines to use the first gate unit as the second gate unit. For the CNOT gate between the logical quantum bits q[0] and q[1] in the logical quantum circuit, similarly, a CNOT gate can be set between the virtual quantum bits q[1] and q[2] in the virtual quantum circuit. For the CNOT gate between the logical quantum bits q[2] and q[3] in the logical quantum circuit, since there is connectivity between the virtual quantum bits q[2] and q[3] in the virtual quantum chip, and there is connectivity between the virtual quantum bits q[2] and q[4], and there is connectivity between the virtual quantum bits q[4] and q[3]. Therefore, the computer device sets a swap gate unit between the virtual quantum bits q[2] and q[4], and after swapping the state of the virtual quantum bit q[2] to the virtual quantum bit q[4], the computer device sets a CNOT gate between the virtual quantum bits q[3] and q[4]. That is to say, for the case where the CNOT gate between the logical quantum bits q[2] and q[3] in the logical quantum circuit is used as the first gate unit, the computer device combines the exchange gate between the virtual quantum bits q[2] and q[4] and the CNOT gate unit between the virtual quantum bits q[3] and q[4] to obtain the second gate unit corresponding to the first gate unit. FIG8 is a schematic diagram of the correspondence between a virtual quantum chip and a physical quantum chip provided by an exemplary embodiment of the present application. As shown in FIG8 , the virtual quantum chip in FIG5 corresponds to a partial structure 810 of the physical quantum chip in FIG8 , wherein the virtual quantum bit q[0] corresponds to the physical quantum bit q

[0010] , virtual quantum bit q[1] corresponds to physical quantum bit q

[0011] , virtual quantum bit q[2] corresponds to physical quantum bit q

[0012] , virtual quantum bit q[4] corresponds to physical quantum bit q

[0013] , virtual quantum bit q[3] corresponds to physical quantum bit q

[0014] . Step A30: After generating the virtual quantum circuit, the computer device generates a physical quantum circuit according to the virtual quantum circuit and the bit mapping relationship. In this step, the computer device determines the physical quantum bits corresponding to at least one virtual quantum bit included in the virtual quantum chip according to the bit mapping relationship; the computer device replaces each virtual quantum bit in the virtual quantum circuit with the physical quantum bit corresponding to the virtual quantum bit to obtain the physical quantum circuit of the quantum task. Fig. 9 is a schematic diagram of a physical quantum chip provided by an exemplary embodiment of the present application. The physical quantum chip includes chrome-plated physical quantum bits 910, namely q

[0010] , q

[0011] , q

[0012] , q

[0013] and q

[0014] . Comparing Figure 9 with Figure 8, it is not difficult to find that the physical quantum circuit can be obtained by simply replacing the virtual quantum bits in the physical quantum circuit with the corresponding physical connected quantum bits. After generating the physical quantum circuit, the computer device generates a corresponding instruction set based on the physical quantum circuit and sends the instruction set to the physical quantum chip. The physical quantum chip executes according to the instruction set to obtain the execution result of the task to be executed. In an optional embodiment, a physical quantum circuit corresponding to a first quantum task is executed by a first partial structure in a physical quantum chip to obtain a first execution result corresponding to the first quantum task; and a physical quantum circuit corresponding to a second quantum task is executed by a second partial structure in a physical quantum chip to obtain a second execution result corresponding to the second quantum task. Among them, the first quantum task and the second quantum task are different tasks that are executed simultaneously, and the first part of the structure and the second part of the structure have a relatively independent relationship in the physical quantum chip. Schematically, the relative independence relationship is used to indicate that there is no overlap of physical quantum bits between the first part structure and the second part structure. For example: the first part structure includes physical quantum bit 1 and physical quantum bit 2, and the second part structure includes physical quantum bit 3 and physical quantum bit 4; the physical quantum circuit corresponding to the first quantum task A is executed through the first part structure, and the physical quantum circuit corresponding to the second quantum task B is executed through the second part structure. The above process introduces the content that multiple quantum tasks can be performed through a physical quantum chip. The physical quantum circuits corresponding to different quantum tasks are executed through different partial structures in the physical quantum chip. Optionally, the process can be implemented as a sequential execution state or a parallel execution state (synchronous execution state). When implemented as a parallel execution state, the corresponding quantum tasks are respectively executed through different partial structures in the physical quantum chip, which improves the execution speed of quantum tasks, avoids the tediousness of executing different quantum tasks through different physical quantum chips, and integrates the logical execution process on a physical quantum chip, which is convenient for the maintenance of the physical quantum chip, and also facilitates the differential adjustment of different partial structures, thereby improving the efficiency of logical processing. For the contents of this embodiment, reference may be made to the above embodiments, and this application will not elaborate on them here. In summary, the above method allows a physical quantum chip to be divided into multiple virtual quantum chips, so that each virtual quantum chip can perform different quantum tasks in the same period of time. Without increasing the number of physical quantum chips, the utilization rate of quantum computing resources and the response speed of the quantum service platform to user requests are improved. The following describes the method for segmenting a virtual quantum chip through several embodiments. In some embodiments, the method for executing a quantum task also includes: a computer device obtains request information for establishing a virtual quantum chip; based on the request information, determines a bit mapping relationship and required topological information of the virtual quantum chip, where the required topological information is used to characterize a topological relationship that needs to be satisfied between virtual quantum bits included in the virtual quantum chip; the computer device determines a partial structure corresponding to the virtual quantum chip in the physical quantum chip based on the bit mapping relationship and the required topological information of the virtual quantum chip. In some embodiments, the request information is used to request the physical quantum chip to be split, to establish a virtual quantum chip and a physical quantum chip. Optionally, the request information is provided by a staff member who maintains the physical quantum chip, or by a user who uses a quantum computing server. Exemplarily, the request information includes at least one of the following: a chip identifier of a physical quantum chip, a chip identifier of a virtual quantum chip, second information for characterizing the required topological information, and third information for characterizing the bit mapping relationship of the virtual quantum chip; wherein the chip identifier of the physical quantum chip is used to uniquely identify the physical quantum chip, and different physical quantum chips have different chip identifiers, and the chip identifier of the virtual quantum chip is used to uniquely identify the virtual quantum chip, and different virtual quantum chips have different chip identifiers. The second information is a program segment for indicating the required topological information, and the third topological information is a program segment for indicating the bit mapping relationship. Optionally, the computer device determines the bit mapping relationship and required topology information of the virtual quantum chip according to the request information, including: formatting the second information to obtain the required topology information of the virtual quantum chip; formatting the third information to obtain the bit mapping relationship of the virtual quantum chip. The above process introduces the content of determining the partial structure corresponding to the virtual quantum chip in the physical quantum chip according to the request information. After obtaining the request information, the physical quantum chip is segmented, and a mapping relationship between the virtual quantum chip and the physical quantum chip is established, and then the bit mapping relationship and required topological information of the virtual quantum chip are determined according to the request information, so as to determine the partial structure corresponding to the virtual quantum chip from the multiple partial structures corresponding to the segmented physical quantum chip. Dividing the physical quantum chip by request information helps to improve the flexibility of the physical quantum chip segmentation process, and facilitates the generation of virtual quantum chips with corresponding topological information according to actual needs. In some embodiments, determining a partial structure corresponding to the virtual quantum chip in the physical quantum chip according to the bit mapping relationship and required topological information of the virtual quantum chip includes: a computer device determines, from the physical quantum chip, the physical quantum bits to be mapped corresponding to the virtual quantum bits included in the virtual quantum chip according to the bit mapping relationship of the virtual quantum chip; when the states of the physical quantum bits to be mapped are all unoccupied, the computer device determines the topological relationship between the physical quantum bits to be mapped according to the physical topology of the physical quantum chip; if the topological relationship between the physical quantum bits to be mapped meets the required topological information, the computer device determines the partial structure of the physical quantum chip including the physical quantum bits to be mapped as the partial structure corresponding to the virtual quantum chip in the physical quantum chip. Optionally, thereafter, the computer device adjusts the state of the physical quantum bits included in the corresponding partial structure in the physical quantum chip to an occupied state. In some embodiments, a computer device determines whether the topological relationship between the physical quantum bits to be mapped satisfies the required topological information; if the topological relationship between the physical quantum bits to be mapped satisfies the required topological information, the computer device determines the partial structure of the physical quantum chip including the physical quantum bits to be mapped as the corresponding partial structure of the virtual quantum chip in the physical quantum chip; if the topological relationship between the physical quantum bits to be mapped does not satisfy the required topological information, the computer device cannot map the partial structure of the physical quantum chip to the virtual quantum chip. The above process introduces the content of determining the corresponding partial structure from the physical quantum chip. With the help of the bit mapping relationship, the physical quantum bits corresponding to the multiple virtual quantum bits in the virtual quantum chip are determined from the physical quantum chip, and the current physical quantum bits are prevented from participating in the execution process of other quantum tasks according to the situation that the physical quantum bits are in an occupied state, so as to avoid the problem of interfering with other quantum tasks; in addition, when multiple physical quantum bits are in an unoccupied state, it is determined whether the topological relationship between the multiple physical quantum bits meets the required topological information corresponding to the request information, and when the required topological information is met, the part including multiple physical quantum bits is determined as the partial structure to be determined, thereby improving the accuracy of determining the partial structure based on the request information. The following two examples introduce the mapping method of the virtual quantum chip. FIG. 10 is a schematic diagram of a virtual quantum chip mapping process provided by an exemplary embodiment of the present application. As shown in FIG10 , the virtual quantum chip includes virtual quantum bits q[0], q[1], and q[2]. The required topological information of the virtual quantum chip is that there is connectivity between virtual quantum bits q[0] and q[1], there is connectivity between virtual quantum bits q[1] and q[2], and there is connectivity between virtual quantum bits q[0] and q[2]. The bit mapping relationship includes: virtual quantum bit q[0] corresponds to physical quantum bit q

[0010] , virtual quantum bit q[1] corresponds to physical quantum bit q

[0011] , and virtual quantum bit q[2] corresponds to physical quantum bit q

[0016] . Referring to the physical topology of the physical quantum chip on the right side of FIG10 , the physical quantum bit to be mapped is in the partial structure 1010, there is connectivity between the physical quantum bits q

[0010] and q

[0011] , there is connectivity between the physical quantum bits q

[0011] and q

[0016] , and there is no connectivity between the physical quantum bits q

[0011] and q

[0016] . The computer device determines that the topological relationship between the physical quantum bits to be mapped does not meet the required topological information. Therefore, the physical quantum chip cannot be split to obtain the virtual quantum chip. FIG. 11 is a schematic diagram of a virtual quantum chip mapping process provided by another exemplary embodiment of the present application. As shown in FIG11 , the virtual quantum chip includes virtual quantum bits q[0], q[1], q[2], and q[3]. The required topological information of the virtual quantum chip is that there is connectivity between virtual quantum bits q[0] and q[1], there is connectivity between virtual quantum bits q[1] and q[2], there is connectivity between virtual quantum bits q[2] and q[3], and there is connectivity between virtual quantum bits q[0] and q[3]. The bit mapping relationship includes: virtual quantum bit q[0] corresponds to physical quantum bit q[0], virtual quantum bit q[1] corresponds to physical quantum bit q[1], virtual quantum bit q[3] corresponds to physical quantum bit q[5], and virtual quantum bit q[2] corresponds to physical quantum bit q[6]. Referring to the physical topology of the physical quantum chip on the right side of FIG11 , the physical quantum bits to be mapped are in partial structure 1110; there is connectivity between the physical quantum bits q[0] and q[1], there is connectivity between the physical quantum bits q[0] and q[5], there is connectivity between the physical quantum bits q[1] and q[6], and there is connectivity between the physical quantum bits q[6] and q[5]. Therefore, the computer device determines that the topological relationship between the physical quantum bits to be mapped meets the required topological information, and can split the physical quantum chip into a virtual quantum chip. The following is an example to introduce and illustrate the execution process B of the quantum task provided by this application. Step B10: The computer device obtains request information for establishing a virtual quantum chip; and determines the bit mapping relationship and required topology information of the virtual quantum chip according to the request information. Step B20, determining the virtual quantum bits included in the virtual quantum chip and the physical quantum bits to be mapped corresponding to them in the physical quantum chip according to the bit mapping relationship of the virtual quantum chip; when the states of the physical quantum bits to be mapped are all unoccupied, determining the topological relationship between the physical quantum bits to be mapped according to the physical topology of the physical quantum chip; if the topological relationship between the physical quantum bits to be mapped meets the required topological information, determining the partial structure of the physical quantum chip including the physical quantum bits to be mapped as the partial structure corresponding to the virtual quantum chip in the physical quantum chip. After the physical quantum chip is divided into multiple virtual quantum bits, the execution process of the quantum task begins. Step B30, the computer device obtains task instruction information; for any step instruction included in the task instruction information, determines the first gate unit corresponding to the step instruction, and at least one logical quantum bit logically processed by the first gate unit; according to the timing information between the various step instructions included in the task instruction information, the first gate units corresponding to the various step instructions are time-sequentially associated to generate a logical quantum circuit for the quantum task. Step B40: The computer device determines the second gate units corresponding to the first gate units in the logic quantum circuit according to the topological information of the virtual quantum chip. This step includes multiple situations and judgment processes. Please refer to the above embodiment for related contents, which will not be described here. Step B50: The computer device generates a virtual quantum circuit for the quantum task according to the second gate units corresponding to the first gate units and the timing relationship between the first gate units in the logical quantum circuit. Step B60: The computer device determines the physical quantum bits corresponding to at least one virtual quantum bit included in the virtual quantum chip according to the bit mapping relationship; replaces each virtual quantum bit in the virtual quantum circuit with the physical quantum bit corresponding to the virtual quantum bit, and obtains the physical quantum circuit of the quantum task. Step B70, the computer device executes the physical quantum circuit through the partial structure in the physical quantum chip to obtain the execution result of the quantum task. In order not to increase the redundant space, the relevant contents of each step of this embodiment can be referred to the embodiments corresponding to each step above, and will not be repeated here. This method allows one physical quantum chip to correspond to multiple virtual quantum chips. The virtual quantum chips are used to limit the physical quantum bits used to perform quantum tasks, so that the same physical quantum bit is not involved in two quantum tasks in the same period of time, causing the execution processes of the two quantum tasks to interfere with each other. The physical topology between the quantum bits is resolved, allowing the physical quantum chip to perform multiple quantum tasks at the same time, which helps to improve the utilization efficiency of quantum computing resources and increase the amount of data. The response speed of the subtask. 12 shows a block diagram of a device for executing a quantum task provided by an exemplary embodiment of the present application. The device 1200 may include: a circuit generation module 1210 , a first mapping module 1220 , a second mapping module 1230 , and a result generation module 1240 . The circuit generation module 1210 is used to obtain a logical quantum circuit, where the logical quantum circuit is an abstract logical circuit used to perform a quantum task. The first mapping module 1220 is used to generate a virtual quantum circuit for the quantum task according to the topological information represented by the virtual quantum chip and the logical quantum circuit, wherein the virtual quantum chip corresponds to a partial structure of the physical quantum chip, the topological information is used to represent the topological relationship between the virtual quantum bits included in the virtual quantum chip, and the virtual quantum circuit is a circuit constructed based on the virtual quantum bits. The second mapping module 1230 is used to generate a physical quantum circuit for the quantum task according to the virtual quantum circuit and a bit mapping relationship between the virtual quantum chip and the physical quantum chip, wherein the bit mapping relationship is used to indicate the physical quantum bit corresponding to the virtual quantum bit in the physical quantum chip. The result generating module 1240 is used to execute the physical quantum circuit through a part of the structure in the physical quantum chip to obtain the execution result of the quantum task. In some embodiments, the result generating module 1240 is further used to execute the physical quantum circuit corresponding to the first quantum task through the first partial structure in the physical quantum chip to obtain a first execution result corresponding to the first quantum task; execute the physical quantum circuit corresponding to the second quantum task through the second partial structure in the physical quantum chip to obtain a second execution result corresponding to the second quantum task; the first quantum task and the second quantum task are different tasks executed synchronously, and the first partial structure and the second partial structure have a relatively independent relationship in the physical quantum chip. In some embodiments, the first mapping module 1220 includes: a gate unit generation submodule, used to determine, according to the topological information of the virtual quantum chip, second gate units corresponding to each first gate unit in the logical quantum circuit, wherein the first gate unit is a quantum gate in the logical quantum circuit used to perform logical processing on a logical quantum bit, and the second gate unit is a quantum gate used to perform the same logical processing as the first gate unit on the virtual quantum bit; and a circuit generation submodule, used to generate a virtual quantum circuit for the quantum task according to the second gate units corresponding to each first gate unit and the timing relationship of each first gate unit in the logical quantum circuit. In some embodiments, the gate unit generation submodule includes: an information determination unit, which is used to, for any one of the first gate units, when the first gate unit is used to perform logical processing on the first logical quantum bit and the second logical quantum bit, determine first information used to characterize the connection association relationship between the first virtual quantum bit and the second virtual quantum bit according to the topological information of the virtual quantum chip; wherein the first virtual quantum bit corresponds to the first logical quantum bit, and the second virtual quantum bit corresponds to the second logical quantum bit; and a gate determination unit, which is used to determine the second gate unit corresponding to the first gate unit according to the first information. In some embodiments, the information determination unit includes a first subunit, which is used to determine the first gate unit as the second gate unit if the first information represents that there is connectivity between the first virtual quantum bit and the second virtual quantum bit; a second subunit, which is used to determine a state exchange link according to the topological information of the virtual quantum chip if the first information represents that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, wherein the state exchange link is used to exchange the state of at least one virtual quantum bit of the first virtual quantum bit and the second virtual quantum bit; according to the state exchange link, determine at least one exchange gate unit; determine an equivalent gate unit obtained by combining the at least one exchange gate unit and the first gate unit as the second gate unit, wherein the exchange gate unit is used to exchange the states of two quantum bits respectively input into the exchange gate unit, and in the equivalent gate unit, the operation timing of the exchange gate unit takes precedence over the operation timing of the first gate unit. In some embodiments, the second subunit is used for determining, for any one of the first state exchange link and the second state exchange link, one of the exchange gate units between any two adjacent virtual quantum bits in the state exchange link when the state exchange link includes at least two virtual quantum bits; wherein the state exchange link includes at least one of the following: the first state exchange link A state exchange link and a second state exchange link, the first state exchange link having at least one virtual quantum bit including the first virtual quantum bit, the second state exchange link having at least one virtual quantum bit including the second virtual quantum bit, and the last virtual quantum bit in the first state exchange link and the last virtual quantum bit in the second state exchange link having connectivity. In some embodiments, the device 1200 further includes: an information determination module, configured to obtain equivalent indication information, wherein the equivalent indication information is used to characterize the permission of at least one different gate unit between the logical quantum circuit and the virtual quantum circuit; when the equivalent indication information characterizes that at least one different gate unit is allowed between the logical quantum circuit and the virtual quantum circuit, determining a state exchange link according to the topological information of the virtual quantum chip; when the equivalent indication information characterizes that at least one different gate unit is not allowed between the logical quantum circuit and the virtual quantum circuit, returning an error prompt, wherein the error prompt is used to characterize the failure of the execution of the quantum task. In some embodiments, the gate unit generating submodule is used to determine, for any one of the first gate units, the first gate unit as the second gate unit when the first gate unit is used to perform logical processing on a logical quantum bit. In some embodiments, the circuit generation module 1210 is used to obtain task indication information, where the task indication information is used to indicate the quantum task to be performed; for any step indication included in the task indication information, determine a first gate unit corresponding to the step indication, and at least one logical quantum bit logically processed by the first gate unit; and according to the timing information between the step indications included in the task indication information, perform timing association on the first gate units corresponding to the step indications respectively, to generate a logical quantum circuit for the quantum task. In some embodiments, the device 1200 further includes: an information acquisition module, used to acquire request information for establishing the virtual quantum chip; an information determination module, used to determine the bit mapping relationship and required topology information of the virtual quantum chip according to the request information, wherein the required topology information is used to characterize the topological relationship that needs to be satisfied between the virtual quantum bits included in the virtual quantum chip; a chip mapping module, used to determine the partial structure corresponding to the virtual quantum chip in the physical quantum chip according to the bit mapping relationship of the virtual quantum chip and the required topology information. In some embodiments, the chip mapping module is used to determine, from the physical quantum chip, the physical quantum bits to be mapped that respectively correspond to the virtual quantum bits included in the virtual quantum chip according to the bit mapping relationship of the virtual quantum chip; when the states of the physical quantum bits to be mapped are all unoccupied, determine the topological relationship between the physical quantum bits to be mapped according to the physical topology of the physical quantum chip; when the topological relationship between the physical quantum bits to be mapped meets the required topological information, determine the partial structure of the physical quantum chip including the physical quantum bits to be mapped as the partial structure corresponding to the virtual quantum chip in the physical quantum chip. In some embodiments, the second mapping module 1230 includes: determining, according to the bit mapping relationship, physical quantum bits corresponding to at least one virtual quantum bit included in the virtual quantum chip; replacing each virtual quantum bit in the virtual quantum circuit with a physical quantum bit corresponding to the virtual quantum bit, to obtain the physical quantum circuit of the quantum task. It should be noted that the device provided in the above embodiment, when realizing its function, only uses the division of the above functional modules as an example. In actual application, the above functions can be assigned to different functional modules as needed, that is, the content structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device provided in the above embodiment belongs to the same concept as the method embodiment, and its implementation process is detailed in the method embodiment, which will not be repeated here. Please refer to the description of the method side embodiment for the beneficial effects of the device provided in the above embodiment, which will not be repeated here. FIG13 shows a block diagram of a computer device provided by an exemplary embodiment of the present application. Generally, the computer device 1300 includes: a processor 1301 and a memory 1302 . The processor 1301 may include one or more processing cores, such as a 4-core processor, a 13-core processor, etc. The memory 1302 may include one or more computer-readable storage media, which may be tangible and non-transitory. The memory 1302 may also include high-speed random access memory and non-volatile memory, such as a In some embodiments, the non-transitory computer-readable storage medium in the memory 1302 stores at least one program, and the at least one program is loaded and executed by the processor 1301 to implement the quantum task execution method provided by the above-mentioned method embodiments. An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the quantum task execution method provided by the above-mentioned method embodiments. The computer readable media may include computer storage media and communication media. Computer storage media include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. An embodiment of the present application also provides a computer program product, which includes a computer program. The computer program is stored in a computer-readable storage medium, and a processor reads and executes the computer program from the computer-readable storage medium to implement the quantum task execution method provided in the above-mentioned method embodiments. It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship. It should be understood that the "multiple" mentioned in this article refers to two or more. In addition, the step numbers described in this article only exemplify a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application do not limit this. The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for executing a quantum task, performed by a computer device, the method comprising: Acquire a logic quantum circuit, wherein the logic quantum circuit is an abstract logic circuit for performing a quantum task; Generate a virtual quantum circuit for the quantum task according to the topological information represented by the virtual quantum chip and the logical quantum circuit, wherein the virtual quantum chip corresponds to a partial structure of a physical quantum chip, the topological information is used to represent the topological relationship between virtual quantum bits included in the virtual quantum chip, and the virtual quantum circuit is a circuit constructed based on the virtual quantum bits; Generate a physical quantum circuit for the quantum task according to the virtual quantum circuit and a bit mapping relationship between the virtual quantum chip and the physical quantum chip, wherein the bit mapping relationship is used to indicate a physical quantum bit corresponding to the virtual quantum bit in the physical quantum chip; The physical quantum circuit is executed by the partial structure in the physical quantum chip to obtain an execution result of the quantum task.

2. The method according to claim 1, wherein: The executing the physical quantum circuit by using the partial structure in the physical quantum chip to obtain the execution result of the quantum task includes: Executing a physical quantum circuit corresponding to a first quantum task by using a first partial structure in the physical quantum chip to obtain a first execution result corresponding to the first quantum task; The physical quantum circuit corresponding to the second quantum task is executed by the second partial structure in the physical quantum chip to obtain a second execution result corresponding to the second quantum task; the first quantum task and the second quantum task are different tasks executed synchronously, and the first partial structure and the second partial structure have a relatively independent relationship in the physical quantum chip.

3. The method according to claim 1 or 2, wherein: The step of generating a virtual quantum circuit for the quantum task according to the topological information represented by the virtual quantum chip and the logical quantum circuit comprises: Determine, according to the topological information of the virtual quantum chip, second gate units corresponding to the first gate units in the logic quantum circuit, wherein the first gate unit is a quantum gate in the logic quantum circuit for performing logical processing on a logic quantum bit, and the second gate unit is a quantum gate for performing the same logical processing on the virtual quantum bit as the first gate unit; A virtual quantum circuit of the quantum task is generated according to the second gate units corresponding to the first gate units and the timing relationship of the first gate units in the logical quantum circuit.

4. The method according to claim 3, wherein: The step of determining, according to the topological information of the virtual quantum chip, second gate units respectively corresponding to the first gate units in the logic quantum circuit comprises: For any one of the first gate units, when the first gate unit is used to perform logic processing on a first logical qubit and a second logical qubit, first information for characterizing a connection association relationship between the first virtual qubit and the second virtual qubit is determined according to the topological information of the virtual quantum chip; wherein the first virtual qubit corresponds to the first logical qubit, and the second virtual qubit corresponds to the second logical qubit; A second door unit corresponding to the first door unit is determined according to the first information.

5. The method according to claim 4, wherein: The step of determining, according to the first information, the second door unit corresponding to the first door unit includes: If the first information indicates that the first virtual quantum bit and the second virtual quantum bit are connected, the first gate unit is determined as the second gate unit; If the first information indicates that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, a state exchange link is determined according to the topological information of the virtual quantum chip, and the state exchange link is used to exchange the The state of at least one virtual quantum bit among the first virtual quantum bit and the second virtual quantum bit; at least one exchange gate unit is determined according to the state exchange link; an equivalent gate unit obtained by combining the at least one exchange gate unit and the first gate unit is determined as the second gate unit, the exchange gate unit is used to exchange the states of two quantum bits respectively input to the exchange gate unit, and in the equivalent gate unit, the operation timing of the exchange gate unit takes precedence over the operation timing of the first gate unit.

6. The method according to claim 5, wherein: The step of determining at least one switching gate unit according to the state switching link comprises: In the case where the state exchange link includes at least two virtual quantum bits, for any two adjacent virtual quantum bits in the state exchange link, one exchange gate unit is determined between the adjacent virtual quantum bits; The state exchange link includes at least one of a first state exchange link and a second state exchange link, the first state exchange link includes at least one virtual quantum bit including the first virtual quantum bit, the second state exchange link includes at least one virtual quantum bit including the second virtual quantum bit, and there is connectivity between the last virtual quantum bit in the first state exchange link and the last virtual quantum bit in the second state exchange link.

7. The method according to claim 5, wherein: Before determining the state exchange link according to the topological information of the virtual quantum chip, the method further includes: Acquire equivalent indication information, where the equivalent indication information is used to characterize an allowable situation for at least one different gate unit between the logic quantum circuit and the virtual quantum circuit; In a case where the equivalent indication information indicates that at least one different gate unit is allowed between the logical quantum circuit and the virtual quantum circuit, determining a state exchange link according to the topology information of the virtual quantum chip; In a case where the equivalent indication information indicates that at least one different gate unit is not allowed between the logical quantum circuit and the virtual quantum circuit, an error prompt is returned, where the error prompt is used to indicate that the execution of the quantum task has failed.

8. The method according to claim 3, wherein: The step of determining, according to the topological information of the virtual quantum chip, second gate units respectively corresponding to the first gate units in the logic quantum circuit comprises: For any one of the first gate units, when the first gate unit is used to perform logical processing on a logical quantum bit, the first gate unit is determined as the second gate unit.

9. The method according to any one of claims 1 to 8, wherein: The acquisition of a logic quantum circuit comprises: Acquiring task indication information, where the task indication information is used to indicate the quantum task to be performed; For any step indication included in the task indication information, determine a first gate unit corresponding to the step indication and at least one logical qubit logically processed by the first gate unit; According to the timing information between the step instructions included in the task instruction information, the first gate units corresponding to the step instructions are time-sequentially associated to generate a logical quantum circuit of the quantum task.

10. The method according to any one of claims 1 to 9, wherein: The method further comprises: Obtaining request information for establishing the virtual quantum chip; Determining, according to the request information, a bit mapping relationship and required topology information of the virtual quantum chip, wherein the required topology information is used to characterize a topological relationship that needs to be satisfied between virtual quantum bits included in the virtual quantum chip; According to the bit mapping relationship of the virtual quantum chip and the required topology information, a partial structure corresponding to the virtual quantum chip in the physical quantum chip is determined.

11. The method according to claim 10, wherein: The determining, according to the bit mapping relationship of the virtual quantum chip and the required topology information, a partial structure corresponding to the virtual quantum chip in the physical quantum chip includes: According to the bit mapping relationship of the virtual quantum chip, determining, from the physical quantum chip, physical quantum bits to be mapped that respectively correspond to the virtual quantum bits included in the virtual quantum chip; When the states of the physical quantum bits to be mapped are all unoccupied states, determining the topological relationship between the physical quantum bits to be mapped according to the physical topology of the physical quantum chip; If the topological relationship between the physical quantum bits to be mapped meets the required topological information, the partial structure of the physical quantum chip including the physical quantum bits to be mapped is determined as the corresponding partial structure of the virtual quantum chip in the physical quantum chip.

12. The method according to any one of claims 1 to 11, wherein: Generating a physical quantum circuit for the quantum task according to the virtual quantum circuit and the bit mapping relationship between the virtual quantum chip and the physical quantum chip includes: Determining, according to the bit mapping relationship, physical quantum bits corresponding to at least one virtual quantum bit included in the virtual quantum chip; Each virtual quantum bit in the virtual quantum circuit is replaced with a physical quantum bit corresponding to the virtual quantum bit to obtain the physical quantum circuit of the quantum task.

13. A device for executing a quantum task, the device comprising: A circuit generation module, used to obtain a logic quantum circuit, wherein the logic quantum circuit is an abstract logic circuit used to perform a quantum task; A first mapping module is used to generate a virtual quantum circuit of the quantum task according to the topological information represented by the virtual quantum chip and the logical quantum circuit, wherein the virtual quantum chip corresponds to a partial structure of the physical quantum chip, the topological information is used to represent the topological relationship between the virtual quantum bits included in the virtual quantum chip, and the virtual quantum circuit is a circuit constructed based on the virtual quantum bits; A second mapping module is used to generate a physical quantum circuit of the quantum task according to the virtual quantum circuit and a bit mapping relationship between the virtual quantum chip and the physical quantum chip, wherein the bit mapping relationship is used to indicate the physical quantum bit corresponding to the virtual quantum bit in the physical quantum chip, and the physical quantum circuit is a circuit constructed based on the physical quantum bit; A result generating module is used to execute the physical quantum circuit through the partial structure in the physical quantum chip to obtain the execution result of the quantum task.

14. The device according to claim 13, wherein: The result generating module is further used to execute the physical quantum circuit corresponding to the first quantum task through the first partial structure in the physical quantum chip to obtain a first execution result corresponding to the first quantum task; execute the physical quantum circuit corresponding to the second quantum task through the second partial structure in the physical quantum chip to obtain a second execution result corresponding to the second quantum task; the first quantum task and the second quantum task are different tasks executed synchronously, and the first partial structure and the second partial structure have a relatively independent relationship in the physical quantum chip.

15. The device according to claim 13 or 14, wherein: The first mapping module is further used to determine, according to the topological information of the virtual quantum chip, second gate units corresponding to the first gate units in the logic quantum circuit, where the first gate unit is a quantum gate in the logic quantum circuit used to perform logical processing on a logic quantum bit, and the second gate unit is a quantum gate used to perform the same logical processing as the first gate unit on the virtual quantum bit; and generate a virtual quantum circuit for the quantum task according to the second gate units corresponding to the first gate units and the timing relationship between the first gate units in the logic quantum circuit.

16. The device according to claim 15, wherein: The first mapping module is further used to determine, for any one of the first gate units, first information used to characterize a connection association relationship between the first virtual quantum bit and the second virtual quantum bit according to the topological information of the virtual quantum chip when the first gate unit is used to perform logical processing on the first logical quantum bit and the second logical quantum bit; wherein the first virtual quantum bit corresponds to the first logical quantum bit, and the second virtual quantum bit corresponds to the second logical quantum bit; and determine the second gate unit corresponding to the first gate unit according to the first information.

17. The device according to claim 16, wherein: The first mapping module is further used to determine the first gate unit as the second gate unit if the first information indicates that there is connectivity between the first virtual quantum bit and the second virtual quantum bit; if the first information indicates that there is no connectivity between the first virtual quantum bit and the second virtual quantum bit, determine a state exchange link according to the topological information of the virtual quantum chip, wherein the state exchange link is used to exchange the state of at least one virtual quantum bit of the first virtual quantum bit and the second virtual quantum bit; determine at least one exchange gate unit according to the state exchange link; determine an equivalent gate unit obtained by combining the at least one exchange gate unit and the first gate unit as the second gate unit, wherein the exchange gate unit is used to exchange the states of two quantum bits respectively input into the exchange gate unit, and in the equivalent gate unit, the operation timing of the exchange gate unit takes precedence over the operation timing of the first gate unit.

18. A computer device, comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the method according to any one of claims 1 to 12.

19. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, wherein the computer program is loaded and executed by a processor to implement the method according to any one of claims 1 to 12.

20. A computer program product, comprising a computer program, wherein the computer program is stored in a computer-readable storage medium, and a processor reads and executes the computer program from the computer-readable storage medium to implement the method according to any one of claims 1 to 12.

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