Superconducting quantum bit mapping method based on specific topological structure

Abstract

The invention provides a superconductive quantum bit mapping method based on a specific topological structure, and belongs to the field of quantum circuit compilation, and the method comprises the following steps: S1, converting a quantum circuit into a graph format, and storing the graph format; s2, converting the topological structure of the quantum computer into a graph format and storing the graph format; s3, collecting parameters of physical characteristics of the quantum computer; s4, sorting the logic bits according to the output of the step S1; s5, sorting equipment bits, and finishing initial mapping; s6, completing the mapping of the adjacent nodes of the initial mapping according to the initial mapping; s7, checking logic bits which are not mapped completely, and repeating the steps S5 and S6 until final mapping is completed; and S8, checking whether the final mapping obtained in the step S7 can be executed and adjusted on the equipment or not. Physical characteristics of logic bits in a quantum circuit and equipment bits of a real quantum computer are extracted, mapping of the logic bits and the equipment bits is found, functions of the quantum circuit are modified, and the speed of finding an execution scheme of the quantum circuit is increased.

Description

Technical Field

[0001] The present invention relates to the field of quantum circuit compilation, and in particular to a superconducting quantum bit mapping method based on a specific topological structure. Background Art

[0002] As a groundbreaking new technology, quantum computers are developing rapidly and driving a revolution in computing power. However, despite the huge potential of quantum computers, their practical application still faces many challenges, one of which is qubit mapping. As a key step in quantum computing, the optimization of qubit mapping directly affects the efficiency and reliability of quantum computing. With the continuous advancement and complexity of quantum devices, new technologies and algorithms need to be continuously explored to cope with changing needs. Research in this field not only promotes the practical application of quantum computers, but also lays the foundation for future technological advances.

[0003] Quantum bit mapping refers to the process of assigning logical qubits (used to represent logical operation units in quantum algorithms) to physical qubits (operation units that actually exist in hardware). Qubit mapping is not only a key link in quantum computing tasks, but also directly affects the execution time, error accumulation and overall performance of quantum circuits. Due to the physical limitations of quantum computing hardware, the connection between each physical qubit is usually not complete. Therefore, many quantum algorithms need to insert swap (SWAP) gates to adjust the bit positions to make them adjacent during actual operation. These additional SWAP gate operations will significantly increase the circuit depth and introduce more noise, which especially affects the calculation accuracy in the high-noise environment of current quantum computers.

[0004] The existing challenges are:

[0005] 1. Physical topological limitations: The physical topological structure of quantum computers (such as linear chains, two-dimensional grids, etc.) limits the direct connection between quantum bits. This limitation makes it impossible to directly perform many two-bit gate operations, and it is necessary to adjust the position of the quantum bits by inserting SWAP gates.

[0006] 2. Noise and error rate: Current quantum computers are still in a high-noise environment. The operation of quantum bits is easily affected by environmental interference, resulting in a high error rate. The increase in SWAP gates will further aggravate this problem because more operations mean more potential sources of error.

[0007] 3. Circuit depth: The inserted SWAP gates significantly increase the depth of the quantum circuit, thereby extending the execution time. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a superconducting quantum bit mapping method based on a specific topological structure, which is used to solve the problems of physical topological limitations, noise and error rate of quantum computers in the prior art.

[0009] To achieve the above objectives and other related objectives, the present invention provides the following technical solutions:

[0010] The superconducting quantum bit mapping method based on a specific topological structure specifically includes the following steps:

[0011] S1, initialize the circuit topology graph G of the quantum circuit Q to be executed. Each logical quantum bit in the quantum circuit Q represents a vertex in the circuit topology graph G. If there is a two-qubit gate between two logical quantum bits in the quantum circuit Q, the corresponding two vertices in the circuit topology graph G are connected, otherwise they are not connected;

[0012] S2, initialize the structure topology graph T of the quantum computer to be run. Each device quantum bit in the quantum computer represents a vertex in the structure topology graph T. If a double quantum bit gate is allowed between two device quantum bits in the quantum computer, the corresponding two vertices in the structure topology graph T are connected, otherwise they are not connected;

[0013] S3, using quantum calibration technology, collects the physical properties of the device quantum bits, including the single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout ;

[0014] S4, according to the output of step S1, sort all the logic bits by mapping requirements, and select the logic bit L0 with the highest mapping requirement;

[0015] S5, according to steps S2 and S3, sort all device bits by quality, select the device bit D0 with the highest quality, and map the logic bit selected in step S4 to the device bit D0: L0→D0;

[0016] S6, regarding the mapping completed in step S5 as the initial mapping, respectively searching for the adjacent nodes whose logic bits and device bits are on the corresponding line topology graph obtained in step S1, sorting the adjacent nodes according to steps S4 and S5, completing the mapping according to the sorting, and updating the initial mapping according to the first bit in the sorting;

[0017] S7, check whether there are any logic bits that have not been mapped in the line topology diagram G, if so, record all the logic bits that have not been mapped to form a set R G , all unmapped device bits form the set R T , and repeat S5, S6;

[0018] S8, according to the final mapping obtained in step S7, check whether all quantum gates in the quantum circuit need to add additional auxiliary gates when executed on the quantum computer and output an executable quantum circuit corresponding to the final mapping.

[0019] In one embodiment of the present invention, step S1 includes:

[0020] S1.1, initialize an array A for each quantum gate in the quantum circuit Q to be executed, where each element in the array A contains the name, action bit and parameter of the quantum gate;

[0021] S1.2, initialize an undirected graph G0, where the vertex set V of the undirected graph G0 represents the logical qubits, and the edge set E represents the existence of a two-qubit gate between two logical qubits;

[0022] S1.3, traverse each element in the array A. If the element is a two-qubit gate and acts on logical qubits i and j, then add an edge connecting vertex i and fixed point j to the undirected graph G0 and form a line topology graph G.

[0023] In one embodiment of the present invention, step S2 includes:

[0024] S2.1, obtain a list of device bits of the quantum computer, each device bit is represented by a unique identifier;

[0025] S2.2, initialize an undirected graph T0, where the vertices of the undirected graph T0 represent device qubits, and the edge E′ represents the two-qubit gate that can be applied between two device qubits;

[0026] S2.3, traverse the device bit list and add the vertex corresponding to each device bit to the vertex set V′;

[0027] S2.4, according to the coupling information of the quantum computer, traverse all device bit pairs. If a double quantum bit gate is allowed between a pair of device bits, add an edge connecting the two vertices in the undirected graph T0 and form a structural topology graph T.

[0028] In one embodiment of the present invention, step S3 includes:

[0029] S3.1, Physical characteristics of measuring device bits, including single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout ;

[0030] S3.2, create F single Array, F doubleArrays and F readout array, and are used to store the measured single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout ;

[0031] S3.3, for the collection in F single Array, F double Arrays and F readout Verify the physical property data in the array to ensure the accuracy and completeness of the data;

[0032] S3.4, associate the verified physical property data with the vertex set V′ of the structural topology graph T to ensure that the physical property data of each vertex is accessible.

[0033] In one embodiment of the present invention, step S4 specifically includes the following steps:

[0034] S4.1, according to the line topology graph G, count the degree of each vertex in the vertex set V, that is, the number of edges connected to it, and sort them from large to small. The result is recorded as the vertex list P G ;

[0035] S4.2, if the vertex degrees in step S4.1 are the same, count the number of single-bit gates that appear on the logical bits in the quantum circuit Q according to array A, sort them from large to small according to the number of single-bit gates, and update the vertex list P G ;

[0036] S4.3, the vertex list P completed in step S4.2 G , the first vertex is selected as the logical bit with the highest mapping requirement.

[0037] In one embodiment of the present invention, S5 specifically includes the following steps:

[0038] S5.1, sort the device bits of the structure topology diagram T in S2.4 according to the method in S4.1, and record the sorting result as P0;

[0039] S5.2, if there are multiple vertices with the same degree, continue to count the sum of the degrees of the neighboring nodes of these vertices in the structural topology graph T, sort them from large to small, and update P0;

[0040] S5.3, according to F in S3.2 single Array, F double Arrays and F readout Array,sort the device bits according to different parameters, and sort the three fidelities from large to small, and record the three sortings as P1, P2, and P3 respectively;

[0041] S5.4, four rankings P0, P1, P2, P3 are obtained from steps S5.1, S5.2, and S5.3. For each vertex with four rankings R0, R1, R2, R3, calculate its comprehensive ranking: R T :=0.1R0+0.5R1+0.15R2+0.25R3, according to the comprehensive ranking R T Sort from small to large, and the result is recorded as P T ;

[0042] S5.5, sorting from high to low according to the comprehensive ranking, and selecting the highest device bit to map with the logic bit with the highest mapping requirement in step S4.3.

[0043] In one embodiment of the present invention, the process of iteratively searching for a mapping in S6 includes the following steps:

[0044] S6.1, taking the initial mapping L0→D0 as input, find the neighboring nodes of the logic bit L0 and the device bit D0 in the initial mapping in the line topology graph G and the structure topology graph T respectively, and then delete the mapped device bits and logic bits, respectively, and record them as N G (L0), N T (D0), if Then go to step S6.5, otherwise sort the neighboring node bits according to steps S4 and S5, N G The element mapping requirements in (L0) are sorted from large to small as {L1, L2, ..., L m},N T The elements in (D0) are sorted from high to low in terms of quality as {D1, D2, ..., D n};

[0045] S6.2, after sorting, recursively perform the following steps for i=1, 2, ..., min{m, n}: Execute the mapping L i →D i , regard i=1 as the initial mapping and recursively execute step S6.1 as input;

[0046] S6.3, check whether all the logical bits found in step S6.1 have been mapped. If not, find the N bits in step S6.1. T (D0) The neighbor nodes of all elements are obtained by deleting the device bits that have been mapped. After sorting by quality, the remaining logical bits are mapped in sequence. If the number of elements still cannot meet the mapping requirements of logical bits, continue to look for The neighbor nodes of all elements are obtained by removing the device bits that have been mapped. After sorting by quality, the remaining logical bits are mapped in sequence;

[0047] S6.4, repeat step S6.3 until all logic bits are mapped to device bits, or no suitable mapping can be found;

[0048] S6.5, Inspection If yes, go to step S6.6; if no, sort the remaining logic bits and device bits according to the result P G , P T , reselect a new initial mapping L0→D0 and go to step S6.1;

[0049] S6.6, output the final mapping result A subset of .

[0050] In one embodiment of the present invention, step S7 specifically includes:

[0051] S7.1, traverse all vertices of the line topology graph G, check whether each vertex has been mapped to a device bit, if so, record all unmapped logical bits to form a set R G ;

[0052] S7.2, traverse all vertices of the topological graph T, check whether each vertex has been mapped to a logical bit, if so, record all unmapped device bits to form a set R T ;

[0053] S7.3, repeat steps S5 and S6 until the set R G and the set R T Is empty.

[0054] In one embodiment of the present invention, the process of adding an additional auxiliary quantum gate in S8 includes the following steps:

[0055] S8.1, according to the final mapping result generated in step S7, find the device bits corresponding to all mapped logic bits in the structure topology graph T, and form a new corresponding subgraph, recorded as graph G';

[0056] S8.2, according to step S1, check whether all the two-bit gates in the circuit can be executed on the device represented by figure G', if yes, go to step S8.4, if not, go to step S8.3;

[0057] S8.3, find the two device bits acted by this two-bit gate through mapping, find a shortest path on the graph G', start from the starting point of the path, perform SWAP operations with the adjacent nodes on the path in turn, and update to the corresponding position of the circuit until the end of the path completes the SWAP operation, perform the required two-bit gate on the end of the path and the previous vertex, then start from the end, perform SWAP operations with the adjacent nodes on the path in turn, and update to the circuit until the starting point completes the SWAP operation;

[0058] S8.4, repeat steps S8.2 and S8.3 until all two-bit gates in the circuit can be executed;

[0059] S8.5 outputs the updated circuit.

[0060] As described above, the superconducting quantum bit mapping method based on a specific topological structure of the present invention has the following beneficial effects:

[0061] 1. Reduce the number of auxiliary gates: By optimizing the mapping of logical qubits to physical qubits, the use of unnecessary auxiliary gates (such as SWAP gates) is reduced. This not only reduces the depth and complexity of quantum circuits, but also reduces the noise and error rate caused by additional operations, thereby improving the efficiency of quantum computing.

[0062] 2. Improve the accuracy and efficiency of mapping: By initializing the circuit topology map and the structural topology map, the connection relationship between the logical qubits in the quantum circuit and the device qubits in the quantum computer is clearly displayed. This provides a clear basis for subsequent mapping and ensures the accuracy and efficiency of mapping.

[0063] 3. Enhance the reliability of quantum computing: Prioritize high-quality device quantum bits for mapping, which can effectively reduce the error rate of single-bit gates and two-bit gates. By comprehensively considering the physical properties of device bits (such as single-bit gate fidelity, two-bit gate fidelity, and reading fidelity), it ensures that the selected device bits have the best performance and improves the reliability of overall quantum computing.

[0064] 3. Support for complex quantum algorithms: This method can handle complex quantum circuits containing a large number of two-bit gates, ensuring that these circuits can be correctly executed on quantum computers with specific topologies.

[0065] 4. Dynamic adjustment and adaptability: By regularly measuring and updating the physical properties of the device’s quantum bits, the mapping strategy can be dynamically adjusted to adapt to changes in the performance of the quantum computer. This ensures the continued effectiveness of the mapping method at different times and on different devices, improving the robustness of the system.

[0066] 5. Handling complex topological structures: Through recursion and multi-level neighbor node search, it can handle complex topological structures and ensure that all logical bits can find appropriate device bits for mapping.

[0067] 6. Ensure the feasibility of the two-bit gates: Ensure that all two-bit gates can be correctly executed on the actual device by generating the corresponding subgraphs, checking the feasibility of the two-bit gates, adding SWAP gates, and repeatedly checking and adding SWAP gates.

[0068] 7. Improve overall performance: By comprehensively considering multiple factors (such as degree, neighbor node degree, and physical characteristics), the optimal device bits are selected for mapping, which reduces the error rate in quantum computing and improves overall computing performance. This enables quantum computers to better realize their potential in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 Shown is a schematic diagram of the process of the present invention;

[0070] Figure 2 An architectural diagram showing the bits of a device;

[0071] Figure 3 Displayed as IBM's heavy-hex architecture;

[0072] Figure 4 The following figure shows the added SWAP operation in step 8.3. DETAILED DESCRIPTION

[0073] The following specific embodiments illustrate the implementation of the present invention, and those familiar with the technology can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0074] See also Figure 1 The present invention provides a superconducting quantum bit mapping method based on a specific topological structure, and the steps include: S1, initializing a circuit topology graph G of a quantum circuit Q to be executed, each logical quantum bit in the quantum circuit Q represents a vertex in the circuit topology graph G, if a double quantum bit gate exists between two logical quantum bits in the quantum circuit Q, then the corresponding two vertices in the circuit topology graph G are connected, otherwise they are not connected; S2, initializing a structural topology graph T of a quantum computer to be run, each device quantum bit in the quantum computer represents a vertex in the structural topology graph T, if a double quantum bit gate is allowed between two device quantum bits in the quantum computer, then the corresponding two vertices in the structural topology graph T are connected, otherwise they are not connected; S3, using quantum calibration technology to collect physical properties of device quantum bits, including single-bit gate fidelity F single, two-bit gate fidelity F double , read fidelity F readout ; S4, according to the output of step S1, sort all the logic bits according to the mapping requirements, and select the logic bit L0 with the highest mapping requirement; S5, according to steps S2 and S3, sort all the device bits according to the quality, and select the device bit D0 with the highest quality, and map the logic bit selected in step S4 to the device bit D0: L0→D0; S6, regard the mapping completed in step S5 as the initial mapping, respectively find the adjacent nodes of its logic bits and device bits on the corresponding line topology map obtained in step S1, sort the adjacent nodes according to steps S4 and S5, complete the mapping according to the sorting, and update the initial mapping according to the first bit in the sorting; S7, check whether there are any logic bits that have not been mapped in the line topology map G, if so, record all the unmapped logic bits to form a set R G , all unmapped device bits form the set R T , and repeat S5, S6; S8, according to the final mapping obtained in step S7, check whether all quantum gates in the quantum circuit need to add additional auxiliary gates when executed on the quantum computer and output the executable quantum circuit corresponding to the final mapping.

[0075] The present invention reduces the use of unnecessary auxiliary gates (such as SWAP gates) by optimizing the mapping of logical qubits to physical qubits, improves the execution efficiency of quantum circuits, and gives priority to high-quality device qubits for mapping, which can effectively reduce the error rate of single-bit gates and double-bit gates and improve the reliability of overall quantum computing.

[0076] The step S1 includes: S1.1, according to each quantum gate in the quantum circuit Q to be executed, initialize an array A, each element in the array A contains the name, action bit and parameter of the quantum gate; S1.2, initialize an undirected graph G0, the vertex set V of the undirected graph G0 represents the logical quantum bit, and the edge set E represents the existence of a dual-qubit gate between two logical quantum bits; S1.3, traverse each element in the array A, if the element represents a dual-qubit gate and acts on logical quantum bits i and j, then add an edge connecting vertex i and fixed point j in the undirected graph G0, and form a circuit topology graph G.

[0077] By initializing the array A and the undirected graph G0, as well as the subsequent traversal and edge-adding process, the interaction relationship between the logical qubits in the quantum circuit is clarified, providing a clear foundation for subsequent mapping; the constructed circuit topology diagram G intuitively displays the structure of the quantum circuit, which helps to consider the interaction relationship when mapping the logical qubits in subsequent steps, thereby optimizing the mapping scheme and reducing the use of unnecessary auxiliary gates; the clear topological structure helps to quickly identify which logical qubits need special attention, thereby improving the efficiency and accuracy of the mapping process.

[0078] The step S2 includes: S2.1, obtaining a device bit list of the quantum computer, each device bit is represented by a unique identifier; S2.2, initializing an undirected graph T0, the vertices of the undirected graph T0 represent device quantum bits, and the edge E′ represents that a two-qubit gate is allowed between two device quantum bits; S2.3, traversing the device bit list, adding the vertex corresponding to each device bit to the vertex set V′; S2.4, traversing all device bit pairs according to the coupling information of the quantum computer, if a two-qubit gate is allowed between a pair of device bits, adding an edge connecting the two vertices to the undirected graph T0, and forming a structural topology graph T.

[0079] By initializing the undirected graph T0 and adding edges based on the coupling information, the connection relationship between the device qubits in the quantum computer is clearly shown. The establishment of the structural topology graph T allows the actual connection between the device qubits to be considered during the mapping process, providing a clear basis for subsequent mapping and optimization. This process not only improves the accuracy and efficiency of the mapping, but also supports complex quantum algorithms, optimizes resource utilization, and simplifies quantum circuit design.

[0080] The step S3 includes: S3.1, measuring the physical characteristics of the device bit, including the single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout ; S3.2, create F single Array, F double Arrays and F readout array, and are used to store the measured single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout ; S3.3, for the collection in F single Array, F double Arrays and F readout The physical property data in the array is verified to ensure the accuracy and completeness of the data; S3.4, the verified physical property data is associated with the vertex set V′ of the structural topology graph T to ensure that the physical property data of each vertex is accessible.

[0081] By verifying the physical property data, the accuracy and completeness of the data are ensured, mapping errors caused by data errors are avoided, and the reliability of mapping is improved; the verified physical property data is associated with the vertex set V′ of the structural topology graph T, so that the performance data of each device quantum bit can be easily obtained during the mapping process, so as to make the optimal mapping decision. By considering the single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout , device qubits with better performance can be prioritized for mapping, thereby reducing the error rate in quantum computing. By regularly measuring and updating the physical properties of device qubits, it can support dynamic adjustment of mapping strategies to adapt to performance changes of quantum computers.

[0082] like Figure 2 This is the architecture diagram of the 66 device bits in the Tianyan-176 superconducting quantum computer. The device bits roughly follow the planar quadrilateral mesh architecture. By sorting the quantum computer devices according to special rules, a greedy search algorithm is used to quickly find the local optimal mapping, ensure the connectivity of the mapping subgraph, and give a warning when the device cannot satisfy the quantum circuit. In practical applications, the topological structures of quantum devices are different, such as Figure 3 heavy-hex architecture, which is a different architecture from the Tianyan superconducting quantum computer.

[0083] Step S4 specifically includes the following steps: S4.1, according to the line topology graph G, count the degree of each vertex in the vertex set V, that is, the number of edges connected to it, and sort them from large to small, and the result is recorded as the vertex list P G ; S4.2, if the vertex degrees in step S4.1 are the same, count the number of single-bit gates that appear on the logical bits in the quantum circuit Q according to array A, sort them from large to small according to the number of single-bit gates, and update the vertex list P G ; S4.3, the vertex list P completed in step S4.2 G , the first vertex is selected as the logical bit with the highest mapping requirement.

[0084] By counting the degree of each vertex in the vertex set V and sorting them from large to small, we can prioritize mapping those logical bits that are most connected in the network. When the degrees of multiple vertices are the same, further sorting them according to the number of single-bit gates can ensure that those logical bits that are used more frequently in quantum circuits are placed in front. By prioritizing the mapping of the most demanded logical bits, we can reduce the number of auxiliary gate operations in quantum circuits, reduce the error rate in quantum computing, and improve the execution efficiency of quantum circuits.

[0085] S5 specifically includes the following steps: S5.1, sort the device bits of the structure topology graph T in S2.4 according to the method in S4.1, and record the sorting result as P0; S5.2, if there are multiple vertices with the same degree, continue to count the sum of the degrees of the neighboring nodes of these vertices in the structure topology graph T, sort them from large to small, and update P0; S5.3, according to F in S3.2 single Array, F double Arrays and F readout Array, sort the device bits according to different parameters respectively, sort the three fidelities from large to small, and record the three sorts as P1, P2, and P3 respectively; S5.4, obtain four sorts P0, P1, P2, and P3 from steps S5.1, S5.2, and S5.3, and calculate the comprehensive ranking of each vertex’s four rankings R0, R1, R2, and R3: R T :=0.1R0+0.5R1+0.15R2+0.25R3, according to the comprehensive ranking R T Sort from small to large, and the result is recorded as P T ; S5.5, sort from high to low according to the comprehensive ranking, and select the highest device bit to map with the logical bit with the highest mapping requirement in step S4.3.

[0086] Count the degree of each device bit, that is, the number of edges connected to it, and sort them from large to small by degree, and the result is recorded as the vertex list P0. This step is to find the device bit with the most connections in the network; if the degree of multiple vertices is the same in step S5.1, it is necessary to further sort the sum of the degrees of adjacent nodes to ensure that the device bits that occupy an important position in the topology are ranked first; then select the highest device bit and map it with the logic bit with the highest mapping requirement in step S4.3 to ensure that the most critical and most needed logic bit is mapped to the device bit with the best performance.

[0087] The process of iteratively searching for mappings in S6 includes the following steps: S6.1, taking the initial mapping L0→D0 as input, searching for the neighboring nodes of the logic bit L0 and the device bit D0 in the initial mapping in the line topology graph G and the structure topology graph T respectively, and then deleting the mapped device bits and logic bits, respectively denoted as N G (L0), N T (D0), if Then go to step S6.5, otherwise sort the neighboring node bits according to steps S4 and S5, N G The element mapping requirements in (L0) are sorted from large to small as {L1, L2, ..., L m},N T The elements in (D0) are sorted from high to low in terms of quality as {D1, D2, ..., D n}; S6.2, after sorting, recursively perform the following steps for i=1, 2, ..., mim{m, n}: Execute the mapping L i →D i , regard i=1 as the initial mapping, and recursively execute step S6.1 as input; S6.3, check whether all the logical bits found in step S6.1 have been mapped, if not, find N in step S6.1 T (D0) The neighbor nodes of all elements are obtained by deleting the device bits that have been mapped. After sorting by quality, the remaining logical bits are mapped in sequence. If the number of elements still cannot meet the mapping requirements of logical bits, continue to look for The neighbor nodes of all elements are obtained by removing the device bits that have been mapped. After sorting by quality, the remaining logical bits are mapped in sequence; S6.4, repeat step S6.3 until all logical bits are mapped to device bits, or no suitable mapping can be found; S6.5, check If yes, go to step S6.6; if no, sort the remaining logic bits and device bits according to the result P G , P T , reselect a new initial mapping L0→D0, enter step S6.1; S6.6, output the final mapping result A subset of .

[0088] The mapping is gradually optimized through an iterative process to ensure that high-quality and high-demand bits are selected as much as possible for each mapping; complex topological structures can be handled through recursion and multi-level neighbor node search; when a suitable mapping cannot be found, the initial mapping is reselected to ensure the flexibility and robustness of the entire mapping process; by comprehensively considering multiple factors (such as degree, neighbor node degree, and physical properties), the optimal device bits are selected for mapping, reducing the error rate in quantum computing.

[0089] The step S7 specifically includes: S7.1, traversing all vertices of the line topology graph G, checking whether each vertex has been mapped to a device bit, if so, recording all unmapped logical bits to form a set R G ; S7.2, traverse all vertices of the structure topology graph T, check whether each vertex has been mapped to a logical bit, if so, record all unmapped device bits to form a set R T ; S7.3, repeat steps S5 and S6 until the set R G and the set R T Is empty.

[0090] By checking the unmapped logical bits and device bits and repeating the mapping process, it is ensured that all logical bits can be successfully mapped to device bits to avoid omissions; through multiple checks and mappings, the completeness and accuracy of the mapping process are ensured; through multiple iterations and checks, complex quantum circuits can be processed to ensure that all logical bits can find appropriate device bits for mapping.

[0091] The process of adding additional auxiliary quantum gates in S8 includes the following steps: S8.1, according to the final mapping result generated in step S7, find the device bits corresponding to all mapped logical bits in the structural topology graph T, and form a new corresponding subgraph, recorded as graph G'; S8.2, according to step S1, check whether all two-bit gates in the circuit can be executed on the device represented by graph G', if yes, proceed to step S8.4, if not, proceed to step S8.3; S8.3, find the two device bits acted by this two-bit gate through mapping, and find a shortest path on graph G' , starting from the starting point of the path, perform SWAP operations with the adjacent nodes on the path in turn, and update them to the corresponding positions in the circuit until the SWAP operation is completed at the end point of the path, execute the required two-bit gates on the end point of the path and the previous vertex, and then start from the end point, perform SWAP operations with the adjacent nodes on the path in turn, and update them to the circuit until the SWAP operation is completed at the starting point; S8.4, repeat steps S8.2 and S8.3 until all two-bit gates in the circuit can be executed, and enter step S8.5; S8.5 outputs the updated circuit.

[0092] Figure 4 To demonstrate the addition of the SWAP operation in step S8.3, it is assumed that during the mapping process, there is a two-bit gate connection between the device bits q0 and q2. In the actual process, quantum routing is adopted to temporarily exchange the positions of q0 and q1 by adding a SWAP gate, so that q0 and q2 can be temporarily connected.

[0093] By generating corresponding subgraphs, checking the feasibility of the two-bit gates, adding SWAP gates, and repeatedly checking and adding SWAP gates, it is ensured that all two-bit gates can be correctly executed on the actual device and the updated circuit is output. This process not only ensures the feasibility of the two-bit gates, but also optimizes the circuit structure and improves the reliability and efficiency of quantum computing.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. All equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A superconducting quantum bit mapping method based on a specific topological structure, characterized in that: The specific steps include: S1, initialize the circuit topology graph G of the quantum circuit Q to be executed. Each logical quantum bit in the quantum circuit Q represents a vertex in the circuit topology graph G. If there is a two-qubit gate between two logical quantum bits in the quantum circuit Q, the corresponding two vertices in the circuit topology graph G are connected, otherwise they are not connected; S2, initialize the structure topology graph T of the quantum computer to be run. Each device quantum bit in the quantum computer represents a vertex in the structure topology graph T. If a double quantum bit gate is allowed between two device quantum bits in the quantum computer, the corresponding two vertices in the structure topology graph T are connected, otherwise they are not connected; S3, using quantum calibration technology, collects the physical properties of the device quantum bits, including the single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout ; S4, according to the output of step S1, sort all the logic bits by mapping requirements, and select the logic bit L0 with the highest mapping requirement; S5, according to steps S2 and S3, sort all device bits by quality, select the device bit D0 with the highest quality, and map the logic bit selected in step S4 to the device bit D0: L0→D0; S6, regarding the mapping completed in step S5 as the initial mapping, respectively searching for the adjacent nodes whose logic bits and device bits are on the corresponding line topology graph obtained in step S1, sorting the adjacent nodes according to steps S4 and S5, completing the mapping according to the sorting, and updating the initial mapping according to the first bit in the sorting; S7, check whether there are any logic bits that have not been mapped in the line topology diagram G, if so, record all the logic bits that have not been mapped to form a set R G , all unmapped device bits form the set R T , and repeat S5, S6; S8, according to the final mapping obtained in step S7, check whether all quantum gates in the quantum circuit need to add additional auxiliary gates when executed on the quantum computer and output an executable quantum circuit corresponding to the final mapping.

2. The superconducting quantum bit mapping method based on a specific topological structure according to claim 1, characterized in that: The step S1 comprises: S1.1, initialize an array A for each quantum gate in the quantum circuit Q to be executed, where each element in the array A contains the name, action bit and parameter of the quantum gate; S1.2, initialize an undirected graph G0, where the vertex set V of the undirected graph G0 represents the logical qubits, and the edge set E represents the existence of a two-qubit gate between two logical qubits; S1.3, traverse each element in the array A. If the element is a two-qubit gate and acts on logical qubits i and j, then add an edge connecting vertex i and fixed point j to the undirected graph G0 and form a line topology graph G.

3. The superconducting quantum bit mapping method based on a specific topological structure according to claim 1, characterized in that: The step S2 comprises: S2.1, obtain a list of device bits of the quantum computer, each device bit is represented by a unique identifier; S2.2, initialize an undirected graph T0, where the vertices of the undirected graph T0 represent device qubits, and the edge E′ represents the two-qubit gate that can be applied between two device qubits; S2.3, traverse the device bit list and add the vertex corresponding to each device bit to the vertex set V′; S2.4, according to the coupling information of the quantum computer, traverse all device bit pairs. If a double quantum bit gate is allowed between a pair of device bits, add an edge connecting the two vertices in the undirected graph T0 and form a structural topology graph T.

4. The superconducting quantum bit mapping method based on a specific topological structure according to claim 3, characterized in that: The step S3 comprises: S3.1, Physical characteristics of measuring device bits, including single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout ; S3.2, create F single Array, F double Arrays and F readout array, and are used to store the measured single-bit gate fidelity F single , two-bit gate fidelity F double , read fidelity F readout ; S3.3, for the collection in F single Array, F double Arrays and F readout Verify the physical property data in the array to ensure the accuracy and completeness of the data; S3.4, associate the verified physical property data with the vertex set V′ of the structural topology graph T to ensure that the physical property data of each vertex is accessible.

5. The superconducting quantum bit mapping method based on a specific topological structure according to claim 4, characterized in that: Step S4 specifically includes the following steps: S4.1, according to the line topology graph G, count the degree of each vertex in the vertex set V, that is, the number of edges connected to it, and sort them from large to small. The result is recorded as the vertex list P G ; S4.2, if the vertex degrees in step S4.1 are the same, count the number of single-bit gates that appear on the logical bits in the quantum circuit Q according to array A, sort them from large to small according to the number of single-bit gates, and update the vertex list P G ; S4.3, the vertex list P completed in step S4.2 G , the first vertex is selected as the logical bit with the highest mapping requirement.

6. The superconducting quantum bit mapping method based on a specific topological structure according to claim 5, characterized in that: S5 specifically includes the following steps: S5.1, sort the device bits of the structure topology diagram T in S2.4 according to the method in S4.1, and record the sorting result as P0; S5.2, if there are multiple vertices with the same degree, continue to count the sum of the degrees of the neighboring nodes of these vertices in the structural topology graph T, sort them from large to small, and update P0; S5.3, according to F in S3.2 single Array, F double Arrays and F readout Array,sort the device bits according to different parameters, and sort the three fidelities from large to small, and record the three sortings as P1, P2, and P3 respectively; S5.4, four rankings P0, P1, P2, P3 are obtained from steps S5.1, S5.2, and S5.

3. For each vertex with four rankings R0, R1, R2, R3, calculate its comprehensive ranking: R T :=0.1R0+0.5R1+0.15R2+0.25R3, according to the comprehensive ranking R T Sort from small to large, and the result is recorded as P T ; S5.5, sorting from high to low according to the comprehensive ranking, and selecting the highest device bit to map with the logic bit with the highest mapping requirement in step S4.

3.

7. The superconducting quantum bit mapping method based on a specific topological structure according to claim 1, characterized in that: The iterative process of searching for mappings in S6 includes the following steps: S6.1, taking the initial mapping L0→D0 as input, find the neighboring nodes of the logic bit L0 and the device bit D0 in the initial mapping in the line topology graph G and the structure topology graph T respectively, and then delete the mapped device bits and logic bits, respectively, and record them as N G (L0), N T (D0), if Then go to step S6.5, otherwise sort the neighboring node bits according to steps S4 and S5, N G The element mapping requirements in (L0) are sorted from large to small as {L1, L2, ..., L m },N T The elements in (D0) are sorted from high to low in terms of quality as {D1, D2, ..., D n }; S6.2, after sorting, recursively perform the following steps for i=1, 2, ..., min{m, n}: Execute the mapping L i →D i , regard i=1 as the initial mapping and recursively execute step S6.1 as input; S6.3, check whether all the logical bits found in step S6.1 have been mapped. If not, find the N bits in step S6.

1. T (D0) The neighbor nodes of all elements are obtained by deleting the device bits that have been mapped. After sorting by quality, the remaining logical bits are mapped in sequence. If the number of elements still cannot meet the mapping requirements of logical bits, continue to look for The neighbor nodes of all elements are obtained by removing the device bits that have been mapped. After sorting by quality, the remaining logical bits are mapped in sequence; S6.4, repeat step S6.3 until all logic bits are mapped to device bits, or no suitable mapping can be found; S6.5, Inspection If yes, go to step S6.6; if no, sort the remaining logic bits and device bits according to the result P G , P T , reselect a new initial mapping L0→D0 and go to step S6.1; S6.6, output the final mapping result A subset of .

8. The superconducting quantum bit mapping method based on a specific topological structure according to claim 1, characterized in that: The step S7 specifically includes: S7.1, traverse all vertices of the line topology graph G, check whether each vertex has been mapped to a device bit, if so, record all unmapped logical bits to form a set R G ; S7.2, traverse all vertices of the topological graph T, check whether each vertex has been mapped to a logical bit, if so, record all unmapped device bits to form a set R T ; S7.3, repeat steps S5 and S6 until the set R G and the set R T Is empty.

9. The superconducting quantum bit mapping method based on a specific topological structure according to claim 1, characterized in that: The process of adding additional auxiliary quantum gates to S8 includes the following steps: S8.1, according to the final mapping result generated in step S7, find the device bits corresponding to all mapped logic bits in the structure topology graph T, and form a new corresponding subgraph, recorded as graph G'; S8.2, according to step S1, check whether all the two-bit gates in the circuit can be executed on the device represented by figure G', if yes, go to step S8.4, if not, go to step S8.3; S8.3, find the two device bits acted by this two-bit gate through mapping, find a shortest path on the graph G', start from the starting point of the path, perform SWAP operations with the adjacent nodes on the path in turn, and update to the corresponding position of the circuit until the end of the path completes the SWAP operation, perform the required two-bit gate on the end of the path and the previous vertex, then start from the end, perform SWAP operations with the adjacent nodes on the path in turn, and update to the circuit until the starting point completes the SWAP operation; S8.4, repeat steps S8.2 and S8.3 until all two-bit gates in the circuit can be executed; S8.5 outputs the updated circuit.

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