AIP module, active phased-array antenna and communication device

Abstract

The invention relates to the field of communication, and discloses an AIP module, an active phased-array antenna and a communication device, the AIP module comprises a substrate, an antenna, a chip and a passive device, the antenna is located on the upper surface of the substrate, the chip and the passive device are located on the lower surface of the substrate, the chip is electrically connected with the antenna, and the chip is electrically connected with the passive device. The antenna, the chip and the passive device are integrated together, wiring on a circuit board can be reduced, the wiring design is simplified, and meanwhile the cost and the design difficulty of the circuit board can be reduced.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to an AIP module, an active phased array antenna and a communication device. Background Art

[0002] Currently, phased array antennas use the AoB (Antenna on Board) form, in which the antenna is set on the upper side of the PCB (Printed Circuit Board), and chips (such as transmitting chips, receiving chips), passive components, etc. are set on the lower side of the PCB.

[0003] As the array architecture design becomes larger and larger, the low-frequency connection wiring between chips (including power lines, control lines and other signal lines, etc.) gradually increases, making the overall wiring compact and complicated. In addition, RF connection lines are required between chips for power division / combination connection, which further increases the complexity of wiring. RF connection is required between the chip and the antenna feed port. The chip is mainly placed on the lower side of the PCB board, and the routing area is limited. Therefore, most of the RF signal lines need to be placed in the inner layer for wiring. The penetration between different RF lines is inevitable. Considering electromagnetic isolation, the internal RF signal lines will be implemented in the form of strip lines. The increase in the number of stacking layers not only increases the cost of the PCB board, but also increases the difficulty of design. In addition, the chip and the antenna are connected through the signal vias in the PCB board. When the types of signal vias on the PCB board overlap too much, the processing difficulty increases. Even if the processing is completed, the yield will be reduced. In addition, certain channel problems are encountered during the processing and manufacturing process, which are difficult to troubleshoot and replace, which can easily cause the entire system to not work properly, or even the entire board to be abandoned, and the utilization rate of the device is low.

[0004] Therefore, how to solve the above technical problems should be the focus of technical personnel in this field. Summary of the invention

[0005] The purpose of this application is to provide an AIP module, an active phased array antenna and a communication device to simplify the wiring on the circuit board and reduce costs, while achieving an integrated and simple design of the active phased array antenna.

[0006] In order to solve the above technical problems, the present application provides an AIP module, including:

[0007] A substrate, an antenna, a chip and a passive device, wherein the antenna is located on the upper surface of the substrate, the chip and the passive device are located on the lower surface of the substrate, the chip and the antenna are electrically connected, and the chip and the passive device are electrically connected; the chip is used to receive and / or send signals.

[0008] Optionally, the substrate includes a radio frequency switching layer, the radio frequency switching layer includes a strip line, a first end of the strip line is connected to a first end of an antenna feed hole, and a second end of the strip line is connected to a first end of a first interconnect via; the second end of the antenna feed hole is connected to a feed port of the antenna, and a second end of the first interconnect via is connected to a signal port of the chip.

[0009] Optionally, the substrate further includes ground layers, which are respectively located above and below the radio frequency switching layer.

[0010] Optionally, it also includes:

[0011] A first ground via hole is located around the strip line and is at least connected to the ground layer above and below the radio frequency switching layer;

[0012] and / or, a second ground via located around the first interconnect via;

[0013] And / or, a third ground via is located around the antenna feeding hole.

[0014] Optionally, the substrate includes a radio frequency switching layer and a ground layer located above the radio frequency switching layer, the radio frequency switching layer includes a strip line, and the strip line includes a coupling feed line.

[0015] One end of the stripline is connected to a first end of a first interconnection via, and a second end of the first interconnection via is connected to a signal port of the chip;

[0016] A coupling slot is provided on the stratum, and the overlapping area of ​​the strip line and the coupling slot in the horizontal direction is the coupling feeder. The coupling feeder realizes signal transmission with the antenna through the coupling slot.

[0017] Optionally, the substrate further includes a low-frequency functional layer, the low-frequency functional layer is connected to a first end of a second interconnection via, and a second end of the second interconnection via is connected to the chip;

[0018] And / or, when the number of the chips is at least two, it also includes a connector and a radio frequency connection line, the connector is used to connect the chips, the first end of the radio frequency connection line is connected to the connector, and the second end of the radio frequency connection line is connected to the interconnection layer.

[0019] Optionally, it further includes: an interconnection layer, wherein the interconnection layer and the chip are located on the same side of the substrate in the AIP module, and the interconnection layer is located around the chip.

[0020] The present application also provides an active phased array antenna, comprising any of the above-mentioned AIP modules and a circuit board, wherein the circuit board has a hollow area, and the hollow area corresponds to the chip and passive components in the AIP module;

[0021] The lower surface of the AIP module is connected to the upper surface of the circuit board through an interconnection layer.

[0022] Optionally, it also includes:

[0023] The heat dissipation component is located in the hollow area.

[0024] Optionally, the interconnection layer and the chip are located on the same side of the substrate in the AIP module, and the interconnection layer is located around the chip.

[0025] Optionally, the chip and the passive device in each of the AIP modules are located in one of the hollow areas, or the chip and the passive device in each of the AIP modules are respectively located in one of the hollow areas;

[0026] And / or, the number of the AIP modules is at least two, and there is a gap between adjacent AIP modules.

[0027] The present application also provides a communication device, comprising any one of the active phased array antennas described above.

[0028] An AIP module provided in the present application includes: a substrate, an antenna, a chip and a passive device, wherein the antenna is located on the upper surface of the substrate, the chip and the passive device are located on the lower surface of the substrate, the chip and the antenna are electrically connected, and the chip and the passive device are electrically connected.

[0029] It can be seen that in the AIP module of the present application, the antenna, chip and passive devices are arranged on the substrate, that is, the antenna, chip and passive devices are integrated together, and there is no need to arrange the chip and antenna on the circuit board, which reduces the wiring on the circuit board and simplifies the wiring design. At the same time, there is no need to arrange RF connection lines inside the circuit board, and the number of stacking layers in the circuit board is reduced, thereby reducing the cost and design difficulty of the circuit board. In the present application, the antenna and chip are respectively located on the upper and lower surfaces of the substrate, and there is no need to arrange signal vias connecting the antenna and the chip on the circuit board, which reduces the processing difficulty of the circuit board and improves the yield. At the same time, when a channel problem occurs on the circuit board, it reduces the difficulty of troubleshooting the channel.

[0030] In addition, the present application also provides an active phased array antenna and a communication device having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A cross-sectional view of an active phased array antenna provided in an embodiment of the present application;

[0033] Figure 2 A schematic cross-sectional view of an active phased array antenna provided in an embodiment of the present application Figure 1 ;

[0034] Figure 3 A schematic cross-sectional view of an active phased array antenna provided in an embodiment of the present application Figure 2 ;

[0035] Figure 4 A bottom view of an active phased array antenna provided in an embodiment of the present application;

[0036] In the figure, 1, AIP module, 2, circuit board, 3, interconnection layer, 4, gap, 5, strip line, 6, antenna feed hole, 7, first interconnection via, 8, first ground via, 9, second ground via, 10, third ground via, 11, substrate, 12, antenna, 13, chip, 14, passive device, 15, package, 16, connector, 17, second interconnection via, 18, RF connection line, 19, gold bonding line, 20, coupling feed line, 21, coupling gap, 111, RF transfer layer, 112, ground layer, 113, low-frequency functional layer, 114, dielectric layer, 21, hollow area. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0039] As described in the background technology section, the antenna, chip and passive components in the current phased array antenna are arranged on the PCB board, which leads to compact and complex wiring on the PCB board and increases the number of PCB board stacking layers, resulting in high cost, high design difficulty, high processing difficulty and other problems.

[0040] In view of this, this application provides an AIP (Antenna in Package) module, please refer to Figure 1 , which may include:

[0041] A substrate 11, an antenna 12, a chip 13 and a passive device 14, wherein the antenna 12 is located on the upper surface of the substrate 11, the chip 13 and the passive device 14 are located on the lower surface of the substrate 11, the chip 13 and the antenna 12 are electrically connected, and the chip 13 and the passive device 14 are electrically connected; the chip 13 is used to receive and / or send signals.

[0042] In this embodiment, the type and quantity of the passive device 14 are not limited and depend on the situation. For example, the passive device 14 can be one or more of a capacitor, an inductor, a resistor, a balun, a power divider, a combiner, etc.

[0043] The chip 13 may be a T / R (Transmit / Receive) chip, or a single transmitting chip, or a single receiving chip. The number of the chips 13 is not limited in this embodiment and depends on the situation.

[0044] The chip 13 and the passive device 14 may be connected by a gold wire bonding process.

[0045] In this embodiment, the number of the AIP modules 1 is not limited, and can be one or more than two. All the AIP modules 1 are located on one circuit board 2 .

[0046] The number of chips 13 in each AIP module 1 can be one or more than two, depending on the number of antennas 12 and the functions to be implemented, which is not limited in this embodiment. In this embodiment, the AIP module 1 is an independent active antenna 12 phased array, and each active phased array can be independently tested and verified. Active phased arrays of different sizes can be realized through the AIP module 1, which has strong scalability and maintainability.

[0047] It should be noted that in this embodiment, the number of antennas 12 in an AIP module 1 is not limited, and it depends on the situation. For example, the number of antennas 12 can be 1, 4, 8, 16, etc.

[0048] Adjacent antennas 12 may be designed with equal spacing or non-equal spacing, both of which are within the protection scope of the present application.

[0049] The shape of the antenna 12 includes but is not limited to square, circle, pentagon, etc.

[0050] It should also be noted that this embodiment does not limit the polarization mode of the antenna 12. For example, the polarization mode of the antenna 12 can be single polarization or multi-polarization.

[0051] As an implementation method, the number of layers of the antenna 12 can be one layer, but this is not specifically limited in this embodiment. Considering the bandwidth and design structure of the antenna 12, the number of layers of the antenna 12 can also be increased. For example, the number of layers of the antenna 12 can be two or three layers.

[0052] In the AIP module 1 of this embodiment, the antenna 12, chip 13 and passive device 14 are arranged on the substrate 11, that is, the antenna 12, chip 13 and passive device 14 are integrated together, and there is no need to arrange the chip 13 and antenna 12 on the circuit board 2, which reduces the wiring on the circuit board 2 and simplifies the wiring design. At the same time, there is no need to arrange RF connection lines inside the circuit board 2, and the number of stacking layers in the circuit board 2 is reduced, thereby reducing the cost and design difficulty of the circuit board 2. In this application, the antenna 12 and the chip 13 are respectively located on the upper and lower surfaces of the substrate 11, and there is no need to arrange signal vias connecting the antenna 12 and the chip 13 on the circuit board 2, which reduces the processing difficulty of the circuit board 2 and improves the yield. At the same time, when a channel problem occurs on the circuit board 2, it reduces the difficulty of troubleshooting the channel.

[0053] Based on the above embodiments, in one embodiment of the present application, please refer to Figure 2 The substrate 11 may include a RF switching layer 111, and the RF switching layer 111 includes a strip line 5, a first end of the strip line 5 is connected to a first end of an antenna feed hole 6, and a second end of the strip line 5 is connected to a first end of a first interconnect via 7; a second end of the antenna feed hole 6 is connected to a feed port of the antenna 12, and a second end of the first interconnect via 7 is connected to a signal port of the chip 13.

[0054] The number of stacked layers in the substrate 11 is not limited in this embodiment and can be set as needed. A dielectric layer 114 is distributed between adjacent metal layers in the substrate 11. The metal layer includes but is not limited to a radio frequency switching layer 111, a ground layer 112, and a functional layer.

[0055] The order of the metal layers with different functions in the substrate 11 is not limited in this embodiment and depends on the circumstances.

[0056] The stacking design needs to consider three aspects: electromagnetic interconnection design, heat dissipation design and force design. The force design mainly considers the bonding strength between the stacking materials, as well as the overall size, weight and thickness stress to prevent deformation.

[0057] Since the distances from the antenna 12 to the chip 13 are different, the phase difference between the chip 13 and the antenna 12 is inconsistent. The RF switching layer 111 can be used to adjust the phases between different channels to achieve channel phase consistency.

[0058] The signal at the second end of the strip line 5 needs to be uniformly transmitted to the antenna 12. In this embodiment, the feeding form of the antenna 12 is not limited.

[0059] In this embodiment, Figure 2 As shown, the second end of the antenna feeding hole 6 is connected to the feeding port of the antenna 12, that is, the antenna 12 adopts a direct feeding form.

[0060] Based on any of the above embodiments, in one embodiment of the present application, Figure 3 As shown, the substrate 11 includes a radio frequency switching layer 111 and a ground layer 112 located above the radio frequency switching layer 111, the radio frequency switching layer 111 includes a strip line 5, and the strip line 5 includes a coupling feed line 20;

[0061] One end of the strip line 5 is connected to a first end of a first interconnection via 7, and a second end of the first interconnection via 7 is connected to a signal port of the chip 13;

[0062] A coupling slot 21 is provided on the stratum, and the overlapping area of ​​the strip line 5 and the coupling slot 21 in the horizontal direction is the coupling feeder 20 . The coupling feeder 20 transmits signals to the antenna 12 through the coupling slot 21 .

[0063] In this embodiment, the antenna 12 adopts a coupled feeding mode, and the signal in the chip 13 reaches the coupled feed line 20 through the strip line 5 and then enters the antenna through the coupling slot 21 .

[0064] Based on any of the above embodiments, in one embodiment of the present application, Figure 2 As shown, the substrate 11 may further include a ground layer 112 , which is located above and below the RF switching layer 111 , respectively.

[0065] The ground layer 112 is provided above and below the RF switching layer 111 , which can effectively prevent oxidation and protect the strip line 5 in the RF switching layer 111 ; on the other hand, it can also shield other signal interference and improve the overall anti-interference capability.

[0066] Based on the above embodiments, in one embodiment of the present application, Figure 2 and Figure 3 As shown, it may also include:

[0067] The first ground via 8 is located around the strip line 5 and is at least connected to the ground layer 112 located above and below the RF switching layer 111 at the same time.

[0068] Since the overall wiring on the substrate 11 is relatively compact, the interference between the RF lines (strip lines 5) is relatively large. By providing the first ground via 8, the anti-interference ability between adjacent RF lines can be enhanced, thereby improving the overall electromagnetic isolation.

[0069] The first ground via 8 can be connected to the ground layers 112 located above and below the RF switching layer 111 at the same time, and can also be connected to other ground layers at the same time.

[0070] Based on any of the above embodiments, in one embodiment of the present application, Figure 2 and Figure 3 As shown, it may also include:

[0071] The second ground via 9 is located around the first interconnection via 7 .

[0072] The second ground via 9 needs to be connected to the ground layer 112, which can improve the shielding effect of the radio frequency signal in the first interconnection via 7 and improve the overall electromagnetic isolation.

[0073] Based on any of the above embodiments, in one embodiment of the present application, Figure 2 As shown, it may also include:

[0074] The third ground via 10 is located around the antenna feeding hole 6 .

[0075] The third ground via 10 needs to be connected to the ground layer 112, which can improve the shielding effect of the radio frequency signal in the antenna feed hole 6, improve the overall electromagnetic isolation, and increase the overall anti-interference ability.

[0076] Based on any of the above embodiments, in one embodiment of the present application, Figure 2 and Figure 3 As shown, the substrate 11 further includes a low-frequency functional layer 113 , the low-frequency functional layer 113 is connected to a first end of a second interconnection via 17 , and a second end of the second interconnection via 17 is connected to the chip 13 .

[0077] The number and position of the low-frequency functional layers 113 are not limited in this embodiment and depend on the actual situation. Figure 2 Two layers are shown as an example.

[0078] The low-frequency functional layer 113 includes a low-frequency electromagnetic connection structure, which is mainly manifested as a power connection, a control connection, an address connection, and other digital signal connection structures.

[0079] All electromagnetic connection signals have corresponding input / output ports on the interconnection layer, and signal transmission between the AIP module 1 and the circuit board 2 can be achieved through the interconnection layer.

[0080] Please refer to Figures 2 to 4 Based on any of the above embodiments, in one embodiment of the present application, in an AIP module 1, when the number of the chips 13 is at least two, a connector 16 is also included for connecting each of the chips 13.

[0081] The connector 16 may be a power splitter or a combiner.

[0082] Figure 4 The middle chip 13 is shown in a 4×4 form as an example. The chip 13 can have 4 channels, and of course can also have other numbers of channels, which is not limited in this embodiment.

[0083] The interconnection between the chips 13 can be a gold wire bonding connection or other forms of radio frequency interconnection, which is not limited in this application.

[0084] The connector 16 and the chip 13 may be connected via a gold bonding wire 19, and all the chips 13 are finally connected to one connector 16. Figure 4 As shown, there are four chips 13 and three connectors 16. The two chips 13 on the left are connected to the connector 16 on the left, and the two chips 13 on the right are connected to the connector 16 on the right. The connector 16 on the left and the connector 16 on the right are respectively connected to the middle connector 16, so that the four chips 13 are finally connected to the middle connector 16.

[0085] The connector 16 and the chip 13 are located on the same side of the substrate 11. The number of the connectors 16 is not limited in this embodiment and depends on the situation. Figure 4 Taking three as an example, the two chips 13 on the left are connected via the leftmost connector 16, the two chips 13 on the right are connected via the rightmost connector 16, the rightmost connector 16 and the leftmost connector 16 are connected to the middle connector 16 together, so that the four chips 13 are finally connected to the middle connector 16.

[0086] As an implementation method, the active phased array antenna 12 may further include a radio frequency connection line 18 , wherein a first end of the radio frequency connection line 18 is connected to the connector 16 , and a second end of the radio frequency connection line 18 is connected to the interconnect layer.

[0087] For example, when the active phased array antenna is used to transmit signals, the RF signal is transmitted from the outside through the interconnection layer 3 to the RF connection line 18, and then to the connector 16, and is divided into four RF inputs, which are respectively input to the RF input ends of the four chips 13. After the RF signal is amplified by the chip 13, it is transmitted from the RF output end of the chip 13 through the feeder in the substrate 11 to the antenna 12 for transmission.

[0088] It should be noted that when there are multiple connectors 16, the first end of the RF connection line 18 is connected to the connector 16 that finally brings together the chips 13. Figure 4 As shown, a first end of the RF connection line 18 is connected to the middle connector 16 .

[0089] The second end of the RF connection line 18 is connected to the interconnect layer, serving as the RF input / output port of the entire AIP module 1 .

[0090] The form of the RF connection line 18 includes but is not limited to any one of a microstrip line, a strip line 5 , and a coplanar waveguide RF transmission line.

[0091] On the basis of any of the above embodiments, in one embodiment of the present application, the chip 13 may be a bare chip, and / or the passive device 14 may be an IPD (Integrated Passive Device) bare chip.

[0092] The bare chip and the IPD bare chip are small in size, which can reduce the area and volume of the AIP module 1 and reduce the cost.

[0093] Based on any of the above embodiments, in one embodiment of the present application, the following may also be included:

[0094] The package body 15 is used to package the bare chip and the IPD bare chip together.

[0095] Using the package body 15 to package the bare chip and the IPD bare chip as a whole can reduce the number of packaging times and reduce costs. At the same time, the package body 15 has the advantages of dust protection, improving the stability of the bonding wire, improving the overall sealing and realizing the electromagnetic shielding function, and it is also convenient for centralized heat dissipation of the chip 13 and the passive device 14.

[0096] The packaging method can be plastic packaging, metal packaging, or ceramic packaging, etc.

[0097] In other embodiments of the present application, the chip 13 may also be a packaged chip, and the passive device 14 may also be other ceramic components.

[0098] On the basis of the above embodiments, in one embodiment of the present application, the AIP module further includes: an interconnection layer 3, wherein the interconnection layer 3 and the chip 13 are located on the same side of the substrate 11 in the AIP module 1, and the interconnection layer 3 is located around the chip 13, thereby realizing that the chip 13 is located in the hollow area 21 of the circuit board 2.

[0099] The present application also provides an active phased array antenna, such as Figure 1 As shown, it includes the AIP module 1 and the circuit board 2 described in any of the above embodiments, the circuit board 2 has a hollow area 21, and the hollow area 21 corresponds to the chip 13 and the passive device 14 in the AIP module 1; the lower surface of the AIP module 1 is connected to the upper surface of the circuit board 2 through an interconnection layer 3.

[0100] In this embodiment, there is no limitation on the number of AIP modules 1 , which may be one or more than two. All AIP modules 1 are located on one circuit board 2 .

[0101] The number of chips 13 in each AIP module 1 can be one or more than two, depending on the number of antennas 12 and the functions to be implemented, and is not limited in this embodiment.

[0102] The hollow area 21 is mainly used to expose the position of the chip 13 to facilitate thermal design.

[0103] It should be pointed out that in this embodiment, the number of hollow areas 21 on the circuit board 2 is not limited and depends on the circumstances.

[0104] As an implementation method, Figure 1 As shown, the chip 13 and the passive device 14 in each AIP module 1 are located in a hollow area 21, so as to package and encapsulate the chip 13 and the passive device 14 and perform heat dissipation design, which can greatly reduce the packaging cost and design difficulty. The hollow area 21 can also reserve sufficient packaging area for the chip 13 encapsulation area.

[0105] As another possible implementation, each chip 13 and each passive component 14 in each AIP module 1 is respectively located in a hollow area 21 .

[0106] The circuit board 2 reduces the chip 13 with receiving and / or transmitting functions and the antenna 12 design, reduces high-frequency electromagnetic interconnection, and reduces the number of low-loss boards. The lower surface space of the circuit board 2 is relatively sufficient, which can be used to place power management chips and control chips, etc. On the one hand, it can improve the overall utilization rate, and on the other hand, only a small amount of RF interconnection design needs to be considered. For the low-frequency electromagnetic interconnection structure design, the demand for boards is not high, and it can be achieved by using conventional FR4 boards, which can greatly reduce costs.

[0107] The circuit board 2 may be a PCB board.

[0108] The interconnection layer is located between the lower surface of the substrate 11 and the upper surface of the circuit board 2, and is located at the edge of the substrate 11. The interconnection layer is also used as the electrical connection input / output port of the entire AIP module 1, including RF input / output, and other power supply, control signal input / output.

[0109] The interconnection layer may be a metal pad, or a BGA (Ball Grid Array) ball, or other forms of interconnection structures, all of which are within the protection scope of the present application.

[0110] It should be pointed out that in order to ensure normal electromagnetic signal transmission between the PCB board and the AIP module 1, the electromagnetic interconnection of the interconnection layer as well as the thermal and mechanical design requirements must be guaranteed.

[0111] The signals on the interconnect layer are mainly electromagnetic interconnect structure signals and ground signals. The electromagnetic interconnect structure signal lines include RF signals, power management related signals, control signals, address signals, other digital signals, ground signals, etc. Among them, the design of electromagnetic interconnect structure signals needs to take into account the RF performance, DC performance, signal integrity, crosstalk, delay, etc. of signal transmission. During the design, optimization simulation can be performed according to the design requirements to achieve the best performance.

[0112] A hollow area 21 is provided on the circuit board 2. After the AIP module 1 is connected to the circuit board 2 through the interconnection layer, the chip 13 and the passive device 14 are located in the hollow area 21, so that the top of the active phased array antenna 12 is the antenna 12, and the bottom is the chip 13 and the passive device 14. The active phased array antenna 12 realizes an integrated design and has the advantages of small size and simple design. With the rise of millimeter wave frequency band communication technology (5G, satellite communication, etc.), the demand for large active phased array antennas 12 has increased dramatically, and the active phased array antenna 12 in this application can be used for millimeter wave communication.

[0113] Based on any of the above embodiments, in one embodiment of the present application, Figure 1As shown, the number of the AIP modules 1 is at least two, and there may be a gap 4 between adjacent AIP modules 1 to prevent extrusion deformation due to processing errors and assembly errors, and to facilitate the removal and reinstallation of an AIP module 1 after it is damaged.

[0114] Based on any of the above embodiments, in one embodiment of the present application, the active phased array antenna 12 may further include:

[0115] The heat dissipation component is located in the hollow area 21 .

[0116] The chip 13 is located in the hollow area 21 , and the heat dissipation component can improve the heat dissipation of the chip 13 .

[0117] The heat dissipation component can be a component with good heat dissipation such as a metal block, which can be configured by the user and is not limited in this embodiment.

[0118] It should be pointed out that in an AIP module, when each chip 13 is located in a hollow area 21, a heat dissipation component can be set in each hollow area 21; when all chips 13 in an AIP module are in a hollow area 21, a heat dissipation component is set in the hollow area 21.

[0119] In order to further improve the heat dissipation effect of the chip 13, as an implementation method, it can also include: a heat conducting component located between the chip 13 and the heat dissipation component.

[0120] The heat-conducting component may cover the package 15 of the chip 13 . The heat-conducting component may be silicone grease or a heat-conducting pad, etc., so that soft contact is achieved between the heat-conducting component and the heat-dissipating component to ensure the heat dissipation of the chip 13 .

[0121] In order to prevent the top antenna 12 from being oxidized, based on any of the above embodiments, in one embodiment of the present application, the active phased array antenna 12 may further include: a protective dielectric layer located on the upper surface of the antenna 12 .

[0122] The material of the protective dielectric layer may be a low-loss dielectric material, and the specific type is not limited in this embodiment.

[0123] Based on any of the above embodiments, in one embodiment of the present application, the number of signal inputs and signal outputs of the chip 13 is more than two, respectively, and more than two signal processing can be implemented simultaneously to realize multi-beam / multi-polarization signal communication.

[0124] The number of signal inputs and signal outputs on each chip 13 is equal.

[0125] On the basis of any of the above embodiments, in one embodiment of the present application, the antenna 12 includes a radiation unit and a parasitic radiation unit, and the parasitic radiation unit is located on the upper surface of the radiation unit.

[0126] The shape of the parasitic radiation unit may be the same as or different from the shape of the antenna 12 .

[0127] By setting a parasitic radiation unit, the bandwidth of the antenna 12 can be expanded and the matching can be adjusted.

[0128] On the basis of any of the above embodiments, in one embodiment of the present application, the active phased array antenna 12 may further include: a parasitic unit located around the antenna 12 .

[0129] The shape of the parasitic unit can be strip or ring.

[0130] By providing a parasitic unit around the antenna 12, the bandwidth of the antenna 12 can be expanded and the matching can be adjusted.

[0131] The present application also provides a communication device, comprising the active phased array antenna described in any of the above embodiments.

[0132] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0133] The above is a detailed introduction to the AIP module, active phased array antenna and communication device provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the scheme of the present application and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. An AIP module, characterized in that: include: A substrate (11), an antenna (12), a chip (13) and a passive component (14), wherein the antenna (12) is located on the upper surface of the substrate (11), the chip (13) and the passive component (14) are located on the lower surface of the substrate (11), the chip (13) and the antenna (12) are electrically connected, and the chip (13) and the passive component (14) are electrically connected; the chip (13) is used to receive and / or send signals.

2. The AIP module according to claim 1, wherein: The substrate (11) comprises a radio frequency switching layer (111), the radio frequency switching layer (111) comprises a strip line (5), a first end of the strip line (5) is connected to a first end of an antenna feed hole (6), and a second end of the strip line (5) is connected to a first end of a first interconnection via (7); a second end of the antenna feed hole (6) is connected to a feed port of the antenna (12), and a second end of the first interconnection via (7) is connected to a signal port of the chip (13).

3. The AIP module according to claim 2, wherein: The substrate (11) further comprises a ground layer (112), which is located above and below the radio frequency switching layer (111), respectively.

4. The AIP module according to claim 3, wherein: Also includes: A first ground via (8) located around the strip line (5) and at least simultaneously connected to the ground layer (112) located above and below the radio frequency switching layer (111); and / or, a second ground via (9) located around the first interconnect via (7); And / or, a third ground via (10) is located around the antenna feed hole (6).

5. The AIP module according to claim 1, wherein: The substrate (11) comprises a radio frequency switching layer (111) and a ground layer (112) located above the radio frequency switching layer (111); the radio frequency switching layer (111) comprises a strip line (5); the strip line (5) comprises a coupling feed line (20); One end of the strip line (5) is connected to a first end of a first interconnection via (7), and a second end of the first interconnection via (7) is connected to a signal port of the chip (13); A coupling slot (21) is provided on the stratum (112); an overlapping area of ​​the strip line (5) and the coupling slot (21) projected in the horizontal direction is the coupling feeder (20); and the coupling feeder (20) transmits signals to the antenna (12) via the coupling slot (21).

6. The AIP module according to claim 1, wherein: The substrate (11) further comprises a low-frequency functional layer (113), wherein the low-frequency functional layer (113) is connected to a first end of a second interconnection via (17), and a second end of the second interconnection via (17) is connected to the chip (13); And / or, when the number of the chips (13) is at least two, it also includes a connector (16) and a radio frequency connection line (18), wherein the connector (16) is used to connect the chips (13), a first end of the radio frequency connection line (18) is connected to the connector (16), and a second end of the radio frequency connection line (18) is connected to the interconnection layer (3).

7. The AIP module according to claim 1, wherein: It also comprises: an interconnection layer (3), wherein the interconnection layer (3) and the chip (13) are located on the same side of the substrate (11) in the AIP module (1), and the interconnection layer (3) is located around the chip (13).

8. An active phased array antenna, characterized in that: Comprising the AIP module (1) and a circuit board (2) according to any one of claims 1 to 6, wherein the circuit board (2) has a hollow area (21), and the hollow area (21) corresponds to the chip (13) and the passive device (14) in the AIP module (1); The lower surface of the AIP module (1) is connected to the upper surface of the circuit board (2) via an interconnection layer (3).

9. The active phased array antenna according to claim 8, characterized in that: Also includes: A heat dissipation component is located in the hollow area (21).

10. The active phased array antenna according to claim 8, characterized in that: The chip (13) and the passive device (14) in each of the AIP modules (1) are both located in one of the hollow areas (21); or, the chip (13) and the passive device (14) in each of the AIP modules (1) are each located in one of the hollow areas (21); And / or, the number of the AIP modules (1) is at least two, and there is a gap (4) between adjacent AIP modules (1).

11. A communication device, characterized in that: Comprising the active phased array antenna as described in any one of claims 8 to 10.

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