MOS tube structure, anti-reverse off power module and vehicle

Abstract

The application relates to a MOS tube structure, an anti-reverse-off power module and a vehicle. The structure comprises multiple wafers, a conductive component and a package. Each wafer has a first pole, a second pole and a drain. Applying a voltage to the first pole and the second pole can make one of the first pole and the second pole conductive or cut off with the drain. The package encapsulates the multiple wafers. The conductive component comprises a first pin, a second pin and multiple drain pins. The drains of the multiple wafers are electrically connected to the corresponding drain pins. The first poles of the multiple wafers are electrically connected to the first pin. The second poles of the multiple wafers are electrically connected to the second pin. At least one of the first poles and the second poles of the multiple wafers is electrically connected in the package. The first pin, the second pin and the multiple drain pins partially extend out of the package to be electrically connected to a PCB. The first poles and / or the second poles of two wafers are electrically connected in the package, the wiring on the PCB is reduced, the wiring on the PCB is simplified, and the wiring design on the PCB is easy.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a MOSFET structure, a reverse turn-off power module, and a vehicle. Background Technology

[0002] A MOSFET (Metal-Oxide-Semiconductor MOSFET) structure consists of two MOSFETs and is widely used in electronic circuits. It can not only act as a switch to cut off the power supply circuit, but also work with external circuits to provide reverse connection protection. Typically, one MOSFET in a MOSFET structure acts as the switch, and the other as the load. By changing the gate voltage of the MOSFET with a control signal, the MOSFET's conduction and cutoff can be controlled, thereby achieving switching control of current transfer.

[0003] In related technologies, MOSFET structures are surface-mount packaged. The two individual MOSFETs are connected to the PCB board, and their sources are connected via external traces on the PCB. This reduces PCB board utilization and increases the design complexity of the PCB board. Utility Model Content

[0004] This application provides a MOSFET structure, a reverse shutdown power module, and a vehicle, which at least partially solve the above-mentioned technical problems by reducing [the number of components].

[0005] To achieve the above objectives, according to a first aspect of this application, a MOS transistor structure includes:

[0006] Multiple wafers, each wafer having a first electrode, a second electrode, and a drain electrode, wherein applying a voltage to the first electrode and the second electrode enables one of the first electrode and the second electrode to be turned on or off with the drain electrode;

[0007] Package body, which encapsulates the plurality of wafers;

[0008] A conductive component includes a first pin, a second pin, and a plurality of drain pins. The drains of the plurality of wafers are electrically connected to the corresponding drain pins. The first electrode of the plurality of wafers is electrically connected to the first pin, and the second electrode of the plurality of wafers is electrically connected to the second pin. At least one of the first electrode and the second electrode of the plurality of wafers is electrically connected within the package. The first pin, the second pin, and the plurality of drain pins are partially exposed through the package for bonding and electrical connection with a PCB board.

[0009] Optionally, the first electrode is the source and the second electrode is the drain.

[0010] Optionally, the first electrodes of the plurality of wafers are electrically connected to each other via wires, and the first electrode of any one of the wafers is electrically connected to the second pin.

[0011] Optionally, the second electrodes of the plurality of wafers are electrically connected to the first pins via wires.

[0012] Optionally, the first pin, the second pin, and the plurality of drain pins are distributed along the side of the package, the package having a first side, and the first pin and the second pin are positioned closer to the first side than the drain pins.

[0013] Optionally, the package has a second side and a third side disposed opposite to each other, the first side being connected between the second side and the third side, the first pin being located on the second side, and the second pin being located on the third side.

[0014] Optionally, the drain pin electrically connected to one of the wafers is located on the second side, and the drain pin electrically connected to the other wafer is located on the third side.

[0015] Optionally, the package has a fourth side, which is disposed opposite to the first side, and the drain pin includes a plurality of sub-pins, with a portion of the sub-pins of two of the drain pins disposed on the fourth side.

[0016] Optionally, the plurality of wafers are mounted on the corresponding drain pins.

[0017] Optionally, the drain pin is a supporting metal substrate, and multiple drain pins correspond to multiple supporting metal substrates. The multiple supporting metal substrates are insulated from each other, and multiple wafers are mounted on the corresponding supporting metal substrates. The drain of each wafer is electrically connected to the corresponding supporting metal substrate.

[0018] Optionally, each of the supporting metal substrates includes a support portion and a lead portion, the lead portion being mounted on one side of the support portion and extending out of the package body, and the wafer being mounted on the support portion of the corresponding supporting metal substrate.

[0019] Optionally, the plurality of wafers includes a first wafer and a second wafer, and the plurality of supporting metal substrates includes a first metal substrate and a second metal substrate. The first wafer is mounted on the first metal substrate, the second wafer is mounted on the second metal substrate, and the first metal substrate and the second metal substrate are mirror images of each other.

[0020] Optionally, the first pin is a third metal substrate, the second pin is a fourth metal substrate, the first electrode of the plurality of wafers is electrically connected to the third metal substrate, and the second electrode of the plurality of wafers is electrically connected to the fourth metal substrate.

[0021] Optionally, both the third metal substrate and the fourth metal substrate include a connection portion and a pin. The pin is located on one side of the connection portion and extends out of the package body. The first electrode of the plurality of wafers is electrically connected to the connection portion of the corresponding third metal substrate, and the second electrode of the plurality of wafers is electrically connected to the connection portion of the corresponding fourth metal substrate.

[0022] Optionally, the first electrode is the source electrode, the second electrode is the gate electrode, and the second electrodes of the first wafer and the second wafer are respectively electrically connected to the connection portion of the fourth metal substrate through wires.

[0023] Optionally, the first electrode of the first wafer and the first electrode of the second wafer are electrically connected by a wire, and the first electrode of the first wafer or the first electrode of the second wafer is electrically connected to the third metal substrate by a wire.

[0024] Optionally, the pin portion includes a plurality of sub-pins, and the plurality of sub-pin portions are arranged at intervals along the side of the package.

[0025] Optionally, an opening is provided on one side of the package, and the projections of the plurality of wafers are located within the opening along the thickness direction of the package.

[0026] Optionally, the drain pin is exposed in the opening on the side opposite to the plurality of wafers.

[0027] Optionally, the conductive component has an anti-oxidation coating on its surface located within the opening.

[0028] Optionally, the first electrode is the gate and the second electrode is the source.

[0029] Optionally, if the first electrodes of the plurality of wafers are electrically connected inside the package, then a first pin and a plurality of second pins are provided, the first electrodes of the plurality of wafers are all electrically connected to the first pin, and the second electrodes of the plurality of wafers are respectively electrically connected to the corresponding second pin;

[0030] If the second electrodes of the plurality of wafers are electrically connected inside the package, then a second pin and a plurality of first pins are provided, the second electrodes of the plurality of wafers are all electrically connected to the second pin, and the first electrodes of the plurality of wafers are respectively electrically connected to the corresponding first pin;

[0031] If the first and second electrodes of the plurality of wafers are electrically connected inside the package, then a first pin and a second pin are provided, the first electrodes of the plurality of wafers are all electrically connected to the first pin, and the second electrodes of the plurality of wafers are all electrically connected to the second pin.

[0032] According to a second aspect of this application, a reverse shutdown power module is provided, comprising:

[0033] The MOS transistor structure as described in any of the above;

[0034] The PCB board has the first pin, the second pin, and the plurality of drain pins of the MOS transistor structure bonded and electrically connected to the PCB board.

[0035] Optionally, it also includes a heat sink, which clamps and fixes the MOS transistor structure to the PCB board.

[0036] Optionally, the conductive component of the MOS transistor structure is closer to the heat sink than the plurality of wafers.

[0037] Optionally, it also includes a housing, which clamps and fixes the MOS transistor structure to the PCB board.

[0038] Optionally, an insulating and thermally conductive layer is provided between the housing and the conductive component.

[0039] Optionally, the package has an opening on the side facing away from the PCB board, and the conductive component is exposed in the opening on the side facing away from the plurality of wafers.

[0040] Optionally, the device also includes a controller mounted on the PCB board. The controller is electrically connected to the first and second terminals of the MOS transistor structure. The controller is used to apply a voltage to the first and second terminals so that one of the first and second terminals is connected to or cut off from the drain.

[0041] Optionally, the PCB board has power traces and control traces on the same layer. The pin group includes a drain pin, a first pin, and a second pin. The drain pin is electrically connected to the power trace, and the first pin and the second pin are electrically connected to the control trace, respectively.

[0042] According to a third aspect of this application, a vehicle is also provided, including the anti-reverse shutdown power module as described in any of the above claims.

[0043] The MOSFET structure of this application includes multiple wafers, conductive components, and a package. The package encapsulates multiple wafers, each wafer having a first electrode, a second electrode, and a drain. One of the first and second electrodes enables the other to conduct or cut off from the drain. The conductive component includes a first pin, a second pin, and a drain pin. The first electrode of the wafer is electrically connected to the first pin, the second pin is electrically connected to the second electrode, and the drain is electrically connected to the drain pin. The first pin, the second pin, and the drain pin are exposed outside the package. The package integrates two wafers and the conductive components, and is bonded and electrically connected to the PCB board. This facilitates the connection between the MOSFET structure and the PCB board. The first and / or second electrodes of the multiple wafers are electrically connected inside the package, reducing the number of traces on the PCB board and thus simplifying the PCB board routing, making PCB board routing design easier.

[0044] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0047] Figure 1 This is a schematic diagram of the overall structure of the first form of the MOS transistor structure provided in the exemplary embodiments of this disclosure;

[0048] Figure 2 This is a schematic diagram of the overall structure of the second form of the MOS transistor structure provided in the exemplary embodiments of this disclosure;

[0049] Figure 3 The drain pin of the MOS transistor structure provided in the exemplary embodiment of this disclosure is shown in schematic diagram of form one;

[0050] Figure 4 This is a schematic diagram of a MOS transistor structure with a drain pin of type two provided in an exemplary embodiment of this disclosure;

[0051] Figure 5 This is a schematic diagram of a MOS transistor structure with a drain pin of type three provided in an exemplary embodiment of this disclosure;

[0052] Figure 6This is a top view of the MOS transistor structure provided in the exemplary embodiments of this disclosure;

[0053] Figure 7 This is a schematic diagram of the first metal substrate or the second metal substrate in the MOS transistor structure provided in the exemplary embodiments of this disclosure;

[0054] Figure 8 This is a schematic diagram of the MOS transistor structure provided in an exemplary embodiment of this disclosure mounted on a PCB board;

[0055] Figure 9 This is a schematic diagram showing the connection relationship between the MOS transistor structure, PCB board, and heat sink provided in an exemplary embodiment of this disclosure.

[0056] Explanation of reference numerals in the attached figures:

[0057] 100. MOSFET structure;

[0058] 110. Multiple wafers; 111. First wafer; 112. Second wafer; 113. First electrode; 114. Second electrode;

[0059] 120. Conductive component; 121. First pin; 122. Second pin; 123. Drain pin; 124. First metal substrate; 1241. Support portion; 1242. Pin portion; 125. Second metal substrate; 126. Third metal substrate; 127. Fourth metal substrate; 128. Wire;

[0060] 130. Encapsulation body; 131. First side; 132. Second side; 133. Third side; 134. Fourth side; 135. Opening;

[0061] 200, PCB board; 210, First control trace; 220, Second control trace; 230, First power trace; 240, Second power trace;

[0062] 300. Radiator;

[0063] 400. Controller. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0065] See Figure 1 and Figure 3This application provides a MOSFET structure 100, which includes multiple wafers 110, conductive components 120, and a package 130. The multiple wafers 110 are packaged within the package 130. Each wafer has a first electrode 113, a second electrode 114, and a drain. Applying a voltage to the first electrode 113 and the second electrode 114 causes one of the first electrode 113 or the second electrode 114 to be connected to or cut off from the drain. The conductive component 120 includes a first pin 121, a second pin 122, and multiple drain pins 123. The drains of the multiple wafers 110 are electrically connected to their corresponding drain pins 123. The first electrodes 113 of the multiple wafers 110 are electrically connected to the first pins 121, and the second electrodes 114 of the multiple wafers 110 are electrically connected to the second pins 122. At least one of the first electrode 113 and second electrode 114 of a plurality of wafers 110 is electrically connected within a package 130. A first pin 121, a second pin 122, and a plurality of drain pins 123 partially penetrate the package 130 and are exposed to the outside for bonding and electrical connection with a PCB board 200. Specifically, the first electrodes 113 or the second electrodes 114 of the plurality of wafers 110 can be directly or indirectly electrically connected within the package 130. A conductive component 120 partially penetrates the package 130 and is exposed to the outside for bonding and connection with the PCB board 200.

[0066] In some embodiments, if the first electrodes 113 of multiple wafers 110 are electrically connected inside the package 130, a first pin 121 and multiple second pins 122 are correspondingly provided. The first electrodes 113 of multiple wafers 110 are all electrically connected to the first pin 121, and the second electrodes 114 of multiple wafers 110 are respectively electrically connected to the corresponding second pins 122. If the second electrodes 114 of multiple wafers 110 are electrically connected inside the package 130, multiple first pins 121 and one second pin 122 are correspondingly provided. The first electrodes 113 of multiple wafers 110 are respectively electrically connected to the corresponding first pins 121, and the second electrodes 114 of multiple wafers 110 are all electrically connected to the second pins 122. If the first electrode 113 and the second electrode 114 of multiple wafers 110 are electrically connected inside the package 130, a first pin 121 and a second pin 122 are provided accordingly. The first electrode 113 of multiple wafers 110 are electrically connected to the first pin 121, and the second electrode 114 of multiple wafers 110 are electrically connected to the second pin 122.

[0067] In this embodiment, the electrical connection design of the wafers within the package 130 is designed to optimize pin configuration and improve circuit performance. When the first terminals 113 of multiple wafers 110 are electrically connected within the package 130, a unified first pin 121 and multiple independent second pins 122 are provided. At this time, the first terminals 113 of multiple wafers 110 are all electrically connected to the unique first pin 121, while the second terminals 114 of each wafer are electrically connected to their corresponding second pins 122, ensuring effective current distribution and transmission.

[0068] If the second electrodes 114 of multiple wafers 110 are electrically connected inside the package 130, the pin configuration is reversed to multiple first pins 121 and a single second pin 122 for a unified function. This design allows each wafer's first electrode 113 to be electrically connected to its dedicated first pin 121, while all the second electrodes 114 of all wafers converge to a unified second pin 122, achieving centralized current convergence and output.

[0069] Furthermore, when the first electrodes 113 and second electrodes 114 of multiple wafers 110 are electrically connected within the package 130, they are configured with a first pin 121 and a second pin 122. This design connects the first electrodes 113 of all wafers to a single first pin 121, and the second electrodes 114 of all wafers to a single second pin 122. This simplified connection method not only effectively reduces the number of pins but also optimizes the layout of internal circuitry and current transmission efficiency, thereby improving overall electrical performance.

[0070] The following example illustrates the use of two wafers, with the first electrode 113 as the source and the second electrode 114 as the gate, where the first electrode 113 and the second electrode 114 of the two wafers are connected inside the package 130.

[0071] In this embodiment, two wafers are used. The two wafers can be of the same type, such as both being N-channel or P-channel, depending on design requirements. Alternatively, complementary types can be chosen, such as one being N-channel and the other P-channel. Both wafers include a semiconductor substrate, typically made of high-purity single-crystal silicon. The semiconductor substrate serves as the physical carrier for the device and is classified as either P-type or N-type. The semiconductor substrate has a first side and a second side arranged opposite to each other. The first side has a source and a gate electrode, and the second side has a drain electrode. An insulating layer, typically made of silicon dioxide, exists between the source and gate electrodes. This insulating layer isolates the conductive path between the gate and the source, allowing the carrier concentration within the semiconductor substrate to be controlled by applying a voltage to the gate. When a positive or negative voltage is applied to the gate, a conductive channel is formed on the surface of the semiconductor substrate below the insulating layer. Taking an N-channel MOS chip as an example, a positive gate voltage will attract electrons in the P-type substrate to gather on the surface. When the voltage reaches a certain threshold, the original P-type semiconductor surface is inverted to N-type, forming an N-type conductive channel connecting the source and drain. At this time, if a suitable voltage is applied between the source and drain, electrons can flow from the source to the drain through the conductive channel, thus realizing current conduction.

[0072] In this embodiment, the package 130 encapsulates two wafers to ensure the stability and durability of the MOSFET structure 100 during use. The package 130 design not only provides physical protection but also reduces electrical interference and improves performance stability. Inside the package 130, the first electrodes 113 of the two wafers are electrically connected via a method such as wires 128. Specifically, the first electrode 113 is the gate, and the second electrode 114 is the source. This design eliminates the need for additional traces on the PCB board 200 to connect the first electrodes 113 of the two wafers when the MOSFET structure 100 is mounted on the PCB board 200, thereby reducing the complexity of the traces on the PCB board 200 and improving the flexibility and efficiency of circuit design. The MOSFET structure 100 is connected to the PCB board 200 via first pin 121, second pin 122, and multiple drain pins 123, ensuring that the MOSFET structure 100 can be quickly and reliably electrically connected to the circuit board in practical applications. The MOSFET structure 100 features a compact design and small size, making it ideal for electrical connections to circuit boards. This simplifies circuit board routing and further reduces manufacturing costs and complexity. Furthermore, this design improves circuit board reliability and maintainability, providing an excellent solution for the miniaturization and integration of electronic devices.

[0073] In some embodiments, see Figure 3Two wafers are laid flat and spaced apart inside the package 130, with the space between them filled by the insulating material of the package 130 to ensure that the two wafers remain in an insulating state. The package 130 includes a top surface and a bottom surface opposite to each other. The drains of the two wafers are located near the bottom surface, and the gates and sources of the two wafers are located on the top surface. The sources of the two wafers are electrically connected by a wire 128. See also... Figure 3 and Figure 4 The conductor 128 can be made of copper wire, aluminum wire, or copper sheet to ensure conductivity and mechanical temperature resistance.

[0074] In some embodiments, see Figure 3 , Figure 4 and Figure 5 The conductive component 120 includes a first pin 121, a second pin 122, and multiple drain pins 123. The gates of the two wafers are electrically connected to the first pin 121 via wires 128. The source of any one wafer is electrically connected to the second pin 122, and the drains of the two wafers are electrically connected to their corresponding drain pins 123.

[0075] In related technologies, the MOSFET structure 100 is surface-mount packaged. The two MOSFETs of the MOSFET structure 100 are connected to the PCB board 200, and are placed back-to-back symmetrically. The gates of the two MOSFETs of the MOSFET structure 100 are electrically connected to the PCB board 200. However, the control traces connecting the two gates are split on different sides by the power traces, resulting in the inability to simultaneously complete power and control traces on a single PCB board 200 layer. This reduces the utilization rate of the PCB board 200 and increases its design complexity.

[0076] To solve this problem, see Figure 3 and Figure 4 This application provides a MOS transistor structure 100. The conductive component 120 includes a first pin 121, a second pin 122, and two drain pins 123. Two wafers are designated as a first wafer 111 and a second wafer 112. The gate of the first wafer 111 is electrically connected to the second pin 122 via a wire 128, and the gate of the second wafer 112 is also electrically connected to the second pin 122 via a wire 128. The wire 128 can be a copper wire, an aluminum wire, or a copper busbar. The source of the first wafer 111 and the source of the second wafer 112 are electrically connected via the wire 128, and the source of either the first wafer 111 or the second wafer 112 is electrically connected to the first pin 121 via the wire 128. The two drain pins 123 are designated as a first drain pin 123 and a second drain pin 123, respectively. The drain of the first wafer 111 is electrically connected to the first drain pin 123, and the drain of the second wafer 112 is electrically connected to the second drain pin 123.

[0077] In this embodiment, since the pin group of the MOS transistor structure 100 only includes a first pin 121 and a second pin 122, when the MOS transistor structure 100 is mounted on the PCB board 200, one control trace connected to the first pin 121 is reduced, saving the trace layer of the PCB board 200, which can reduce the cost of the PCB board 200, while ensuring the integrity of the ground plane and improving the electromagnetic compatibility performance of the product.

[0078] In some embodiments, see Figure 1 , Figure 3 and Figure 6 The pin group is distributed along the side of the package 130, which has a cubic structure with four sides: a first side 131, a second side 132, a third side 133, and a fourth side 134. The first side 131 is opposite to the fourth side 134, and the second side 132 is opposite to the third side 133. The first pin 121, the second pin 122, and the drain pin 123 are distributed along the side of the package 130, with the first pin 121 and the second pin 122 positioned closer to the first side 131 than the drain pin 123.

[0079] It is understood that a controller 400 is mounted on the PCB board 200, and when the MOSFET structure 100 is mounted on the PCB board 200, the controller 400 is positioned close to the first side 131. The PCB board 200 has two control traces, and the source and gate of the MOSFET structure 100 are electrically connected to the controller 400 through corresponding control traces. In addition, the PCB board 200 also has power traces, which are electrically connected to the drain of the MOSFET structure 100. The MOSFET structure 100 is electrically connected to the product to be controlled through the power traces. The power traces and control traces are set separately and do not interfere with each other. Therefore, the layout of power and control traces can be completed simultaneously within one layer of traces on the PCB board 200, thereby simplifying the design of the PCB board 200.

[0080] In some embodiments, see Figure 3 and Figure 6 The package 130 has a second side 132 and a third side 133 that are disposed opposite to each other. The first side 131 is connected between the second side 132 and the third side 133. The first pin 121 is located on the second side 132 and the second pin 122 is located on the third side 133.

[0081] In the embodiments of this application, see Figure 8When the MOSFET structure 100 is mounted on the PCB board 200, the first control trace 210 connects the second pin 122 to the controller 400, and the second control trace 220 connects the first pin to the controller 400. By placing the first pin 121 and the second pin 122 on opposite sides of the package 130, the routing space for the first control trace 210 and the second control trace 220 is large, which is beneficial for the routing design of the PCB board 200.

[0082] In some embodiments, see Figure 3 and Figure 6 The drain pin 123, which is electrically connected to one of the wafers, is located on the second side 132, and the drain pin 123, which is electrically connected to the other wafer, is located on the third side 133.

[0083] See Figure 3 and Figure 6 The package comprises two wafers, a first wafer 111 and a second wafer 112. Two drain pins 123 are designated as a first drain pin and a second drain pin, respectively. The drain of the first wafer 111 is electrically connected to the first drain pin 123, and the drain of the second wafer 112 is electrically connected to the second drain pin 123. The package 130 has a first side 131, a second side 132, a third side 133, and a fourth side 134. The first side 131 and the fourth side 134 are opposite to each other, and the second side 132 and the third side 133 are opposite to each other. The first drain pin 123 and the second pin 122 are located on the second side 132, with the first drain pin 123 being further away from the first side 131 than the second drain pin 122. The second drain pin 123 and the first pin 121 are located on the third side 133, with the second drain pin 123 being further away from the first side 131 than the first drain pin 121.

[0084] See Figure 8 When the MOSFET structure 100 is mounted on the PCB board 200, the PCB board 200 has two power traces, such as the first power trace 230 and the second power trace 240. The first power trace 230 is connected to the first drain pin 123, and the second power trace 240 is connected to the second drain pin 123. The first power trace 230 and the second power trace 240 are located on both sides of the package body 130, respectively. The wiring space of the power traces is large, which is beneficial to the wiring design of the PCB board 200.

[0085] In some embodiments, see Figure 3 and Figure 6 The package 130 has a fourth side 134, which is disposed opposite to the first side 131. The drain pin 123 includes a plurality of sub-pins, and some of the sub-pins of the two drain pins 123 are disposed on the fourth side 134.

[0086] For example, see Figure 1 , Figure 3 , Figure 4 and Figure 6 The two drain pins 123 are designated as the first drain pin 123 and the second drain pin 123, respectively. Each drain pin 123 includes multiple sub-pins distributed around the periphery of the package body 130. The sub-pins of the first drain pin 123 are electrically connected to the drain of the first wafer 111. The multiple sub-pins of the second drain pin 123 are electrically connected to the drain of the second wafer 112. Specifically, some sub-pins of the first drain pin 123 are located on the second side 132, and the remaining sub-pins are located on the fourth side 134. Similarly, some sub-pins of the second drain pin 123 are located on the third side 133, and the remaining sub-pins are located on the fourth side 134. The sub-pins of the first drain pin 123 on the fourth side 134 are positioned closer to the second side 132, and the sub-pins of the second drain pin 123 on the fourth side 134 are positioned closer to the third side 133.

[0087] In this embodiment, when the MOSFET structure 100 is mounted on the PCB board 200, the PCB board 200 has two power traces, such as a first power trace 230 and a second power trace 240. The first power trace 230 is connected to the first drain pin 123, and the second power trace 240 is connected to the second drain pin 123. The first power trace 230 and the second power trace 240 are located on both sides of the package body 130, respectively. The wiring space of the power traces is large, which is beneficial to the wiring design of the PCB board 200.

[0088] Furthermore, each drain pin 123 includes multiple sub-pins, which are distributed across two sides of the package 130. This design expands the arrangement space of the drain pins 123, improving design flexibility. The current-carrying capacity and heat dissipation capacity of the dual MOSFET can also be increased by increasing the number or area of ​​the sub-pins.

[0089] In some embodiments, see Figure 3 , Figure 4 and Figure 5 Multiple wafers 110 are mounted on corresponding drain pins 123. Specifically, a first wafer 111 is mounted on a first drain pin 123, and the drain of the first wafer 111 is electrically connected to the surface of the first drain pin 123. The drain of a second wafer 112 is mounted on a second drain pin 123, and the drain of the second wafer 112 is electrically connected to the surface of the second drain pin 123.

[0090] In the embodiments of this application, multiple wafers 110 are mounted on corresponding drain pins 123 to achieve efficient electrical connection and signal transmission. The first wafer 111 is securely mounted on the first drain pin 123 via its drain, ensuring a tight fit between its drain and the surface of the first drain pin 123, forming a reliable electrical connection. Similarly, the drain of the second wafer 112 is precisely mounted on the second drain pin 123, ensuring a seamless fit between its drain and the surface of the second drain pin 123, ensuring a stable electrical connection. This mounting method not only improves wafer stability but also optimizes electrical performance, reduces resistance loss, and thus improves the efficiency of the entire system.

[0091] In some embodiments, the drain pin 123 is a supporting metal substrate, and multiple drain pins 123 correspond to multiple supporting metal substrates. The multiple supporting metal substrates are insulated from each other, and multiple wafers 110 are mounted on the corresponding supporting metal substrates. The drain of the wafer is electrically connected to the corresponding supporting metal substrate.

[0092] In this embodiment, the drain pin 123 is designed as a supporting metal substrate, such as a rectangular plate structure. Multiple drain pins 123 correspond to multiple supporting metal substrates, which are isolated from each other by an insulating material to prevent electrical interference and short circuits. Furthermore, multiple semiconductor wafers are precisely mounted on their respective supporting metal substrates, enabling a robust electrical connection between the drain of each wafer and its corresponding supporting metal substrate. This design not only improves the reliability and stability of the semiconductor device but also optimizes its heat dissipation capabilities, ensuring effective operation in high-performance applications.

[0093] In some embodiments, see Figure 7 Each supporting metal substrate includes a support portion 1241 and a lead portion 1242. The lead portion 1242 is mounted on one side of the support portion 1241 and extends outside the package 130. The wafer is mounted on the support portion 1241 of the corresponding supporting metal substrate.

[0094] In this embodiment, each supporting metal substrate comprises a support portion 1241 and a lead portion 1242. The lead portion 1242 is mounted on one side of the support portion 1241 and extends to the outside of the package 130 for easy connection to external circuitry. The wafer is fixed to the support portion 1241 of the corresponding supporting metal substrate to ensure its stability and effective electrical performance. The supporting metal substrate not only provides physical support but also ensures reliable electrical contact between the wafer and external circuitry. This structural design improves the mechanical strength and electrical performance of the entire package 130, making it suitable for various electronic device applications.

[0095] In some embodiments, see Figure 3 , Figure 4and Figure 5 The plurality of wafers 110 include a first wafer 111 and a second wafer 112. The supporting metal substrate includes a first metal substrate 124 and a second metal substrate 125. The first wafer 111 is mounted on the first metal substrate 124, and the drain of the first wafer 111 is electrically connected to the first metal substrate 124. The second wafer 112 is mounted on the second metal substrate 125, and the drain of the second wafer 112 is electrically connected to the second metal substrate 125. The first metal substrate 124 and the second metal substrate 125 are mirror images of each other.

[0096] In this embodiment, two wafers are connected by two metal substrates, which greatly improves the integration and space utilization of the package structure, and realizes the miniaturization and lightweight design of the dual MOS transistors. The first metal substrate 124 and the second metal substrate 125 are designed to be mirror images of each other, with the pin portion 1242 located on both sides of the package body 130. This structural design not only enhances the overall performance of the device, but also optimizes its adaptability and reliability in different application scenarios.

[0097] In some embodiments, the first pin 121 is a third metal substrate 126, the second pin 122 is a fourth metal substrate 127, the first electrode 113 of the plurality of wafers 110 is electrically connected to the third metal substrate 126, and the second electrode 114 of the plurality of wafers 110 is electrically connected to the fourth metal substrate 127.

[0098] For example, the conductive component 120 includes a first metal substrate 124, a second metal substrate 125, a third metal substrate 126, and a fourth metal substrate 127 that are mutually insulated. The first metal substrate 124, the second metal substrate 125, the third metal substrate 126, and the fourth metal substrate 127 are partially exposed through the package 130. A first wafer 111 is mounted on the first metal substrate 124, and a second wafer 112 is mounted on the second metal substrate 125. The drain of the first wafer 111 is directly electrically connected to the first metal substrate 124, and the drain of the second wafer 112 is directly electrically connected to each other, thereby ensuring efficient current transmission. The gates of a plurality of wafers 110 are all electrically connected to the fourth metal substrate 127, and the sources of a plurality of wafers 110 are all electrically connected to the third metal substrate 126. Furthermore, the gates of a plurality of wafers 110 are all electrically connected to the fourth metal substrate 127, while all their sources are electrically connected to the fourth metal substrate 127. This design not only simplifies the overall circuit structure but also improves the reliability and performance of the conductive component 120, ensuring stability and efficiency in various application scenarios.

[0099] In this embodiment, two wafers are connected by four metal substrates, and pins are formed outside the package 130, which greatly improves the integration and space utilization of the package structure. The pins formed by the four metal substrates can achieve electrical connection in a more compact layout, reduce line crossing, and realize the miniaturization and lightweight design of dual MOSFETs.

[0100] In some embodiments, both the third metal substrate 126 and the fourth metal substrate 127 include connecting portions and pins. The pins are located on one side of the connecting portion and extend beyond the package 130 to facilitate external electrical connections. The first electrodes 113 of the plurality of wafers 110 are electrically connected to the corresponding connecting portions of the third metal substrate 126 to ensure smooth current conduction. Similarly, the second electrodes 114 of the plurality of wafers 110 are electrically connected to the corresponding connecting portions of the fourth metal substrate 127. This layout design improves the overall electrical performance and reliability of the system, and also effectively helps with heat dissipation and enhances circuit stability.

[0101] In some embodiments, see Figure 3 , Figure 4 and Figure 5 The gates of the first wafer 111 and the second wafer 112 are electrically connected to the fourth metal substrate 127 via wires 128. This design ensures that the gates of the two wafers can effectively communicate electrically with the third metal substrate 126, thereby improving the stability and performance of the overall circuit. It can reduce resistance loss and improve current transmission efficiency, making it suitable for various high-performance electronic device applications.

[0102] In some embodiments, the source of the first wafer 111 or the source of the second wafer 112 is electrically connected within the package 130 via a wire 128, and the source of the first wafer 111 or the source of the second wafer 112 is electrically connected to the third metal substrate 126 via the wire 128.

[0103] In some embodiments, the third metal substrate 126 is located on the side of the first metal substrate 124 near the first side 131, and the fourth metal substrate 127 is located on the side of the second metal substrate 125 near the first side 131. The first metal substrate 124, the second metal substrate 125, the third metal substrate 126, and the fourth metal substrate 127 are laid flat in the same plane.

[0104] In this embodiment, the first metal substrate 124 is used for drain signal transmission of the first wafer 111. The second metal substrate 125 is used for drain signal transmission of the second wafer 112. The third metal substrate 126 is used for transmitting the source control signal of the dual MOSFETs. The fourth metal substrate 127 is used for transmitting the gate control signal of the dual MOSFETs. Through precise insulation and isolation design, it is ensured that the signals do not interfere with each other, enabling the dual MOSFETs to work stably and efficiently. In addition, the first metal substrate 124 and the second metal substrate 125 respectively support the first wafer 111 and the second wafer 112, simplifying the installation process and effectively dissipating heat. The heat generated by the first wafer 111 and the second wafer 112 is transferred to the outside of the package 130 through the first metal substrate 124 and the second metal substrate 125, significantly improving the heat dissipation performance and lifespan of the dual MOSFETs.

[0105] In some embodiments, both the first metal substrate 124 and the second metal substrate 125 are designed to include a support portion 1241 and a plurality of sub-pins. The plurality of sub-pins are spaced apart on the sides of the support portion 1241 and extend beyond the exterior of the package 130. The plurality of sub-pins are spaced apart along the sides of the package 130 to ensure good electrical connection and mechanical support. The overall strength of the package 130 is improved, while also simplifying the connection process with external circuits, effectively enhancing the reliability and stability of the component.

[0106] In some embodiments, see Figure 1 and Figure 2 An opening 135 is provided on one side of the package 130, and the projection of the wafer is located within the opening 135 along the thickness direction of the package 130.

[0107] In this embodiment, one or two openings 135 are designed on one side of the package 130 to improve the heat dissipation performance of the MOS transistor structure 100. When an opening 135 is provided on one side of the package 130, the projections of both wafers are located within the opening 135 along the thickness direction of the package 130. The advantage of this design is that it can concentrate heat dissipation, effectively dissipating heat through a single opening 135, reducing the operating temperature of the chip, and improving the stability and efficiency of the entire system.

[0108] Alternatively, in another design scheme, see... Figure 1The package 130 has two openings 135 on its side, each corresponding to the projection of only one wafer. The advantage of this design is that it manages heat dissipation for both chips through the openings 135 while preserving the package 130 between them, ensuring the structural strength and heat dissipation of the dual MOSFETs. Through this professional thermal management design, during operation of the MOSFET structure 100, the wafer, as the main heat-generating component, can quickly dissipate heat through the openings 135 on the package 130. This not only improves heat dissipation efficiency but also extends the lifespan of the MOSFETs, ensuring safe operation of the device under high load conditions.

[0109] In some embodiments, the wafer is mounted on the conductive component 120, and the side of the conductive component 120 facing away from the wafer is exposed in the opening 135.

[0110] In this embodiment, the conductive component 120 includes a first metal substrate 124 and a second metal substrate 125. A first wafer 111 is mounted on the first metal substrate 124, and a second wafer 112 is mounted on the second metal substrate 125. The sides of the first metal substrate 124 and the second metal substrate 125 facing away from the wafer are exposed within the opening 135. During operation, the wafer, as the main heat-generating component, transmits heat to the pin group via the conductive component 120, which then diffuses it into the air. Another portion of the heat is diffused into the surrounding environment through the opening 135 via the conductive component 120, allowing the heat generated by the wafer to dissipate quickly and improving heat dissipation efficiency.

[0111] For other embodiments, see Figure 2 and Figure 6 Multiple openings 135 are formed on the package 130. Along the thickness direction of the package 130, the first metal substrate 124, the second metal substrate 125, the third metal substrate 126 and the fourth metal substrate 127 are partially exposed in the corresponding openings 135 on the package 130, which further improves the heat dissipation performance of the MOS transistor structure 100.

[0112] In some embodiments, the surface of the conductive component 120 located within the opening 135 is provided with an anti-oxidation coating. For example, a portion of the first metal substrate 124 and the second metal substrate 125 facing away from the wafer is exposed within the opening 135, and the portions of the first metal substrate 124 and the second metal substrate 125 located within the opening 135 are provided with an anti-oxidation coating.

[0113] The anti-oxidation coating can be formed by plating a low-activity metal, such as tin, gold, or silver, onto the surfaces of the first metal substrate 124 and the second metal substrate 125 exposed within the opening 135. This prevents the oxidation of the first and second metal substrates 125 from affecting conductivity and improves the reliability of the conductive component 120.

[0114] In some embodiments, see Figure 1 The pin group includes multiple gull-wing feet. For example, the first pin 121 and the second pin 122 are both gull-wing feet, and the sub-pins are also gull-wing feet. Each gull-wing foot includes a first connection portion and a second connection portion. The first connection portion is closer to the package body 130 than the second connection portion, and the horizontal plane of the first connection portion is higher than the horizontal plane of the second connection portion. The MOSFET structure 100 is soldered to the PCB board 200 via the gull-wing feet, facilitating soldering operations. Furthermore, the gull-wing feet provide good vibration resistance.

[0115] In some embodiments, an anti-oxidation coating is applied to the surface of the seagull-shaped feet. This anti-oxidation coating can be formed by plating a low-activity metal onto the surface of the seagull-shaped feet, such as tin, gold, or silver. Applying an anti-oxidation coating to the surface of the seagull-shaped feet prevents oxidation from affecting conductivity and improves the reliability of the seagull-shaped feet.

[0116] According to the second aspect of this disclosure, see Figure 8 A reverse shutdown protection power module is provided, comprising a MOSFET structure 100 as described above and a PCB board 200. The pin group of the MOSFET structure 100 is bonded to the PCB board 200. This reverse shutdown protection power module has all the beneficial effects of the MOSFET structure 100 described above, which will not be elaborated further in this disclosure.

[0117] In some embodiments, see Figure 9 It also includes a heat sink 300, and a MOSFET structure 100 located between the heat sink 300 and the PCB. The heat sink 300 and the PCB board 200 clamp and fix the MOSFET structure 100.

[0118] In this embodiment, the MOSFET structure 100 is cleverly installed between the heat sink 300 and the PCB board 200 to optimize its thermal management performance. Specifically, the MOSFET structure 100 is directly and tightly connected to the heat sink 300, allowing the heat generated by the dual MOSFETs during operation to be quickly and effectively absorbed and dissipated by the heat sink 300, thereby significantly improving the heat dissipation efficiency of the MOSFET structure 100 and ensuring its stable operation in high-temperature environments. Furthermore, after the heat sink 300 is assembled with the PCB board 200, it not only clamps and fixes the MOSFET structure 100 but also simplifies its installation process. Since it eliminates the need for complex connection structures such as screws to fix the dual MOSFETs to the PCB board 200, this design not only simplifies the installation steps of the MOSFET structure 100 but also helps reduce its overall size. This design makes the overall layout of the device more compact, while reducing the complexity of production and maintenance, providing strong support for the miniaturization and efficiency of electronic products.

[0119] In some embodiments, the conductive component 120 of the MOS transistor structure 100 is closer to the heat sink 300 than the wafer.

[0120] In this embodiment, the heat generated by the MOS transistor structure 100 during tooling is transmitted to the heat sink 300 through the conductive component 120, and is absorbed and dissipated by the heat sink 300, thereby achieving heat dissipation of the MOS transistor structure 100 and improving the heat dissipation efficiency and reliability of the MOS transistor structure 100.

[0121] In some embodiments, the anti-reverse shutdown power module further includes a housing, within which a PCB board 200 is mounted, and the housing and PCB board 200 clamp and fix the MOSFET structure 100. This simplifies the installation of the MOSFET structure 100, making the overall layout of the device more compact and providing strong support for the miniaturization and efficiency of electronic products. The housing can be made of metal, allowing the heat generated by the MOSFET structure 100 to dissipate into the air through the housing, thus improving the heat dissipation of the MOSFET structure 100.

[0122] In some embodiments, an insulating and thermally conductive layer is provided between the housing and the conductive component 120. The material of the thermally conductive insulating layer can be thermally conductive silicone grease. By providing an insulating and thermally conductive layer, thermal conductivity and insulation between the conductive component 120 and the heat sink 300 are achieved, improving the safety of the reverse shutdown power module.

[0123] In some embodiments, an insulating and thermally conductive layer is provided between the conductive component 120 and the heat sink 300.

[0124] In some embodiments, see Figure 1 and Figure 2 The package 130 has an opening 135 on the side away from the PCB board 200, and the conductive component 120 is exposed in the opening 135 on the side away from the wafer.

[0125] In this embodiment, the heat generated by the MOS transistor structure 100 during operation is diffused into the opening 135 through the conductive component 120, and then absorbed and dissipated by the heat sink 300 or the housing, thereby significantly improving the heat dissipation efficiency of the MOS transistor structure 100 and ensuring its stable operation in high-temperature environments.

[0126] In some implementations, a controller 400 is also included, mounted on the PCB board 200. The controller 400 is electrically connected to the first terminal 113 and the second terminal 114 of the MOSFET structure 100. The drain of the MOSFET structure 100 is electrically connected to the product to be controlled. The controller 400 applies a voltage to the first terminal 113 and the second terminal 114, causing one of the first terminal 113 and the second terminal 114 to be either turned on or off with the drain. Specifically, the first terminal 113 is the source, and the second terminal 114 is the gate. The controller 400 applies a voltage to the source and the gate to control whether the source and the drain are turned on or off, thereby controlling the switching of the product to be controlled.

[0127] In some embodiments, see Figure 8 The PCB board 200 design includes power traces and control traces on the same layer, which are connected to pin groups respectively. Specifically, the PCB board 200 has a first power trace 230, a second power trace 240, a first control trace 210, and a second control trace 220. The first power trace 230 and the second power trace 240 are located on opposite sides of the MOSFET structure 100. The first power trace 230 is electrically connected to the first drain pin 123, and the second power trace 240 is electrically connected to the second drain pin 123. The first control trace 210 is electrically connected to the second pin 122, and the second control trace 220 is electrically connected to the drain pin 123. By setting power traces and control traces on the same layer that are electrically connected to the dual MOSFETs on the PCB board 200, the routing design within the PCB board 200 is simplified, the number of routing layers is reduced, and thus the cost is lowered.

[0128] According to a third aspect of this disclosure, a vehicle is provided that includes the aforementioned reverse shutdown power module, and the vehicle has all the beneficial effects of the aforementioned reverse shutdown power module, which will not be repeated here.

[0129] The vehicle may be a gasoline-powered vehicle, a plug-in hybrid electric vehicle, or a new energy vehicle, etc., and this disclosure does not make any specific restrictions.

[0130] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0131] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0132] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0133] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A MOS transistor structure (100), characterized in that, include: Multiple wafers (110), each wafer having a first electrode (113), a second electrode (114) and a drain, wherein applying a voltage to the first electrode (113) and the second electrode (114) enables one of the first electrode (113) and the second electrode (114) to be turned on or off with the drain; Package (130) encapsulates the plurality of wafers (110); A conductive component (120) includes a first pin (121), a second pin (122), and a plurality of drain pins (123). The drains of the plurality of wafers (110) are electrically connected to the corresponding drain pins (123). The first electrode (113) of the plurality of wafers (110) is electrically connected to the first pin (121). The second electrode (114) of the plurality of wafers (110) is electrically connected to the second pin (122). At least one of the first electrode (113) and the second electrode (114) of the plurality of wafers (110) is electrically connected within the package (130). The first pin (121), the second pin (122), and the plurality of drain pins (123) partially penetrate the package (130) and are exposed to the outside for bonding and electrical connection with the PCB board (200).

2. The MOS transistor structure (100) according to claim 1, characterized in that, The first electrode (113) is the source electrode, and the second electrode (114) is the drain electrode.

3. The MOS transistor structure (100) according to claim 2, characterized in that, The first poles (113) of the plurality of wafers (110) are electrically connected to each other by wires (128), and the first pole (113) of any one of the wafers is electrically connected to the second pin (122).

4. The MOS transistor structure (100) according to claim 3, characterized in that, The second electrode (114) of the plurality of wafers (110) is electrically connected to the first pin (121) via wires (128).

5. The MOS transistor structure (100) according to any one of claims 1 to 4, characterized in that, The first pin (121), the second pin (122) and the plurality of drain pins (123) are distributed along the side of the package (130), the package (130) having a first side (131), the first pin (121) and the second pin (122) being positioned closer to the first side (131) than the drain pins (123).

6. The MOS transistor structure (100) according to claim 5, characterized in that, The package (130) has a second side (132) and a third side (133) disposed opposite to each other, the first side (131) is connected between the second side (132) and the third side (133), the first pin (121) is located on the second side (132), and the second pin (122) is located on the third side (133).

7. The MOS transistor structure (100) according to claim 6, characterized in that, The drain pin (123) electrically connected to one of the wafers is located on the second side (132), and the drain pin (123) electrically connected to the other wafer is located on the third side (133).

8. The MOS transistor structure (100) according to claim 6, characterized in that, The package (130) has a fourth side (134) which is disposed opposite to the first side (131). The drain pin (123) includes a plurality of sub-pins, and a portion of the sub-pins of two drain pins (123) are disposed on the fourth side (134).

9. The MOS transistor structure (100) according to claim 5, characterized in that, The plurality of wafers (110) are mounted on the corresponding drain pins (123).

10. The MOS transistor structure (100) according to claim 9, characterized in that, The drain pin (123) is a supporting metal substrate, and the plurality of drain pins (123) correspond to the plurality of supporting metal substrates. The plurality of supporting metal substrates are insulated from each other. The plurality of wafers (110) are mounted on the corresponding supporting metal substrates, and the drain of the wafer is electrically connected to the corresponding supporting metal substrate.

11. The MOS transistor structure (100) according to claim 10, characterized in that, Each of the supporting metal substrates includes a support portion (1241) and a lead portion (1242), the lead portion (1242) being mounted on one side of the support portion and extending outside the package (130), and the wafer being mounted on the support portion (1241) of the corresponding supporting metal substrate.

12. The MOS transistor structure (100) according to claim 11, characterized in that, The plurality of wafers (110) includes a first wafer (111) and a second wafer (112), and the plurality of supporting metal substrates includes a first metal substrate (124) and a second metal substrate (125). The first wafer (111) is mounted on the first metal substrate (124), and the second wafer (112) is mounted on the second metal substrate (125). The first metal substrate (124) and the second metal substrate (125) are mirror images of each other.

13. The MOS transistor structure (100) according to claim 12, characterized in that, The first pin (121) is a third metal substrate (126), the second pin (122) is a fourth metal substrate (127), the first electrode (113) of the plurality of wafers (110) is electrically connected to the third metal substrate (126), and the second electrode (114) of the plurality of wafers (110) is electrically connected to the fourth metal substrate (127).

14. The MOS transistor structure (100) according to claim 13, characterized in that, Both the third metal substrate (126) and the fourth metal substrate (127) include a connection portion and a pin. The pin is located on one side of the connection portion and extends out of the package body (130). The first electrode (113) of the plurality of wafers (110) is electrically connected to the corresponding connection portion of the third metal substrate (126), and the second electrode (114) of the plurality of wafers (110) is electrically connected to the corresponding connection portion of the fourth metal substrate (127).

15. The MOS transistor structure (100) according to claim 14, characterized in that, The first electrode (113) is the source electrode, and the second electrode (114) is the gate electrode. The second electrode (114) of the first wafer (111) and the second electrode (114) of the second wafer (112) are electrically connected to the connection portion of the fourth metal substrate (127) through wires (128).

16. The MOS transistor structure (100) according to claim 15, characterized in that, The first electrode (113) of the first wafer (111) is electrically connected to the first electrode (113) of the second wafer (112) via a wire (128), and the first electrode (113) of the first wafer (111) or the first electrode (113) of the second wafer (112) is electrically connected to the third metal substrate (126) via a wire (128).

17. The MOS transistor structure (100) according to claim 12, characterized in that, The pin portion (1242) includes a plurality of sub-pins, and the plurality of sub-pin portions (1242) are arranged at intervals along the side of the package body (130).

18. The MOS transistor structure (100) according to claim 9, characterized in that, An opening (135) is provided on one side of the package (130), and the projections of the plurality of wafers (110) are located within the opening (135) along the thickness direction of the package (130).

19. The MOS transistor structure (100) according to claim 18, characterized in that, The drain pin (123) is exposed in the opening (135) on the side opposite to the plurality of wafers (110).

20. The MOS transistor structure (100) according to claim 19, characterized in that, The conductive component (120) has an anti-oxidation coating on its surface located within the opening (135).

21. The MOS transistor structure (100) according to claim 1, characterized in that, The first electrode (113) is the gate electrode, and the second electrode (114) is the source electrode.

22. The MOS transistor structure (100) according to claim 1, characterized in that, If the first electrode (113) of the plurality of wafers (110) is electrically connected inside the package (130), then a first pin (121) and a plurality of second pins (122) are provided. The first electrode (113) of the plurality of wafers (110) is electrically connected to the first pin (121), and the second electrode (114) of the plurality of wafers (110) is electrically connected to the corresponding second pin (122). If the second electrode (114) of the plurality of wafers (110) is electrically connected inside the package (130), then a second pin (122) and a plurality of first pins (121) are provided, the second electrode (114) of the plurality of wafers (110) are all electrically connected to the second pin (122), and the first electrode (113) of the plurality of wafers (110) are respectively electrically connected to the corresponding first pin (121); If the first electrode (113) and the second electrode (114) of the plurality of wafers (110) are electrically connected inside the package (130), then a first pin (121) and a second pin (122) are provided, the first electrode (113) of the plurality of wafers (110) are all electrically connected to the first pin (121), and the second electrode (114) of the plurality of wafers (110) are all electrically connected to the second pin (122).

23. A reverse shutdown power module, characterized in that, include: The MOS transistor structure (100) as described in any one of claims 1 to 22; The PCB board (200) has the first pin (121), the second pin (122) and multiple drain pins (123) of the MOS transistor structure (100) in a bonded and electrically connected manner.

24. The anti-reverse shutdown power module according to claim 23, characterized in that, It also includes a heat sink (300), which clamps and fixes the MOS transistor structure (100) with the PCB board (200).

25. The anti-reverse shutdown power module according to claim 24, characterized in that, The conductive component (120) of the MOS transistor structure (100) is closer to the heat sink (300) than the plurality of wafers (110).

26. The anti-reverse shutdown power module according to claim 23, characterized in that, It also includes a housing, which clamps and fixes the MOS transistor structure (100) to the PCB board (200).

27. The anti-reverse shutdown power module according to claim 26, characterized in that, An insulating and thermally conductive layer is provided between the housing and the conductive component (120).

28. The anti-reverse shutdown power module according to claim 24 or 26, characterized in that, The package (130) has an opening (135) on the side away from the PCB board (200), and the conductive component (120) is exposed in the opening (135) on the side away from the plurality of wafers (110).

29. The anti-reverse shutdown power module according to claim 23, characterized in that, It also includes a controller (400) mounted on the PCB board (200). The controller (400) is electrically connected to the first terminal (113) and the second terminal (114) of the MOS transistor structure (100). The controller (400) is used to apply a voltage to the first terminal (113) and the second terminal (114) so ​​that one of the first terminal (113) and the second terminal (114) is turned on or off with the drain.

30. The anti-reverse shutdown power module according to claim 29, characterized in that, The PCB board (200) has power traces and two control traces on the same layer. The drain pin (123) is electrically connected to the power trace, and the first pin (121) and the second pin (122) are electrically connected to the corresponding control traces.

31. A vehicle, characterized in that, Includes the anti-reverse shutdown power module as described in any one of claims 23 to 30.

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