A test system for nand flash memory

Abstract

This application discloses a NAND flash memory testing system, comprising: an ARM processor communicatively connected to a main control chip, configured to send test commands to the main control chip and receive test response data from the main control chip for a flash memory chip under test, and determine the test result of the flash memory chip under test based on the test response data; the main control chip communicatively connected to both the ARM processor and the flash memory chip under test, configured to receive test commands from the ARM processor, perform test operations on the flash memory chip under test based on the test commands, simultaneously collect test response data from the flash memory chip under test in response to the test operations, and send the test response data to the ARM processor. This application can improve the testing efficiency of flash memory chips under test.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a NAND flash memory testing system. Background Technology

[0002] Among all storage media, NAND flash memory has become the absolute mainstream storage solution due to its advantages such as non-volatility, high density, low power consumption, and shock resistance, and is widely used in various storage products such as solid-state drives and memory cards.

[0003] Although NAND Flash memory is widely used due to its many advantages, it also suffers from inherent, irreversible wear and tear due to its physical limitations. Therefore, it is necessary to conduct rapid, rigorous, and quantitative testing to determine the lifespan of NAND Flash.

[0004] However, existing NAND Flash testing methods typically use a single microprocessor (such as a low-end MPU) or an FPGA as the core controller for circuit construction. These methods have limited processing power, and the controller / processor needs to be responsible for parsing test instructions, controlling the logic of the test process, and performing heavy data read / write, erase operations, and verification calculations on the Flash chip for endurance testing. Resources are often scarce, test throughput is low, and the testing cannot meet the requirements of high-frequency, large-volume testing, thus becoming a bottleneck for improving efficiency.

[0005] Therefore, there is an urgent need for a NAND flash memory testing system to solve the problem of low testing efficiency of flash memory chips in existing technologies. Summary of the Invention

[0006] In view of this, the present invention provides a NAND flash memory testing system, the main purpose of which is to solve the problem of low testing efficiency of flash memory chips.

[0007] To address the aforementioned problems, this application provides a NAND flash memory testing system, comprising: An ARM processor, communicatively connected to a main control chip, is used to send test commands to the main control chip and to receive test response data sent by the main control chip for the flash memory chip under test, and to determine the test result of the flash memory chip under test based on the test response data. The main control chip is communicatively connected to both the ARM processor and the flash memory chip under test. It is used to receive test commands sent by the ARM processor, perform test operations on the flash memory chip under test based on the test commands, collect test response data of the flash memory chip under test in response to the test operations, and send the test response data to the ARM processor.

[0008] Optionally, the testing system includes: a test socket for placing the flash memory chip to be tested; The flash memory chip under test is connected to the main control chip via the test socket.

[0009] Optionally, the ARM processor communicates with the main control chip via a high-speed bus.

[0010] Optionally, the testing system further includes: a host computer; The host computer is communicatively connected to the ARM processor; The host computer is used to receive the test results sent by the ARM processor and display the test results.

[0011] Optionally, the host computer communicates with the ARM processor via a physical layer chip.

[0012] Optionally, the ARM processor is a processor with two built-in ARM Cortex-R series real-time cores; The first core in the ARM processor is used to send test commands; The second core in the ARM processor is used to receive test response data.

[0013] Optionally, the system further includes: a voltage and current detection chip; The detection terminal of the voltage and current detection chip is electrically connected to the test socket and is used to detect the voltage and current of the flash memory chip under test on the test socket when performing test operations. The output terminal of the voltage and current detection chip is communicatively connected to the ARM processor, and is used to send the voltage and the current to the ARM processor.

[0014] Optionally, the system further includes a power module, which is electrically connected to the ARM processor, the main control chip, the voltage and current detection chip, and the test socket, respectively, and is used to supply power to the ARM processor, the main control chip, the voltage and current detection chip, and the flash memory chip under test on the test socket.

[0015] This application discloses a NAND flash memory testing system. By setting up a flash memory testing system with a main control chip and an ARM dual-core processor, it tests the performance and lifespan of the flash memory chip under test. It realizes that communication and other tasks are assigned to the main control chip, while high-speed data processing tasks such as reading, writing, and verification of the flash memory are assigned to the ARM processor, thus achieving task-level parallel processing and improving the efficiency of flash memory chip testing.

[0016] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a system architecture diagram of a NAND Flash testing system according to an embodiment of this application. Detailed Implementation

[0018] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0019] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0020] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0021] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0022] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.

[0023] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0024] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as the basis and representative basis for the claims to teach those skilled in the art to use this application in a variety of substantially any suitable detailed structures.

[0025] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.

[0026] This application provides a NAND flash memory testing system, such as... Figure 1 As shown, it includes: an ARM processor and a main control chip.

[0027] An ARM processor, communicatively connected to a main control chip, is used to send test commands to the main control chip and to receive test response data sent by the main control chip for the flash memory chip under test, and to determine the test result of the flash memory chip under test based on the test response data. The main control chip is communicatively connected to both the ARM processor and the flash memory chip under test. It receives test commands from the ARM processor, performs test operations on the flash memory chip under test based on these commands, collects test response data from the flash memory chip under test in response to the test operations, and sends the test response data back to the ARM processor. In this embodiment, a single main control chip can be used to execute instructions / test commands issued by the ARM processor to perform relevant erase, write, and read operations on the flash chip / flash memory chip under test.

[0028] In this embodiment, the testing system may further include: a test socket / Flash test socket for placing the flash memory chip under test, wherein the flash memory chip under test is communicatively connected to the main control chip through the test socket.

[0029] In this embodiment, the ARM processor communicates with the main control chip via a high-speed bus PCLE.

[0030] In this embodiment, the NAND Flash testing system further includes a host computer and a voltage and current detection chip. The host computer is communicatively connected to the ARM processor. The host computer receives test results sent by the ARM processor and displays the test results. Specifically, the host computer communicates with the ARM processor through a physical layer chip (PHY).

[0031] The detection terminal of the voltage and current detection chip is electrically connected to the test socket and is used to detect the voltage and current of the flash memory chip under test during the test operation. The output terminal of the voltage and current detection chip is communicatively connected to the ARM processor and is used to send the voltage and current to the ARM processor. The ARM processor then forwards the voltage and current to the host computer for display.

[0032] In other words, the voltage and current detection chip 105 will read the voltage and current on the flash chip / the flash memory chip under test, and send the voltage and current data to the ARM processor 102 through the I2C interface. The ARM processor 102 will then output the data to the host computer through the PHY chip and the network port for corresponding processing, and finally display the results in the host computer window.

[0033] In this embodiment, the ARM processor is a processor with two built-in ARM Cortex-R series real-time cores; the first core of the ARM processor is used to send test commands; and the second core of the ARM processor is used to receive test response data.

[0034] The system in this embodiment also includes a power module, which is electrically connected to the ARM processor, the main control chip, the voltage and current detection chip, and the test socket, respectively, and is used to supply power to the ARM processor, the main control chip, the voltage and current detection chip, and the flash memory chip under test on the test socket.

[0035] In this embodiment, the NAND Flash testing system operates as follows: The ARM dual-core processor 102 communicates with the main control chip 101 via a PCIe high-speed interface. The ARM dual-core processor 102 issues erase / write / read commands and other test tasks / commands to the main control chip 101. The main control chip 101 executes the test commands to complete the detection of the flash memory chip under test on the test socket 104 and returns data such as erase / write times to the ARM dual-core processor 102 for data preprocessing. The voltage and current detection chip 105 reads the voltage and current data from the flash chip / flash memory chip under test and sends the voltage and current data to the ARM dual-core processor 102 via the I2C interface. The ARM dual-core processor 102 then outputs the data to the host computer via the PHY chip / physical layer chip and then via the network port for further processing. Finally, the results are displayed in the host computer window.

[0036] This embodiment of a NAND flash memory testing system, by setting up a main control chip and an ARM dual-core processing system for flash memory testing, tests the performance and lifespan of the flash memory chip under test. It achieves the allocation of communication and other tasks to the main control chip, and the allocation of high-speed data processing tasks such as low-level reading, writing and verification of flash memory to the ARM processor, realizing task-level parallel processing, thus improving the efficiency of flash memory chip testing.

[0037] In this application, the ARM processor adopts a dual-core processor, where one core is responsible for sending instructions and data, and the other core is dedicated to receiving and verifying responses. This avoids the overhead of frequent switching between different tasks by a single core, thereby greatly improving the testing speed and processing efficiency.

[0038] The test system in this application possesses advantages in power management. The refined and efficient power management, leading to improved system stability and energy efficiency, allows for independent and granular power management of different modules. When the system is only performing light tasks (such as waiting for instructions from the host computer or data logging), the operating system can dynamically reduce the main core's operating frequency and voltage (DVFS), or place the core in a low-power idle state. In extreme cases, even temporarily unused peripheral devices (such as certain USB or network interfaces) can be powered off. Furthermore, it can utilize a simpler power tree design, possessing a more defined voltage threshold and a more stable power supply.

[0039] The testing system described in this application significantly reduces the development threshold and timeframe. Thanks to the rich operating system support (such as Linux) and robust driver framework of the ARM platform, developers can focus on testing logic and upper-level applications without delving into low-level hardware timing design, thereby greatly saving development time and effort.

[0040] The testing system described in this application is scalable and maintainable. The ARM-based testing platform more easily integrates advanced functions such as networking, file systems, databases, and graphical interfaces, facilitating test case management, data recording and analysis, and remote monitoring. System function expansion and subsequent maintenance are also more convenient.

[0041] The testing system in this application more closely resembles the verification environment of real-world application scenarios. ARM processors, as the main control chips in many embedded terminals, form the core of the testing platform, enabling a more realistic reflection of the actual workload, access patterns, and system interactions of NAND Flash in the final product, thus making the test results more valuable for practical reference.

[0042] The testing system in this application features precise timing control, improving test accuracy. Since the ARM dual-core is dedicated to Flash operations with high real-time requirements, its task scheduling is not interfered with by upper-level management tasks, ensuring that the access timing to the Flash chip strictly conforms to the specifications. This reduces test errors caused by response delays and improves the reliability and accuracy of test results.

[0043] The test system in this application adopts a modular design to enhance system scalability. This architecture separates control from data processing, with modules communicating through explicit interfaces. When support for higher speeds or more channels of Flash chips is required, the ARM dual-core module or its interface speed can be primarily upgraded, while the main control system requires minimal modification. This makes the system easy to upgrade and expand, adapting to future technological developments.

[0044] The test system in this application saves on adapters and improves related speeds. In this method, the main controller and ARM can use the NVMe protocol, allowing direct PCIe connection between the main controller and ARM, eliminating the need for adapters while ensuring extreme speed and extremely low latency. The test system in this application is highly integrated. The ARM and main control pins are directly brought out to the relevant networks, reducing the use of related chips and reducing the design workload during the PCB design stage.

[0045] The above embodiments are merely exemplary embodiments of this application and are not intended to limit this application. The scope of protection of this application is defined by the claims. Those skilled in the art can make various modifications or equivalent substitutions to this application within its substance and scope of protection, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this application.

Claims

1. A NAND flash memory testing system, characterized in that, include: An ARM processor, communicatively connected to a main control chip, is used to send test commands to the main control chip and to receive test response data sent by the main control chip for the flash memory chip under test, and to determine the test result of the flash memory chip under test based on the test response data. The main control chip is communicatively connected to both the ARM processor and the flash memory chip under test. It is used to receive test commands sent by the ARM processor, perform test operations on the flash memory chip under test based on the test commands, collect test response data of the flash memory chip under test in response to the test operations, and send the test response data to the ARM processor.

2. The method as described in claim 1, characterized in that, The testing system includes: a test socket for placing the flash memory chip to be tested; The flash memory chip under test is connected to the main control chip via the test socket.

3. The system as described in claim 1, characterized in that, The ARM processor is connected to the main control chip via a high-speed bus.

4. The system as described in claim 1, characterized in that, The testing system also includes: a host computer; The host computer is communicatively connected to the ARM processor; The host computer is used to receive the test results sent by the ARM processor and display the test results.

5. The system as described in claim 4, characterized in that, The host computer communicates with the ARM processor through a physical layer chip.

6. The system as described in claim 1, characterized in that, The ARM processor is a processor with two built-in ARM Cortex-R series real-time cores; The first core in the ARM processor is used to send test commands; The second core in the ARM processor is used to receive test response data.

7. The system as described in claim 1, characterized in that, The system also includes: a voltage and current detection chip; The detection terminal of the voltage and current detection chip is electrically connected to the test socket and is used to detect the voltage and current of the flash memory chip under test on the test socket when performing test operations. The output terminal of the voltage and current detection chip is communicatively connected to the ARM processor, and is used to send the voltage and the current to the ARM processor.

8. The system according to any one of claims 1-7, characterized in that, The system also includes a power module, which is electrically connected to the ARM processor, the main control chip, the voltage and current detection chip, and the test socket, respectively, and is used to supply power to the ARM processor, the main control chip, the voltage and current detection chip, and the flash memory chip under test on the test socket.

Images