Power overvoltage protection circuit, method and apparatus

Abstract

This application provides a power supply overvoltage protection circuit, method, and device. The circuit includes: a power management chip to be protected, an auxiliary power supply, a first switching circuit, a second switching circuit, and a third switching circuit. The input terminal of the first switching circuit is connected to the output terminal of the power management chip, and is used to generate a first detection signal based on the voltage output by the power management chip. The input terminal of the second switching circuit is connected to the output terminal of the first switching circuit, and the second switching circuit is powered by the auxiliary power supply. It is used to logically invert the first detection signal and generate a second detection signal. The input terminal of the third switching circuit is connected to the output terminal of the second switching circuit, and the output terminal of the third switching circuit is connected to the enable terminal of the power management chip, used to control the level state of the enable terminal based on the second detection signal. This circuit can achieve timely overvoltage detection and protection without relying on external monitoring.

Description

Technical Field

[0001] This application relates to the field of power management and power protection circuits, and more particularly to a power overvoltage protection circuit, method, and device. Background Technology

[0002] In high-performance electronic devices such as servers and switches, point-to-point power supply solutions typically employ voltage regulators and feedback voltage divider networks to regulate the load-side voltage.

[0003] However, existing solutions mostly rely on CPLDs (Complex Programmable Logic Devices) or microcontrollers to monitor anomalies based on power status signals, which can easily create detection blind spots before power-on initialization or when monitoring is not enabled; once the feedback line is open, the output voltage may quickly become unstable and cause overvoltage.

[0004] Therefore, improving the reliability of detection and protection against overvoltage caused by feedback line abnormalities when external monitoring is lacking or delayed has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides power supply overvoltage protection circuits, methods, and devices to solve the aforementioned technical problems. The power supply overvoltage protection circuit addresses the overvoltage risk caused by abnormal output of the power management chip, especially abnormal feedback lines. It constructs a voltage state detection and enable control mechanism independent of external monitoring units. Even in the absence of external monitoring, with delayed initialization, or under complex electromagnetic environments, it can still promptly identify the output state of the power management chip and trigger protection, thereby improving the real-time performance and reliability of overvoltage detection and protection.

[0006] In a first aspect, embodiments of this application provide a power overvoltage protection circuit, including: a power management chip to be protected, an auxiliary power supply, a first switching circuit, a second switching circuit, and a third switching circuit;

[0007] The input terminal of the first switching circuit is connected to the output terminal of the power management chip, and is used to generate a first detection signal based on the voltage output by the power management chip;

[0008] The input terminal of the second switching circuit is connected to the output terminal of the first switching circuit. The second switching circuit is powered by an auxiliary power supply and is used to logically invert the first detection signal and generate a second detection signal.

[0009] The input terminal of the third switching circuit is connected to the output terminal of the second switching circuit, and the output terminal of the third switching circuit is connected to the enable terminal of the power management chip, for controlling the level state of the enable terminal according to the second detection signal.

[0010] In one possible implementation, the first switching circuit includes a first resistor, a second resistor, and a first switching transistor;

[0011] The first resistor and the second resistor are connected in series between the output terminal of the power management chip and ground;

[0012] The connection node between the first resistor and the second resistor is connected to the control terminal of the first switching transistor.

[0013] The output terminal of the first switching transistor is grounded, and the input terminal of the first switching transistor is connected to the input terminal of the second switching circuit as the output terminal of the first switching circuit.

[0014] In one possible implementation, the second switching circuit includes a third resistor, a fourth resistor, and a second switching transistor;

[0015] The third resistor is connected between the auxiliary power supply and the control terminal of the second switching transistor;

[0016] The fourth resistor is connected between the auxiliary power supply and the input terminal of the second switching transistor, and the third resistor is connected in parallel with the fourth resistor;

[0017] The control terminal of the second switching transistor is connected to the input terminal of the first switching circuit;

[0018] The output terminal of the second switch is grounded, and the input terminal of the second switch is connected to the input terminal of the third switch circuit as the output terminal of the second switch circuit.

[0019] In one possible implementation, the third switching circuit includes a third switching transistor;

[0020] The control terminal of the third switch is connected to the output terminal of the second switch circuit.

[0021] The output terminal of the third switch is grounded, and the input terminal of the third switch is connected to the enable terminal of the power management chip.

[0022] In one possible implementation, the third switching circuit further includes a Zener diode;

[0023] The Zener diode is connected in reverse parallel between the enable terminal of the power management chip and ground to provide overvoltage clamping protection for the enable terminal.

[0024] In one possible implementation, the circuit further includes a feedback circuit;

[0025] The feedback circuit is connected between the output terminal of the power management chip, the feedback pin of the power management chip, and ground, and is used to perform voltage division sampling on the output voltage of the power management chip and provide a feedback signal to the power management chip.

[0026] In one possible implementation, the feedback circuit includes a fifth resistor and a sixth resistor;

[0027] The fifth resistor and the sixth resistor are connected in series between the output terminal of the power management chip and ground, and the connection node of the fifth resistor and the sixth resistor is connected to the feedback pin of the power management chip.

[0028] In one possible implementation, the feedback circuit further includes a seventh resistor;

[0029] The seventh resistor is connected in series with the fifth resistor and is connected between the output terminal of the power management chip and the feedback pin.

[0030] Secondly, embodiments of this application provide a power supply overvoltage protection method, applied to the power supply overvoltage protection circuit as described in the first aspect, the method comprising:

[0031] Detect the voltage output from the power management chip's output terminal;

[0032] A control signal is generated based on the voltage; the control signal indicates whether the enable terminal of the power management chip is enabled.

[0033] According to the control signal, the enable terminal level of the power management chip is adjusted to change the output state of the power management chip; the output state includes the output on state and the output off state of the power management chip.

[0034] In one possible implementation, generating a control signal based on the voltage includes:

[0035] Based on the first switching circuit in the power overvoltage protection circuit, the voltage is converted into a first detection signal; the first detection signal indicates whether an overvoltage has occurred at the output terminal of the power management chip.

[0036] Based on the second switching circuit in the power overvoltage protection circuit, the first detection signal is logically inverted to generate a second detection signal; the second detection signal represents a level state opposite to that of the first detection signal.

[0037] Based on the third switching circuit in the power overvoltage protection circuit, a control signal is generated according to the second detection signal.

[0038] In one possible implementation, a control signal is generated based on the second detection signal, including:

[0039] If the second detection signal is high, a low-level control signal is generated to cause the power management chip to enter the output shutdown state.

[0040] If the second detection signal is low, a high-level control signal is generated to keep the power management chip in the output on state.

[0041] Thirdly, embodiments of this application provide a power overvoltage protection device, including: a memory and a processor;

[0042] The memory stores computer-executed instructions;

[0043] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0044] The power overvoltage protection circuit, method, and device provided in this application, by connecting a first switching circuit to the output terminal of a power management chip to generate a first detection signal based on the output voltage, using a second switching circuit powered by an auxiliary power supply to logically invert the first detection signal and generate a second detection signal, and using a third switching circuit to control the level state of the enable terminal of the power management chip based on the second detection signal, can quickly complete abnormal detection and enable control directly based on the output state of the power management chip when an external monitoring unit is missing or has a delayed response. This can promptly suppress the spread of risk when an abnormality such as an open circuit in the feedback line causes an output overvoltage, thereby improving the safety and reliability of the power system operation. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0046] Figure 1 Schematic diagram of the power supply overvoltage protection circuit provided in this application Figure 1 ;

[0047] Figure 2 Schematic diagram of the power supply overvoltage protection circuit provided in this application Figure 2 ;

[0048] Figure 3 Schematic diagram of the power supply overvoltage protection circuit provided in this application Figure 3 ;

[0049] Figure 4 A flowchart illustrating the power supply overvoltage protection method provided in this application;

[0050] Figure 5A schematic diagram of the power supply overvoltage protection method and device provided in this application;

[0051] Figure 6 This is a schematic diagram of the power overvoltage protection device provided in this application.

[0052] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0053] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0054] In servers, network switches, industrial controllers and other high-performance electronic devices, power management systems are typically responsible for providing stable power and real-time regulation to core chips and their loads. Among these, voltage regulators and their feedback control networks are key components for ensuring output voltage accuracy and system safety.

[0055] In such scenarios, power management chips typically acquire the output voltage through a feedback line and combine it with an internal control loop to maintain the target voltage stability. The normal connection status of the feedback line directly affects whether the load-side voltage is within the controlled range.

[0056] Due to the complexity of the device startup sequence, the power supply often enters the working state before the main control logic. During this stage, the relevant monitoring modules may not have completed initialization or may not be enabled due to low power configuration, abnormal reset, or other reasons, causing the power system to operate without external real-time supervision.

[0057] For such high-reliability devices, feedback anomalies during power-up can not only affect the stability of individual power modules, but may also further impact processors, memory, and other critical components. Therefore, designing protection around the overvoltage risk caused by feedback circuit anomalies has become a common application scenario in the field of power management.

[0058] In existing technologies, to address the problem of output voltage runaway caused by abnormal feedback circuits, an external monitoring chip is typically used to determine the power supply status, and then the monitoring chip triggers shutdown protection based on a good power supply signal or an overvoltage signal.

[0059] Specifically, the voltage regulator sends the output voltage to the feedback terminal through a feedback voltage divider network to maintain closed-loop regulation; at the same time, the complex programmable logic device or microcontroller in the system reads the power status signal after power-on and controls the enable or shutdown control terminal to act when an abnormality is detected, so as to achieve overvoltage suppression.

[0060] This solution can respond to some power anomalies when the monitoring module is working properly and has been initialized, but it requires that the external monitoring logic must be started and remain online.

[0061] If the feedback line becomes open due to poor soldering, component aging, mechanical stress, or environmental interference, the output voltage may rise rapidly due to the energy release of the buck circuit itself and the imbalance of the control loop, even exceeding the safety threshold before the monitoring logic intervenes.

[0062] Since external monitoring modules often lag behind the power supply unit's startup, there is a natural overlap between their monitoring window and the fault occurrence window. Therefore, it is very easy to form a detection blind spot during this stage, resulting in slow protection action or even complete failure.

[0063] Meanwhile, the feedback line is usually located in a relatively sensitive analog detection channel, which is susceptible to electromagnetic interference, wiring coupling and transient noise. The monitoring module's judgment of its status may be jittery, misjudged or delayed, which further weakens the reliability of the protection strategy.

[0064] Furthermore, if the relevant nodes of the enable terminal are not configured with independent overvoltage isolation measures when the output voltage rises abnormally, a chain of damages such as pin breakdown and control link failure may occur, causing the fault to expand from a single feedback abnormality to damage to the entire power module and even downstream load devices.

[0065] It is evident that while existing protection methods relying on external monitoring signals are relatively simple in structure, they have significant limitations in the initial startup phase, when monitoring is not enabled, and in complex electromagnetic environments, making it difficult to meet the power safety and robustness requirements of high-performance equipment.

[0066] In view of this, how to achieve more timely and reliable detection and shutdown protection against overvoltage risks caused by abnormal feedback lines when external monitoring is lacking or lagging has become an urgent technical problem to be solved.

[0067] To address the aforementioned issues, and considering the operational characteristics of existing power management systems, an overvoltage protection circuit can be constructed. This circuit includes a power management chip to be protected, an auxiliary power supply, a first switching circuit, a second switching circuit, and a third switching circuit. The input of the first switching circuit is connected to the output of the power management chip, generating a first detection signal based on the voltage output by the power management chip. The input of the second switching circuit is connected to the output of the first switching circuit and is powered by the auxiliary power supply. It inverts the first detection signal logically to generate a second detection signal. The input of the third switching circuit is connected to the output of the second switching circuit, and its output is connected to the enable terminal of the power management chip, controlling the level of the enable terminal based on the second detection signal. Through this detection and control link formed by multiple cascaded switching circuits, an autonomous judgment mechanism can be established around the output state of the power management chip without relying on an external monitoring chip for continuous online operation. The enable terminal level can be directly adjusted based on the detection results, thereby promptly cutting off or suppressing the operation of the power management chip when the feedback line is abnormal, preventing the output voltage from continuing to rise and reducing the risk of damage to downstream devices. This technical approach is suitable for systems with high requirements for power supply stability and fault response speed, and provides a foundation for subsequent descriptions of specific circuit structures and operating processes.

[0068] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0069] Figure 1 Schematic diagram of the power supply overvoltage protection circuit provided in this application Figure 1 ,like Figure 1 As shown, the circuit includes:

[0070] Power management chip to be protected ( Figure 1 The circuit consists of a VR IC (power management chip), an auxiliary power supply, a first switching circuit, a second switching circuit, and a third switching circuit; the input terminal of the first switching circuit is connected to the output terminal of the power management chip. Figure 1 The input of the first switching circuit is connected to the output of the second switching circuit, which is powered by an auxiliary power supply. The second switching circuit is used to logically invert the first detection signal and generate the second detection signal. The input of the third switching circuit is connected to the output of the second switching circuit, and the output of the third switching circuit is connected to the enable terminal of the power management chip. Figure 1It is connected to the EN pin in the circuit and is used to control the level state of the enable terminal according to the second detection signal, thereby controlling the power supply to be turned off.

[0071] In practical applications, the first switching circuit can directly respond to the voltage change at the output terminal of the power management chip and generate a corresponding first detection signal. The second switching circuit relies on the auxiliary power supply to keep working, and outputs a second detection signal after logically inverting the first detection signal. The third switching circuit then directly changes the level of the enable terminal based on the second detection signal, thereby quickly limiting or shutting down the operation of the power management chip when the output rises abnormally.

[0072] Since the detection link goes directly from the output to the enable terminal, and the second switching circuit does not rely on the external monitoring module for initialization, an autonomous protection path can still be established in the early stage of startup or when external monitoring is missing. This allows overvoltage caused by feedback abnormalities to be suppressed in time, thereby reducing the risk of continuous output rise causing damage to downstream loads and control pins. Therefore, it helps to improve the safety, response speed and robustness of the power supply system.

[0073] Figure 2 Schematic diagram of the power supply overvoltage protection circuit provided in this application Figure 2 ,like Figure 2 As shown, in this embodiment... Figure 1 Based on the embodiments, the first switching circuit, the second switching circuit, and the third switching circuit will be described in detail.

[0074] like Figure 2 As shown, the first switching circuit includes a first resistor R1, a second resistor R2, and a first switching transistor Q1; the first resistor R1 and the second resistor R2 are connected in series between the output terminal (VOUT) of the power management chip and ground; the connection node of the first resistor R1 and the second resistor R2 is connected to the control terminal of the first switching transistor Q1; the output terminal of the first switching transistor Q1 is grounded, and the input terminal of the first switching transistor Q1 is connected to the input terminal of the second switching circuit as the output terminal of the first switching circuit.

[0075] The first switching transistor is an N-channel MOS transistor (N-channel metal-oxide-semiconductor effect transistor), with the gate (G) as the control terminal, the drain (D) as the input terminal, and the source (S) as the output terminal.

[0076] The first resistor R1 is the upper voltage divider resistor, used to limit the sampling voltage amplitude. The second resistor R2 is the lower voltage divider resistor, used to set the conduction threshold of the first switching transistor. By adjusting the resistance ratio of the first resistor R1 and the second resistor R2, the overvoltage protection trigger point can be flexibly set.

[0077] When the output voltage of the power management chip is normal, the voltage of the voltage divider node is lower than the conduction threshold of the first switch Q1, the first switch Q1 is in the off state, and the first switching circuit outputs a high level.

[0078] When the output voltage of the power management chip rises to the preset overvoltage threshold, the voltage of the voltage divider node reaches the turn-on voltage of the first switch Q1. The first switch Q1 turns on, pulling the output of the first switching circuit low and outputting a valid first detection signal, providing the trigger condition for the subsequent operation of the second switching circuit.

[0079] The first detection signal is a level signal used to characterize whether an overvoltage has occurred at the output of the power management chip. When the output voltage is normal, the first detection signal is high, indicating that no overvoltage has occurred. When the output voltage exceeds a preset overvoltage threshold, the first detection signal becomes low, indicating that an overvoltage has occurred. The first detection signal is directly input to the second switching circuit as the input basis for the second switching circuit to perform logic inversion processing.

[0080] like Figure 2 As shown, the second switching circuit includes a third resistor R3, a fourth resistor R4, and a second switching transistor Q2; the third resistor R3 is connected between the auxiliary power supply and the control terminal of the second switching transistor Q2; the fourth resistor R4 is connected between the auxiliary power supply and the input terminal of the second switching transistor Q2, and the third resistor R3 and the fourth resistor R4 are connected in parallel; the control terminal of the second switching transistor Q2 is connected to the input terminal of the first switching circuit; the output terminal of the second switching transistor Q2 is grounded, and the input terminal of the second switching transistor Q2 is connected to the input terminal of the third switching circuit as the output terminal of the second switching circuit.

[0081] Among them, the second switch Q2 is an N-channel MOSFET, with the gate G as the control terminal, the drain D as the input terminal, and the source S as the output terminal.

[0082] The third resistor R3 is a gate bias resistor, used to provide a stable power-on bias for the second switch Q2, and works with the first switching circuit to achieve level switching.

[0083] The fourth resistor R4 is a pull-up resistor, used to pull the output terminal to a high level when the second switch Q2 is turned off, so as to ensure the level integrity and driving capability of the second detection signal.

[0084] When the first detection signal is high, the second switch Q2 is turned on, the output of the second switching circuit is pulled low, and a low-level second detection signal is output.

[0085] When the first detection signal is low, the second switch Q2 is turned off, and the output of the second switching circuit is pulled up to a high level by the fourth resistor, thus outputting a high-level second detection signal.

[0086] The second detection signal is a level signal, which is obtained by logically inverting the first detection signal and is used to drive the operation of the subsequent third switching circuit.

[0087] The second detection signal is logically opposite to the first detection signal, and can convert the overvoltage state into an effective drive level suitable for the control enable terminal, ensuring reliable execution of the protection action.

[0088] like Figure 2 As shown, the third switching circuit includes a third switching transistor Q3; the control terminal of the third switching transistor Q3 is connected to the output terminal of the second switching circuit; the output terminal of the third switching transistor Q3 is grounded, and the input terminal of the third switching transistor Q3 is connected to the enable terminal EN of the power management chip.

[0089] Among them, the third switch Q3 is an N-channel MOSFET, with the gate G as the control terminal, the drain D as the input terminal, and the source S as the output terminal.

[0090] When the second detection signal is high, the third switch Q3 is turned on, pulling the enable pin of the power management chip low, causing the chip to enter the shutdown state and stop outputting.

[0091] When the second detection signal is low, the third switch Q3 is turned off, the enable terminal EN returns to the normal operating level, and the power management chip starts up and outputs normally.

[0092] The third switch Q3 directly controls the EN level of the enable terminal based on the second detection signal, without the need for software intervention or external monitoring modules, achieving pure hardware fast shutdown. It can still respond instantaneously in extreme scenarios such as feedback open circuit and output loss of control, avoiding overvoltage damage to downstream loads.

[0093] like Figure 2 As shown, the third switching circuit also includes a Zener diode D1; the Zener diode D1 is connected in reverse parallel between the enable terminal EN of the power management chip and ground, and is used to provide overvoltage clamping protection for the enable terminal EN to prevent transient high voltage, electrostatic interference or abnormal peak voltage from breaking down the enable pin.

[0094] When the voltage at the enable terminal EN exceeds the reverse breakdown voltage of the Zener diode D1, the Zener diode D1 turns on, clamping the voltage at the enable terminal EN within a safe voltage range and ensuring that the chip's control pins are not damaged.

[0095] During normal operation, Zener diode D1 is reverse-biased and does not affect the EN level of the enable terminal. When an abnormal high voltage occurs, Zener diode D1 immediately enters a breakdown clamping state, absorbing surge energy, protecting the enable terminal from damage, and improving the overall circuit's anti-interference capability and operational reliability in complex electromagnetic environments.

[0096] Figure 3 Schematic diagram of the power supply overvoltage protection circuit provided in this application Figure 3 ,like Figure 3 As shown, in this embodiment... Figure 2 Based on the embodiments, the feedback circuit will be described in detail.

[0097] like Figure 3 As shown, the power overvoltage protection circuit also includes a feedback circuit; the feedback circuit is connected between the output terminal of the power management chip, the feedback pin FB of the power management chip, and ground, and is used to perform voltage division sampling of the output voltage of the power management chip and provide a feedback signal to the power management chip.

[0098] The feedback circuit provides voltage sampling for the normal voltage regulation operation of the power management chip, enabling the chip to adjust the duty cycle in real time according to the output voltage to maintain a stable output voltage.

[0099] The feedback circuit is independent of the first, second, and third switching circuits and does not interfere with each other. Even if the feedback circuit experiences an open circuit, poor soldering, or component failure, the first, second, and third switching circuits can still operate normally independently, achieving rapid shutdown protection during output overvoltage and significantly improving the overall reliability and safety of the power supply system.

[0100] like Figure 3 As shown, the feedback circuit includes a fifth resistor R5 and a sixth resistor R6; the fifth resistor R5 and the sixth resistor R6 are connected in series between the output terminal of the power management chip and ground, and the connection node of the fifth resistor R5 and the sixth resistor R6 is connected to the feedback pin FB of the power management chip.

[0101] Among them, the fifth resistor R5 is the upper voltage divider resistor, with one end connected to the output terminal of the power management chip and the other end connected to the feedback pin FB. The sixth resistor R6 is the lower voltage divider resistor, with one end connected to the feedback pin FB and the other end grounded.

[0102] The fifth resistor R5 and the sixth resistor R6 form a voltage divider network, which divides the output voltage of the power management chip proportionally and sends it to the feedback pin FB. The power management chip adjusts the output according to the voltage value of the feedback pin FB to stabilize the output voltage at the target value.

[0103] The ratio of the resistance values ​​of the fifth resistor R5 to the sixth resistor R6 directly determines the output voltage of the power management chip. For example, when R5:R6 = 2:1, the output voltage = VFB × (1 + R5 / R6), where VFB is the feedback reference voltage (e.g., 0.6V). Increasing the value of R5 or decreasing the value of R6 increases the output voltage; conversely, decreasing R5 or increasing R6 decreases the output voltage. By adjusting the ratio of the fifth resistor R5 to the sixth resistor R6, the power management chip can flexibly adapt to the power supply requirements of different loads, while the dynamic adjustment of the voltage divider network optimizes the stability and response speed of the output voltage.

[0104] The feedback signal is a DC level signal after voltage division, which is used to characterize the real-time magnitude of the output voltage of the power management chip and is the core basis for the chip to achieve closed-loop voltage regulation.

[0105] like Figure 3 As shown, the feedback circuit also includes a seventh resistor R7; the seventh resistor R7 is connected in series with the fifth resistor R5 and is connected between the output terminal of the power management chip and the feedback pin FB.

[0106] The seventh resistor R7 is a series adjustable resistor, which, together with the fifth resistor R5 and the sixth resistor R6, forms a three-stage voltage divider structure. This structure is used to further finely adjust the feedback voltage division ratio, improve the output voltage setting accuracy, and at the same time improve the stability and dynamic response speed of the feedback loop, suppressing output voltage ripple and overshoot.

[0107] The seventh resistor R7 and the fifth resistor R5 are connected in series to form the upper voltage divider branch, together with the sixth resistor R6, forming a complete voltage divider network. By changing the value of the seventh resistor R7, the output voltage of the power management chip can be fine-tuned without significantly altering the fifth resistor R5 and the sixth resistor R6. For example, when a lower output voltage is needed, the value of the seventh resistor R7 can be increased, thereby reducing the overall voltage division ratio of the voltage divider network; conversely, when a higher output voltage is needed, the value of the seventh resistor R7 can be decreased. This design improves the flexibility and adaptability of circuit design, meeting the output voltage accuracy requirements of different loads.

[0108] The following section will further explain the power supply overvoltage protection circuit in four application scenarios.

[0109] When the power management chip starts up normally, and the fifth resistor R5 and the sixth resistor R6 in the feedback circuit are connected normally, the power management chip maintains the output voltage at the target value (such as 3.3V) according to the feedback signal.

[0110] At this time, the voltage at the voltage divider node between the first resistor R1 and the second resistor R2 in the first switching circuit Q1 is lower than the conduction threshold of the first switching transistor Q1, so the first switching transistor Q1 remains off, and the first detection signal is high. The second switching transistor Q2 is turned on under the high-level drive, and the second detection signal is low. The third switching transistor Q3 remains off, the enable terminal EN of the power management chip remains high, the power management chip maintains normal output, and the entire circuit is in a stable operating state.

[0111] When the fifth resistor R5 in the feedback circuit fails and becomes open, while the sixth resistor R6 remains normal, the feedback pin FB of the power management chip loses its normal sampling signal, and the output voltage rises uncontrollably, approaching the input voltage and entering an overvoltage state.

[0112] When the output voltage rises to a preset overvoltage threshold (e.g., 5V), the voltage at the voltage divider node of the first switching circuit reaches the turn-on voltage of the first switching transistor Q1, causing Q1 to turn on and output a low-level first detection signal. The second switching transistor Q2 is turned off because its gate is pulled low, outputting a high-level second detection signal. The third switching transistor then turns on, pulling the enable pin of the power management chip low. The power management chip immediately shuts off its output, achieving overvoltage protection and preventing damage to the power chip and subsequent loads.

[0113] When the sixth resistor R6 in the feedback circuit fails and becomes open, while the fifth resistor R5 remains normal, the voltage at the feedback pin FB of the power management chip increases, and the output voltage is pulled to near the feedback reference voltage (such as 0.6V / 0.8V), which is abnormally low.

[0114] At this time, the voltage at the voltage divider node of the first switching circuit is lower than the conduction threshold of the first switching transistor Q1, so Q1 remains off, and the first detection signal is high. The second switching transistor Q2 is on, and the second detection signal is low. The third switching transistor Q3 remains off, its enable terminal remains high, and the power management chip remains on, but the output voltage is abnormal, and the overvoltage protection action is not triggered.

[0115] When both the fifth resistor R5 and the sixth resistor R6 in the feedback circuit fail and become open, the power management chip completely loses closed-loop control, and the output voltage rises rapidly and uncontrollably, entering a severe overvoltage state.

[0116] When the output voltage reaches the overvoltage threshold, the first switch Q1 turns on, outputting a low-level first detection signal. The second switch Q2 turns off, outputting a high-level second detection signal. The third switch Q3 turns on, pulling the enable pin low, and the power management chip quickly shuts down, achieving overvoltage protection and preventing the chip and subsequent loads from being damaged by high voltage.

[0117] Figure 4 This is a flowchart illustrating the power supply overvoltage protection method provided in this application, as shown below. Figure 4 As shown, the method is applied to the power supply overvoltage protection circuit in the above embodiments, and the method includes:

[0118] S401, Detect the voltage output by the power management chip.

[0119] For example, the output voltage of the power management chip is sampled and detected in real time through a first switching circuit. The input terminal of the first switching circuit is connected to the output terminal of the power management chip to monitor the output voltage of the power management chip in real time.

[0120] S402. Generate a control signal based on the voltage; the control signal indicates whether the enable terminal of the power management chip is enabled.

[0121] For example, the power overvoltage protection circuit compares the voltage with a preset protection threshold and generates a control signal based on the comparison result. The control signal indicates whether to enable the power management chip's enable pin. That is, when the voltage is greater than the preset protection threshold, the power supply needs to be cut off, so the power management chip's enable pin is not enabled, causing the power management chip to stop working and thus protecting the downstream devices; when the voltage is less than or equal to the protection threshold, the power supply does not need to be cut off, so the power management chip's enable pin is enabled, causing the power management chip to continue working.

[0122] In some specific implementations, the above-mentioned generation of control signals based on voltage includes:

[0123] Based on the first switching circuit in the power overvoltage protection circuit, the voltage is converted into a first detection signal; the first detection signal indicates whether an overvoltage has occurred at the output terminal of the power management chip; based on the second switching circuit in the power overvoltage protection circuit, the first detection signal is logically inverted to generate a second detection signal; the second detection signal indicates a level state opposite to the first detection signal; based on the third switching circuit in the power overvoltage protection circuit, a control signal is generated according to the second detection signal.

[0124] For example, the first switching circuit includes a first switching transistor. By controlling the on and off of the first switching transistor, the analog quantity of the output voltage can be converted into a first detection signal in digital level form, thereby intuitively reflecting whether an overvoltage state has been entered.

[0125] In the specific implementation process, the output voltage is input to the gate of the first switching transistor. By comparing the gate voltage corresponding to the output voltage with the conduction threshold of the first switching transistor, it is determined whether the output voltage is in an overvoltage state. When the output voltage exceeds the preset protection threshold, the gate voltage is greater than the conduction threshold, which is determined to be an overvoltage state. The first switching transistor is turned on, and the first switching circuit outputs a low-level first detection signal. Otherwise, it is a normal state, the first switching transistor is turned off, and the first switching circuit outputs a high-level first detection signal.

[0126] The second switching circuit includes a second switching transistor. By controlling the conduction and cutoff of the second switching transistor, the level of the first detection signal can be flipped and the logic inverted, thereby adapting to the driving requirements of the subsequent third switching circuit.

[0127] The input terminal of the second switching circuit is connected to the output terminal of the first switching circuit to receive the first detection signal. The second switching circuit performs logic inversion on the first detection signal. When the first detection signal is low, the second switching transistor is cut off, thereby flipping the low-level first detection signal to a high level; when the first detection signal is high, the second switching transistor is turned on, thereby flipping the high-level first detection signal to a low level.

[0128] The third switching circuit includes a third switching transistor. By controlling the conduction and cutoff of the third switching transistor, the level of the enable terminal can be directly pulled low or maintained at a high level, thereby realizing direct hardware-level control of the power management chip.

[0129] Specifically, if the second detection signal is high, a low-level control signal is generated to cause the power management chip to enter the output shutdown state; if the second detection signal is low, a high-level control signal is generated to cause the power management chip to maintain the output on state.

[0130] For example, the input terminal of the third switching circuit is connected to the output terminal of the second switching circuit to receive the second detection signal. When the second detection signal is low, the third switching transistor is turned off, generating a high-level control signal. This high-level control signal maintains the high level of the enable terminal, ensuring the power management chip remains in the output on state. When the second detection signal is high, the third switching transistor is turned on, generating a low-level control signal. This low-level control signal pulls down the level of the enable terminal, causing the power management chip to enter the output off state, thereby protecting the downstream devices of the power management chip.

[0131] S403. Adjust the enable pin level of the power management chip according to the control signal to change the output state of the power management chip; the output state includes the output on state and output off state of the power management chip.

[0132] For example, when the control signal is high, the enable pin of the power management chip is pulled high externally, and the chip maintains the output on state and supplies power normally.

[0133] When the control signal is low, the enable pin is directly pulled low, and the power management chip immediately enters the output shutdown state, stopping the voltage output and realizing hardware-level fast overvoltage protection.

[0134] The power supply overvoltage protection method provided in this application embodiment detects the output voltage in real time through pure hardware. A two-stage switching circuit performs level sampling and logic inversion to generate a control signal characterizing the overvoltage state. Finally, the overvoltage protection is achieved by directly forcibly pulling down the enable terminal by controlling the switching transistor. The entire process requires no external monitoring unit, no software intervention, and no initialization timing dependency. It can respond instantaneously in scenarios such as open feedback resistors and output runaway, fundamentally solving the problems of protection lag and detection blind spots in traditional solutions.

[0135] Figure 5 This is a schematic diagram of the power supply overvoltage protection method and device provided in this application, as shown below. Figure 5 As shown, the power overvoltage protection method device 50 provided in this embodiment includes:

[0136] The detection module 501 is used to detect the voltage output by the output terminal of the power management chip;

[0137] The generation module 502 is used to generate a control signal based on the voltage; the control signal indicates whether the enable terminal of the power management chip is enabled.

[0138] The adjustment module 503 is used to adjust the enable terminal level of the power management chip according to the control signal, so as to change the output state of the power management chip; the output state includes the output on state and the output off state of the power management chip.

[0139] In one possible implementation, the generation module 502 is further configured to:

[0140] Based on the first switching circuit in the power overvoltage protection circuit, the voltage is converted into a first detection signal; the first detection signal indicates whether an overvoltage has occurred at the output of the power management chip.

[0141] Based on the second switching circuit in the power overvoltage protection circuit, the first detection signal is logically inverted to generate a second detection signal; the second detection signal represents a level state opposite to that of the first detection signal.

[0142] Based on the third switching circuit in the power overvoltage protection circuit, a control signal is generated according to the second detection signal.

[0143] In one possible implementation, the generation module 502 is further configured to:

[0144] If the second detection signal is high, a low-level control signal is generated to cause the power management chip to enter the output shutdown state.

[0145] If the second detection signal is low, a high-level control signal is generated to keep the power management chip in the output on state.

[0146] The power overvoltage protection method and device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0147] Figure 6 This is a structural schematic diagram of the power supply overvoltage protection device provided in this application. Figure 6 As shown, the power overvoltage protection device 60 provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the power overvoltage protection device 60 further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus.

[0148] In a specific implementation, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to perform the above-described method.

[0149] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0150] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0151] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0152] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0153] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0154] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0155] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0156] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0157] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0158] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0159] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0160] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0161] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0162] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A power supply overvoltage protection circuit, characterized in that, include: The power management chip to be protected, the auxiliary power supply, the first switching circuit, the second switching circuit, and the third switching circuit; The input terminal of the first switching circuit is connected to the output terminal of the power management chip, and is used to generate a first detection signal based on the voltage output by the power management chip; The input terminal of the second switching circuit is connected to the output terminal of the first switching circuit. The second switching circuit is powered by an auxiliary power supply and is used to logically invert the first detection signal and generate a second detection signal. The input terminal of the third switching circuit is connected to the output terminal of the second switching circuit, and the output terminal of the third switching circuit is connected to the enable terminal of the power management chip, for controlling the level state of the enable terminal according to the second detection signal.

2. The circuit according to claim 1, characterized in that, The first switching circuit includes a first resistor, a second resistor, and a first switching transistor; The first resistor and the second resistor are connected in series between the output terminal of the power management chip and ground; The connection node between the first resistor and the second resistor is connected to the control terminal of the first switching transistor. The output terminal of the first switching transistor is grounded, and the input terminal of the first switching transistor is connected to the input terminal of the second switching circuit as the output terminal of the first switching circuit.

3. The circuit according to claim 1, characterized in that, The second switching circuit includes a third resistor, a fourth resistor, and a second switching transistor; The third resistor is connected between the auxiliary power supply and the control terminal of the second switching transistor; The fourth resistor is connected between the auxiliary power supply and the input terminal of the second switching transistor, and the third resistor is connected in parallel with the fourth resistor; The control terminal of the second switching transistor is connected to the input terminal of the first switching circuit; The output terminal of the second switch is grounded, and the input terminal of the second switch is connected to the input terminal of the third switch circuit as the output terminal of the second switch circuit.

4. The circuit according to claim 1, characterized in that, The third switching circuit includes a third switching transistor; The control terminal of the third switch is connected to the output terminal of the second switch circuit. The output terminal of the third switch is grounded, and the input terminal of the third switch is connected to the enable terminal of the power management chip.

5. The circuit according to claim 4, characterized in that, The third switching circuit also includes a Zener diode; The Zener diode is connected in reverse parallel between the enable terminal of the power management chip and ground to provide overvoltage clamping protection for the enable terminal.

6. The circuit according to any one of claims 1-5, characterized in that, The circuit also includes a feedback circuit; The feedback circuit is connected between the output terminal of the power management chip, the feedback pin of the power management chip, and ground, and is used to perform voltage division sampling on the output voltage of the power management chip and provide a feedback signal to the power management chip.

7. The circuit according to claim 6, characterized in that, The feedback circuit includes a fifth resistor and a sixth resistor; The fifth resistor and the sixth resistor are connected in series between the output terminal of the power management chip and ground, and the connection node of the fifth resistor and the sixth resistor is connected to the feedback pin of the power management chip.

8. The circuit according to claim 7, characterized in that, The feedback circuit also includes a seventh resistor; The seventh resistor is connected in series with the fifth resistor and is connected between the output terminal of the power management chip and the feedback pin.

9. A power supply overvoltage protection method, characterized in that, The method, applied to a power supply overvoltage protection circuit as described in any one of claims 1-8, comprises: Detect the voltage output from the power management chip's output terminal; A control signal is generated based on the voltage; the control signal indicates whether the enable terminal of the power management chip is enabled. According to the control signal, the enable terminal level of the power management chip is adjusted to change the output state of the power management chip; the output state includes the output on state and the output off state of the power management chip.

10. The method according to claim 9, characterized in that, Based on the voltage, a control signal is generated, including: Based on the first switching circuit in the power overvoltage protection circuit, the voltage is converted into a first detection signal; the first detection signal indicates whether an overvoltage has occurred at the output terminal of the power management chip. Based on the second switching circuit in the power overvoltage protection circuit, the first detection signal is logically inverted to generate a second detection signal; the second detection signal represents a level state opposite to that of the first detection signal. Based on the third switching circuit in the power overvoltage protection circuit, a control signal is generated according to the second detection signal.

11. The method according to claim 10, characterized in that, Based on the second detection signal, a control signal is generated, including: If the second detection signal is high, a low-level control signal is generated to cause the power management chip to enter the output shutdown state. If the second detection signal is low, a high-level control signal is generated to keep the power management chip in the output on state.

12. A power supply overvoltage protection device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in claims 9-11.

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