Analog-digital conversion device and analog-digital conversion method
By introducing negatively correlated first and second slope signal generators into the analog-to-digital converter, the delay problem of the time-interleaved slope analog-to-digital converter is solved, and a faster conversion time is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
AI Technical Summary
Existing time-interleaved slope analog-to-digital converters suffer from operational latency issues.
An analog-to-digital converter is used, which includes a first slope signal generator and a second slope signal generator. The conversion efficiency is improved by using negatively correlated slope signals, and an output signal is generated by a comparator.
The operational latency of analog-to-digital conversion has been reduced, and the conversion time has been shortened to less than half of the maintenance period.
Smart Images
Figure CN122247422A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to analog-to-digital conversion apparatus and methods, and more particularly to analog-to-digital conversion apparatus and methods that can reduce operation delays. Background Technology
[0002] Analog-to-digital converters (ADCs) are commonly used in electronic devices to convert analog signals into digital signals that the devices can process. A time-interleaved slope ADC is one type of ADC. However, due to the limitations of its operating conditions, the operation of a time-interleaved slope ADC is somewhat delayed. Summary of the Invention
[0003] In view of the shortcomings of the prior art, one of the objectives of this disclosure is (but not limited to) to provide an analog-to-digital conversion apparatus and an analog-to-digital conversion method to improve the shortcomings of the prior art.
[0004] In some embodiments, the analog-to-digital converter includes a first slope signal generator, a second slope signal generator, and a comparator. The first slope signal generator generates a first slope signal, wherein the first slope signal rises and falls within a voltage range at least with a first slope. The second slope signal generator generates a second slope signal, wherein the second slope signal rises and falls within a voltage range at least with a second slope, and the at least first slope is negatively correlated with the at least second slope. The comparator generates an output signal based on the first slope signal, the second slope signal, and the input signal.
[0005] In some embodiments, the analog-to-digital conversion method includes: generating a first slope signal via a first slope signal generator, wherein the first slope signal rises and falls back and forth in a voltage range with at least a first slope; generating a second slope signal via a second slope signal generator, wherein the second slope signal rises and falls back and forth in a voltage range with at least a second slope, and the at least one first slope is negatively correlated with the at least one second slope; and generating an output signal via a comparator based on the first slope signal, the second slope signal, and an input signal.
[0006] The technical means embodied in the embodiments of this disclosure can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion apparatus and analog-to-digital conversion method of this disclosure can reduce operation delay.
[0007] The features, implementation, and technical effects of this disclosure are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0008] Figure 1This is a schematic diagram of an analog-to-digital converter according to some embodiments of the present disclosure;
[0009] Figure 2 A flowchart illustrating an analog-to-digital conversion method according to some embodiments of this disclosure; and
[0010] Figure 3 This is a timing diagram of an analog-to-digital converter according to some embodiments of the present disclosure.
[0011] Symbol Explanation
[0012] 100: Analog-to-digital converter
[0013] 110: First slope signal generator
[0014] 120: Second slope signal generator
[0015] 130: Comparator
[0016] 140: Digital Logic Processor
[0017] 200: Method
[0018] 210-230: Steps
[0019] Cs3: Capacitor
[0020] cmp1, cmp2, cmpN: Output signals
[0021] cmp1X, cmp2X, cmpNX: Output signals
[0022] DFF1, DFF1X: Flip-flops (reactive switches)
[0023] D1[3:0]: Data signal
[0024] D1~DN: Data signals
[0025] Dout: Data signal
[0026] Dcnt[3:0], Dcntx[3:0]: Count values
[0027] GND: Grounding voltage
[0028] Out1: First output terminal
[0029] Out2: Second output terminal
[0030] P1~P6, Phol: Points
[0031] SW1: First switch
[0032] SW2: Second switch
[0033] SW3: Third switch
[0034] SW4: Fourth Switch
[0035] Scon1: First control signal
[0036] Scon2: Second control signal
[0037] Sre1: First reset signal
[0038] Sre2: Second reset signal
[0039] T1~T3: Period
[0040] T11: Period
[0041] T12: Period
[0042] Vslope1: First slope signal
[0043] Vslope2: Second slope signal
[0044] Vi,1, Vi,2, Vi,N, Vi,p, Vi,n: input signal
[0045] VDD: Power supply voltage
[0046] I: Current source current
[0047] V1, V2: Voltage levels
[0048] Vr: Voltage range Detailed Implementation
[0049] All terms used herein have their ordinary meanings. The definitions of the terms above in commonly used dictionaries, and the examples of any term used in this disclosure, are merely illustrative and should not be construed as limiting the scope or meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.
[0050] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, “circuit” can refer to a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.
[0051] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, third, etc., are used herein to describe and identify individual elements. Therefore, a first element herein may also be referred to as a second element without departing from the intent of this disclosure. For ease of understanding, similar elements in the figures will be designated with the same reference numerals.
[0052] To address the operational delay issue in existing time-interleaved slope analog-to-digital converters (ADCs), this disclosure proposes an analog-to-digital conversion apparatus and an analog-to-digital conversion method, detailed below.
[0053] Figure 1 This is a schematic diagram of an analog-to-digital converter 100 according to some embodiments of the present disclosure. As shown, the analog-to-digital converter 100 includes a first slope signal generator 110, a second slope signal generator 120, a comparator 130, a capacitor Cs3, flip-flops DFF1 and DFF1X, and a digital logic processor 140.
[0054] In some embodiments, the analog-to-digital converter 100 may be, but is not limited to, a time-interlaced slope analog-to-digital converter, the operation of which is described below. The analog-to-digital converter 100 may sample the input signal using capacitor Cs3, and then comparator 130 compares the sampled signal with the first slope signal Vslope1 and the second slope signal Vslope2 generated by the first slope signal generator 110 and the second slope signal generator 120. Before comparator 130 generates a comparison result, the counter value Dcnt[3:0] continues to count until comparator 130 generates a comparison result. When the positive terminal (positive pole) of comparator 130 is greater than the negative terminal (negative pole), the output signal cmpN generated by comparator 130 changes from negative to positive. The rising edge of the output signal cmpN changing from negative to positive will trigger the flip-flop (such as flip-flop DFF1, flip-flop DFF1X). The flip-flop will store the current result of the count (such as Dcnt[3:0], Dcntx[3:0]) and send it to the digital logic processor 140. After processing by the digital logic processor 140, the data signal D1[3:0] is generated. As described above, the analog-to-digital converter 100 completes one conversion process.
[0055] To illustrate how the analog-to-digital converter 100 of this disclosure reduces operating latency, please also refer to... Figure 2 and Figure 3 , Figure 2 A flowchart illustrating an analog-to-digital conversion method 200 is provided based on some embodiments of this disclosure. Figure 3A timing diagram of an analog-to-digital converter 100 is provided according to some embodiments of this disclosure.
[0056] Please see Figure 2 Step 210 involves generating a first slope signal using a first slope signal generator, wherein the first slope signal rises and falls back and forth within a voltage range with at least a first slope. For example, please refer to... Figure 1 , Figure 3 The first slope signal generator 110 generates a first slope signal Vslope1. This first slope signal Vslope1 rises with one slope and falls with another slope in the voltage range Vr to complete one round of rise and fall, and the first slope signal Vslope1 rises and falls back and forth in the voltage range Vr repeatedly.
[0057] Please see Figure 2 Step 220 involves generating a second slope signal using a second slope signal generator. The second slope signal rises and falls within a voltage range with at least one second slope, and at least one first slope is negatively correlated with at least one second slope. For example, please refer to... Figure 1 , Figure 3 The second slope signal generator 120 generates a second slope signal Vslope2. This second slope signal Vslope2 rises with one slope and falls with another slope within the voltage range Vr, completing one round trip. The second slope signal Vslope2 repeatedly rises and falls within the voltage range Vr. As shown in the figure, the slope of the first slope signal Vslope1 is negatively correlated with the slope of the second slope signal Vslope2.
[0058] Please see Figure 2 Step 230 involves using a comparator to generate an output signal based on the first slope signal, the second slope signal, and the input signal. For example, please refer to... Figure 1 , Figure 3 Taking the input signal Vi,1 as an example, the comparator 130 generates output signals cmp1 and com1X based on the first slope signal Vslope1, the second slope signal Vslope2 and the input signal Vi,1.
[0059] In detail, please refer to period T3. At point P4, comparator 130 generates output signal com1X based on the second slope signal Vslope2 and input signal Vi,1. At this time, the digital output will output the counting result of Dcntx[3:0]. As can be seen from the figure, after the analog-to-digital converter 100 of this disclosure adds the second slope signal Vslope2, the point P4 where the output signal is generated is located before the time point Phol, and the time point Phol is located at half of the maintenance period (Thold / 2). In addition, if the analog-to-digital converter 100 of this disclosure only uses the first slope signal Vslope1, then the point P5 where the output signal is generated is located after the time point Phol. This proves that the conversion time of this disclosure is shortened, less than half of the maintenance period (Thold / 2).
[0060] Therefore, compared to using only a single slope signal, the analog-to-digital converter 100 of this disclosure uses two slope signals (such as the first slope signal Vslope1 and the second slope signal Vslope2), which can shorten the conversion time of this disclosure to less than half of the holding period (Thold / 2). In other words, the operation latency of this disclosure is shortened to less than half of the holding period (Thold / 2).
[0061] Some embodiments of this disclosure will be described one by one below. However, this disclosure is not limited to the embodiments described below. The embodiments described below are only used to introduce the technical concepts of this disclosure so that this disclosure can be easily understood.
[0062] Referring to period T1, after the analog-to-digital converter 100 of this disclosure adds the second slope signal Vslope2, the point P1 where the output signal is generated is earlier than the point P2 where only the first slope signal Vslope1 is used. Furthermore, referring to period T2, at point P3, the comparator 130 can generate the output signal com1 based on the first slope signal Vslope1 and the input signal Vi,1. At this time, the digital output will output the counting result of Dcnt[3:0].
[0063] In some embodiments, when at least one first slope of the first slope signal Vslope1 is positive, at least one second slope of the second slope signal Vslope2 is negative. When at least one first slope of the first slope signal Vslope1 is negative, at least one second slope of the second slope signal Vslope2 is positive. For example, during the first period T11, the slope of the first slope signal Vslope1 is positive, and the slope of the second slope signal Vslope2 is negative. During the first period T12, the slope of the first slope signal Vslope1 is negative, and the slope of the second slope signal Vslope2 is positive.
[0064] In some embodiments, the voltage range Vr includes a low voltage level V1 and a high voltage level V2, and at least one first slope of the first slope signal Vslope1 includes a first positive slope and a first negative slope. The first slope signal Vslope1 rises from the low voltage level V1 to the high voltage level V2 with a first positive slope during a first period T11, and then falls from the high voltage level V2 to the low voltage level V1 with a first negative slope during a second period T12.
[0065] In some embodiments, at least one second slope Vslope2 of the second slope signal Vslope2 includes a second positive slope and a second negative slope. The second slope signal Vslope2 drops from a high voltage level V2 to a low voltage level V1 with a second negative slope during a first period T11, and then rises from a low voltage level V1 to a high voltage level V2 with a second positive slope during a second period T12.
[0066] In some embodiments, comparator 130 generates an output signal based on the rising period of a first slope signal Vslope1 and the input signal. In some embodiments, comparator 130 generates an output signal based on the falling period of a second slope signal Vslope2 and the input signal.
[0067] In some embodiments, please refer to Figure 1 The first slope signal generator 110 includes a first output terminal Out1, a first switch SW1, and a second switch SW2. The first switch SW1 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the first switch SW1 is used to receive a current source current I. The second terminal (as shown below) of the first switch SW1 is coupled to the first output terminal Out1. The second switch SW2 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the second switch SW2 is coupled to the first output terminal Out1. The second terminal (as shown below) of the second switch SW2 is used to receive... Figure 3 The low voltage level V1 is shown. First switch SW1 and second switch SW2 output a first slope signal Vslope1 based on the first control signal Scon1 and the first reset signal Sre1. For example, when the first control signal Scon1 is high, the first slope signal Vslope1 gradually increases... Figure 3 The high voltage level V2 is shown to charge. When the first reset signal Sre1 is high, the first slope signal Vslope1 is reset to the low voltage level V1.
[0068] In some embodiments, please refer to Figure 1The second slope signal generator 120 includes a second output terminal Out2, a third switch SW3, and a fourth switch SW4. The third switch SW3 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the third switch SW3 receives... Figure 3 The high voltage level V2 is shown. The second terminal (as shown below) of the third switch SW3 is coupled to the second output terminal Out2. The fourth switch SW4 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the fourth switch SW4 is coupled to the second output terminal Out2. The second terminal (as shown below) of the fourth switch SW4 is used to receive the current source current I. The third switch SW3 and the fourth switch SW4 output the second slope signal Vslope2 according to the second control signal Scon2 and the second reset signal Sre2. For example, when the second control signal Scon2 is high, the second slope signal Vslope2 slowly slopes towards... Figure 3 The low voltage level V1 is discharged. When the second reset signal Sre2 is high, the second slope signal Vslope2 is reset to... Figure 3 The high voltage level V2 is shown.
[0069] In some embodiments, the first switch SW1 and the fourth switch SW4 output a first slope signal Vslope1 and a second slope signal Vslope2 respectively based on a first control signal Scon1 and a second control signal Scon2; or the second switch SW2 and the third switch SW3 output the first slope signal Vslope1 and the second slope signal Vslope2 respectively based on a first reset signal Sre1 and a second reset signal Sre2. In another embodiment, please refer to... Figure 1 The control signals and reset signals can be divided into two groups. For example, the first control signal Scon1 and the first reset signal Sre1 can be one group, and the second control signal Scon2 and the second reset signal Sre2 can be one group. The phases of the first control signal Scon1 and the first reset signal Sre1 can be different from the phases of the second control signal Scon2 and the second reset signal Sre2. In some embodiments, please refer to... Figure 1 The capacitor Cs3 disclosed herein is not limited to two; other suitable quantities may be used depending on actual needs.
[0070] It should be noted that this disclosure does not imply... Figures 1 to 3 The embodiments shown are limited and are merely illustrative of one implementation of this disclosure to facilitate understanding of the technology. The scope of this disclosure is defined by the claims. Modifications and refinements made by those skilled in the art to the embodiments of this disclosure without departing from the concept of this disclosure still fall within the scope of the claims.
[0071] In summary, the technical means embodied in the embodiments of this disclosure can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion apparatus and analog-to-digital conversion method of this disclosure can reduce operation delay.
[0072] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its express or implied content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the claims of this specification.
Claims
1. An analog-to-digital converter, comprising: A first slope signal generator is used to generate a first slope signal, wherein the first slope signal rises and falls back and forth in a voltage range with at least a first slope. A second slope signal generator is configured to generate a second slope signal, wherein the second slope signal rises and falls within the voltage range with at least a second slope, and the at least one first slope is negatively correlated with the at least one second slope; and A comparator is used to generate an output signal based on the first slope signal, the second slope signal, and an input signal.
2. The analog-to-digital converter of claim 1, wherein when the at least one first slope is positive, the at least one second slope is negative.
3. The analog-to-digital converter of claim 1, wherein when the at least one first slope is negative, the at least one second slope is positive.
4. The analog-to-digital converter of claim 1, wherein the voltage range includes a low voltage level and a high voltage level, and the at least one first slope includes a first positive slope and a first negative slope, wherein the first slope signal is raised from the low voltage level to the high voltage level with the first positive slope in a first period, and then drops from the high voltage level to the low voltage level with the first negative slope in a second period.
5. The analog-to-digital converter of claim 4, wherein the at least one second slope includes a second positive slope and a second negative slope, wherein the second slope signal decreases from the high voltage level to the low voltage level with the second negative slope during the first period, and then increases from the low voltage level to the high voltage level with the second positive slope during the second period.
6. The analog-to-digital converter of claim 1, wherein the comparator generates the output signal based on a rise period of the first slope signal and the input signal.
7. The analog-to-digital converter of claim 6, wherein the comparator generates the output signal based on a falling period of the second slope signal and the input signal.
8. The analog-to-digital conversion apparatus of claim 5, wherein the first slope signal generator comprises: First output terminal; A first switch, comprising: One terminal is used to receive current from a current source; and A second terminal, coupled to the first output terminal; and A second switch, comprising: A first terminal, coupled to the first output terminal; and The second terminal is used to receive the low voltage level; The first switch and the second switch output the first slope signal according to a first control signal and a first reset signal.
9. The analog-to-digital conversion apparatus of claim 8, wherein the second slope signal generator comprises: A second output terminal; A third switch, comprising: One terminal is used to receive the high voltage level; and A second terminal, coupled to the second output terminal; and A fourth switch, comprising: A first terminal is coupled to the second output terminal; and The second terminal is used to receive the current from the current source; The third switch and the fourth switch output the second slope signal according to a second control signal and a second reset signal.
10. An analog-to-digital conversion method, comprising: A first slope signal is generated by a first slope signal generator, wherein the first slope signal rises and falls back and forth in a voltage range with at least a first slope. A second slope signal is generated by a second slope signal generator, wherein the second slope signal rises and falls within the voltage range with at least a second slope, and the at least one first slope is negatively correlated with the at least one second slope; and A comparator generates an output signal based on the first slope signal, the second slope signal, and an input signal.