Nanowire array and method of making the same, semiconductor device

Abstract

This invention relates to a nanowire array, its fabrication method, and a semiconductor device. The fabrication method of the nanowire array includes: providing a heterostructure; forming multiple grooves on two opposing sidewalls of the heterostructure along a first direction; performing a deposition process on the heterostructure to form an amorphous precursor layer covering the sidewalls of the heterostructure and filling the grooves; performing an etching process on the heterostructure to remove the amorphous precursor layer covering the sidewalls of the heterostructure; sequentially and repeatedly performing the deposition and etching processes until the amorphous precursor layer completely fills the grooves; and performing a crystallization process on the heterostructure to crystallize the amorphous precursor layer located in the grooves, forming a nanowire array. In this way, nanowires can be grown at specified locations and directions, achieving precise control over the size, position, and growth direction of the nanowires.

Description

[0001] This application claims priority to Chinese Patent Application No. 2025114292840, filed on November 27, 2025, entitled “Nanowire Array and Preparation Method Thereof, Semiconductor Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of nanowire technology, and in particular to a nanowire array, its fabrication method, and a semiconductor device. Background Technology

[0003] With the continuous increase in the integration density of semiconductor devices and the further miniaturization of their size, semiconductor nanowires have become key structural units for next-generation micro-nano logic, sensing, and display applications.

[0004] In related technologies, semiconductor nanowires can be fabricated using top-down etching techniques or VLS (gas-liquid-solid) vertical growth mode. Specifically, top-down etching techniques can fabricate nanowire structures in the 10nm-100nm range suitable for gate-all-around field-effect transistors (GAAFETs), thereby obtaining novel nanowire functional devices with excellent performance. VLS vertical growth mode is a bottom-up growth technique that can produce large-area nanowire arrays in batches. Nanowire arrays obtained based on VLS vertical growth mode can be used for the fabrication of gate-all-around field-effect transistors and are widely used in the field of integrated circuits.

[0005] However, in actual fabrication, top-down etching techniques rely on expensive, high-precision photolithography (EBL) and other cutting-edge technologies, such as electron beam etching (EBL). This technology is constrained by foreign advanced equipment, facing a "bottleneck" problem. Furthermore, it involves multiple trenching operations and precise spacing control during the trenching process, making the process highly complex. VLS (Vertical Laser Light) growth, on the other hand, faces limitations due to incompatibility with planar micro / nanostructure processes, and reliance on planar transfer techniques can easily lead to reduced yields. Therefore, simplifying the complexity of nanowire fabrication processes and achieving compatibility between nanowire fabrication and planar micro / nanostructure processes has become an urgent technical problem to be solved. Summary of the Invention

[0006] Therefore, it is necessary to provide a nanowire array and its fabrication method, as well as a semiconductor device, to address the problems of complex nanowire fabrication processes and incompatibility between nanowire fabrication processes and planar micro / nano structure processes.

[0007] A method for fabricating a nanowire array includes: providing a heterogeneous stacked structure; the heterogeneous stacked structure includes at least alternating layers of a first heterogeneous film and a second heterogeneous film; forming a plurality of grooves on two opposing sidewalls of the heterogeneous stacked structure along a first direction; wherein the grooves extend from the sidewalls of the second heterogeneous film into the second heterogeneous film; the plurality of grooves located on the same sidewall are spaced apart along a vertical direction and extend along a second direction; the first direction is perpendicular to the vertical direction, and the second direction is perpendicular to the first direction; performing a deposition process on the heterogeneous stacked structure to form an amorphous precursor layer covering the sidewalls of the heterogeneous stacked structure and filling the grooves; performing an etching process on the heterogeneous stacked structure to remove the amorphous precursor layer covering the sidewalls of the heterogeneous stacked structure; sequentially and repeatedly performing the deposition process and the etching process until the amorphous precursor layer completely fills the grooves; and performing a crystallization process on the heterogeneous stacked structure to crystallize the amorphous precursor layer located in the grooves to form a nanowire array.

[0008] In one embodiment, when performing a single deposition process on a heterogeneous multilayer structure, the thickness of the amorphous precursor layer filling the groove is less than the groove depth; the deposition process is one or more of physical vapor deposition, chemical vapor deposition, and plasma-enhanced chemical vapor deposition; the material of the amorphous precursor layer includes one or more of amorphous silicon, amorphous germanium, and amorphous alloys. This avoids the problem of defects such as voids and cracks that easily occur inside the material due to rapid solidification or shrinkage when completely filled to an excessive thickness in a single step; it allows for independent control of the thickness of each amorphous precursor layer, enabling precise control of the nanowire diameter to meet specific application requirements.

[0009] In one embodiment, when performing an etching process on the heterostructure, the etching rate of the amorphous precursor layer covering the sidewalls of the heterostructure is greater than the etching rate of the amorphous precursor layer filling the grooves; the etching process is an in-situ etching process; the process gas used in the etching process includes one or more of hydrogen, argon, helium, octafluorocyclobutane, hexafluoroethane, carbon tetrafluoride, and sulfur hexafluoride. The amorphous precursor layer covering the sidewalls of the heterostructure is preferentially removed, while the amorphous precursor layer in the grooves is retained due to its lower etching rate.

[0010] In one embodiment, a substrate is provided; a first heterogeneous film layer and a second heterogeneous film layer are alternately deposited on the substrate to form an alternating thin film stack structure; the alternating thin film stack structure is etched to form a plurality of heterogeneous stack structures spaced apart along a first direction; the two opposite sidewalls of the heterogeneous stack structure along the first direction are vertical sidewalls. This avoids uneven distribution and reduced density of the nanowire array subsequently formed on the sidewalls of the heterogeneous stack structure, and improves the regularity, density, and structural stability of the subsequently formed nanowire arrangement.

[0011] In one embodiment, multiple grooves are formed on two opposing sidewalls of the heterostructure along a first direction, including: etching the heterostructure to remove a portion of the second heterostructure layer, thereby forming multiple grooves; the two opposing sidewalls of the heterostructure along the first direction form an alternating surface structure; wherein, during etching of the heterostructure, the etching rate of the second heterostructure layer is greater than the etching rate of the first heterostructure layer. Selective etching of the exposed vertical sidewalls of the heterostructure can be performed to obtain the alternating surface structure.

[0012] In one embodiment, when etching the heterostructure, the etching depth of the groove along the first direction is 1 nm to 100 nm, and the etching depth of the groove along the vertical direction is 1 nm to 50 nm. By precisely controlling the groove depth and width, the size and morphology of the nanowires subsequently formed in the grooves can be precisely controlled, which is beneficial to optimizing the growth quality of the nanowires and the device performance.

[0013] In one embodiment, the first heterostructure is a silicon oxide layer, and the second heterostructure is a silicon nitride layer; when etching the heterostructure, the etching liquid is a phosphoric acid solution, and the mass fraction of phosphoric acid in the phosphoric acid solution is 80%~90%;

[0014] Alternatively, the first heterostructure is a silicon nitride layer and the second heterostructure is a silicon oxide layer; when etching the heterostructure, the etching liquid is a hydrofluoric acid solution or a buffered oxide etching solution; when the etching liquid is a hydrofluoric acid solution, the mass fraction of hydrofluoric acid in the hydrofluoric acid solution is 0.5% to 40%.

[0015] In one embodiment, a crystallization process is performed on the heterogeneous stacked structure, including: subjecting an amorphous precursor layer located in multiple grooves to high-temperature heating or laser crystallization to transform the material of the amorphous precursor layer from an amorphous state to a crystalline state. By employing high-temperature heating or laser crystallization to crystallize the amorphous precursor layer into nanowires, no metal catalyst is required, thus further improving the purity of the nanowires.

[0016] Based on this, this application also provides a nanowire array, which is prepared using the nanowire array preparation method described in any of the above embodiments.

[0017] Based on this, this application also provides a semiconductor device, which includes the nanowire array described in the above embodiments.

[0018] The above-mentioned method for fabricating nanowire arrays has two advantages. First, it can grow nanowires at specified positions and directions, solving the problem of incompatibility between nanowire fabrication technology and planar micro / nano structure technology. Second, it can achieve precise control of nanowire size without the need for high-precision photolithography etching technology and without multiple grooving operations, resulting in a lower complexity of the fabrication process. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic flowchart illustrating the fabrication method of the nanowire array provided in this application embodiment;

[0021] Figures 2 to 9 This is a schematic cross-sectional view of the nanowire array during its fabrication process, as provided in the embodiments of this application. Detailed Implementation

[0022] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional scope of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0024] In this invention, numerical ranges are involved. Unless otherwise specified, the numerical ranges are considered continuous and include the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe features or characteristics, the ranges may be merged. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included.

[0025] Innovation in the structure and key processes of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) devices is an important technological direction for the continuous development of integrated circuits.

[0026] GAAFET devices represent an advanced architecture in the evolution of MOSFET technology. GAAFET devices can achieve full gate-to-channel enclosure through nanowires to enhance device control. However, nanowire fabrication presents challenges such as high process complexity and incompatibility with planar micro / nanostructure fabrication processes.

[0027] Based on this, this application provides a method for preparing a nanowire array. Figure 1 A schematic flowchart illustrating the fabrication method of the nanowire array provided in this application embodiment; as shown in the figure, the method includes:

[0028] Step S101: Provide a heterogeneous stacked structure; the heterogeneous stacked structure includes at least alternating layers of a first heterogeneous film and a second heterogeneous film.

[0029] Step S102: A plurality of grooves are formed on two opposite sidewalls of the heterogeneous stacked structure along the first direction; wherein, the grooves extend from the side of the second heterogeneous film layer into the second heterogeneous film layer; the plurality of grooves located on the same sidewall are spaced apart along the vertical direction and extend along the second direction; the first direction is perpendicular to the vertical direction and the second direction is perpendicular to the first direction;

[0030] Step S103: Perform a deposition process on the heterogeneous stacked structure to form an amorphous precursor layer covering the sidewalls and filling the grooves of the heterogeneous stacked structure;

[0031] Step S104: Perform an etching process on the heterostructure to remove the amorphous precursor layer covering the sidewalls of the heterostructure.

[0032] Step S105: Sequentially and repeatedly perform the deposition and etching processes until the amorphous precursor layer completely fills the groove.

[0033] Step S106: Perform a crystallization process on the heterogeneous stacked structure to crystallize the amorphous precursor layer located in the groove to form a nanowire array.

[0034] It is understood that the nanowire array fabrication method proposed in this application can, on the one hand, directly guide the nanowire array to grow onto the sidewall of the heterostructure, thereby achieving precise control over the position and growth direction of the nanowires; on the other hand, by sequentially and repeatedly performing deposition and etching processes, it ensures that the amorphous precursor layer completely fills the grooves, thereby achieving precise control over the size of the nanowires.

[0035] In summary, the nanowire array fabrication method proposed in this application can, on the one hand, grow nanowires at specified positions and directions, solving the problem of incompatibility between nanowire fabrication processes and planar micro / nano structure processes; on the other hand, it can achieve precise control of nanowire size without the need for high-precision photolithography etching technology and without the need for multiple trenching operations, and its fabrication process has low complexity.

[0036] Furthermore, it eliminates the need for top-down etching techniques to fabricate nanowire arrays, and avoids issues such as material selection and structural size limitations during the fabrication process. For example, GAAFET devices require precise control of epitaxial deposition thickness, and post-etching surface treatment is complex. Silicon-germanium materials are prone to diffusion at high temperatures, requiring strict temperature management. The standard cell width CPP (Contacted Poly Pitches) is affected by the contact width and pad thickness, necessitating a balance between resistance and capacitance.

[0037] It should also be understood that although the steps in the above flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least some of the steps in the above flowchart may include multiple steps or stages, and these steps or stages are not necessarily completed at the same time, nor are they necessarily performed sequentially.

[0038] Figures 2 to 9 This is a schematic cross-sectional view of the nanowire array during its fabrication process, as provided in the embodiments of this application. Below, in conjunction with... Figures 2 to 9 The preparation method of the nanowire array provided in the embodiments of this application and its beneficial effects are further described in detail.

[0039] First, please refer to Figure 4 Step S101 is executed to provide a heterogeneous stacked structure 120; the heterogeneous stacked structure 120 includes at least alternating layers of a first heterogeneous film 101 and a second heterogeneous film 102.

[0040] In some embodiments, please refer to Figures 2 to 4The specific steps of providing the heterogeneous stacked structure 120 may include: providing a substrate 100; alternately depositing a first heterogeneous film layer 101 and a second heterogeneous film layer 102 on the substrate 100 to form an alternating thin film stacked structure 110; etching the alternating thin film stacked structure 110 to form a plurality of heterogeneous stacked structures 120 spaced apart along a first direction x; the two sidewalls of the heterogeneous stacked structure 120 opposite each other along the first direction x are vertical sidewalls.

[0041] In some embodiments, substrate 100 may be a silicon substrate, such as a single-crystal silicon substrate, a polycrystalline silicon substrate, a heavily doped n-type silicon substrate, or a heavily doped p-type silicon substrate; substrate 100 may also be a glass substrate, a polymer substrate, or a metal thin film substrate covered by a dielectric layer.

[0042] In some embodiments, the first heterogeneous film layer 101 and the second heterogeneous film layer 102 can be formed by one or more thin film deposition techniques, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), thermal evaporation, or various sputtering physical vapor deposition (PVD) techniques.

[0043] In some embodiments, the first heterostructure layer 101 and the second heterostructure layer 102 can be dielectric thin films or amorphous semiconductor thin films; the materials of the first heterostructure layer 101 and the second heterostructure layer 102 are different, and the first heterostructure layer 101 and the second heterostructure layer 102 have different gas phase or liquid phase etching rates; specifically, the material of the dielectric thin film layer may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride or aluminum oxide; the material of the amorphous semiconductor thin film layer may include amorphous silicon, amorphous germanium or amorphous germanium silicon.

[0044] It should be noted that, in this embodiment, the fabrication method of the nanowire 140 array is described using an alternating thin film stack structure 110 that includes only alternatingly stacked first heterogeneous film layers 101 and second heterogeneous film layers 102 as an example. In some other embodiments, the alternating thin film stack structure 110 can also be a multilayer thin film structure with multiple heterogeneous film layers stacked alternately, and adjacent heterogeneous film layers can have different gas phase or liquid phase etching rates; the alternating thin film stack structure 110 can also be referred to as a "heterogeneous alternating stacked thin film structure". For example, the alternating thin film stack structure 110 may include alternatingly stacked first heterogeneous film layer 101, second heterogeneous film layer 102, and third heterogeneous film layer. Based on this, the heterogeneous stack structure 120 formed by etching the alternating thin film stack structure 110 may also include alternatingly stacked first heterogeneous film layer 101, second heterogeneous film layer 102, and third heterogeneous film layer.

[0045] In some specific embodiments, the thickness of each heterogeneous film layer in the alternating thin film stack structure 110 can be 1 nm to 1000 nm, including the endpoint values; the cyclic stacking period of each heterogeneous film layer can be 1 to 100.

[0046] In some embodiments, please refer to Figure 3 When etching the alternating thin film stacked structure 110 to form multiple heterogeneous stacked structures 120 spaced apart along the first direction x, a photoresist layer can first be formed on the alternating thin film stacked structure 110. Then, a design pattern can be defined using photolithography, electron beam direct writing, or mask technology, and the desired planar pattern can be transferred onto the photoresist layer to form a patterned photoresist layer 103. Then, using the patterned photoresist layer 103 as a mask, the alternating thin film stacked structure 110 can be etched using inductively coupled plasma (ICP) etching or reactive ion etching (RIE) to form multiple heterogeneous stacked structures 120.

[0047] In some specific embodiments, when etching the alternating thin film stack structure 110, a reactive gas with surface anisotropy, isotropy and passivation characteristics can be used to etch the alternating thin film stack structure 110, or different etching atmospheres can be used alternately and cyclically to etch the alternating thin film stack structure 110; when etching the alternating thin film stack structure 110, the etching process gas can include one or more of C4F8, CF4, SF6 and O2.

[0048] It should be noted that when etching the alternating thin film stack structure 110, different reactive gas ratios and alternating processes can be selected to etch the alternating thin film stack structure 110 according to the material of the heterogeneous film layer in the alternating thin film stack structure 110, so as to form a heterogeneous stack structure 120 with vertical sidewalls (vertical etched sidewalls).

[0049] It is understood that in the above process, the embodiments of this application can achieve vertical sidewalls in the heterogeneous stacked structure 120 through only one photolithography (or electron beam direct writing) and one etching process. Here, the vertical sidewalls of the heterogeneous stacked structure 120 can avoid uneven distribution and reduced arrangement density of the nanowire array subsequently formed on the sidewalls of the heterogeneous stacked structure 120, and can improve the regularity, density and structural stability of the subsequently formed nanowire arrangement.

[0050] Then, please refer to Figure 5In step S102, a plurality of grooves T are formed on two opposite sidewalls of the heterogeneous stacked structure 120 along the first direction x; wherein, the grooves T extend from the side of the second heterogeneous film layer 102 into the second heterogeneous film layer 102; the plurality of grooves T located on the same sidewall are spaced apart along the vertical direction z and extend along the second direction y; the first direction x is perpendicular to the vertical direction z, and the second direction y is perpendicular to the first direction x.

[0051] In some embodiments, the number of grooves T on the two sidewalls of the heterogeneous stacked structure 120 is equal; and the grooves T on the same sidewall are equally spaced; the grooves T on the heterogeneous stacked structure 120 can be arranged along the first direction x and the vertical direction z to form an array of m rows and n columns.

[0052] In some embodiments, please refer to Figure 5 Forming multiple grooves T on two opposite sidewalls along the first direction x of the heterogeneous stacked structure 120 may include: etching the heterogeneous stacked structure 120 to remove part of the second heterogeneous film layer 102, thereby forming multiple grooves T; the two opposite sidewalls along the first direction x of the heterogeneous stacked structure 120 form an alternating surface structure; wherein, when etching the heterogeneous stacked structure 120, the etching rate of the second heterogeneous film layer 102 is greater than the etching rate of the first heterogeneous film layer 101.

[0053] Understandably, by utilizing the fact that the etching rate of the second heterostructure 102 is greater than that of the first heterostructure 101, and the mutual masking effect of the stacked layers, selective etching can be performed on the vertical sidewalls of the exposed heterostructure 120 to obtain an alternating surface structure; the alternating surface structure can also be called a "multi-level groove structure with alternating vertical sidewalls" or an "alternating vertical groove sidewall structure". The location on the sidewall of the heterostructure 120 where the groove T is formed by etching can be defined as a concave surface; the remaining unetched sidewall surface can be defined as a convex surface (slope).

[0054] Here, the groove T can serve as a physical template for subsequent nanowire growth, guiding the nanowires to align in the direction of the groove T, thereby enabling precise control of the nanowire position.

[0055] In some embodiments, the etching depth of the groove T along the first direction x can be defined as the groove depth of the groove T, and the etching depth of the groove T along the vertical direction z can be defined as the groove width of the groove T. In this embodiment, when etching the heterogeneous stacked structure 120, the etching depth of the groove T along the first direction x can be 1nm to 100nm, such as 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc.; the etching depth of the groove T along the vertical direction z can be 1nm to 50nm, such as 1nm, 10nm, 20nm, 30nm, 40nm or 50nm, etc.

[0056] Understandably, by precisely controlling the depth and width of the groove T, the size and morphology of the nanowires subsequently formed in the groove T can be precisely controlled, thereby optimizing the growth quality of the nanowires and the device performance. The fabrication process with controllable nanowire size is crucial for the carrier transport efficiency of nanowires in electronic devices.

[0057] In some embodiments, the heterostructure 120 can be etched by selective vapor phase etching (dry vapor phase etching) or liquid phase etching (wet etching), forming multiple grooves T on two opposite sidewalls of the heterostructure 120 along the first direction x. For example, etching can be performed using etching components containing hydrofluoric acid (HF), hydrochloric acid (HCl), phosphoric acid (H3PO4), or chlorine (Cl2) that correspond to the material of the heterostructure.

[0058] It should be noted that by adjusting etching parameters (such as the composition, power, and time of the etching gas or liquid), alternating surface structures can be formed simultaneously in the same process step. This simplifies the process and reduces manufacturing costs. Furthermore, the depth and width of the groove T can also be controlled by adjusting the etching parameters without introducing additional process steps.

[0059] In some specific embodiments, the first heterostructure 101 is a silicon oxide layer, and the second heterostructure 102 is a silicon nitride layer; when etching the heterostructure 120, the etching liquid can be a phosphoric acid solution, and the mass fraction of phosphoric acid in the phosphoric acid solution can be 80%~90%, including endpoint values; for example, the mass fraction of phosphoric acid in the phosphoric acid solution can be 82%, 85%, 87%, or 89%, etc.; when etching the heterostructure 120, the etching temperature can be 160℃~170℃, including endpoint values; for example, the etching temperature can be 162℃, 164℃, 165℃, or 168℃, etc.; in the embodiments of this application, the mass fraction of phosphoric acid in the phosphoric acid solution can be 85%; the etching temperature can be 165℃; and the etching process time can be 1s~1000s.

[0060] Understandably, phosphoric acid solution exhibits a high etching selectivity between silicon nitride and silicon oxide layers, ensuring minimal damage to the silicon oxide layer during silicon nitride etching. However, excessively high phosphoric acid concentrations in the solution lead to an overly rapid etching rate, potentially causing localized over-etching and deteriorating the sidewall smoothness of the heterostructure 120. Conversely, excessively low phosphoric acid concentrations result in a decreased etching rate, necessitating extended processing time and increased production costs. Therefore, the optimal phosphoric acid concentration in the solution is 80%–90%.

[0061] In some other specific embodiments, the first heterostructure 101 is a silicon nitride layer, and the second heterostructure 102 is a silicon oxide layer; when etching the heterostructure 120, the etching liquid can be a hydrofluoric acid solution or a buffered oxide etchant (BOE); when the etching liquid is a hydrofluoric acid solution, the mass fraction of hydrofluoric acid in the hydrofluoric acid solution can be 0.5% to 40%; the etching process time is 1s to 100s.

[0062] Understandably, hydrofluoric acid or buffered oxide etching solutions offer a high etching selectivity between silicon nitride and silicon oxide layers, ensuring minimal damage to the silicon nitride layer during silicon oxide etching. However, excessively high hydrofluoric acid concentrations in the solution can lead to excessively rapid etching, resulting in localized over-etching and deterioration of the sidewall smoothness of the heterostructure 120. Conversely, excessively low concentrations result in a decreased etching rate, necessitating longer processing times and increased production costs. Therefore, the optimal hydrofluoric acid concentration in the solution is typically between 0.5% and 40%.

[0063] Then, please refer to Figure 6 In step S103, a deposition process is performed on the heterogeneous stacked structure 120 to form an amorphous precursor layer 130 covering the sidewalls of the heterogeneous stacked structure 120 and filling the groove T.

[0064] Specifically, when performing a deposition process on the heterogeneous stacked structure 120, one or more amorphous precursor layers 130 can be covered on the sidewalls of the heterogeneous stacked structure 120 and the bottom of the groove T. The material of the amorphous precursor layer 130 can correspond to the composition of the nanowires to be grown subsequently.

[0065] In some embodiments, the deposition process can be one or more of physical vapor deposition, chemical vapor deposition, and plasma-enhanced chemical vapor deposition; the material of the amorphous precursor layer 130 can include one or more of amorphous silicon (a-Si), amorphous germanium (a-Ge), and amorphous alloys. For example, the amorphous precursor layer 130 can be a stacked structure of amorphous silicon and amorphous germanium, and the amorphous precursor layer 130 can also be referred to as an "amorphous semiconductor precursor thin film layer".

[0066] In some embodiments, when performing a single deposition process on the heterostructure 120, the thickness of the amorphous precursor layer 130 filling the groove T can be less than the groove depth of the groove T; for example, the thickness of each deposited amorphous precursor layer 130 can be 1 nm to 100 nm. Here, the thickness of the amorphous precursor layer 130 is the dimension of the amorphous precursor layer 130 along the first direction x. Furthermore, in the single deposition process, the amorphous precursor layer 130 uniformly covers the sidewalls of the heterostructure 120 and the interior of the groove T, forming a conformal deposition, and the thickness of the amorphous precursor layer 130 filling the interior of the groove T is similar to the thickness of the amorphous precursor layer 130 on the sidewalls of the heterostructure 120.

[0067] Understandably, by limiting the thickness of the amorphous precursor layer 130 in a single filling of the groove T to less than the groove depth of T, complete filling of the groove T can be achieved through multiple depositions. During multiple depositions, the material of each amorphous precursor layer 130 can flow sufficiently before solidification, filling microscopic voids and forming a denser structure. This avoids the problem of voids, cracks, and other defects that can easily occur inside the material due to rapid solidification or shrinkage when a single complete filling is too thick. In addition, multiple depositions allow for independent control of the thickness of each amorphous precursor layer 130, enabling precise control of the nanowire diameter to meet specific application requirements.

[0068] Then, step S104 is performed to perform an etching process on the heterostructure 120 to remove the amorphous precursor layer 130 covering the sidewalls of the heterostructure 120.

[0069] In some embodiments, when performing an etching process on the heterostructure 120, the etching rate of the amorphous precursor layer 130 covering the sidewalls of the heterostructure 120 is greater than the etching rate of the amorphous precursor layer 130 filling the groove T. Thus, the amorphous precursor layer 130 covering the sidewalls of the heterostructure 120 is preferentially removed, while the amorphous precursor layer 130 in the groove T is retained due to its lower etching rate. This avoids the continuous accumulation of the amorphous precursor layer 130 on the sidewalls of the heterostructure 120 during subsequent deposition processes, preventing the amorphous precursor layer 130 from completely filling the groove T. This significantly improves filling efficiency, reduces the risk of voids, and optimizes the morphology and performance of the subsequently formed nanowires.

[0070] In some embodiments, the etching process can be an in-situ etching process; the etching gas can be a plasma gas corresponding to the material of the amorphous precursor layer 130; for example, the process gas used in the etching process can include one or more of hydrogen (H2), argon (Ar), helium (He), octafluorocyclobutane (C4F8), hexafluoroethane (C2F6), carbon tetrafluoride (CF4), and sulfur hexafluoride (SF6).

[0071] Then, please refer to Figure 7 Step S105 is executed, and the deposition and etching processes are performed sequentially and repeatedly until the amorphous precursor layer 130 completely fills the groove T.

[0072] In some embodiments, after etching the heterostructure 120, the method for fabricating the nanowire array may further include: determining whether the amorphous precursor layer 130 has completely filled the groove T; if the amorphous precursor layer 130 has not completely filled the groove T, continuing to perform the next deposition process and etching process; if the amorphous precursor layer 130 has completely filled the groove T, stopping the deposition process and etching process, and continuing to perform subsequent processes.

[0073] In some specific embodiments, when the amorphous precursor layer 130 does not completely fill the groove T, step S103 can be executed again to deposit the amorphous precursor layer 130 again. Since the previous etching process will cover the amorphous precursor layer 130 on the sidewall of the heterostructure 120, after this deposition process, the thickness of the amorphous precursor layer 130 in the groove T is greater than the thickness of the amorphous precursor layer 130 covering the sidewall of the heterostructure 120.

[0074] Understandably, by repeatedly depositing and etching the amorphous precursor layer 130 in alternating cycles, the thickness of the amorphous precursor layer 130 covering the sidewalls of the heterostructure 120 can be prevented from increasing with the increase of the thickness of the amorphous precursor layer 130 within the groove T. As the process is repeated, the thickness of the amorphous precursor layer 130 inside the groove T gradually increases, eventually completely removing the excess amorphous precursor layer 130 from the sidewall surface of the heterostructure 120 and achieving complete filling of the amorphous precursor layer 130 inside the groove T.

[0075] It should be noted that the shape and size of the nanowires can be precisely designed by restricting the internal space of the groove T and precisely programming the filling amount (quantitative supply) of the amorphous precursor layer 130 within the groove T. Therefore, by adjusting the thickness between heterogeneous stacks and the thickness of the amorphous precursor layer 130, and by precisely controlling the complete filling of the amorphous precursor layer 130 within the groove T, the growth size of the nanowires can be precisely controlled. Thus, the nanowire array fabrication method provided in this application embodiment is not merely for growing simple linear arrays, but can grow programmable three-dimensional stacked nanowire structures.

[0076] It should also be noted that the nanowire array fabrication method provided in this application embodiment can be achieved by traditional thin film deposition technology, thereby inheriting and maintaining the area process characteristics of traditional thin film processes, and can be widely used in flat panel displays TFT (Thin Film Transistor), biosensing, flexible wearable electronics and related new electronic logic devices.

[0077] Finally, please refer to Figure 8 In step S106, a crystallization process is performed on the heterogeneous stacked structure 120 to crystallize the amorphous precursor layer 130 located in the groove T, forming an array of nanowires 140.

[0078] In some embodiments, a crystallization process is performed on the heterogeneous stacked structure 120, including: performing high-temperature heating or laser crystallization on the amorphous precursor layer 130 located in a plurality of grooves T to transform the material of the amorphous precursor layer 130 from an amorphous state to a crystalline state.

[0079] Specifically, in a vacuum or inert gas protected environment, the amorphous precursor layer 130 within the confined space (i.e., groove T) can be heated or irradiated with laser through high-temperature treatment or laser heating, causing the amorphous precursor layer 130 to crystallize (transform from an amorphous state into crystalline nanowires 140), forming a three-dimensional stacked nanowire array. The three-dimensional stacked nanowire array can also be referred to as a "three-dimensional sidewall nanowire array framework" or a "three-dimensional vertically arranged nanowire array structure".

[0080] It should be noted that the preparation of nanowires in the VLS vertical growth mode usually uses metal catalysts, which may remain on the surface of the nanowires and affect the performance and stability of electronic devices and other applications. In this application, high-temperature heating or laser crystallization is used to crystallize the amorphous precursor layer 130 to form nanowires 140 without the need for metal catalysts, which can further improve the purity of nanowires 140.

[0081] The three-dimensional stacked nanowire array provided in this application embodiment can grow and arrange high-density nanowire channels on a limited planar projected area, thereby significantly improving the current load and driving capability of the nanowire 140 array as a transistor device channel. The three-dimensional stacked nanowire array provided in this application embodiment provides an important technical foundation for realizing novel three-dimensional electronic devices.

[0082] In some embodiments, after forming the nanowire array 140, the fabrication method of the nanowire array may further include: etching away portions of the first heterostructure layer 101 and the second heterostructure layer 102 located between the plurality of nanowires 140, thereby suspending and releasing the nanowires 140. The suspended nanowire array can realize the fabrication of stacked gate-around transistors and be applied in logic devices.

[0083] In some specific embodiments, the heterogeneous film can be etched away in a high-cleanliness environment using etching components (etching gas or liquid) that correspond to the material of the heterogeneous film, such as hydrofluoric acid, phosphoric acid, or buffered oxide etching solution, and employing appropriate wet or dry etching techniques.

[0084] In some embodiments, after the nanowires 140 are released from the air, the method for fabricating the nanowire array 140 may further include: patterning the surface of the nanowires 140 to define regions of specific geometries for the deposition of electrode materials; depositing electrode materials in the regions of specific geometries to fabricate source and drain electrodes in situ; the materials of the source and drain electrodes may include amorphous silicon germanium or metals with different work functions such as gold, platinum, nickel, aluminum, and titanium.

[0085] In some embodiments, please refer to Figure 9 After the nanowire 140 is released from its suspension, the fabrication method of the nanowire array can further include: forming a gate dielectric 151 that fully surrounds the surface of the nanowire 140; patterning a gate structure on the surface of the gate dielectric 151; and forming a gate electrode 152 that fully surrounds the gate dielectric 151 to obtain a gate-all-around field-effect transistor. A gate-all-around field-effect transistor can also be called a "gate-all-around transistor" or a "full-ring gate field-effect transistor".

[0086] In some specific embodiments, the gate dielectric 151 can be formed using an atomic layer deposition process; the material of the gate dielectric 151 may include high-k dielectric layer materials such as alumina (Al2O3), hafnium dioxide (HfO2) or zirconium dioxide (ZrO2); the material of the gate electrode 152 may include polycrystalline silicon, titanium nitride (TiN) or metals such as gold, platinum, nickel, and aluminum.

[0087] In summary, the nanowire array fabrication method proposed in this application (also known as "heterogeneous step three-dimensional guided technology" or "three-dimensional stacked nanowire array growth method") can reliably and in batches fabricate high-density three-dimensional nanowire arrays (high-density three-dimensional vertical sidewall nanowire arrays). These nanowire arrays can be used to fabricate three-dimensional stacked gate-around transistors and can be widely applied to semiconductor micro-nano electronic devices.

[0088] Based on this, this application also provides a nanowire array, which is prepared using the nanowire array preparation method described in any of the above embodiments.

[0089] Based on this, this application also provides a semiconductor device, which includes the nanowire array described in the above embodiments.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for preparing a nanowire array, characterized by, The method for fabricating the nanowire array includes: A heterogeneous stacked structure is provided; the heterogeneous stacked structure includes at least alternating layers of a first heterogeneous film and a second heterogeneous film. Multiple grooves are formed on two opposite sidewalls of the heterogeneous laminate structure along a first direction; wherein the grooves extend from the side of the second heterogeneous film layer into the second heterogeneous film layer; the multiple grooves located on the same sidewall are spaced apart in a vertical direction and extend in a second direction; the first direction is perpendicular to the vertical direction, and the second direction is perpendicular to the first direction; A deposition process is performed on the heterogeneous stacked structure to form an amorphous precursor layer covering the sidewalls of the heterogeneous stacked structure and filling the grooves; An etching process is performed on the heterostructure to remove the amorphous precursor layer covering the sidewalls of the heterostructure; The deposition process and the etching process are performed sequentially and repeatedly until the amorphous precursor layer completely fills the groove; A crystallization process is performed on the heterogeneous stacked structure to crystallize the amorphous precursor layer located in the groove, thereby forming the nanowire array.

2. The method for preparing a nanowire array according to claim 1, characterized in that, When performing the deposition process once on the heterogeneous stacked structure, the thickness of the amorphous precursor layer filling the groove is less than the groove depth; And / or, the deposition process is one or more of physical vapor deposition, chemical vapor deposition, and plasma-enhanced chemical vapor deposition; the material of the amorphous precursor layer includes one or more of amorphous silicon, amorphous germanium, and amorphous alloys.

3. The method for preparing a nanowire array according to claim 1, characterized in that, When the etching process is performed on the heterostructure, the etching rate of the amorphous precursor layer covering the sidewall of the heterostructure is greater than the etching rate of the amorphous precursor layer filling the groove. And / or, the etching process is an in-situ etching process; the process gas used in the etching process includes one or more of hydrogen, argon, helium, octafluorocyclobutane, hexafluoroethane, carbon tetrafluoride, and sulfur hexafluoride.

4. The method of claim 1, wherein the nanowire array is formed on a substrate. The heterogeneous stacked structure is provided, comprising: Provide substrate; The first heterogeneous film layer and the second heterogeneous film layer are alternately deposited on the substrate to form an alternating thin film stack structure; The alternating thin film stack structure is etched to form a plurality of heterogeneous stack structures spaced apart along the first direction; the two opposite sidewalls of the heterogeneous stack structure along the first direction are vertical sidewalls.

5. The method of claim 1, wherein the nanowire array is formed on a substrate. A plurality of grooves are formed on two opposite sidewalls of the heterogeneous laminate structure along the first direction, including: The heterogeneous stacked structure is etched to remove part of the second heterogeneous film layer, forming a plurality of grooves; the two opposite sidewalls of the heterogeneous stacked structure along the first direction form an alternating surface structure; wherein, when the heterogeneous stacked structure is etched, the etching rate of the second heterogeneous film layer is greater than the etching rate of the first heterogeneous film layer.

6. The method for fabricating a nanowire array according to claim 5, characterized in that, When etching the heterogeneous stacked structure, the etching depth of the groove along the first direction is 1 nm to 100 nm, and the etching depth of the groove along the vertical direction is 1 nm to 50 nm.

7. The method for fabricating a nanowire array according to claim 5, characterized in that, The first heterostructure is a silicon oxide layer, and the second heterostructure is a silicon nitride layer; when etching the heterostructure, the etching liquid is a phosphoric acid solution, and the mass fraction of phosphoric acid in the phosphoric acid solution is 80%~90%; Alternatively, the first heterostructure layer is a silicon nitride layer, and the second heterostructure layer is a silicon oxide layer; When etching the heterogeneous stacked structure, the etching liquid is a hydrofluoric acid solution or a buffered oxide etching solution; when the etching liquid is the hydrofluoric acid solution, the mass fraction of hydrofluoric acid in the hydrofluoric acid solution is 0.5%~40%.

8. The method of claim 1, wherein the nanowire array is formed on a substrate. Performing the crystallization process on the heterostructure includes: The amorphous precursor layer located in the plurality of grooves is subjected to high-temperature heating treatment or laser crystallization treatment to transform the material of the amorphous precursor layer from an amorphous state to a crystalline state.

9. A nanowire array, characterized in that, The nanowire array is prepared using the method described in any one of claims 1 to 8.

10. A semiconductor device, characterized by comprising: The semiconductor device includes the nanowire array of claim 9.

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