Method for preparing planar ultrafine close-packed grooves and nanowires without high-precision photolithography

Abstract

The application discloses a kind of preparation plane super fine close-order groove structure in combination with the laminated structure on vertical sidewall and CMP process, and through plane solid-liquid-solid nanowire growth method, preparation plane super fine close-order nanowire can be positioned, and array is realized through programming guide technology.The application is expected to break through the key technical bottleneck that plane super fine nanowire cannot be prepared by large-scale integration for a long time due to the limitation of photolithography technology, can realize plane super fine nanowire array on the wafer substrate without high lattice quality under low thermal budget, micron level photolithography precision, and can be used in three-dimensional integration back end on a large scale.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for preparing a planar ultra-fine dense groove and nanowire without high-precision lithography, and more particularly to a method for preparing a planar ultra-fine dense nanowire array using a plasma-enhanced chemical vapor deposition (PECVD) lamination preparation technology, which is suitable for the microelectronic field and three-dimensional integration. BACKGROUND

[0002] As a typical one-dimensional nanomaterial, crystalline silicon nanowires have great application value in nanoelectronic devices, optoelectronic devices, quantum electronics, flexible / stretchable electronics, and bioelectronics. Currently, the growth of nanowires mainly applies the planar solid-liquid-solid (IPSLS) growth mode, which uses hydrogenated amorphous silicon film as a precursor and grows crystalline silicon nanowire structures by absorbing amorphous silicon with metal catalyst nanoparticles. At the same time, the IPSLS growth mode can realize the size control of nanowires under the growth channel of double-sided restriction.

[0003] However, the currently available positioning integrated large-scale ultra-fine dense nanowire array needs to rely on high-precision lithography technology and high-quality wafer substrates, which is limited by technical barriers and high costs, and the three-dimensional integrated backend devices lack high-lattice-quality wafers.

[0004] The applicant's research group has previously applied for a patent CN 114400248 A, a method for accurately guiding the growth of nanowires with high uniformity of diameter, which also mentions the generation of nanowires in planar dense grooves. However, the planar groove morphology of this patent is defined by lithography patterning to guide the groove, and the groove width and spacing layer distance are directly limited by the lithography precision, which is micron wide. Moreover, this patent limits the growth of nanowires by limited etching of amorphous silicon.

[0005] How to realize ultra-fine dense crystalline nanowire channels without high-precision lithography and wafer substrates is a technical problem that needs to be solved by the research group recently. The breakthrough of this technology has important scientific research and industrialization value. SUMMARY

[0006] The present application proposes a method for preparing a planar ultra-fine dense groove and growing nanowires without high-precision lithography, which can realize a growth groove array below 15 nm under 2-micron precision lithography conditions, and further grow a nanowire array of about 10 nm, which is beneficial to realize low-cost, low-precision nanowire large-scale integrated devices and multi-field applications.

[0007] The present application provides a method for preparing a planar ultra-fine dense groove and nanowire without high-precision lithography, characterized by comprising the following steps:

[0008] 1) Define edge pattern on substrate by mask lithography, etch the substrate by dry etching to form protrusion with vertical sidewall;

[0009] 2) Deposit two different dielectric layers on the substrate defined by the edge pattern in step 1, the thickness of the dielectric layers determines the width and distance of the trenches.

[0010] 3) Remove the dielectric layers on the top of the edge pattern by CMP to expose the two dielectric layers deposited in step 2.

[0011] 4) Treat the surface with etching liquid with different etching rate for the two dielectric layers to form planar and densely packed growth trenches.

[0012] 5) Define catalytic metal on the surface of the growth trenches by mask lithography, deposit a strip of catalytic metal layer by evaporation or sputtering.

[0013] 6) Increase the temperature above the melting point of the catalytic metal, introduce reducing gas plasma to convert the catalytic metal layer into separated metal nanoparticles.

[0014] 7) Reduce the temperature below the melting point of the catalytic metal nanoparticles, deposit a thin film of amorphous semiconductor precursor on the surface of the structure, then increase the temperature to a suitable temperature to melt the nanoparticles, the nanoparticles absorb the amorphous semiconductor precursor at the front end and deposit crystalline nanowires at the back end, the nanowires grow along the planar and densely packed growth trenches.

[0015] 8) Remove the remaining amorphous semiconductor precursor by etching with hydrogen plasma, ICP or RIE to obtain planar and densely packed nanowires.

[0016] As a preferred embodiment, the substrate material in step 1 is crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide or sapphire.

[0017] As a preferred embodiment, the two different dielectric layers in step 2 are silicon nitride, silicon oxide, aluminum oxide or silicon carbide, and the deposition technique is PECVD or ALD.

[0018] As a preferred embodiment, the etching liquid in step 4 is hydrofluoric acid, hot phosphoric acid, silicon oxide, aluminum oxide, silicon nitride or silicon oxide for etching silicon nitride and silicon oxide, and hydrochloric acid is used for wet etching.

[0019] As preferred, the catalytic metal in step 5) is one of In, Sn, Bi, Ga or a metal alloy thereof.

[0020] As preferred, the precursor layer in step 7) is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or other amorphous alloy layer, and a heterostructure (such as a-Ge / a-Si) thereof.

[0021] The technical scheme provided in the application has at least the following technical effects or advantages:

[0022] 1) The present application combines the stack structure on the vertical sidewall and the CMP process, without the need of high-precision photolithography to prepare a planar ultra-fine dense groove structure, and through the planar solid-liquid-solid (IPSLS) nanowire growth method, a planar ultra-fine dense nanowire that can be positioned is prepared, and array is realized through programming guide technology, that is, the diameter of the nanowire and the thickness of the interval layer can be controlled by depositing a medium layer with different thicknesses, and 2um photolithography can make the subsequent planar line width below 20nm, and the required photolithography precision is lower than the 90nm photolithography precision required by the SAQP technology. The present application is expected to break through the key technical bottleneck that the planar ultra-fine nanowire cannot be prepared on a large scale due to the limitation of photolithography technology for a long time, and the planar ultra-fine nanowire array can be realized without a wafer substrate under low thermal budget and micron-level photolithography precision, which can provide high-quality crystalline silicon channels for back-end devices and three-dimensional integration.

[0023] 2) The present application does not need a high-quality lattice wafer as a substrate, the selection of the substrate material will be more extensive, and the three-dimensional integration can be served, and in the absence of a wafer substrate, an ultra-fine dense groove is simply prepared, combined with the IPSLS growth mode, and a high-quality ultra-fine dense crystalline silicon nanowire channel is provided for application in a back-end device.

[0024] 3) The present application grows an ultra-fine crystalline silicon nanowire array with a diameter less than 10nm and a pitch less than 10nm by using the IPSLS growth technology and the groove restriction. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The preparation flowchart of the planar ultra-fine dense nanowire provided for the embodiment 1 of the present application is shown in the figure. Wherein: Figure 1 a. The guide pattern is defined on the substrate by photolithography, and the channel with vertical sidewall is etched by ICP, Figure 1 b. Two kinds of medium layer stacks are cyclically deposited by PECVD, Figure 1 c. The top end of the pattern is removed by the CMP process and is planarized, Figure 1 d. The growth groove is etched by the etching solution, Figure 1 e. The belt-shaped catalytic metal layer is deposited at one end of the channel, Figure 1f hydrogen plasma treatment catalytic metal layer forms metal droplets, covers amorphous precursor layer, grows nanowire, and then etches amorphous silicon.

[0026] Figure 2 For example 1 of the present application from Figure 1 a structure to Figure 1 b structure specific process schematic. Figure 2 a→b→c process cycle N times in the deposition of Figure 2 d, N-layer laminated structure.

[0027] Figure 3 is the embodiment 1 of the present application Figure 1 d, Figure 1 f cross-sectional enlarged schematic diagram, Figure 3 a is the smooth growth groove obtained after selective etching of the etching solution, Figure 3 b is Figure 3 a groove growth to obtain nanowire, Figure 3 c is the growth groove obtained under the condition of extremely high selectivity of the etching solution, which means that the etching solution does not react with one kind of material film or the reaction rate is much lower than that of another film, Figure 3 d is Figure 3 c groove growth to obtain nanowire.

[0028] Figure 4 is the flow chart of the present application embodiment 2 to realize higher density planar ultra-fine dense growth groove and nanowire growth on the multi-groove sidewall. DETAILED DESCRIPTION

[0029] In order to better understand the above technical solutions, the above technical solutions will be described in detail in combination with the description of the drawings and specific embodiments. EMBODIMENT

[0030] As Figures 1-3 shown: the present embodiment provides a method for preparing planar ultra-fine dense groove and nanowire without high-precision lithography, which comprises the following steps:

[0031] 1) Use silicon wafer, glass, compound (such as silicon nitride, silicon oxide, silicon oxynitride) or other metal materials as substrate, define edge pattern on the substrate by using low-precision mask plate lithography technology, use dry etching process such as inductively coupled plasma etching (ICP) to anisotropically etch the substrate to form a protruding morphology with a vertical sidewall, as shown in Figure 1 a;

[0032] 2) Using the pattern formed in the first step as the substrate, two different dielectric layers are cyclically deposited on the substrate using the PECVD process. The good conformality of the PECVD process allows the dielectric layers to form alternating dense layers on the vertical sidewalls. Alternating dielectric layers of different thicknesses can be designed and deposited according to the requirements of the nanowire diameter and spacing. The thickness of the film determines the width and spacing of the trenches, such as Figure 1 As shown in b; Figure 2 The process a→b→c is cycled N times to obtain Figure 2 d N-layer stacked structure;

[0033] 3) Use CMP process to remove the vertically stacked dielectric layer on top of the pattern and expose the two dielectric layers alternating horizontally, such as Figure 1 As shown in c;

[0034] 4) Treat the surface with a corrosive liquid having different etching rates for the two dielectric layers, preferably with an etching rate ratio higher than 2, to form planar closely packed growth grooves, such as Figure 1 d- Figure 1 f; if the selected corrosive liquid can react to both dielectric layers, but the etching rate is different, it is easy to obtain a smooth arc-shaped groove morphology, such as Figure 3 in Figure 3 a. Figure 3 b. If the selected corrosive liquid only reacts with one dielectric layer, the etching effect on the other dielectric layer is negligible, and a rectangular cross-section groove morphology is easily obtained, such as Figure 3 c. Figure 3 d; Therefore, this technical solution can prepare grooves of different morphologies to meet different needs;

[0035] 5) Using the planar close-packed growth trench formed in the previous step as the substrate, the catalytic metal is defined perpendicular to the trench using mask lithography technology again. A strip-shaped catalytic metal layer is locally deposited by evaporation or sputtering.

[0036] 6) In a PECVD vacuum system, the temperature is raised to above the melting point of the catalytic metal, and a reducing gas plasma is introduced to treat the catalytic metal layer, thereby converting the catalytic metal layer into separated metal nanoparticles;

[0037] 7) Lower the temperature to below the melting point of the catalytic metal particles, and deposit a thin film of amorphous semiconductor precursor over the entire surface of the structure. Then, raise the temperature to an appropriate level to remelt the nanometal particles, causing them to absorb the amorphous layer at their front ends and deposit crystalline nanowires at their rear ends. Due to the guiding effect of the confining channels, the nanowires will grow along the densely packed guiding channels in the plane.

[0038] 8) The remaining amorphous semiconductor precursor is removed by etching process such as hydrogen plasma, ICP or RIE, etc. The planar close-packed nanowires are obtained.

[0039] The planar ultra-fine close-packed trench structure is prepared without high-precision photolithography by combining the stack structure on the vertical sidewall and the CMP process. The planar ultra-fine close-packed nanowires are prepared by the planar solid-liquid-solid (IPSLS) nanowire growth method, and the array is realized by the programming guide technology (as long as the thickness of the medium layer is deposited to control the diameter of the nanowire and the thickness of the spacer layer). The present application is expected to break through the key technical bottleneck of large-scale integrated preparation of planar ultra-fine nanowires due to the limitation of photolithography technology for a long time. The planar ultra-fine nanowire array can be realized on the substrate without wafer under low heat budget and low photolithography precision, and can be widely used in the back end of three-dimensional integration. Embodiment

[0040] As shown in Figure 4 The preparation method of the present embodiment is the same as that of embodiment 1, except that the substrate is etched to form a protruding topography with two vertical sidewalls, and two planar close-packed nanowires are prepared. By analogy, the present application can also prepare multiple planar close-packed nanowire structures simultaneously according to the needs.

[0041] The method for defining ultra-fine guide trenches provided by embodiments 1 and 2 of the present application is equivalent to using micron-level photolithography combined with PECVD thin film deposition technology to obtain nanometer-level trench width and pitch on a plane, replacing high-cost high-precision photolithography such as DUV and EUV. Compared with the self-aligned quadruple patterning technology (SAQP), the present technical solution does not require multiple cycles of deposition and etching, and ensures the accurate control of the width and pitch of the guide trench while the process steps are relatively simple and stable. The width and pitch of the guide trench in the embodiment are determined by the thickness of the deposited film, with a precision of several nanometers to several tens of nanometers. That is, using 2um photolithography can make the subsequent planar line width reach below 20nm, which has a prominent technical advantage over the prior art.

[0042] The above only describes the preferred embodiments of the present application. It should be noted that for ordinary skilled persons in the technical field, several improvements can be made without departing from the principles of the present application, and these improvements should also be considered as the protection scope of the present application.

Claims

1. A method for preparing planar ultrafine densely packed grooves and nanowires without high-precision photolithography, characterized in that: The steps include: 1) defining an edge pattern on a substrate using a mask lithography technique, and etching the substrate using a dry etching process to form a protruding morphology with vertical sidewalls; 2) using the edge pattern defined in the first step as a substrate, cyclically and alternately depositing two different dielectric layers on the substrate; 3) using a CMP process to remove the vertically stacked dielectric layer on top of the edge pattern, exposing the two dielectric layers that are alternately stacked in the horizontal direction; 4) Treating the surface with a corrosive liquid having different etching rates for the two dielectric layers to form planar, closely packed growth grooves; 5) Using the planar close-packed growth trench formed in step 4 as a substrate, the catalytic metal is again defined using mask lithography technology, and a strip-shaped catalytic metal layer is locally deposited by evaporation or sputtering; 6) Raising the temperature to above the melting point of the catalytic metal and introducing a reducing gas plasma for treatment to transform the catalytic metal layer into separated metal nanoparticles; 7) Lowering the temperature to below the melting point of the catalytic metal particles, and depositing a thin film layer of amorphous semiconductor precursor on the entire surface of the structure; then raising the temperature to an appropriate temperature to remelt the nanometal particles, causing the front end to absorb the amorphous layer, while crystalline nanowires are deposited at the rear end. Under the guidance of the growth grooves, the nanowires grow along the densely packed guide channels in the plane; 8) The remaining amorphous semiconductor precursor is removed by etching processes such as hydrogen plasma, ICP or RIE to obtain planar densely packed nanowires.

2. The method for fabricating planar ultrafine densely packed grooves and nanowires without high-precision photolithography according to claim 1, characterized in that: The substrate material in step 1) is crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide or sapphire.

3. The method for fabricating planar ultrafine and densely packed grooves and nanowires without high-precision photolithography according to claim 1, wherein: In step 2), the materials of the two different dielectric layers are silicon nitride, silicon oxide, aluminum oxide or silicon carbide, and the deposition technology is PECVD or ALD.

4. The method for fabricating planar ultrafine densely packed grooves and nanowires without high-precision photolithography according to claim 1, characterized in that: The corrosive liquid in step 4) is hydrofluoric acid, hot phosphoric acid, silicon oxide, aluminum oxide, silicon nitride or silicon oxide for silicon nitride and silicon oxide for silicon nitride stacking, and hydrochloric acid is used for wet etching.

5. The method for preparing planar ultrafine densely packed grooves and nanowires without high-precision photolithography according to claim 1, characterized in that: The catalytic metal in step 5) is one of In, Sn, Bi, Ga or a metal alloy thereof.

6. The method for preparing planar ultrafine densely packed grooves and nanowires without high-precision photolithography according to claim 1, characterized in that: In the step 7), the precursor layer is one of amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon aC, or a heterogeneous stacked structure thereof.

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