Superconducting single photon chip, method of manufacture, detector and super-resolution imaging method

Abstract

This invention provides a superconducting single-photon chip, comprising: a substrate, a first nanowire, a first isolation layer, a second nanowire, a second isolation layer, and a ground layer stacked sequentially; the first straight lines of the first nanowire are parallel to each other; the second straight lines of the second nanowire are parallel to each other; the perpendicular projections of each second straight line are orthogonal to each first straight line, forming a rectangular grid-like region. Based on the rectangular grid-like region, photons can be imaged using the superconducting single-photon chip. This invention also provides a method for fabricating the superconducting single-photon chip, utilizing mature fabrication processes. This invention further provides a superconducting single-photon detector, including a first sensor group disposed at both ends of the first nanowire and a second sensor group disposed at both ends of the second nanowire. This invention also provides a super-resolution imaging method, which, based on the superconducting single-photon chip, can further improve imaging accuracy using mature fabrication processes.

Description

Technical Field

[0001] This invention relates to the field of superconducting single-photon imaging, and in particular to a superconducting single-photon chip, a method for fabricating the superconducting single-photon chip, a superconducting single-photon detector, and a super-resolution imaging method. Background Technology

[0002] Superconducting nanowire single photon detectors (SNSPDs) have become core devices for quantum fundamental research, dark matter detection, cosmic microwave background mapping, and quantum information systems due to their quantum properties, low-temperature (<4 Kelvin) noise suppression capabilities, near 100% detection efficiency, wide spectral response energy from ultraviolet to mid-infrared, and ultra-low dark count rate at the millihertz level.

[0003] To achieve imaging capabilities, existing technologies primarily employ a pixelation strategy of "one detector, one pixel," coupled with a cryogenic signal readout architecture, which falls into two categories: digital readout architecture and analog multiplexing architecture. However, both of these architectures suffer from poor compatibility, low resolution, and physical limitations on resolution.

[0004] Therefore, how to provide a superconducting single-photon detector with high resolution, simple readout, good low-light performance, and high reliability has become one of the technical problems that urgently need to be solved by those skilled in the art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superconducting single-photon chip, a method for fabricating a superconducting single-photon chip, a superconducting single-photon detector, and a super-resolution imaging method, in order to solve the problems of poor compatibility and low resolution of superconducting single-photon detectors in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a superconducting single-photon chip, comprising at least: a substrate, a first nanowire, a first isolation layer, a second nanowire, a second isolation layer, and a ground layer; the substrate serves as a substrate for the superconducting single-photon chip; the first nanowire is formed on the substrate; the first nanowire extends in a serpentine pattern and includes sequentially alternating first straight lines and first connecting lines, each first straight line being parallel to each other and located in a first direction; the first isolation layer is formed on the first nanowire for electrically isolating the first nanowire and the second nanowire; the second nanowire is formed on the first isolation layer; the second nanowire extends in a serpentine pattern and includes sequentially alternating first straight lines and first connecting lines. Alternating second straight lines and second connecting lines, each second straight line is parallel to each other and located in a second direction, which is perpendicular to the first direction; the vertical projection of each second straight line is orthogonal to each first straight line and forms a rectangular grid-like region; a second isolation layer is formed on the second nanowire for electrically isolating the second nanowire and the ground layer; the ground layer is formed on the second isolation layer for providing a reference potential for the superconducting single-photon chip; wherein, the two opposite segments of each first straight line based on the rectangular grid-like region are both longer than the segment of itself located within the rectangular grid-like region; the two opposite segments of each second straight line based on the rectangular grid-like region are both longer than the segment of itself located within the rectangular grid-like region.

[0008] Optionally, the first connecting line is a straight line or a smooth curve.

[0009] Optionally, the second connecting line is a straight line or a smooth curve.

[0010] Optionally, the spacing between adjacent first lines and the spacing between adjacent second lines are both 100 nm to 10 μm.

[0011] Alternatively, the spacing between adjacent first lines is equal to the spacing between adjacent second lines.

[0012] Optionally, the lengths of the two opposite line segments of the first straight line based on the rectangular grid area are both 100 μm to 10 mm, and are greater than the lengths of the line segments of the first straight line within the rectangular grid area; the lengths of the two opposite line segments of the second straight line based on the rectangular grid area are both 100 μm to 10 mm, and are greater than the lengths of the line segments of the second straight line within the rectangular grid area.

[0013] Optionally, the width of the first nanowire outside the rectangular grid region is more than 1.5 times its own width within the rectangular grid region; the width of the second nanowire outside the rectangular grid region is more than 1.5 times its own width within the rectangular grid region.

[0014] To achieve the above and other related objectives, the present invention also provides a method for fabricating a superconducting single-photon chip, wherein the method comprises at least the following steps: S1: providing a substrate; forming a first thin film on the substrate; patterning the first thin film to obtain a first nanowire; forming a first isolation layer on the first nanowire; S2: forming a second thin film on the first isolation layer; patterning the second thin film to obtain a second nanowire; forming a second isolation layer on the second nanowire; forming a ground layer on the second isolation layer.

[0015] Optionally, in step S1, the first thin film uses any one of the superconducting materials; in step S2, the second thin film uses any one of the superconducting materials.

[0016] To achieve the above and other related objectives, the present invention also provides a superconducting single-photon detector, which includes at least: a first sensor group, a second sensor group, and the superconducting single-photon chip; the first sensor group includes a first sensor and a second sensor; the first and second sensors are respectively disposed at both ends of a first nanowire of the superconducting single-photon chip; the second sensor group includes a third sensor and a fourth sensor; the third and fourth sensors are respectively disposed at both ends of a second nanowire of the superconducting single-photon chip.

[0017] To achieve the above and other related objectives, the present invention also provides a super-resolution imaging method based on the superconducting single-photon chip or the superconducting single-photon detector described above. The super-resolution imaging method includes at least the following steps: S1: An imaging light signal is emitted from the surface of the superconducting single-photon chip, and the imaging light signal reaches a rectangular grid-like region; a first signal and a second signal are obtained at both ends of a first nanowire, and a third signal and a fourth signal are obtained at both ends of a second nanowire; S2: Based on the first and second signals, the imaging position of the imaging light signal in a second direction is obtained; based on the third and fourth signals, the imaging position of the imaging light signal in a first direction is obtained; wherein, the number of imaging positions in the first direction is equal to 2*N-1, where N represents the number of intersections of the rectangular grid-like region in the first direction; the number of imaging positions in the second direction is equal to 2*M-1, where M represents the number of intersections of the rectangular grid-like region in the second direction.

[0018] Optionally, in step S2, the imaging position of the imaging light signal in the second direction is obtained based on the reception time difference between the first signal and the second signal; and the imaging position of the imaging light signal in the first direction is obtained based on the reception time difference between the third signal and the fourth signal.

[0019] As described above, the superconducting single-photon chip, the method for fabricating the superconducting single-photon chip, the superconducting single-photon detector, and the super-resolution imaging method of the present invention have the following beneficial effects:

[0020] 1. The present invention sets both the first nanowire and the second nanowire as serpentine lines, and orthogonally projects the vertical projections of each second straight line to each first straight line to form a rectangular grid area. This allows the imaging position corresponding to the midpoint of adjacent intersection points in the first direction to be obtained, as well as the imaging position corresponding to the midpoint of adjacent intersection points in the second direction, thereby improving the imaging resolution.

[0021] 2. This invention, by making the line segment of the first straight line outside the rectangular grid area longer than the line segment of itself within the rectangular grid area, can distinguish the imaging positions corresponding to adjacent intersection points in the second direction, thus providing a basis for high-resolution imaging; by making the line segment of the second straight line outside the rectangular grid area longer than the line segment of itself within the rectangular grid area, can distinguish the imaging positions corresponding to adjacent intersection points in the first direction, thus providing a basis for high-resolution imaging.

[0022] 3. In this invention, the width of the first and second nanowires outside the rectangular grid region is greater than their width within the rectangular grid region. This allows the nanowires within the rectangular grid region to function as both photon responders and signal transmitters, while the nanowires outside the rectangular grid region only function as signal transmitters. Attached Figure Description

[0023] Figure 1 The diagram shown is a structural schematic of the superconducting single-photon chip of the present invention.

[0024] Figure 2 The diagram shown is a structural schematic of the first nanowire of the present invention.

[0025] Figure 3 The diagram shown is a structural schematic of the second nanowire of the present invention.

[0026] Figure 4 The diagram shows the intersection of the vertical projection of the second nanowire and the first nanowire of the present invention.

[0027] Figure 5 The diagram shows a first type of triggering of photons on the superconducting single-photon chip of this invention.

[0028] Figure 6 This diagram illustrates a second type of triggering of photons on the superconducting single-photon chip of the present invention.

[0029] Figure 7 The diagram shows a flow chart of the fabrication method of the superconducting single-photon chip of the present invention.

[0030] Figure 8 The diagram shown is a schematic diagram of the first intermediate structure of the superconducting single-photon chip of the present invention.

[0031] Figure 9 The diagram shown is a schematic diagram of the second intermediate structure of the superconducting single-photon chip of the present invention.

[0032] Figure 10 The diagram shown is a schematic of the third intermediate structure of the superconducting single-photon chip of the present invention.

[0033] Figure 11 The diagram shown is a schematic of the fourth intermediate structure of the superconducting single-photon chip of the present invention.

[0034] Figure 12 The diagram shown is a schematic of the fifth intermediate structure of the superconducting single-photon chip of the present invention.

[0035] Figure 13 The diagram shown is a schematic of the sixth intermediate structure of the superconducting single-photon chip of the present invention.

[0036] Figure 14 The diagram shown is a schematic of the seventh intermediate structure of the superconducting single-photon chip of the present invention.

[0037] Figure 15 The diagram shown is a structural schematic of the superconducting single-photon detector of the present invention.

[0038] Figure 16 The diagram shown is a flowchart of the super-resolution imaging method of the present invention.

[0039] Figure 17 The diagram shows different photon imaging positions of the super-resolution imaging method of the present invention.

[0040] Component designation explanation

[0041] 1 Superconducting single-photon chip

[0042] 1a substrate

[0043] 11 silicon wafer

[0044] 12. SiO2 coating covering the surface of the silicon wafer

[0045] 1b First Nanowire

[0046] 13 First straight line

[0047] 14 First connecting line

[0048] 1c First isolation layer

[0049] 1d second nanowire

[0050] 15 Second straight line

[0051] 16 Second connecting line

[0052] 17 rectangular grid areas

[0053] 1e Second Isolation Layer

[0054] 1f grounding layer

[0055] 1g First Thin Film

[0056] 1h second thin film

[0057] 2 First sensor group

[0058] 2a First Sensor

[0059] 2b Second Sensor

[0060] 3. Second sensor group

[0061] 3a Third Sensor

[0062] 3b Fourth Sensor Detailed Implementation

[0063] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] Please see Figures 1-17 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] Digital readout architectures rely on single-flux quantum (SFQ) logic or nanowire cryotron (nTron) technology. On the one hand, the manufacturing process of SFQ logic technology is poorly compatible with the superconducting nanowire process of SNSPD, making it difficult to integrate digital readout architectures monolithically. On the other hand, although nTron technology shares a material platform with SNSPD and can realize basic components such as logic gates and shift registers, it cannot build multi-level logic circuits to perform complex intra-pixel processing, resulting in an array size that can only reach the 10³ pixel level, making it difficult for digital readout architectures to meet high-resolution requirements.

[0066] Analog multiplexing architectures need to reduce the complexity of cryogenic electronics through frequency division multiplexing, time-of-flight discrimination, or row and column addressing. However, analog multiplexing architectures still suffer from low resolution or resolution limitations imposed by physical constraints. For example, one type of Microwave Kinetic Inductance Detector (MKID) uses frequency division multiplexing to achieve a 20,440-pixel array, but the pixel pitch is as high as 150 μm. Another hybrid architecture based on thermally coupled row and column matrices and delay line readout has achieved a 400,000-pixel SNSPD camera, but its physical pixel pitch is still limited to 5 μm.

[0067] Furthermore, although computer-based super-resolution technology can achieve a 4-16 times improvement in virtual resolution, it relies on statistical inference rather than direct photon localization, which easily introduces systematic errors in quantum correlation patterns and weak signal localization. Moreover, it is limited by the Shannon-Nyquist sampling criterion determined by the physical pixel spacing, and cannot reproduce the true information capacity of high pixel density detectors.

[0068] Therefore, in order to solve the above problems, this invention proposes a superconducting single-photon chip, a method for fabricating the superconducting single-photon chip, a superconducting single-photon detector, and a super-resolution imaging method. The specific technical solutions are as follows:

[0069] Example 1

[0070] like Figure 1 As shown, this embodiment provides a superconducting single-photon chip 1, including: a substrate 1a, a first nanowire 1b, a first isolation layer 1c, a second nanowire 1d, a second isolation layer 1e, and a ground layer 1f.

[0071] like Figure 1 As shown, substrate 1a is used to provide a substrate for superconducting single-photon chip 1.

[0072] Specifically, in this embodiment, substrate 1a is used to provide mechanical support and an insulating substrate. As an example, substrate 1a includes a silicon wafer 11 and a silicon dioxide (SiO2) coating 12 covering the upper surface of the silicon wafer. In practical applications, the specific type of substrate 1a can be set as needed, and is not limited to this embodiment.

[0073] like Figure 1 As shown, a first nanowire 1b is formed on a substrate 1a; the first nanowire 1b extends in a serpentine pattern and includes first straight lines 13 and first connecting lines 14 that are alternately connected in sequence, with each first straight line 13 being parallel to each other and located in a first direction.

[0074] Specifically, in this embodiment, such as Figure 2 As shown, the first nanowire 1b extends in a serpentine pattern on the substrate 1a. Figure 2 The dashed lines represent portions of the first straight lines 13 omitted due to size limitations. Each first straight line 13 is located in a first direction and parallel to each other. The first connecting line 14 can be a straight line or a smooth curve. As an example, the spacing between adjacent first straight lines 13 is 100 nm to 10 μm, including but not limited to 200 nm, 500 nm, 800 nm, 1 μm, 3 μm, and 5 μm. In practical applications, the specific spacing between adjacent first straight lines 13 can be set as needed, and is not limited to this embodiment. Furthermore, the first nanowire 1b should be made of a superconducting material capable of detecting single photons. As an example, the first nanowire 1b can be made of niobium nitride (NbN). In practical applications, the specific material of the first nanowire 1b can be set as needed, and is not limited to this embodiment.

[0075] like Figure 1 As shown, a first isolation layer 1c is formed on the first nanowire 1b for electrically isolating the first nanowire 1b and the second nanowire 1d.

[0076] Specifically, in this embodiment, the first isolation layer 1c not only electrically isolates the first nanowire 1b and the second nanowire 1d, but also thermally couples the first nanowire 1b and the second nanowire 1d, ensuring that the first nanowire 1b can still be triggered after the photon triggers the second nanowire 1d. As an example, the first isolation layer 1c can be made of SiO2 material. In practical applications, the specific type of the first isolation layer 1c can be set as needed, and is not limited to this embodiment.

[0077] like Figure 1 As shown, the second nanowire 1d is formed on the first isolation layer 1c; the second nanowire 1d extends in a serpentine shape and includes second straight lines 15 and second connecting lines 16 connected alternately in sequence, each second straight line 15 is parallel to each other and located in a second direction, the second direction is perpendicular to the first direction; the vertical projection of each second straight line 15 is orthogonal to each first straight line 13 and forms a rectangular grid-like region 17.

[0078] Specifically, in this embodiment, such as Figure 3 As shown, the second nanowire 1d extends in a serpentine pattern in the first insulating layer 1c. Figure 3 The dashed lines represent portions of the second straight lines 15 omitted due to size limitations. Each second straight line 15 is located in the second direction and parallel to each other. The second connecting line 16 can be a straight line or a smooth curve. As an example, the spacing between adjacent second straight lines 15 can be equal to the spacing between adjacent first straight lines to simplify chip layout. The spacing between adjacent second straight lines 15 is 100nm to 10μm, including but not limited to 200nm, 500nm, 800nm, 1μm, 3μm, and 5μm. In practical applications, the specific spacing between adjacent second straight lines 15 can be set as needed and is not limited to this embodiment. Furthermore, the first direction and the second direction are perpendicular to each other, such as... Figure 4 As shown, the vertical projection of the second straight line 15 is orthogonal to the first straight line 13 and forms a rectangular grid-like region 17, wherein the row direction of the rectangular grid-like region 17 is the first direction and the column direction is the second direction. Furthermore, the second nanowire 1d should also be made of a superconducting material capable of detecting single photons. As an example, the second nanowire 1d is also made of niobium nitride (NbN). In practical applications, the specific material of the second nanowire 1d can be set as needed, and is not limited to this embodiment.

[0079] Specifically, in this embodiment, such as Figure 4 As shown, the lengths of the two opposing line segments of the first straight line 13 based on the rectangular grid region 17 are both greater than the length of the line segment itself located within the rectangular grid region 17. This is to distinguish the imaging positions corresponding to adjacent intersection points in the second direction. As an example, the lengths of the two opposing line segments of a single first straight line 13 based on the rectangular grid region 17 are both between 100μm and 10mm, including but not limited to 200μm, 500μm, 800μm, 1mm, 5mm, and 9mm, and are greater than the length of the line segment itself located within the rectangular grid region 17 (the specific length greater needs to be sufficient to distinguish the imaging positions of adjacent intersection points in the second direction). In practical applications, the length of the first straight line 13 inside and outside the rectangular grid region 17 can be set as needed, not limited to this embodiment. Further, as... Figure 4As shown, the lengths of the two opposing line segments of the second straight line 15 based on the rectangular grid region 17 are both greater than the length of the line segment within the rectangular grid region 17 itself. This is to distinguish the imaging positions corresponding to adjacent intersection points in the first direction. As an example, the lengths of the two opposing line segments of a single second straight line 15 based on the rectangular grid region 17 are both between 100μm and 10mm, including but not limited to 200μm, 500μm, 800μm, 1mm, 5mm, and 9mm, and are greater than the length of the line segment within the rectangular grid region 17 itself (the specific length exceeding this length needs to be sufficient to distinguish the imaging positions of adjacent intersection points in the first direction). In practical applications, the length of the second straight line 15 inside and outside the rectangular grid region 17 can be set as needed, and is not limited to this embodiment.

[0080] Specifically, in this embodiment, such as Figure 4 As shown, the width of the first nanowire 1b outside the rectangular grid region 17 is at least 1.5 times its width inside the rectangular grid region 17, including but not limited to 2, 3, 5, and 7 times; the width of the second nanowire 1d outside the rectangular grid region 17 is at least 1.5 times its width inside the rectangular grid region 17, including but not limited to 2, 3, 5, and 7 times. In practical applications, the width difference between the first and second nanowires inside and outside the rectangular grid region 17 can be set as needed, and is not limited to this embodiment. Furthermore, the reason why the width of the first and second nanowires outside the rectangular grid region 17 is greater than their width inside the rectangular grid region 17 is to make the current density of the first and second nanowires outside the rectangular grid region 17 lower than their current density inside the rectangular grid region 17. Therefore, the nanowires inside the rectangular grid region 17 have the function of responding to photons and transmitting signals, while the nanowires outside the rectangular grid region 17 only have the function of transmitting signals.

[0081] like Figure 1 As shown, a second isolation layer 1e is formed on the second nanowire 1d for electrical isolation between the second nanowire 1d and the ground layer 1f.

[0082] Specifically, in this embodiment, the second isolation layer 1e is used to electrically isolate the second nanowire 1d and the ground layer 1f, and also to thermally couple and control the second nanowire 1d, ensuring that the second nanowire 1d can be triggered after photons reach the chip surface corresponding to the chip process surface. As an example, the second isolation layer 1e can also be made of SiO2 material. In practical applications, the specific type of the second isolation layer 1e is set as needed, and is not limited to this embodiment.

[0083] like Figure 1 As shown, the ground layer 1f is formed on the second isolation layer 1e and is used to provide a reference potential for the superconducting single-photon chip 1.

[0084] Specifically, in this embodiment, when photons trigger the first and second nanowires, corresponding signals are generated. Therefore, a reference potential needs to be set to facilitate signal transmission. As an example, the ground layer 1f can be made of gold (Au). In practical applications, the specific material of the ground layer 1f can be set as needed, and is not limited to this embodiment.

[0085] It should be noted that after the photon reaches the rectangular grid region 17, as... Figure 5 As shown, when a photon falls on the first straight line 13 and is located on the midline of two adjacent second straight lines 15, one first straight line 13 and two second straight lines 15 can be triggered. The position of the photon in the second direction is determined by the signal time difference at the two ends of the nanowire of the triggered first straight line 13, and the position in the first direction is determined by the average of the signal time differences at the two ends of the nanowire of the triggered second straight lines 15. The imaging position of the photon is thus determined, and the minimum resolvable imaging position in the first direction is reduced by a factor of two, making the resolvable imaging distance in the first direction more precise and improving the imaging resolution. Furthermore, as... Figure 6 As shown, when a photon falls on the second straight line 15 and is located on the midline of two adjacent first straight lines 13, it can trigger two first straight lines 13 and one second straight line 15. The position of the photon in the second direction is determined by the average of the signal time difference between the two triggered first straight lines 13 at both ends of the nanowire, and the position in the first direction is determined by the signal time difference between the one triggered second straight line 15 at both ends of the nanowire. The imaging position of the photon can also be determined, and at the same time, the minimum resolvable imaging position in the second direction is also reduced by a factor of two, making the resolvable imaging distance in the second direction more precise and improving the imaging resolution.

[0086] Example 2

[0087] like Figure 7 As shown, this embodiment provides a method for fabricating a superconducting single-photon chip 1, including the following steps:

[0088] like Figure 7 As shown, in step S1, a substrate 1a is provided; a first thin film 1g is formed on the substrate 1a, and the first thin film 1g is patterned to obtain a first nanowire 1b; a first isolation layer 1c is formed on the first nanowire 1b.

[0089] Specifically, in this embodiment, such as Figure 8 As shown, substrate 1a can be made of a material that can provide mechanical support and an insulating substrate for the entire chip. As an example, a 268 nm thick thermally grown SiO2 coating 12 is applied to the surface of a 2-inch diameter silicon wafer 11 to provide substrate 1a for the entire chip. In practical applications, the specific material and process of substrate 1a can be set as needed, and are not limited to this embodiment.

[0090] Specifically, in this embodiment, such as Figure 9 and Figure 10 As shown, the first nanowire 1b is obtained by patterning the first thin film 1g. The first thin film 1g can be any superconducting material, enabling the first nanowire 1b to detect single photons. As an example, a 7 nm thick niobium nitride thin film is deposited on substrate 1a as the first thin film 1g, and the first nanowire 1b, extending in a serpentine pattern, is fabricated on the first thin film 1g using electron beam lithography (EBL) and CF4 reactive ion etching (RIE). In practical applications, the specific material and fabrication process of the first nanowire 1b can be set as needed, and this embodiment is not limited to this one. Furthermore, alignment marks can be pre-fabricated on the substrate 1a where the first nanowire 1b is located to accurately position the second nanowire 1d relative to the first nanowire 1b. As an example, gold (Au) alignment marks can be used. In practical applications, the specific material and process of the alignment marks can be set as needed, and this embodiment is not limited to this one.

[0091] Specifically, in this embodiment, such as Figure 11 As shown, the first isolation layer 1c requires electrical isolation and thermal coupling control of the first nanowire 1b and the second nanowire 1d. As an example, a 50 nm thick SiO2 layer is prepared on the first nanowire 1b by plasma-enhanced chemical vapor deposition (PECVD), and the SiO2 layer is then subjected to chemical mechanical polishing (CMP) to reduce the surface roughness from approximately 3 nm to approximately 0.35 nm, thus achieving the preparation of the first isolation layer 1c. In practical applications, the specific materials and processes of the first isolation layer 1c can be set according to needs, and are not limited to this embodiment.

[0092] like Figure 7 As shown, in step S2, a second thin film 1h is formed on the first isolation layer 1c, and the second thin film 1h is patterned to obtain a second nanowire 1d; a second isolation layer 1e is formed on the second nanowire 1d; and a ground layer 1f is formed on the second isolation layer 1e.

[0093] Specifically, in this embodiment, such as Figure 12 and Figure 13As shown, the second nanowire 1d is obtained by patterning the second thin film 1h. The second thin film 1h can be any superconducting material, enabling the second nanowire 1d to detect single photons. As an example, a 7 nm thick niobium nitride thin film is used as the second thin film 1h, and the second nanowire 1d, extending in a serpentine pattern, is fabricated on the second thin film 1h using electron beam lithography and CF4 reactive ion etching. Furthermore, the straight lines of the second nanowire 1d and the straight lines of the first nanowire 1b are orthogonal to each other within the rectangular grid region 17. In practical applications, the specific material and fabrication process of the second nanowire 1d can be set as needed, and are not limited to this embodiment.

[0094] Specifically, in this embodiment, such as Figure 14 As shown, the second isolation layer 1e needs to provide electrical isolation between the second nanowire 1d and the ground layer 1f, and to control the thermal coupling of the second nanowire 1d. As an example, a SiO2 layer is prepared on the second nanowire 1d by plasma-enhanced chemical vapor deposition, and the SiO2 layer is then chemically and mechanically polished to achieve the fabrication of the second isolation layer 1e. In practical applications, the specific materials and processes for the second isolation layer 1e can be determined according to requirements, and are not limited to this embodiment.

[0095] Specifically, in this embodiment, such as Figure 1 As shown, the ground layer 1f needs to provide a reference potential for the signals generated after the first and second nanowires are triggered. As an example, a 50 nm thick Au layer can be prepared by electron beam physical vapor deposition (EB-PVD) as the ground layer 1f. The ground layer 1f provides a grounding loop for the first and second nanowires respectively. In practical applications, the specific materials and processes of the ground layer 1f can be set as needed, and are not limited to this embodiment.

[0096] Specifically, in this embodiment, the fabrication method of the superconducting single-photon chip 1 can adopt mature semiconductor fabrication processes in each step, without the need to develop new materials or equipment, and is compatible with existing semiconductor production lines, making it easy to scale up mass production.

[0097] It should be noted that this embodiment can be used to prepare the superconducting single-photon chip 1 of Embodiment 1, or other superconducting single-photon chips 1 that are the same as or similar to the inventive concept of the embodiments.

[0098] Example 3

[0099] like Figure 15 As shown, this embodiment provides a superconducting single-photon detector, including: a first sensor group 2, a second sensor group 3, and a superconducting single-photon chip 1.

[0100] like Figure 15As shown, the first sensor group 2 includes a first sensor 2a and a second sensor 2b; the first and second sensors are respectively disposed at both ends of the first nanowire 1b of the superconducting single-photon chip 1.

[0101] Specifically, in this embodiment, the first sensor 2a is disposed at the first end of the first nanowire 1b, and is used to receive the first signal output at the first end after the first nanowire 1b is triggered; the second sensor 2b is disposed at the second end of the first nanowire 1b, and is used to receive the second signal output at the second end after the first nanowire 1b is triggered. As an example, both the first and second sensors can be room temperature low-noise amplifiers. In practical applications, the specific types of the first and second sensors can be set as needed, and are not limited to this embodiment.

[0102] like Figure 15 As shown, the second sensor group 3 includes a third sensor 3a and a fourth sensor 3b; the third and fourth sensors are respectively disposed at both ends of the second nanowire 1d of the superconducting single-photon chip 1.

[0103] Specifically, in this embodiment, the third sensor 3a is disposed at the first end of the second nanowire 1d, and is used to receive the third signal output at the first end after the second nanowire 1d is triggered; the fourth sensor 3b is disposed at the second end of the second nanowire 1d, and is used to receive the fourth signal output at the second end after the second nanowire 1d is triggered. As an example, both the third and fourth sensors can be room temperature low-noise amplifiers. In practical applications, the specific types of the third and fourth sensors can be set as needed, and are not limited to this embodiment.

[0104] It should be noted that this embodiment may include the superconducting single-photon chip 1 of Embodiment 1, or other superconducting single-photon chips 1 that are the same as or similar to the inventive concept of the embodiment.

[0105] Example 4

[0106] like Figure 16 As shown, this embodiment provides a super-resolution imaging method, including the following steps;

[0107] like Figure 16 As shown, in step S1, an imaging light signal is emitted onto the surface of the superconducting single-photon chip 1, and the imaging light signal reaches the rectangular grid region 17; a first signal and a second signal are obtained at both ends of the first nanowire 1b, and a third signal and a fourth signal are obtained at both ends of the second nanowire 1d.

[0108] Specifically, in this embodiment, the surface where the first nanowire 1b and the second nanowire 1d are located is the surface of the superconducting single-photon chip 1. Since the nanowires in the rectangular grid region 17 have the function of responding to photons and transmitting signals, after the first and second nanowires in the rectangular grid region 17 are triggered, the two ends of the first nanowire 1b generate a first signal and a second signal, respectively, and the two ends of the second nanowire 1d generate a third signal and a fourth signal, respectively.

[0109] like Figure 16 As shown, in step S2, the imaging position of the imaging light signal in the second direction is obtained based on the first and second signals; the imaging position of the imaging light signal in the first direction is obtained based on the third and fourth signals; wherein, the number of imaging positions in the first direction is equal to 2*N-1, where N represents the number of intersections of the rectangular grid region 17 in the first direction; the number of imaging positions in the second direction is equal to 2*M-1, where M represents the number of intersections of the rectangular grid region 17 in the second direction.

[0110] Specifically, in this embodiment, the time when the first signal is received is called the first time, and the time when the second signal is received is called the second time. Based on the time difference between the first time and the second time, the imaging position of the imaging light signal in the second direction can be calculated. As an example, such as Figure 17 As shown, A, B, and C are located on the same second straight line 15. Point B is the midpoint between points A and C. The difference between the first and second times the imaging light signal is obtained at point A is denoted as tx1-tx2. The imaging position of point A in the second direction is calculated using tx1-tx2. As another example, ... Figure 17 As shown, the time difference of the imaging light signal at point A is tx1-tx2, and the time difference at point C is (tx1-τx)-(tx2+τx), where τx represents the transmission time difference of the signal from point A to point C on the first nanowire 1b. The imaging position at point B in the second direction is calculated using [tx1-tx2+(tx1-τx)-(tx2+τx)] / 2 = tx1-τx-tx2 (due to the instantaneous response capability of the nanowire to the trigger signal, tx1-τx-tx2 is the time difference between the first and second signals received at both ends of the first nanowire 1b). Furthermore, the imaging positions in the second direction can be obtained not only through the intersections of the rectangular grid region 17, but also through the midpoints of each intersection point in the second direction. That is, the number of imaging positions in the second direction is equal to 2*M-1, where M represents the number of intersections of the rectangular grid region 17 in the second direction.

[0111] Specifically, in this embodiment, the time when the third signal is received is called the third time, and the time when the fourth signal is received is called the fourth time. Based on the time difference between the third time and the fourth time, the imaging position of the imaging light signal in the first direction can be calculated. As an example, such as Figure 17 As shown, A, D, and E are located on the same first straight line 13. Point D is the midpoint between points A and E. The difference between the third and fourth times obtained by the imaging light signal at point A is denoted as ty1-ty2. The imaging position of point A in the first direction is calculated using ty1-ty2. As another example, ... Figure 17 As shown, the time difference of the imaging light signal at point A is ty1-ty2, and the time difference at point E is (ty1-τy)-(ty2+τy), where τy represents the transmission time difference of the signal from point A to point E on the second nanowire 1d. Using [ty1-ty2+(ty1-τy)-(ty2+τy)] / 2=ty1-τy-ty2 (due to the instantaneous response capability of the nanowire to the trigger signal, ty1-τy-ty2 is the time difference between the third and fourth signals received at point D at both ends of the second nanowire 1d), the imaging position of point D in the first direction is calculated using ty1-τy-ty2. Furthermore, not only can the imaging position in the first direction be obtained through the intersections of the rectangular grid region 17, but also through the midpoints of each intersection in the first direction, more imaging positions in the first direction can be obtained. That is, the number of imaging positions in the first direction is equal to 2*N-1, where N represents the number of intersections of the rectangular grid region 17 in the first direction.

[0112] Specifically, in this embodiment, in the first direction, the distance of the smallest resolvable imaging position is shortened from AE to AB, and in the second direction, the distance of the smallest resolvable imaging position is also shortened from AC to AB. Therefore, the imaging resolution of the superconducting single-photon chip 1 for the imaging light signal is doubled, achieving super-resolution imaging. Furthermore, when the distance between nanowires is set to the micrometer level using mature process technology, the superconducting single-photon chip 1 of this embodiment can further improve the imaging accuracy from the micrometer level to the sub-micrometer level, eliminating the single dependence of imaging accuracy on process technology. Moreover, achieving super-resolution imaging through physical factors avoids system errors caused by computational super-resolution, improving the realism of high-pixel detectors. Even further, the superconducting single-photon chip 1 of this embodiment only requires two sets of sensors to complete the signal acquisition of two nanowires, avoiding the integration difficulties of digital architecture and the multi-channel design of analog architecture, significantly reducing the size, weight, and cost of the low-temperature readout system. Furthermore, the superconducting single-photon chip 1 of this embodiment also exhibits excellent ultra-low-light imaging performance, solving the problems of high noise and detail loss in existing systems under low light conditions.

[0113] It should be noted that this embodiment can be implemented based on the superconducting single-photon chip 1 of Embodiment 1, or based on the superconducting single-photon detector of Embodiment 3, or based on other superconducting single-photon chips 1 or superconducting single-photon detectors that are the same as or similar to the inventive concept of the embodiments.

[0114] In summary, the superconducting single-photon chip of the present invention comprises: a substrate, a first nanowire, a first isolation layer, a second nanowire, a second isolation layer, and a ground layer stacked sequentially; the first nanowire extends in a serpentine pattern, including a first straight line and a first connecting line, each first straight line being parallel to each other and located in a first direction; the second nanowire extends in a serpentine pattern and includes a second straight line and a second connecting line, each second straight line being parallel to each other and located in a second direction, the second direction being perpendicular to the first direction; the vertical projections of each second straight line are orthogonal to each first straight line, forming a rectangular grid-like region. Based on the rectangular grid-like region, photons can be imaged using the superconducting single-photon chip. The fabrication method of the superconducting single-photon chip of the present invention utilizes a mature fabrication process to fabricate the superconducting single-photon chip, which is beneficial for the industrial production of superconducting single-photon chips. The superconducting single-photon detector of the present invention includes a first sensor group disposed at both ends of the first nanowire and a second sensor group disposed at both ends of the second nanowire, used to detect the first, second, third, and fourth signals of the superconducting single-photon chip. The super-resolution imaging method of this invention is based on a superconducting single-photon chip or a superconducting single-photon detector. It can further improve imaging accuracy based on mature fabrication processes, eliminating the sole dependence of imaging accuracy on process technology. Furthermore, this invention also has the advantages of significantly reduced readout complexity, excellent ultra-low light imaging performance, and reliable high-resolution imaging results. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A superconducting single-photon chip, characterized in that, The superconducting single-photon chip includes at least: a substrate, a first nanowire, a first isolation layer, a second nanowire, a second isolation layer, and a ground layer; The substrate is used to provide a base for the superconducting single-photon chip; The first nanowire is formed on the substrate; the first nanowire extends in a serpentine pattern and includes sequentially alternating first straight lines and first connecting lines, each first straight line being parallel to each other and located in a first direction; The first isolation layer is formed on the first nanowire and is used to electrically isolate the first nanowire and the second nanowire; The second nanowire is formed on the first isolation layer; the second nanowire extends in a serpentine pattern and includes second straight lines and second connecting lines that are alternately connected in sequence, each second straight line is parallel to each other and located in a second direction, the second direction being perpendicular to the first direction; the vertical projection of each second straight line is orthogonal to each first straight line and forms a rectangular grid-like region; The second isolation layer is formed on the second nanowire to electrically isolate the second nanowire from the ground layer; The grounding layer is formed on the second isolation layer and is used to provide a reference potential for the superconducting single-photon chip; In each of the first straight lines, the two opposite line segments based on the rectangular grid area are both longer than the line segments within the rectangular grid area itself; in each of the second straight lines, the two opposite line segments based on the rectangular grid area are both longer than the line segments within the rectangular grid area itself.

2. The superconducting single-photon chip according to claim 1, characterized in that: The first connecting line is a straight line or a smooth curve.

3. The superconducting single-photon chip according to claim 1 or 2, characterized in that: The second connecting line is a straight line or a smooth curve.

4. The superconducting single-photon chip according to claim 1, characterized in that: The spacing between adjacent first lines and adjacent second lines is 100 nm to 10 μm.

5. The superconducting single-photon chip according to claim 4, characterized in that: The distance between adjacent first straight lines is equal to the distance between adjacent second straight lines.

6. The superconducting single-photon chip according to any one of claims 1-5, characterized in that: The lengths of the two opposite line segments of the first straight line based on the rectangular grid area are both 100 μm to 10 mm, and are greater than the lengths of the line segments of the first straight line within the rectangular grid area; the lengths of the two opposite line segments of the second straight line based on the rectangular grid area are both 100 μm to 10 mm, and are greater than the lengths of the line segments of the second straight line within the rectangular grid area.

7. The superconducting single-photon chip according to any one of claims 1-5, characterized in that: The width of the first nanowire outside the rectangular mesh region is more than 1.5 times its own width within the rectangular mesh region; the width of the second nanowire outside the rectangular mesh region is more than 1.5 times its own width within the rectangular mesh region.

8. A method for fabricating a superconducting single-photon chip, used to fabricate the superconducting single-photon chip according to any one of claims 1-7, characterized in that, The method for fabricating the superconducting single-photon chip includes at least the following steps: S1: Provide a substrate; form a first thin film on the substrate; pattern the first thin film to obtain a first nanowire; form a first isolation layer on the first nanowire; S2: A second thin film is formed on the first isolation layer, and the second thin film is patterned to obtain a second nanowire; a second isolation layer is formed on the second nanowire; a ground layer is formed on the second isolation layer.

9. The method for fabricating a superconducting single-photon chip according to claim 8, characterized in that: In step S1, the first thin film uses any one of the superconducting materials; in step S2, the second thin film uses any one of the superconducting materials.

10. A superconducting single-photon detector, characterized in that, The superconducting single-photon detector includes at least: a first sensor group, a second sensor group, and a superconducting single-photon chip as described in any one of claims 1-7; The first sensor group includes a first sensor and a second sensor; the first and second sensors are respectively disposed at both ends of the first nanowire of the superconducting single-photon chip; The second sensor group includes a third sensor and a fourth sensor; the third and fourth sensors are respectively disposed at both ends of the second nanowire of the superconducting single-photon chip.

11. A super-resolution imaging method, implemented based on the superconducting single-photon chip according to any one of claims 1-7 or the superconducting single-photon detector according to claim 10, characterized in that, The super-resolution imaging method includes at least the following steps: S1: The superconducting single-photon chip emits an imaging light signal from its surface, which reaches a rectangular grid-like region; a first signal and a second signal are obtained at both ends of the first nanowire, and a third signal and a fourth signal are obtained at both ends of the second nanowire. S2: Based on the first and second signals, obtain the imaging position of the imaging light signal in the second direction; based on the third and fourth signals, obtain the imaging position of the imaging light signal in the first direction; wherein, the number of imaging positions in the first direction is equal to 2*N-1, where N represents the number of intersections of the rectangular grid region in the first direction; the number of imaging positions in the second direction is equal to 2*M-1, where M represents the number of intersections of the rectangular grid region in the second direction.

12. The super-resolution imaging method according to claim 11, characterized in that: In step S2, the imaging position of the imaging light signal in the second direction is obtained based on the reception time difference between the first signal and the second signal; the imaging position of the imaging light signal in the first direction is obtained based on the reception time difference between the third signal and the fourth signal.

Images