Data protection method and system based on TPM encryption

Abstract

The present application relates to the technical field of encrypted data protection, in particular to a data protection method and system based on TPM encryption, comprising: extracting file index node and directory item features, generating root node digest through hierarchical aggregation logic and measuring to platform configuration register, establishing hardware anchor topology based on storage root key; analyzing data stream to generate feature keywords, generating hardware derived credentials using TPM hardware unique key, constructing balanced search tree and encapsulating to generate ciphertext mapping index. Analyzing I / O request, performing hardware anchored logical integrity comparison for metadata operation; quantifying hardware evaluation value for data content operation, if threshold is met, synchronous hardware verification is performed, otherwise, physical block is located based on ciphertext mapping index and verification operation is pushed into delay queue asynchronously. The present application realizes strong binding of data and hardware and fast addressing of ciphertext through software and hardware cooperative anchoring, effectively balancing data security protection and high concurrency I / O throughput performance.

Description

Technical Field

[0001] This invention relates to the field of encrypted data protection technology, specifically to a data protection method and system based on TPM encryption. Background Technology

[0002] In the field of large-scale file systems and database retrieval technologies, the physical storage structure and logical indexing mechanism of data are crucial to determining system performance and stability. With the explosive growth of data volume, ensuring that data blocks stored on disk and their organizational structure are not illegally tampered with, while maintaining high-efficiency retrieval performance, is a core challenge in storage architecture design. Traditional storage solutions often rely on the operating system's file management module; once system-level permissions are compromised, the file system's directory tree structure and underlying data pages face the risk of being directly read or logically corrupted.

[0003] Existing technologies attempt to introduce a hardware layer for storage isolation. For example, existing technologies directly call the TPM interface through the application layer to encapsulate the data stream written to the storage medium at the hardware level, preventing the data content from being directly exposed by the operating system cache. In addition, in virtualized storage architectures, existing technologies deploy backend processors in the virtual machine monitor, which intercept I / O requests and forward the virtual machine's data write operations to the hardware chip for processing, thus achieving hardware-level isolation of storage instructions.

[0004] However, when the above technologies are applied to high-concurrency file systems and structured databases, they have significant shortcomings in storage organization and retrieval mechanisms: First, there is a mismatch between the storage I / O model and hardware throughput. Modern file systems rely on high-speed block device read / write, while existing solutions directly map data read / write requests to low-speed hardware interaction commands. When performing high-frequency file metadata retrieval or full database table scans, this hardware interaction can cause severe I / O blocking, leading to a precipitous drop in storage system throughput and failing to meet real-time retrieval requirements. Second, there is a lack of index structures supporting encrypted retrieval. Existing technologies only focus on the disk-based format of data content, neglecting the construction of retrieval structures such as inverted indexes and B+ trees. Data loses its original lexical or numerical characteristics after hardware encapsulation, preventing database engines from establishing effective index paths at the storage layer. When performing queries based on specific conditions, the system is forced to degenerate into full data loading and parsing, significantly reducing information retrieval efficiency. Finally, file system metadata lacks underlying protection. Existing solutions protect the file data body, but critical metadata such as inodes, directory entries, and allocation tables describing file organization are still exposed to the software file system layer. Metadata determines the logical topology of data. Once the metadata structure is damaged, even if the data blocks are intact, the file system will be unable to address or recover the data due to logical chain breaks.

[0005] In summary, there is a need for a mechanism that deeply integrates hardware trust mechanisms into the file system's index building, metadata management, and I / O scheduling processes, ensuring the integrity of the storage structure while balancing data security and high-concurrency I / O throughput performance.

[0006] To address this, a data protection method and system based on TPM encryption is proposed. Summary of the Invention

[0007] The purpose of this invention is to provide a data protection method and system based on TPM encryption, which effectively balances data security protection and high-concurrency I / O throughput performance while ensuring the integrity of the storage structure.

[0008] To achieve the above objectives, the present invention provides the following technical solution: Data protection methods based on TPM encryption include: Extract the features of the indices and directory entries of the file storage structure to generate leaf node summaries; process the leaf node summaries according to hierarchical aggregation logic to generate root node summaries; measure the root node summaries to the platform configuration register, obtain the storage root key and authenticate the register value, output the hardware anchored topology and back it up; Parse the write request data stream to generate feature keywords; use the TPM hardware unique key to map and transform the feature keywords to generate hardware derived credentials and store them in the controlled cache; use the hardware derived credentials as keys to build a balanced search tree, and encapsulate the tree nodes of the balanced search tree to generate a ciphertext mapping index. Parse the target object type in the I / O request instruction; when the target object type is a metadata operation, calculate the feature summary of the target object type and perform a file logical integrity comparison with the hardware anchored topology; when the target object type is a data content operation, quantify the data content operation into a hardware evaluation value. If the hardware evaluation value meets the preset verification threshold, the hardware derived credential is verified by TPM and the data physical block is located based on the ciphertext mapping index; if the hardware evaluation value does not meet the preset verification threshold, the data physical block is obtained after being decrypted based on the ciphertext mapping index, and the verification operation is asynchronously pushed into the delay queue.

[0009] Preferably, the specific process of generating leaf node digests and root node digests includes: traversing the metadata area of ​​the file storage structure, extracting index node and directory entry features, wherein the index node includes index node number, permission bits and timestamp, and the directory entry features include file name and directory level pointer; performing cryptographic hash operations on the index node and directory entry features to generate a fixed-length message digest, which serves as the leaf node digest; according to hierarchical aggregation logic, performing binary serial concatenation on the leaf node digests of the same level in physical address order; performing hash operations on the concatenated leaf node digests, and recursively performing concatenation and hash operations upwards along the tree structure until a unique root node digest is generated.

[0010] Preferably, the specific process of outputting the hardware anchoring topology includes: overlaying the root node digest into the platform configuration register through an extension operation and updating the register value; obtaining the stored root key and performing a digital authentication operation on the register value to generate a hardware authentication credential carrying timing information; performing structured encapsulation on the root node digest and the hardware authentication credential, outputting the hardware anchoring topology and backing it up to the protected storage space of the trusted execution environment.

[0011] Preferably, the specific process of generating feature keywords, hardware derived credentials, and ciphertext mapping index includes: parsing file write operation instructions to extract payload data, performing semantic segmentation and noise filtering to extract feature keywords; using the TPM hardware unique key to perform key mapping transformation on the feature keywords, outputting a fixed-length binary sequence as a hardware derived credential and writing it into a controlled cache area; establishing a mapping relationship between the hardware derived credential and the physical storage address of the data, constructing a balanced search tree with the hardware derived credential as the key and the physical storage address of the data as the data value; performing structured encryption encapsulation on the tree nodes of the balanced search tree to generate a ciphertext mapping index.

[0012] Preferably, the specific process of parsing the target object type in the I / O request instruction includes: extracting the operation control code and target logical address pointer contained in the I / O request instruction; retrieving the address layout mapping table of the file storage structure; performing address matching between the target logical address pointer and the metadata storage area and data content storage area in the address layout mapping table; if the target logical address pointer falls into the metadata storage area, determining that the target object type is a metadata operation; if the operation control code belongs to the attribute change category, determining that the target object type is a metadata operation; when the target logical address pointer falls into the data content storage area, determining that the target object type is a data content operation.

[0013] Preferably, the specific process of performing file logical integrity comparison and quantifying data content operations into hardware evaluation values ​​for the metadata operation includes: when the target object type is confirmed to be a metadata operation, reading the indices and directory item features corresponding to the target logical addressing pointer; performing one-way mapping and hierarchical aggregation logic on the indices and directory item features to generate feature summaries; parsing the hardware anchoring topology to extract the root node summary, performing a consistency comparison between the feature summary and the root node summary, and outputting the logical integrity verification result; when the target object type is confirmed to be a data content operation, monitoring the response queue length and processing latency values ​​in the TPM interface instructions, performing a weighted summation operation, and outputting the hardware evaluation value.

[0014] Preferably, the specific process of verifying the hardware-derived credential through TPM and locating the data physical block based on the ciphertext mapping index includes: performing a numerical comparison between the hardware evaluation value and a preset verification threshold; when the hardware evaluation value meets the preset verification threshold, importing the feature keywords obtained by parsing and matching into the TPM internal isolation environment; performing a real-time mapping transformation on the feature keywords using the TPM hardware unique key to generate a baseline verification credential; retrieving the hardware-derived credential associated with the current operation from the ciphertext mapping index; performing a binary bitwise comparison between the baseline verification credential and the hardware-derived credential; outputting a verification pass instruction when the comparison results are consistent, and parsing the data physical storage address based on the ciphertext mapping index to obtain the data physical block; and outputting a verification failure instruction when the comparison results are inconsistent.

[0015] Preferably, the specific process of asynchronously pushing the verification operation into the delay queue based on the data physical block includes: if the hardware evaluation value does not meet the preset verification threshold, performing decapsulation processing on the ciphertext mapping index using the symmetric key to reconstruct the balanced search tree retrieval view; retrieving the hardware derived credential from the controlled cache as the retrieval key value to traverse the balanced search tree retrieval view and match the target index node; parsing the target index node and extracting the data physical storage address, locating the data physical block and performing data read / write access; extracting feature keywords, hardware derived credential, and the current operation time to encapsulate into a verification operation; asynchronously pushing the verification operation into the tail of the memory delay queue and suspending the TPM hardware verification instruction.

[0016] A data protection system based on TPM encryption includes: The hardware anchoring construction module extracts the features of the index nodes and directory entries of the file storage structure to generate leaf node summaries; processes the leaf node summaries according to hierarchical aggregation logic to generate root node summaries; measures the root node summaries to the platform configuration register, obtains the storage root key, authenticates the register value, outputs the hardware anchoring topology, and backs it up. The ciphertext index generation module parses the write request data stream to generate feature keywords; it maps and transforms the feature keywords using the TPM hardware unique key to generate hardware derived credentials and stores them in a controlled cache; it uses the hardware derived credentials as keys to build a balanced search tree and encapsulates the tree nodes of the balanced search tree to generate a ciphertext mapping index. The I / O verification scheduling module parses the target object type in the I / O request command. When the target object type is a metadata operation, it calculates the feature summary of the target object type and performs a file logical integrity comparison with the hardware anchoring topology. When the target object type is a data content operation, it quantifies the data content operation into a hardware evaluation value. If the hardware evaluation value meets the preset verification threshold, it verifies the hardware derivation certificate through TPM and locates the data physical block based on the ciphertext mapping index. If the hardware evaluation value does not meet the preset verification threshold, it obtains the data physical block after decryption based on the ciphertext mapping index and asynchronously pushes the verification operation into the delay queue.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention generates a root node digest from the inode and directory entry features of the file storage structure through hierarchical aggregation logic, and directly measures this digest to the platform configuration register, using the storage root key to digitally authenticate the register value. This hardware-software co-design strongly binds the metadata topology of the file storage structure to the trusted hardware state. Once the file metadata is tampered with at the disk level, the aggregated root digest will not match the hardware anchored topology, thus effectively solving the technical problem that the metadata integrity of traditional files cannot be directly verified by the hardware trusted root in offline attack scenarios.

[0018] 2. This invention employs a technique of parsing and writing data streams to extract characteristic keywords, and then using the TPM hardware's unique key to perform a mapping transformation on the keywords to generate hardware-derived credentials. By using this hardware-derived credential as a key to construct a balanced search tree and generate a ciphertext mapping index, the construction of the index itself must rely on the key of a specific physical chip. This achieves physical binding between data and hardware, preventing cross-device data reading after hard drive theft; furthermore, by utilizing the structural characteristics of the balanced search tree, the location and addressing of physical data blocks can be directly completed in the ciphertext index state, avoiding the performance loss of traditional solutions that require complete file decryption before locating content.

[0019] 3. This invention monitors the response queue length and processing latency of the TPM interface in real time and quantifies them into a hardware evaluation value. By comparing this hardware evaluation value with a preset verification threshold, when the hardware load is too high and the hardware evaluation value fails to meet the threshold, the physical block is directly located using the ciphertext mapping index to prioritize data read and write access. At the same time, the verification operation is encapsulated and pushed into a delay queue for suspension. This evaluation-based adaptive traffic distribution mechanism effectively smooths out I / O blocking jitter caused by hardware security devices without sacrificing eventual consistency security verification, achieving a dynamic balance between security level protection and performance throughput. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating the structure of the TPM-based data protection method of the present invention. Figure 2 This is a schematic diagram of the dynamic verification process based on hardware evaluation values ​​in an embodiment of the present invention; Figure 3 This is a schematic diagram of the TPM-based data protection system of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Please see Figures 1 to 3 This invention provides a data protection method and system based on TPM encryption, the technical solution of which is as follows: Example 1

[0023] Reference Figure 1 This is a flowchart illustrating the structure of the TPM-based encryption-based data protection method of the present invention. This embodiment provides a specific application scenario for the TPM-based encryption-based data protection method, primarily applied in high-security distributed storage nodes or classified archive file servers where data privacy and logical structure integrity are extremely important. In this application environment, the host server integrates a TPM2.0 trusted hardware chip compliant with the TCG specification. The underlying file storage structure not only needs to defend against external network attacks but also needs to address the risks of offline data theft and metadata tampering after the physical hard drive is stolen. Simultaneously, it must maintain high-concurrency I / O data stream read / write throughput performance while ensuring hardware-level trust anchoring. The specific operation steps are as follows: Extract the features of the index nodes and directory entries of the file storage structure to generate leaf node summaries; process the leaf node summaries according to hierarchical aggregation logic to generate root node summaries; measure the root node summaries to the platform configuration register, obtain the storage root key, authenticate the register value, and output the hardware anchored topology; Extract file data streams and perform word segmentation to generate feature keywords; use the TPM hardware unique key to map and transform the feature keywords to generate hardware derived credentials; use the hardware derived credentials as keys to build a balanced search tree, and encapsulate the tree nodes of the balanced search tree to generate a ciphertext mapping index. Parse the target object type in the I / O request command; when the target object type is a metadata operation, calculate the feature summary of the target object type and perform a file logical integrity comparison with the hardware anchored topology; when the target object type is a data content operation, quantize the TPM load obtained from the monitoring interface into a hardware evaluation value; If the hardware evaluation value meets the preset verification threshold, TPM is invoked to verify the hardware derived credentials. After successful verification, the data physical block is located based on the ciphertext mapping index. If the hardware evaluation value does not meet the preset verification threshold, the verification operation is asynchronously pushed into the delay queue based on the data physical block.

[0024] Furthermore, the specific process of generating leaf node digests and root node digests includes: traversing the metadata area of ​​the file storage structure, extracting index node and directory entry features, wherein the index node includes the index node number, permission bits, and timestamp, and the directory entry features include the file name and directory level pointer; performing cryptographic hash operations on the index node and directory entry features to generate a fixed-length message digest, which serves as the leaf node digest; according to hierarchical aggregation logic, performing binary serial concatenation on the leaf node digests of the same level in physical address order; performing hash operations on the concatenated leaf node digests, and recursively performing concatenation and hash operations upwards along the tree structure until a unique root node digest is generated.

[0025] Specifically, during the file protection initialization phase, the background scanning process traverses the metadata area of ​​the host server's file storage structure (such as Ext4 or NTFS format). It reads specific inode attributes, such as the inode number "Inode_8902", the permission control bit "0750", and the last modified timestamp "1709280000"; at the same time, it reads the corresponding directory entry characteristics, including the filename "system_config.dat" and a hexadecimal pointer to the parent directory.

[0026] The SHA-256 algorithm is used to perform cryptographic hashing on the extracted feature fields. The specific process is as follows: the above fields are arranged in a fixed order of "filename + inode number + access control bit + timestamp + level pointer"; to ensure the unique parsing of the data stream, a preset hexadecimal separator (such as "0x7C", i.e. the character "|") is inserted between each field, and a fixed-length indicator indicating the byte length of each field is added to the prefix of each field; the arranged combined fields are converted into a UTF-8 encoded binary bit stream as the input operator; the standard SHA-256 algorithm is called to perform one-way hashing, and a 64-bit fixed-length hexadecimal string is output as the leaf node digest.

[0027] When executing hierarchical aggregation logic, a bottom-up recursive processing mechanism is adopted, and the processing order of sibling nodes is standardized to eliminate hash ambiguity: First, the ascending order of the combination of "logical block address" and "inode number" is used as a globally unique sorting criterion. For all child items under the same parent directory, leaf nodes (specific files) are extracted first, and an initial sort is performed according to their inode numbers from smallest to largest. This logic ensures that the hash base of the logical hierarchy remains unchanged when performing defragmentation or physical sector migration.

[0028] If both leaf nodes and intermediate nodes (subdirectories) exist under the same parent directory, the priority concatenation logic based on node type is executed: the summaries of all leaf nodes are concatenated in binary serial order according to the aforementioned sorting rules, and 4-byte check bits are filled between each summary to generate the "file feature block" of the directory; then, the parent node summaries of each subdirectory that have been calculated are obtained, sorted in lexicographical order according to their directory names, and used as suffixes immediately after the "file feature block" for a second binary serial concatenation.

[0029] The concatenated complete data stream is then subjected to a second SHA-256 operation to generate a digest of the parent node at the current level. This process recursively ascends along the directory tree structure until all branches converge at the root directory, outputting a unique root node digest. When an addition or deletion operation occurs, only the affected leaf node path needs to be located, and the local recursive calculation from that node to the root directory is retried according to the aforementioned standard sorting rules, thereby achieving dynamic consistency maintenance of the hardware-anchored topology.

[0030] This technical solution maps scattered file metadata features to a hierarchical hash structure, compressing the entire logical state into a unique root node digest value. This ensures that any subtle tampering with file permissions, names, or storage locations will trigger an avalanche-like change in the root digest through hierarchical transmission, thus providing a highly sensitive verification benchmark for TPM hardware anchoring.

[0031] Furthermore, the specific process of outputting the hardware anchoring topology includes: overlaying the root node digest into the platform configuration register through an extension operation and updating the register value; obtaining the stored root key and performing digital authentication operations on the register value to generate a hardware authentication credential carrying timing information; performing structured encapsulation on the root node digest and the hardware authentication credential, outputting the hardware anchoring topology and backing it up to the protected storage space of the trusted execution environment.

[0032] Specifically, after the root node digest is calculated, the TPM hardware interface is called, and the 256-bit root node digest is used as the input parameter to perform an extension operation on the specified platform configuration register (e.g., PCR index number 10) to write the root node digest overlaid into the platform configuration register.

[0033] To avoid the avalanche effect of PCR expansion operations that could lead to frequent failures of the hardware anchored topology, in high-frequency write scenarios with thousands of writes per second, PCR expansion of the physical TPM is not directly triggered in real time. Instead, a "shadow register" and "batch merging" mechanism is introduced: First, the root node digests that change frequently are hashed and accumulated in the shadow register of a trusted memory region. When the accumulation count reaches a preset threshold or is in an idle state, the final digest value of the shadow register is used as a single increment to perform a one-time expansion on the physical TPM. This "many-to-one" synchronization mechanism effectively alleviates the pressure of unlimited PCR value extension and ensures the performance stability of the hardware anchored topology.

[0034] The specific operation process of performing the superimposed write is as follows: First, read the current original value in the platform configuration register; use the original value as the first operator and the root node digest as the second operator, and perform binary serial concatenation in a preset order to generate a combined bit stream; call the same hash algorithm as that used to generate the leaf node digest, perform hash operation on the combined bit stream, and write the hash value obtained from the operation back to the platform configuration register to complete the value update.

[0035] Subsequently, the asymmetric signature private key stored in the hardware is obtained as the storage root key, and a digital authentication operation is performed on the updated platform configuration register value. A trusted reference instruction (TPM2_Quote) is sent to the TPM, digitally signing the current PCR value using the storage root key, and introducing a hardware-generated random number to prevent replay attacks. The digital authentication operation process includes: concatenating the updated register value with the current hardware clock counter value and the random number; extracting the encrypted digest of the concatenated data using the storage root key; and generating an unforgeable binary data block as the hardware authentication credential. During this process, a unique event sequence number is associated with this PCR update operation, and this sequence number is synchronously recorded in a backup copy to ensure that the cumulative state of the PCR can be restored according to the event sequence during the boot or topology verification phase, achieving deterministic backtracking of the hardware anchoring state.

[0036] Finally, the original root node digest and hardware authentication credentials are structurally encapsulated according to a predefined identifier length field format, which consists of a type identifier, a length declaration, and a data payload. The byte length of the root node digest is written into the length declaration, and the original digest text is filled into the data payload; the length of the hardware authentication credentials is calculated and written into the length declaration, and then binary data is filled into the data payload; the data blocks are concatenated in binary serial order according to a preset order, and a start delimiter is added to the header to output the hardware anchoring topology.

[0037] This technical solution achieves a strong binding between file state and specific physical host machine by physically "imprinting" the root digest at the software level to the hardware register and applying a digital signature. This mechanism ensures that the hardware-anchored topology has non-repudiation and timeliness; any topology data forged by bypassing the hardware environment cannot be verified due to the lack of a correct storage root key signature.

[0038] Furthermore, the specific process of generating feature keywords, hardware derived credentials, and ciphertext mapping index includes: parsing file write operation instructions to extract payload data, performing semantic segmentation and noise filtering to extract feature keywords; using the TPM hardware unique key to perform key mapping transformation on the feature keywords, outputting a fixed-length binary sequence as a hardware derived credential and writing it into a controlled buffer; establishing a mapping relationship between the hardware derived credential and the physical storage address of the data, constructing a balanced search tree with the hardware derived credential as the key and the physical storage address of the data as the data value; and performing structured encryption encapsulation on the tree nodes of the balanced search tree to generate a ciphertext mapping index.

[0039] Specifically, when the execution entity intercepts a file write request at the underlying driver level, it parses the data packet structure of the request and separates the payload data in plain text or binary form as a file data stream. The file data stream is then segmented. For example, for a text stream containing confidential engineering drawing data, meaningless conjunctions are filtered out based on a pre-defined stop word list. This pre-defined stop word list is a lexicon pre-built based on file metadata features and language logic, selecting character fragments with independent referential meaning as feature keywords. To eliminate encoding ambiguity, the feature keywords are uniformly converted into raw byte streams in UTF-8 encoding format. If the length of a single byte stream does not meet the 512-bit block size, padding is performed according to the PKCS#7 standard to ensure the standardization of operator length.

[0040] Subsequently, the raw byte stream after feature keyword processing is input into the trusted hardware. The TPM hardware unique key (256 bits long), embedded within the chip and not exportable, is invoked to perform a hash message authentication code operation on the feature keywords based on the standard SHA-256 algorithm. The specific process of performing the hash message authentication code operation includes: The unique TPM hardware key is obtained and processed into an internal padding key and an external padding key according to a preset logical operator, so that the operation process of the feature keyword is deeply coupled with the hardware fingerprint; the preset logical operator includes a first XOR constant term and a second XOR constant term.

[0041] First-stage hashing: Pad the TPM hardware unique key with zeros to the end to make it 512 bits, and perform a bitwise XOR operation with the preset first XOR constant (hexadecimal value 0x36) to obtain a 512-bit internal padding key; Second-stage hashing: Perform a bitwise XOR operation between the same TPM hardware unique key and a preset second XOR constant (hexadecimal value 0x5C) to obtain a 512-bit external padding key.

[0042] Subsequently, the internal padding key and the feature keyword byte stream are concatenated and concatenated, and the first round of SHA-256 hash operation is performed to output the first intermediate hash value. Next, the external padding key and the first intermediate hash value are concatenated in binary serial form, and the second round of SHA-256 hash operation is performed, ultimately outputting a 256-bit fixed-length hardware derived credential. Through these two rounds of hash locking, a strong physical binding is established between the hardware derived credential and the TPM hardware unique key.

[0043] After obtaining the hardware derivation credential, the operation of establishing a mapping relationship between the hardware derivation credential and the physical storage address of the data is performed. The balanced search tree specifically adopts a B+ tree structure, with its order set to m (e.g., m=256). The tree nodes of the B+ tree use a structured layout, and each internal node contains an array of key-value pairs. The node attribute fields include node level, current number of key-value pairs, and parent node pointer; where Key is the hardware-derived credential and Pointer is the physical address pointer to the child node.

[0044] Subsequently, following the data structure rules of a balanced search tree (B+ tree), the key-value pair data units are inserted into the index tree. When the number of key-value pairs in a node reaches m, the node is split to ensure the tree's hierarchical balance. Finally, structured encryption is performed on the tree nodes to generate a ciphertext mapping index. Specifically, for each B+ tree node to be permanently stored, a preset 256-bit symmetric key (such as an AES-256 key) is used to encrypt the entire data of the node in GCM mode using the Advanced Encryption Standard (AES).

[0045] The AES-GCM mode not only converts key-value pairs and pointer arrays into ciphertext, but also simultaneously generates a 128-bit authentication tag. The symmetric key is distributed in a controlled manner from the non-volatile memory within the TPM and is loaded into the memory isolation area via the authorization bus only when verifying hardware evaluation values ​​or executing asynchronous desealing logic.

[0046] By independently encrypting and encapsulating the data, the complete index structure residing on the storage medium is presented as a ciphertext mapping index.

[0047] The encrypted mapping index exists in physical storage as encrypted blocks. During a search, the processing logic does not blindly decrypt globally; instead, based on the current traversal path, it reads the target node into a memory isolation area and performs real-time decryption to restore the numerical relationships of the hardware-derived credentials within that node. After determining the direction of the next level pointer using the comparison logic of the balanced search tree, the plaintext memory of the current node is immediately released. This ensures that without decryption authorization, it is impossible to obtain data distribution logic or perform reverse keyword derivation by traversing the storage medium.

[0048] This technical solution utilizes non-transferable hardware keys to generate index key values, enabling a strong cryptographic binding between the data index and a specific physical host. Even if the physical storage medium is moved to another device, the index structure cannot be restored due to the lack of the corresponding hardware key. Simultaneously, the balanced search tree structure of the ciphertext state supports rapid location without decrypting the entire file, balancing high data security with retrieval efficiency.

[0049] Furthermore, the specific process of parsing the target object type in the I / O request instruction includes: extracting the operation control code and target logical addressing pointer contained in the I / O request instruction; retrieving the address layout mapping table of the file storage structure; performing address matching between the target logical addressing pointer and the metadata storage area and data content storage area in the address layout mapping table; if the target logical addressing pointer falls into the metadata storage area, determining that the target object type is a metadata operation; if the operation control code belongs to the attribute change category, determining that the target object type is a metadata operation; when the target logical addressing pointer falls into the data content storage area, determining that the target object type is a data content operation.

[0050] Specifically, when the underlying driver intercepts an input / output request, it parses the header information of the request data packet to extract the operation control code representing the specific action and the target logical address pointer used to locate the storage location. Subsequently, it retrieves the address layout mapping table of the file storage structure. This mapping table is a dynamic mapping relationship generated by parsing the superblock and block group descriptors, which clearly defines the boundary between the metadata storage area and the data content storage area in the storage medium.

[0051] When the target logical addressing pointer falls within the edge threshold range of the metadata storage area, a calibration judgment is performed. The edge threshold range refers to a preset deviation (e.g., set to 1024 logical block lengths) extending from the boundary address of the metadata storage area towards the data content storage area, used to cover address overlap areas caused by delayed allocation. During calibration, the correlation weight is calculated by comparing with a preset metadata feature template. The preset metadata feature template includes: Structure guide template: contains a predefined inode start position, a fixed offset for the directory entry, and its corresponding specific hexadecimal modulus; Logical topology template: contains the link count value in the block group descriptor and the format characteristics of the parent node pointer.

[0052] The specific process of performing the address matching is as follows: the extracted target logical addressing pointer is compared with the interval threshold in the address layout mapping table. If the pointer value falls within the metadata storage interval, the current operation object is determined to be a metadata operation. As a preferred implementation, when the target logical addressing pointer falls within the edge threshold range of the metadata storage interval, the storage sector context corresponding to the target logical addressing pointer is retrieved, and the data structure identifier therein is extracted; the correlation weight between the data structure identifier and the preset metadata feature template is calculated; and the address matching result is calibrated based on the correlation weight to determine the target object type.

[0053] Specifically, when the pointer is located at the boundary of an interval, the prefix bytes of the logical block pointed to by the pointer are read in advance as context, and the presence of a directory entry header character is searched within it. If the correlation weight between the extracted identifier and the preset metadata feature template containing inode format characteristics exceeds the edge threshold, it is determined to be a metadata operation, thereby eliminating ambiguity in dynamic storage allocation scenarios. If the extracted operation control code, after comparison with a preset mask, is confirmed to belong to the attribute change category such as permission modification, timestamp change, or owner change, the current request is determined to be a metadata operation; conversely, if the pointer value falls within the data content storage interval and the operation control code is a standard block read / write instruction, the current operation object is determined to be a data content operation. In this determination process, cross-validation of address space, instruction semantics, and content features ensures accurate identification of structural changes and pure data throughput.

[0054] This technical solution achieves precise separation of metadata maintenance operations from ordinary data read / write operations by performing dual analysis of the address characteristics and instruction semantics of I / O instructions. This mechanism lays the foundation for subsequent implementation of differentiated protection strategies, ensuring strict topology consistency verification of critical file structure changes, and enabling load-adaptive hardware evaluation value detection for massive data throughput, thus achieving a balance between fine-grained security control and overall performance.

[0055] Furthermore, the specific process of performing file logic integrity comparison for metadata operations and quantifying data content operations into hardware evaluation values ​​includes: when the target object type is confirmed to be a metadata operation, reading the indices and directory entry features corresponding to the target logical addressing pointer; performing one-way mapping and hierarchical aggregation logic on the indices and directory entry features to generate feature summaries; parsing the hardware anchoring topology to extract the root node summary, performing consistency comparison between the feature summary and the root node summary, and outputting the logical integrity verification result; when the target object type is confirmed to be a data content operation, monitoring the response queue length and processing latency values ​​in the TPM interface instructions, performing weighted summation operations, and outputting hardware evaluation values.

[0056] Specifically, when it is determined that the current operation is targeting metadata, the real-time index node number, permission bit data, and directory pointer corresponding to the file are read.

[0057] The process of executing the hierarchical aggregation logic is as follows: perform a hash operation on the above-mentioned index node and directory item features to generate the current branch summary, and retrieve the intermediate node summaries of the other non-changed branches. Perform recursive hash superposition according to the hierarchical correspondence until the real-time root node summary covering the entire set is derived as the feature summary.

[0058] Subsequently, the previously established hardware anchoring topology is decapsulated from memory, and the root node digest of the initial storage is parsed and extracted. A binary bit-by-bit consistency comparison is performed between the feature digest and the root node digest. If they are completely identical, the logical integrity verification result is output.

[0059] On the other hand, when a data content operation is confirmed, a hardware evaluation mechanism is initiated. Since some TPM chips do not expose the queue status of their internal registers, this embodiment uses a driver-level interception method to obtain real-time parameters: the specific monitoring process is executed by a monitoring hook function pre-embedded in the TPM device driver layer. This hook function intercepts the push and pop timestamps of underlying transmission functions (such as the tpm_transmit function in Linux), calculates the difference between sending the command and receiving the complete response message, and defines it as the processing latency; simultaneously, it counts the number of submitted but not yet responded commands in the driver-level circular buffer in real time, defining it as the response queue length. This method does not require sending additional query commands to the TPM, avoiding secondary consumption of hardware bandwidth.

[0060] The maximum capacity of the hardware response queue and a preset processing latency threshold are pre-defined. These pre-defined maximum capacity and processing latency threshold are determined based on the physical characteristics and throughput limits of the trusted hardware, specifically including: Maximum capacity value: Set based on the physical overflow limit of the hardware response buffer. For example, if the maximum depth of the instruction concurrent processing queue is 16 or 32 according to the design specifications of the Trusted Platform Module, then this physical limit value is set as the maximum capacity value to assess the current percentage of instruction backlog. Processing latency threshold: Set according to the maximum allowable I / O wait latency for the business (e.g., set to 100 milliseconds). For example, in a real-time file interaction scenario, if a hardware latency exceeding 100 milliseconds will cause an application-layer timeout, then 100 milliseconds is set as the processing latency threshold to assess the degree of lag in hardware operations.

[0061] The specific process of performing the numerical normalization and weighted summation operations is as follows: First, normalization is performed. The real-time response queue length is divided by the maximum capacity value to obtain the queue saturation score; the real-time processing latency is divided by the processing latency threshold to obtain the latency pressure score. To handle boundary anomalies, it is stipulated that if the response queue length or processing latency is 0, the corresponding score is 0; if the processing latency exceeds the threshold, the latency pressure score is forcibly set to the upper limit of 1.0. Subsequently, a linear weighted summation is performed using preset weighting coefficients, and the hardware evaluation value is output.

[0062] Hardware evaluation value = (queue saturation weight × queue saturation score) + (latency stress weight × latency stress score); In this configuration, the queue saturation weight plus the latency pressure weight equals 1. In this example, for high-throughput storage scenarios, the queue saturation weight is set to 0.6, and the latency pressure weight to 0.4. The technical basis for this coefficient allocation is that in memory, instruction backlog (queue depth) reflects the sustained load saturation of the hardware processor more effectively than single latency fluctuations; therefore, the queue metric is given a higher weight. The dynamic adjustment mechanism will periodically monitor the application layer's I / O timeout rate. If the timeout rate exceeds a preset percentage (e.g., 5%), the latency pressure weight will be automatically increased to improve sensitivity to latency fluctuations.

[0063] In a preferred embodiment, the steps after outputting the hardware evaluation value further include: comparing the hardware evaluation value with a preset load security threshold; when the hardware evaluation value is lower than the load security threshold, performing synchronous hardware authentication verification on the current data content operation; when the hardware evaluation value exceeds the load security threshold, marking the current data content operation as a delayed verification item, and switching from synchronous verification mode to background delayed verification mode based on asynchronous task queue.

[0064] Specifically, a load safety threshold is set (e.g., 0.75). When the calculated hardware evaluation value is lower than this threshold, it indicates that the hardware still has the capacity to handle real-time computation. At this time, real-time synchronous hardware authentication verification is performed on all data operations to ensure strong atomicity of data writing and verification.

[0065] Conversely, if a large-scale burst of writes causes the hardware evaluation value to exceed 0.75, it indicates that continuing synchronous verification will lead to severe I / O queuing and application-layer timeouts. In this case, the current data operation is marked as a delayed verification item, and the system automatically switches to asynchronous mode. In asynchronous mode, the physical write of data is completed first, while the related authentication operations are pushed into a background queue for processing. Verification is then performed to complete the verification once the hardware evaluation value falls back to a safe range.

[0066] This solution achieves adaptive contraction of security policies, which dynamically alleviates the computational pressure on trusted hardware during peak data periods and avoids performance collapse while ensuring the absolute integrity of core metadata.

[0067] This technical solution adopts a differentiated verification strategy: strict "full-path hash comparison" is implemented on metadata to ensure that the logical skeleton has not been tampered with; and "hardware evaluation value quantification" is implemented on data content operations. By evaluating hardware throughput pressure in real time, a quantitative decision basis is provided for subsequent dynamic mode switching between "synchronous security verification" and "asynchronous delay verification".

[0068] Furthermore, the specific process of verifying hardware-derived credentials through TPM and locating data physical blocks based on ciphertext mapping index includes: performing a numerical comparison between the hardware evaluation value and a preset verification threshold; when the hardware evaluation value meets the preset verification threshold, importing the feature keywords obtained by parsing and matching into the TPM internal isolation environment; performing real-time mapping transformation on the feature keywords using the TPM hardware unique key to generate a baseline verification credential; retrieving the hardware-derived credential associated with the current operation from the ciphertext mapping index; performing a binary bitwise comparison between the baseline verification credential and the hardware-derived credential; outputting a verification pass instruction when the comparison results are consistent, and parsing the data physical storage address according to the ciphertext mapping index to obtain the data physical block; and outputting a verification failure instruction when the comparison results are inconsistent.

[0069] Specifically, a preset verification threshold reflecting the hardware load tolerance is pre-set. This preset verification threshold is a baseline percentage based on the maximum authentication frequency the hardware can handle per unit time, serving as the boundary between real-time and delayed verification. When the calculated hardware evaluation value is less than or equal to this threshold, it indicates that the current hardware is in an unsaturated state and meets the real-time verification conditions. At this time, the feature keywords to be written or read are imported into the internal isolation environment through the protected hardware bus. Considering the fixed nature of the hardware controller logic of standard physical buses (such as SPI or LPC), the specific process of importing the feature keywords into the TPM internal isolation environment does not directly modify the physical layer signals, but rather performs application protocol obfuscation at the software payload layer within the framework of the standard TCG communication protocol.

[0070] The specific process of importing the feature keywords into the TPM internal isolation environment includes: obtaining the transmission limit of the current communication protocol; generating a random redundant payload with a length limited by the limit; performing bit-level interleaving and encapsulation of the feature keywords and the random redundant payload to generate an obfuscated data packet conforming to the bus protocol frame format; importing the obfuscated data packet into the internal isolation environment through the physical transmission bus, and performing reverse deinterleaving and restoration using a synchronization factor to extract the feature keywords.

[0071] Specifically, the maximum transmission unit payload length allowed by the current bus communication protocol is detected. A set of pseudo-random binary sequences with a length limited to this payload length is generated as random redundant payloads. According to a preset bit-level interleaving algorithm, feature keywords are discretely embedded into the random redundant payloads to construct obfuscated data packets that conform to the standard bus protocol frame structure (such as FIFO or TIS instruction format conforming to TPM2.0 specification) and exhibit random distribution characteristics on the logical link.

[0072] The specific process of executing the preset bit-level interleaving algorithm includes: The random disturbance value of the current hardware clock is obtained as the step size factor; the feature keyword is divided into bit segments of length M, and the random redundant payload is divided into mask segments of length N; according to the step size factor, the bit segments are nonlinearly inserted into the gaps of the mask segments to generate an obfuscated data packet with random distribution characteristics on the logical link; the step size factor is encapsulated in the reserved field of the protocol frame as a synchronization factor for restoring data in the internal isolation environment.

[0073] The specific method of nonlinear insertion is as follows: using the step size factor as the initial offset, a cyclic shift mapping address is calculated in the mask segment, and the bit segments are discretely embedded into the gaps corresponding to the mapping addresses. Subsequently, the step size factor is encapsulated through the authorized session or protected parameter area (such as the parameter part protected by HMAC) in the TPM standard instructions. Since the step size factor is hidden in the parameter stream conforming to the TCG standard, it not only avoids illegal occupation of reserved fields in the standard protocol frame, but also ensures that the data packet can be recognized and transparently transmitted by the standard physical controller.

[0074] Once the obfuscated data packet enters an internal isolation environment (such as the TPM internal processing unit or the TEE security zone), controlled parsing code running within this environment extracts a synchronization factor (i.e., a step size factor) from the protected parameter stream. It then performs reverse nonlinear extraction and bit concatenation logic to accurately reconstruct the original feature keywords. This scheme dynamically adjusts the interleaving step size, ensuring that even if the payload of a data packet captured on the bus physical link is parsed, the true keyword content cannot be reconstructed without the synchronization factor, effectively improving the defense against physical probing.

[0075] Using an internally stored, unreadable TPM hardware unique key, a real-time mapping transformation is performed on the feature keywords to generate a temporary baseline verification credential. The specific process of performing this real-time mapping transformation includes: Retrieve the hash message authentication code algorithm logic that is completely identical to that used when initially generating the hardware derived credential, and load the same first XOR constant term and second XOR constant term; use the TPM hardware unique key to perform bitwise XOR again with the first and second XOR constant terms to reconstruct the internal padding key and external padding key that are strongly bound to the current physical hardware environment; perform the first stage hash with the imported feature keywords and the reconstructed internal padding key, and perform the second stage hash with the obtained intermediate value and the external padding key to output the benchmark verification credential.

[0076] The logic for performing the real-time mapping transformation must be consistent with the aforementioned process of generating hardware-derived credentials to ensure the uniqueness of the output results under the same key environment. Simultaneously, the hardware-derived credential associated with the current operation is retrieved from the ciphertext mapping index on the storage medium.

[0077] The binary bitwise comparison of the baseline verification credential and the hardware-derived credential is performed: if they match perfectly, it proves that the current operation request originates from legitimate physical hardware and the index structure has not been tampered with. Subsequently, a verification pass instruction is output, and the associated encrypted index node is decrypted to parse the logical block address or sector number of the data on the storage medium. Based on the parsed address, a low-level access instruction is sent to the storage controller to locate and read the corresponding target data physical block. If the comparison does not match, it is determined to be an illegal hardware transplant or index tampering attack, and a blocking operation is immediately performed, referring to... Figure 2 .

[0078] This technical solution employs a synchronous verification mechanism of "real-time calculation - real-time comparison" to ensure that every data access request must undergo on-site authentication by the hardware root of trust. This process eliminates the possibility of unauthorized access using forged indexes or by copying hard drive data on unauthorized devices, achieving real-time strong binding between data access permissions and physical hardware identity.

[0079] Furthermore, the specific process of asynchronously pushing the verification operation into the delay queue based on the data physical block includes: if the hardware evaluation value does not meet the preset verification threshold, using the symmetric key to perform decapsulation processing on the ciphertext mapping index and reconstructing the balanced search tree retrieval view; retrieving the hardware derived credential from the controlled cache as the retrieval key value to traverse the balanced search tree retrieval view and match the target index node; parsing the target index node and extracting the data physical storage address, locating the data physical block and performing data read / write access; extracting feature keywords, hardware derived credentials and the current operation time and encapsulating them into a verification operation; asynchronously pushing the verification operation into the tail of the memory delay queue and suspending the TPM hardware verification instruction.

[0080] Specifically, when the calculated hardware evaluation value fails to meet the preset verification threshold, the current hardware is determined to be in a high-load congestion state, and the verification operation is asynchronously pushed into the delay queue.

[0081] The basis and physical meaning of setting the preset verification threshold include: Hardware response deterministic benchmark: preset based on the maximum load percentage of the hardware certification chip while maintaining linear response time. For example, if stress testing determines that when the hardware load exceeds 80%, its instruction processing latency will exhibit non-linear jumps, then 0.8 is set as the preset verification threshold; Business tolerance benchmark: set according to the sensitivity of the application scenario to I / O latency. In high-performance file access scenarios, to ensure the real-time performance of data reading and writing, the preset verification threshold can be set at a lower level (e.g., 0.7) to trigger asynchronous mode earlier to smooth the load.

[0082] The specific process of performing the decapsulation process and locating the physical data block includes: retrieving the symmetric key pre-stored in a protected area of ​​the kernel (such as an SGX secure enclave); performing software-level decryption on the ciphertext mapping index in a controlled kernel context; and reconstructing the balanced search tree retrieval view. Since the TPM is under high load at this time, it no longer calls the hardware to generate credentials, but directly retrieves the pre-stored hardware-derived credentials from the controlled cache as the retrieval key, traversing the balanced search tree retrieval view to match the corresponding target index node. Subsequently, the target index node is parsed and the physical storage address of the data is extracted. Based on this, an instruction is sent to the storage controller to locate the physical data block, and data read / write access is given priority.

[0083] While granting access, the current time is obtained as the operation time data. The characteristic keywords, hardware-derived credentials, operation time data, and the block index of the corresponding physical data block are then associated and encapsulated to generate a verification operation object with a unique transaction ID. To prevent attackers from tampering with the "time window" at the kernel level, the TPM's internal message authentication interface is called, and a hardware-level message authentication code is calculated for the verification operation object using a non-exportable hardware key.

[0084] Subsequently, the verification operation object carrying the hardware-level message authentication code is written to the tail of the memory delay queue, and a "transaction table to be verified" is maintained in memory simultaneously, recording the mapping relationship between transaction IDs and corresponding process PIDs. At this point, the real-time hardware verification instruction for this access is suspended, allowing hardware resources to prioritize high-priority scheduled tasks.

[0085] The delay queue is consumed by an independent daemon thread in kernel mode when the hardware evaluation value falls back to a safe range. If the verification feedback fails, the following compensation process is executed: Logical isolation: Block subsequent write-back operations on the affected data blocks based on the transaction ID; State rollback: Using file logs or snapshot copies, restore the file storage structure to a trusted state before this asynchronous I / O; Audit evidence storage: The characteristic keywords of the verification failure and the PCR register value are recorded as error event logs and forcibly written back to the non-volatile storage area of ​​TPM.

[0086] This technical solution effectively addresses the I / O blocking issue caused by the low throughput of TPM hardware in scenarios with sudden high concurrency traffic by employing an asynchronous optimistic strategy of "execute first, verify later." This mechanism, while ensuring eventual data security and consistency, utilizes a memory queue to smooth out hardware performance fluctuations, ensuring low-latency response capabilities for critical business operations.

[0087] This invention achieves a deep integration of security strength and performance through hardware-software collaborative anchoring and adaptive load scheduling. First, by using TPM hardware to solidify the file topology, the risks of unauthorized migration and offline tampering of storage media are effectively eliminated. Second, an encrypted balanced search tree is constructed based on the unique key of the TPM hardware, enabling on-demand decryption and location in encrypted states, significantly improving retrieval efficiency while ensuring data privacy. Finally, by introducing a hardware-aware asynchronous verification mechanism, the I / O blocking problem caused by low throughput of domestically developed hardware is successfully solved, building an inherently secure protection system with performance elasticity while ensuring business continuity in high-concurrency scenarios.

[0088] Example 2

[0089] Reference Figure 3 This is a schematic diagram of the TPM-based encryption data protection system of the present invention. This embodiment provides a specific application scenario for the TPM-based encryption data protection system. The system is deployed in a high-performance file server equipped with a trusted computing chip, and achieves full lifecycle protection of stored data through a modular hardware and software collaborative architecture. Logically, the system is divided into a hardware anchoring construction module, a ciphertext index generation module, and an I / O verification scheduling module. The specific functions of each module are implemented as follows: Hardware Anchoring Construction Module: This module runs at the operating system kernel level and is responsible for establishing a trusted baseline for the file system. Specifically, this module periodically or during the system boot phase traverses the metadata area of ​​the file storage structure, reading inode features including inode numbers, permission control bits, and modification timestamps, as well as directory entry features containing filenames and hierarchical relationships. This module performs a one-way hash operation on these features to generate leaf node digests, and recursively concatenates digests of the same level according to physical address order based on hierarchical aggregation logic, ultimately generating a unique root node digest. Subsequently, this module calls the trusted hardware interface to overlay the root node digest into the specified platform configuration register, and calls the stored root key to perform digital authentication operations on the updated register value, generating a hardware anchoring topology containing time-series signature information, thereby solidifying the logical structure state of the file system into the physical hardware.

[0090] The encrypted index generation module: When a new file write request is detected, the filtering driver selects feature keywords from the payload data stream to be written and transmits them to the TPM chip via the secure bus. Using the TPM hardware-unique key, which is fuse-broken and non-exportable within the chip, an asymmetric mapping transformation is performed on the feature keywords to derive a hardware-derived credential with physical identity attributes. Using this hardware-derived credential as the retrieval key, the logical block address of the data on the disk is encapsulated as an association value to construct a balanced search tree. Block encryption is performed on each node of the balanced search tree using a symmetric key to generate an encrypted mapping index residing on the storage medium. This structure ensures that the index view cannot be effectively retrieved or traversed due to key loss when removed from the current physical hardware environment.

[0091] I / O verification and scheduling module: When processing I / O request commands in real time, the system performs target object identification by parsing the operation control code and address pointer of the command. Metadata integrity verification: If the target is a metadata operation such as renaming or permission modification, the feature digest of the target object is calculated in real time, and the feature digest is matched bit by bit with the baseline value in the hardware anchoring topology to ensure that the file system logical skeleton has not been illegally tampered with.

[0092] Data access load balancing: If the target is data reading and writing, the command response queue length and processing latency of the TPM interface are obtained in real time. Hardware evaluation values ​​are quantified and output by performing normalized weighted calculations on the parameters.

[0093] When the hardware evaluation value is within the preset verification threshold, the synchronous verification path is executed: at this time, the hardware resources are sufficient, the system directly calls TPM to perform real-time verification of the hardware derived credentials, and decrypts the ciphertext mapping index according to the comparison result, so as to achieve strong security control of "authentication first, access later".

[0094] When the hardware evaluation value exceeds the preset verification threshold, an asynchronous verification path is executed: To ensure I / O throughput in high-concurrency scenarios, the system prioritizes using the session key in memory to software decapsulate the index and allow physical block access. At the same time, the system encapsulates the feature keywords, credentials, and operation timestamps into verification objects and pushes them into a memory delay queue, where a background process completes "retrospective" verification after the hardware load decreases.

[0095] To verify the effectiveness of this solution in balancing security and performance, this embodiment underwent stress testing in the following environment: a standard server equipped with dual standard voltage processors, 64GB of memory, and TPM2.0 hardware modules, running Linux Kernel 5.4 and using Ext4 file system.

[0096] Quantitative comparison experiment of throughput and latency: In a simulated high-concurrency write scenario of 10,000+ IOPS, when using a traditional synchronous hardware verification scheme, the average I / O latency of the system surged from 3ms to over 120ms due to limitations in the serial processing capability of the TPM hardware, resulting in a throughput decrease of approximately 70%. However, with the adaptive asynchronous verification mechanism of this scheme, the system automatically switches to the asynchronous path when the hardware evaluation value triggers the 0.8 threshold. Tests show that the average I / O latency at the application layer stabilizes between 5ms and 8ms, and the overall system throughput remains above 92% of the baseline value, successfully avoiding the performance collapse caused by hardware bottlenecks.

[0097] Memory Consumption and Capacity Strategy of Delayed Queues: To address the memory overhead introduced by asynchronous verification, this embodiment sets a dynamic capacity limit for the delayed queue. Capacity Limit Setting: The maximum depth of the delayed queue is set to N = 1,000,000 verification operation objects. Assuming each object contains approximately 256 bytes of feature keywords, credentials, and MAC addresses, its maximum memory usage is approximately 256MB. For a system with 64GB of memory, this is less than 0.4%, having a negligible impact on system stability. Overflow Handling Strategy: If the delayed queue reaches its capacity limit and the hardware evaluation value does not decrease, the system will activate a "backpressure" mechanism: temporarily reducing the I / O priority of non-core processes, or forcibly discarding some low-risk verification tasks and recording them in the security audit log, prioritizing the continuity of access between the system kernel and high-priority applications.

[0098] Computational overhead analysis: During the decapsulation process of the ciphertext mapping index, due to the use of the AES-256-GCM symmetric encryption algorithm, the computational pressure is mainly shared by the CPU's AES-NI hardware acceleration instruction set. Test monitoring shows that when performing large-scale index reconstruction, the CPU utilization rate only increases by about 3% to 5%, which is far lower than the CPU context switching overhead caused by I / O wait.

[0099] This system achieves hardware-level tamper-proofing of the file logical structure through the combination of hierarchical aggregation logic and platform configuration register anchoring. It utilizes the TPM hardware unique key to generate hardware-derived credentials and constructs a ciphertext mapping index, strongly binding data to specific physical hardware to prevent unauthorized cross-device access and supporting fast addressing in ciphertext environments. Furthermore, by quantifying hardware evaluation values ​​and adaptively scheduling synchronous verification and asynchronous delay queues, it effectively resolves the conflict between the low-speed characteristics of trusted hardware and high-concurrency I / O requirements, achieving a dynamic balance between high-level data security and high-performance system throughput.

[0100] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A data protection method based on TPM encryption, characterized in that, include: Extract features from the inodes and directory entries of the file storage structure to generate leaf node summaries; The root node summary is generated by processing the leaf node summaries according to hierarchical aggregation logic. The root node digest is measured to the platform configuration register, the root key is obtained and the register value is authenticated, the hardware anchored topology is output and backed up; Parse the write request data stream to generate feature keywords; The TPM hardware unique key is used to map and transform the feature keywords to generate hardware derived credentials, which are then stored in a controlled cache. The hardware derived credentials are used as keys to build a balanced search tree, and the tree nodes of the balanced search tree are encapsulated to generate a ciphertext mapping index. Parse the target object type in the I / O request command; When the target object type is metadata operation, calculate the feature summary of the target object type and perform a file logical integrity comparison with the hardware anchoring topology; when the target object type is data content operation, quantify the data content operation into a hardware evaluation value. If the hardware evaluation value meets the preset verification threshold, the hardware derived credential is verified by TPM and the data physical block is located based on the ciphertext mapping index; if the hardware evaluation value does not meet the preset verification threshold, the data physical block is obtained after being decrypted based on the ciphertext mapping index, and the verification operation is asynchronously pushed into the delay queue.

2. The data protection method based on TPM encryption according to claim 1, characterized in that, The specific process of generating leaf node digests and root node digests includes: traversing the metadata area of ​​the file storage structure, extracting index node and directory entry features, wherein the index node includes the index node number, permission bits, and timestamp, and the directory entry features include the file name and directory level pointer; performing cryptographic hash operations on the index node and directory entry features to generate a fixed-length message digest, which serves as the leaf node digest; according to the hierarchical aggregation logic, performing binary serial concatenation on the leaf node digests of the same level in physical address order; performing hash operations on the concatenated leaf node digests, and recursively performing concatenation and hash operations upwards along the tree structure until a unique root node digest is generated.

3. The data protection method based on TPM encryption according to claim 1, characterized in that, The specific process of outputting the hardware anchoring topology includes: overlaying the root node digest into the platform configuration register through an extension operation and updating the register value; obtaining the stored root key and performing digital authentication operations on the register value to generate a hardware authentication credential carrying timing information; performing structured encapsulation on the root node digest and the hardware authentication credential, outputting the hardware anchoring topology and backing it up to the protected storage space of the trusted execution environment.

4. The data protection method based on TPM encryption according to claim 1, characterized in that, The specific process of generating feature keywords, hardware derived credentials, and ciphertext mapping index includes: parsing file write operation instructions to extract payload data, performing semantic segmentation and noise filtering to extract feature keywords; using the TPM hardware unique key to perform key mapping transformation on the feature keywords, outputting a fixed-length binary sequence as a hardware derived credential and writing it into a controlled buffer; establishing a mapping relationship between the hardware derived credential and the physical storage address of the data, constructing a balanced search tree with the hardware derived credential as the key and the physical storage address of the data as the data value; and performing structured encryption encapsulation on the tree nodes of the balanced search tree to generate a ciphertext mapping index.

5. The data protection method based on TPM encryption according to claim 1, characterized in that, The specific process of parsing the target object type in the I / O request instruction includes: extracting the operation control code and target logical address pointer contained in the I / O request instruction; retrieving the address layout mapping table of the file storage structure; performing address matching between the target logical address pointer and the metadata storage area and data content storage area in the address layout mapping table; if the target logical address pointer falls into the metadata storage area, determining that the target object type is a metadata operation; if the operation control code belongs to the attribute change category, determining that the target object type is a metadata operation; when the target logical address pointer falls into the data content storage area, determining that the target object type is a data content operation.

6. The data protection method based on TPM encryption according to claim 1, characterized in that, The specific process of performing file logical integrity comparison for metadata operations and quantifying data content operations into hardware evaluation values ​​includes: when the target object type is confirmed to be a metadata operation, reading the indices and directory entry features corresponding to the target logical addressing pointer; performing one-way mapping and hierarchical aggregation logic on the indices and directory entry features to generate feature summaries; parsing the hardware anchoring topology to extract the root node summary, performing a consistency comparison between the feature summary and the root node summary, and outputting the logical integrity verification result; when the target object type is confirmed to be a data content operation, monitoring the response queue length and processing latency values ​​in the TPM interface instructions, performing a weighted summation operation, and outputting the hardware evaluation value.

7. The data protection method based on TPM encryption according to claim 1, characterized in that, The specific process of verifying hardware-derived credentials through TPM and locating data physical blocks based on ciphertext mapping index includes: performing a numerical comparison between the hardware evaluation value and a preset verification threshold; when the hardware evaluation value meets the preset verification threshold, importing the feature keywords obtained by parsing and matching into the TPM internal isolation environment; performing real-time mapping transformation on the feature keywords using the TPM hardware unique key to generate a baseline verification credential; retrieving the hardware-derived credential associated with the current operation from the ciphertext mapping index; performing a binary bitwise comparison between the baseline verification credential and the hardware-derived credential; outputting a verification pass instruction when the comparison results match, and parsing the data physical storage address based on the ciphertext mapping index to obtain the data physical block; and outputting a verification failure instruction when the comparison results do not match.

8. The data protection method based on TPM encryption according to claim 1, characterized in that, The specific process of asynchronously pushing the verification operation into the delay queue based on the data physical block includes: if the hardware evaluation value does not meet the preset verification threshold, using the symmetric key to perform decapsulation processing on the ciphertext mapping index and reconstructing the balanced search tree retrieval view; retrieving the hardware derived credential from the controlled cache as the retrieval key value to traverse the balanced search tree retrieval view and match the target index node; parsing the target index node and extracting the data physical storage address, locating the data physical block and performing data read and write access; extracting feature keywords, hardware derived credential, and the current operation time and encapsulating them into a verification operation; asynchronously pushing the verification operation into the tail of the memory delay queue and suspending the TPM hardware verification instruction.

9. A data protection system based on TPM encryption, characterized in that, include: The hardware anchoring construction module extracts the features of the index nodes and directory entries of the file storage structure to generate leaf node summaries; The root node summary is generated by processing the leaf node summaries according to hierarchical aggregation logic. The root node digest is measured to the platform configuration register, the root key is obtained and the register value is authenticated, the hardware anchored topology is output and backed up; The encrypted index generation module parses the write request data stream to generate feature keywords; The TPM hardware unique key is used to map and transform the feature keywords to generate hardware derived credentials, which are then stored in a controlled cache. The hardware derived credentials are used as keys to build a balanced search tree, and the tree nodes of the balanced search tree are encapsulated to generate a ciphertext mapping index. The I / O verification and scheduling module parses the target object type in the I / O request command; When the target object type is a metadata operation, calculate the feature summary of the target object type and perform a file logical integrity comparison with the hardware anchoring topology; when the target object type is a data content operation, quantify the data content operation into a hardware evaluation value; if the hardware evaluation value meets the preset verification threshold, verify the hardware derived certificate through TPM and locate the data physical block based on the ciphertext mapping index; if the hardware evaluation value does not meet the preset verification threshold, obtain the data physical block after decryption based on the ciphertext mapping index, and asynchronously push the verification operation into the delay queue.

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