Superconducting integrated circuit and method of manufacturing the same
By employing a stacked structured process and etch stop layer technology in superconducting integrated circuits, the problems of repeatability and high defect density in existing technologies have been solved, enabling the fabrication of superconducting integrated circuits with low defect density and supporting the construction of large-scale quantum computing devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INFINEON TECHNOLOGIES AG
- Filing Date
- 2025-12-16
- Publication Date
- 2026-06-23
AI Technical Summary
Existing technologies suffer from reproducibility issues and high defect density in the manufacture of superconducting integrated circuits, making it difficult to achieve significant scaling.
A layered structuring process is employed, including the formation of a superconducting layer and a dielectric layer, and the formation of a Josephson junction (JJ) structure through an etching process. A metal layer is used as an etch stop layer to control the etching precision, resulting in a reliable and reproducible superconducting integrated circuit.
It enables the fabrication of superconducting integrated circuits with low defect density, supports the construction of large-scale quantum computing devices, and provides reliable and reproducible scalability.
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Figure CN122270046A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to superconducting integrated circuits and methods for manufacturing superconducting integrated circuits. Background Technology
[0002] Superconducting integrated circuits can be used in a variety of technological fields. For example, quantum computing devices that operate superconducting qubits can be based on superconducting integrated circuits. Quantum computing is a promising approach to solving specific tasks significantly faster than conventional computers. One way to implement circuits for quantum computers is to create qubits that include superconducting Josephson junctions (JJs) and capacitors. Current techniques for implementing superconducting integrated circuits often suffer from reproducibility issues and defect densities, and typically do not allow for significant scalability. In this context, it is desirable to provide a precise and reproducible method for fabricating superconducting integrated circuits that simultaneously allows for direct and easy scalability. Summary of the Invention
[0003] This disclosure relates to a method of manufacturing a superconducting integrated circuit. The method includes forming a first superconducting layer. The method further includes forming a layer stack over the first superconducting layer, wherein the layer stack includes a Josephson junction (JJ) layer stack, a metal layer disposed over the JJ layer stack, and a fourth superconducting layer disposed over the metal layer, wherein the JJ layer stack includes: a second superconducting layer electrically coupled to the first superconducting layer, a third superconducting layer disposed over the second superconducting layer, and an electrically insulating barrier layer disposed between the second and third superconducting layers. The method further includes structuring the fourth superconducting layer, including performing a first etch process, wherein the metal layer serves as an etch stop layer and a first portion of the metal layer is exposed. The method further includes structuring the layer stack to form a JJ structure. The method further includes forming a dielectric layer over the JJ structure. The method further includes structuring the dielectric layer, including performing a second etch process, wherein the metal layer serves as an etch stop layer and a second portion of the metal layer is exposed. The method further includes forming a fifth superconducting layer over the structured dielectric layer, wherein the fifth superconducting layer is electrically coupled to the third superconducting layer.
[0004] Another aspect of this disclosure relates to a superconducting integrated circuit. The superconducting integrated circuit includes a first superconducting layer. The superconducting integrated circuit also includes a JJ structure disposed above the first superconducting layer, wherein the JJ structure includes: a second superconducting layer electrically coupled to the first superconducting layer, a third superconducting layer disposed above the second superconducting layer, and an electrically insulating barrier layer disposed between the second and third superconducting layers. The superconducting integrated circuit also includes a metal layer disposed above the JJ structure. The superconducting integrated circuit also includes a fourth superconducting layer disposed above the metal layer. The superconducting integrated circuit also includes a fifth superconducting layer disposed above the fourth superconducting layer, wherein the fifth superconducting layer is electrically coupled to the third superconducting layer.
[0005] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description
[0006] This disclosure is illustrated by way of example and in a non-limiting manner, in which the same reference numerals may refer to similar or identical elements. The elements in the figures are not necessarily proportional to each other. Features of the various illustrated examples may be combined unless they exclude each other.
[0007] Figure 1 includes Figures 1A to 1O The diagram schematically illustrates a method for manufacturing a superconducting integrated circuit 100 according to the present disclosure.
[0008] Figure 2 A superconducting integrated circuit 200 according to the present disclosure is schematically illustrated.
[0009] Figure 3 The superconducting integrated circuit 300 according to the present disclosure is schematically illustrated. Detailed Implementation
[0010] The following description relates to superconducting (or superconducting) integrated circuits comprising one or more Josephson junctions (JJs) and methods for their fabrication. Since the Josephson effect is based on a quantum mechanical tunneling process, superconducting integrated circuits using JJs can represent examples of superconducting quantum circuits. In one example, the methods described herein can be used to realize a quantum computing device. However, it should be understood that this disclosure is not limited to methods for fabricating quantum computing devices, but is intended to cover all methods for fabricating superconducting integrated circuit devices comprising one or more JJs (i.e., superconducting Josephson junction quantum circuits).
[0011] In some examples, superconducting integrated circuits may include or correspond to resonant circuits. Resonant circuits typically include capacitors and inductors. Resonant circuits can be linear resonant circuits (e.g., harmonic oscillators) or nonlinear resonant circuits (e.g., nonharmonic oscillators). In quantum devices, resonant circuits can also be referred to as quantum oscillators. The technique used in quantum computing is to use JJ junctions to make the resonant circuit nonlinear (or in other words, to make the oscillator potential nonharmonic). In quantum computing devices, quantum nonharmonic oscillators can be used to form qubits. That is, nonlinear resonant circuits can form (or operate) qubits. A qubit formed by one or more (nonlinear) Josephson junctions in a (therefore nonlinear) resonant circuit can also be referred to as a Josephson qubit.
[0012] Other examples of superconducting JJ quantum circuits could be Josephson parametric amplifiers or traveling-wave parametric amplifiers (TWPAs). Such devices can provide high gain and quantum-confined noise. In one example, to build a large-scale multi-qubit quantum processor, multiplexed qubit readouts may be desirable, requiring amplifiers with high bandwidth, high gain, and low added noise. This capability can be provided by TWPAs. Yet another example of electronic devices including superconducting integrated circuits could be single-flux quantum (SFQ) devices. Such devices can be transistor-like devices where voltage pulses generated by the JJ in a superconducting electronic (quantum) circuit (rather than voltage levels generated by transistors in semiconductor electronics) can be used to encode, process, and transmit digital information. Superconducting integrated circuits including multiple SFQ devices can allow the formation of (R)SFQ (fast) single-flux quantum) logic.
[0013] Now for reference Figures 1A to 1O The diagram schematically illustrates a method for manufacturing a superconducting integrated circuit 100 according to the present disclosure. More specifically, Figures 1A to 1O This is a schematic cross-sectional view illustrating stages of a method for manufacturing a superconducting integrated circuit according to the present disclosure. An exemplary superconducting integrated circuit 100 manufactured by this method is shown in... Figure 10 As shown in the image.
[0014] exist Figure 1A In this process, substrate 2 may be provided. For example, substrate 2 may comprise or be made of at least one of sapphire or silicon. In a specific example, substrate 2 may be a high-resistivity crystalline silicon substrate. Substrate 2 can be used as a carrier for superconducting integrated circuits fabricated thereon. In particular, no integrated circuits or integrated devices are formed in substrate 2.
[0015] A first superconducting layer 4 of superconducting material can be formed. In the illustrated example, the first superconducting layer 4 can be formed on the top surface of the substrate 2. The first superconducting layer 4 can initially be an unstructured and continuous layer that can be deposited over the entire top surface of the substrate 2. For example, the first superconducting layer 4 can be deposited using at least one of CVD (chemical vapor deposition), PVD (physical vapor deposition), sputtering, etc. A superconducting material can be considered as a material that can become superconducting at the operating temperature of the superconducting integrated circuit to be manufactured. Therefore, the term "superconducting" can refer to the conductive state of a material at a circuit operating temperature that can be several mK. For example, a superconducting material can include or correspond to at least one of Nb, Al, Ta, and TiN. In particular, the first superconducting layer 4 can include or correspond to a superconducting metal layer.
[0016] The first superconducting layer 4 can be structured to form a structured first superconducting layer. The structured first superconducting layer 4 may include multiple portions 4A to 4C of superconducting material. For example, portions 4A to 4C may be electrically and / or physically disconnected from each other. In the illustrated case, an exemplary number of three portions 4A to 4C is shown. However, it should be understood that this arrangement may include other portions not shown for simplicity. For example, the structured first superconducting layer 4 can be performed by a patterning process, which may, for example, use a photomask, a photoresist (not shown), and an etching process. Alternatively, or additionally, other structuring processes compatible with semiconductor manufacturing may be used.
[0017] The first dielectric layer 6 may be formed on the structured first superconducting layer 4. The first dielectric layer 6 may be a continuous, unstructured layer of dielectric material. The first dielectric layer 6 may cover the entire substrate 2. For example, the dielectric layer 6 may include at least one of silicon oxide, silicon nitride, or a combination of these materials (oxynitrides), or may be made of at least one of silicon oxide, silicon nitride, or a combination of these materials (oxynitrides).
[0018] exist Figure 1B In this embodiment, the first dielectric layer 6 can be structured to form exposed portions 8A and 8B of the structured first superconducting layer 4. The structured first dielectric layer 6 can partially or completely cover regions of the substrate 2, wherein the superconducting material of the first superconducting layer 4 has been removed. Additionally, the structured first dielectric layer 6 can partially cover at least some portions 4A to 4C of the structured first superconducting layer 4. In other words, at selected regions of portions 8A and 8B of the structured first superconducting layer 4, the first dielectric layer 6 can be opened such that at least a portion of portions 8A and 8B can be exposed. For example, the structured first dielectric layer 6 can be performed using patterning processes (e.g., photolithography and etching) as previously described in conjunction with the structured first superconducting layer 4.
[0019] exist Figure 1C In this embodiment, a layer stack 10 comprising multiple stacked layers can be formed on top of a structured first superconducting layer 4 and a structured dielectric layer 6. The layer stack 10 can be a continuous, unstructured stack of layers, as indicated by the shaded areas. In the illustrated case, the layer stack 10 can cover the entire substrate 2. For example, the individual layers of the layer stack 10 can be deposited by sputtering or any other suitable deposition process. In the illustrated example, the layer stack 10 can be non-planar because the layers arranged beneath it have been previously structured.
[0020] Now for reference Figure 1DThis describes the individual layers of layer stack 10. Layer stack 10 may include a Josephson junction (JJ) layer stack 12, which may include or correspond to three layers stacked as superconducting / tunneling barrier / superconducting materials. In a specific, but not limited, example, JJ layer stack 12 may be an Nb / AlOx / Nb three-layer stack. JJ layer stack 12 may include a second superconducting layer 14, a third superconducting layer 18 disposed above the second superconducting layer 14, and an electrically insulating barrier layer 16 disposed between the second superconducting layer 14 and the third superconducting layer 18. The second superconducting layer 14 may be electrically coupled to a first superconducting layer 4 (or a portion thereof) disposed below it. The electrically insulating barrier layer 16 may be a JJ barrier layer, which may be a functional layer of JJ layer stack 12. The electrically insulating barrier layer 16 may be configured to provide JJ tunneling.
[0021] The second superconducting layer 14 may be a superconducting material, which may include or correspond to at least one of Nb, Al, Ta, and TiN. In particular, the second superconducting layer 14 may include or correspond to a superconducting metal layer. In a non-limiting example, the thickness of the second superconducting layer 14 in the vertical direction may range from about 8 nm to about 12 nm, for example, about 10 nm. The second superconducting layer 14 may be referred to as the bottom electrode of the JJ layer stack 12 or the bottom electrode of the JJ structure to be formed later.
[0022] For example, the electrically insulating barrier layer 16 may comprise at least one of aluminum oxide (AlOx) or magnesium oxide (MgOx). In a non-limiting example, the thickness of the electrically insulating barrier layer 16 in the vertical direction may range from about 1 nm to about 2 nm. As will become apparent later, the barrier layer 16 may be used as an etch stop layer in a later method step.
[0023] The third superconducting layer 18 may be a superconducting material, which may include or correspond to at least one of Nb, Al, Ta, and TiN. In particular, the third superconducting layer 18 may include or correspond to a superconducting metal layer. In a non-limiting example, the thickness of the third superconducting layer 18 in the vertical direction may range from about 16 nm to about 24 nm, for example, about 20 nm. The third superconducting layer 18 may be referred to as the top electrode of the JJ layer stack 12 or the top electrode of the JJ structure to be formed later.
[0024] The layer stack 10 may include a metal layer 20 disposed on top of the JJ layer stack 12, and more particularly, a metal layer 20 disposed on top of the third superconducting layer 18. Specifically, the metal layer 20 may include or correspond to a superconducting material. For example, the metal layer 20 may include at least one of Ru or Al. In a non-limiting example, the thickness of the metal layer 20 in the vertical direction may range from about 5 nm to about 20 nm. Specifically, the thickness of the metal layer 20 in the vertical direction may be less than the coherence length of the superconducting material disposed beneath the third superconducting layer 18.
[0025] The layer stack 10 may include a fourth superconducting layer 22 disposed on the metal layer 20. The fourth superconducting layer 22 may be a superconducting material, which may include or correspond to at least one of Nb, Al, Ta, and TiN. In particular, the fourth superconducting layer 22 may include or correspond to a superconducting metal layer. In a non-limiting example, the thickness of the fourth superconducting layer 22 in the vertical direction may range from about 40 nm to about 60 nm, for example, about 50 nm. In particular, the fourth superconducting layer 22 and the metal layer 20 may be made of different materials. As will become apparent later, the fourth superconducting layer 22 may be used as a hard mask in later method steps.
[0026] exist Figure 1E In this process, a first photoresist mask 24 can be formed on the layer stack 10, more specifically on the fourth superconducting layer 22. The first photoresist mask 24 can be formed at locations where the JJ structure will be formed from the layer stack 10. In the illustrated example, the first photoresist mask 24 can be formed on a layer that has previously been... Figure 1B The method steps expose a portion 4B of the structured first superconducting layer 4 above it. In one example, the first resist mask 24 may include or may correspond to a photoresist material.
[0027] Now for reference Figure 1F The details of the arrangement are shown. More specifically, the combination is illustrated. Figure 1D The previously described layer stack and the first resist mask 24 arranged thereon. Figure 1FIn this embodiment, the fourth superconducting layer 22 can be structured. In the illustrated example, the structured fourth superconducting layer 22 may include or correspond to the first etching process. Here, the fourth superconducting layer 22 can be etched with high selectivity to the metal layer 20, which can serve as an etch stop layer. That is, etching can be stopped on the metal layer 20, such that a first portion 26 of the metal layer 20 can be exposed. The etch stop layer 20 can be configured to protect the three-layer stack of superconducting / tunneling barrier / superconducting material disposed beneath it. It should be noted that the etch stop layer 20 provides improved control over the first etching process compared to other techniques. Due to the use of the etch stop layer 20, the thickness of the third superconducting layer 18 disposed above the barrier layer 16 can be defined solely by the prior deposition of the third superconducting layer 18, but can be completely independent of the first etching process. In a specific but non-limiting example, the fourth superconducting layer 22 can be made of Nb, and the metal layer 20 can be made of Ru, wherein the first etching process can be based on chlorine chemistry, such that the Nb layer can be etched and the etching process can be stopped on the Ru layer.
[0028] exist Figure 1G In this process, after performing the first etching process, the first exposed portion 26 of the first resist mask 24 and the metal layer 20 can be removed. Specifically, the first exposed portion 26 of the first resist mask 24 and the metal layer 20 can be removed simultaneously and / or based on the same process. In one example, simultaneously removing the exposed portion 26 of the first resist mask 24 and the metal layer 20 can include, or may correspond to, applying a photoresist remover (or photoresist stripper) to the first exposed portion 26 of the first resist mask 24 and the metal layer 20. The third superconducting layer 18 can remain unchanged by applying a photoresist remover. It should be understood that the type of photoresist remover applied can depend on the materials selected for the first resist mask 24, the metal layer 20, and the third superconducting layer 18.
[0029] exist Figure 1HIn this process, the layer stack 10 can be structured to form a JJ structure 28. Specifically, structuring the layer stack 10 to form a JJ structure may include, or may correspond to, performing an etching process in which the structured fourth superconducting layer 22 (see Figure 1) can be used as a hard mask. The portions of the layer stack 10 not covered by the hard mask can be (particularly completely) removed, while the portions of the layer stack 10 covered by the hard mask can be protected and therefore retained. The etching process can be controlled to stop at a portion 4B of the structured first superconducting layer 4. In one example, the etching process may include, or may correspond to, an ion beam etching (IBE) process. The IBE process can be used to etch the metal and dielectric of the layer stack 10 to form the JJ structure 28. The IBE can be anisotropic and is therefore particularly suitable for forming a JJ structure 28 with substantially vertical sidewalls. Figure 1H As can be seen, the bottom of the JJ structure can be electrically coupled to part 4B of the structured first superconducting layer 4.
[0030] Now for reference Figure 1I The diagram shows the various layers of the formed JJ structure 28. The JJ structure 28 may include (from bottom to top) a portion of a second superconducting layer 14 forming the bottom electrode of the JJ, a portion of a barrier layer 16 configured to provide tunneling for the JJ, a portion of a third superconducting layer 18 forming the top electrode of the JJ, a portion of a metal layer 20, and a portion of a fourth superconducting layer 22.
[0031] exist Figure 1J In this process, a second dielectric layer 30 can be formed on the JJ structure 28. The second dielectric layer 30 can be an unstructured, continuous layer that can cover the entire substrate 2. (As shown in the image...) Figure 1J As can be seen, the second dielectric layer 30 may contact the first dielectric layer 6 at some locations and the first superconducting layer 4 at other locations. The second dielectric layer 30 may include or be made of one of the dielectric materials previously specified for the first dielectric layer 6. In a specific but non-limiting example, the second dielectric layer 30 may be a silicon nitride layer with a thickness in the vertical direction ranging from about 20 nm to about 40 nm, for example, about 30 nm. For example, the dielectric material of the second dielectric layer 30 and the dielectric material of the first dielectric layer 6 may include the same dielectric material or may be the same dielectric material. Alternatively, the dielectric materials of the second dielectric layer 30 and the first dielectric layer 6 may be different and may therefore be selectively structured.
[0032] exist Figure 1KIn this embodiment, a second photoresist mask 32 can be formed on the second dielectric layer 30. Specifically, the second photoresist mask 32 can be formed for patterning the top contact of the JJ. In the illustrated example, the second photoresist mask 32 can be formed over the entire second dielectric layer 30, except for the region located above the JJ structure 28. In this region, the second photoresist mask 32 can have an opening 34, the bottom of which is formed by the second dielectric layer 30. In the top view, the outline of the opening 34 can be (particularly completely) arranged within the outline of the JJ structure 28. In one example, the second photoresist mask 32 can include or may correspond to a photoresist material. The second photoresist mask 32 and its combination Figure 1E The first resist mask 24 described earlier can be made of the same material or a different material.
[0033] Now for reference Figure 1L The details of this arrangement are shown. More specifically, a JJ structure 28 having a second dielectric layer 30 and a second photoresist mask 32 disposed thereon is illustrated. Figure 1L In this embodiment, the second dielectric layer 30 can be structured. In the illustrated example, structuring the second dielectric layer 30 may include or correspond to a second etching process. Here, the second dielectric layer 30 and the underlying fourth superconducting layer 22 can be etched with high selectivity to the metal layer 20, similar to how a bonding process is performed. Figure 1F In the previously described first etching process, the metal layer 20 can be used as an etch stop layer. That is, etching can be stopped on the metal layer 20, allowing the second portion 36 of the metal layer 20 to be exposed. The etch stop layer 20 can therefore be configured to protect the three-layer stack of superconducting / tunneling barrier / superconducting material disposed beneath it. It should be noted that the use of the etch stop layer 20 allows for reliable structuring of the opening 34 and provides a large process window for opening the contact, while protecting the JJ structure from over-etching damage. Thus, achieving very good process uniformity across the entire substrate 2 is possible. In a specific but non-limiting example, the second dielectric layer 30 can be made of silicon nitride, the fourth superconducting layer 22 can be made of Nb, and the metal layer 20 can be made of Ru. The second etching process for etching the second dielectric layer 30 can be selected such that it is selective for the etch stop layer material. For example, the second etching process can be based on fluorine-based chemistry (e.g., CF4+CHF3), where the etching process can be stopped on the Ru layer.
[0034] exist Figure 1MIn this process, after performing the second etching process, the second exposed portion 36 of the second resist mask 32 and the metal layer 20 can be removed. Specifically, the second exposed portion 36 of the second resist mask 32 and the metal layer 20 can be removed simultaneously and / or based on the same process. In one example, simultaneously removing the exposed portion 36 of the second resist mask 32 and the metal layer 20 can include, or may correspond to, applying a photoresist remover (or photoresist stripper) to the second exposed portion 36 of the second resist mask 32 and the metal layer 20. The third superconducting layer 18 can remain unchanged by applying a photoresist remover. It should be understood that the type of photoresist remover applied can depend on the materials selected for the second resist mask 32, the metal layer 20, and the third superconducting layer 18.
[0035] Now for reference Figure 1N This illustrates the arrangement after the removal of the second resist mask 32 and the second exposed portion 36 of the metal layer 20. As can be seen, the top structure of the JJ structure 28 may be uncovered at the location of the opening 34 (see previous). Figure 1L ).
[0036] exist Figure 10 In this embodiment, the first dielectric layer 6 and the second dielectric layer 30 may be opened at one or more selected locations 38 above one or more portions 4A to 4C of the structured first superconducting layer 4. In the illustrated example, dielectric layers 6 and 30 may be opened at selected locations 38 above portion 4A of the first superconducting layer 4. However, it should be understood that in other examples, one or more additional openings may be formed at locations where only the first dielectric layer 6 or only the second dielectric layer 30 may exist.
[0037] The resulting arrangement may include: a region on a structured first superconducting layer without a dielectric layer disposed on top (e.g., at position 38), a region covered by a dielectric material having a vertical thickness T2 defined by a second dielectric layer 30 (e.g., at position 40), and a region having a thicker dielectric material formed on top by a first dielectric layer 6 and a second dielectric layer 30 having a total thickness T1 in the vertical direction, wherein T1 > T2.
[0038] For example, the opening at the selected location 38 can be used for contact formation, such as, for example, pad formation. Additionally, or alternatively, a region of dielectric material with thickness T2 can be used to form a capacitor with high area capacitance. Additionally, or alternatively, a region of dielectric material with thickness T1 can be used to form a capacitor with lower area capacitance. That is, the combination of the first dielectric layer 6 and the second dielectric layer 30 can provide the possibility of having different area capacitances. This can provide flexibility in the design of superconducting integrated circuits to be manufactured by the described method. For example, TWPA can use capacitors with different capacitances in superconducting integrated circuits.
[0039] Still referencing Figure 10 A fifth superconducting layer 42 of superconducting material may be formed on the second dielectric layer 30. The material of the fifth superconducting layer 42 may include or correspond to one or more materials previously specified for other superconducting layers incorporated into the arrangement. The superconducting material of the fifth superconducting layer 42 may be the same as or different from the superconducting materials of the other superconducting layers. Since the second dielectric layer 30 has an opening on the JJ structure 28, the fifth superconducting layer 42 may be electrically coupled to the third superconducting layer 18.
[0040] In another step, the fifth superconducting layer 42 can be structured to form a structured fifth superconducting layer 42 comprising multiple portions 42A to 42C of superconducting material. For example, the superconducting portions 42A to 42C can be electrically and / or physically disconnected from each other. A portion of the structured fifth superconducting layer 42 (here: portion 42A) can be arranged opposite to a portion 4A of the structured first superconducting layer 4, wherein a first dielectric layer 6 and a second dielectric layer 30 are disposed therebetween. Thus, the structured first superconducting layer 4 and the structured fifth superconducting layer 42 can be structured to form a capacitor C1 comprising a capacitor dielectric material. The first electrode of the capacitor C1 may include or may correspond to a portion 4A of the first superconducting layer 4, and the second electrode of the capacitor C1 may include or may correspond to a portion 42A of the fifth superconducting layer 42. The capacitor dielectric material may include a portion of the first dielectric layer 6 and a portion of the second dielectric layer 30. Since the thickness T1 can be chosen to be relatively large, this arrangement can form a capacitor C1 with a low area capacitance. Another portion of the structured fifth superconducting layer 42 (here: portion 42B) can be formed to the top of the JJ structure 28. Portions 4B of the structured first superconducting layer 4 and 42B of the structured fifth superconducting layer 42 can be used to contact the JJ structure 28 at the bottom and top sides, respectively.
[0041] In the illustrated example, a portion 42B of the fifth superconducting layer 42 can be electrically coupled to a portion 4A of the structured first superconducting layer 4. The portion 42B of the structured fifth superconducting layer 42 can fill the opening at position 38 in the first dielectric layer 6 and the second dielectric layer 30, allowing a conductive via connection V to be formed. This conductive via connection V extends through the dielectric material and connects the portion 4A of the structured first superconducting layer 4 to the portion 42B of the structured fifth superconducting layer 42. In the illustrated example, capacitor C1 can be electrically coupled to the JJ structure 28 via the conductive via connection V.
[0042] Figure 10 An exemplary superconducting integrated circuit 100 according to this disclosure is shown. In the illustrated case, the superconducting integrated circuit 100 formed over a substrate 2 may include a JJ structure 28, a via connection V, and a capacitor C1. In one example, the capacitor C1 and the JJ structure 28 may form portions of a qubit (or transport qubit). Note that, in combination Figure 2 An exemplary diagram of the transport qubit is shown and described.
[0043] It should be understood that the superconducting integrated circuit 100 may include one or more additional components. In the illustrated example, at a selected location 40, a portion of the structured fifth superconducting layer 42 (here: portion 42C) may be arranged opposite a portion of the structured first superconducting layer 4 (here: portion 4C), wherein a second dielectric layer 30 of thickness T2 is disposed therebetween. This arrangement may form a capacitor C2 (C2 > C1) with a high area capacitance. In particular, the capacitance C2 may depend on the thickness T2 and the lateral dimension of the capacitor C2. It should be understood that in some examples, the capacitor C2 may be electrically connected to a portion of the superconducting integrated circuit and thus may form part of the superconducting integrated circuit.
[0044] It should be noted that the method of Figure 1 may include one or more additional steps, which are not described in detail for simplicity. For example, in another step, one or both of the dielectric layers 6 and 30 may be opened to expose the lower portion of the first superconducting layer 4. In this way, the contact pad area can be defined so that electrical contacts (not shown) to external circuitry can be provided. In another example, Figure 10 The entire arrangement shown can be encapsulated by a passivation layer (not shown) to protect the circuit components from external influences.
[0045] It should also be understood that, if technically possible and useful, the steps of this method can be at least partially interchanged, modified, and / or performed simultaneously. For example, the first superconducting layer 4 need not be structured prior to the deposition of the three-layer stack 12. Alternatively, the structuring of the first superconducting layer 4 and the three-layer stack 12 can be performed together. In this case, the first superconducting layer 4 can be part of the three-layer stack 12.
[0046] The method steps in Figure 1 can at least partially utilize an integrated approach that allows for the formation of superconducting circuits including JJ structures, with a process compatible with scalable semiconductor manufacturing. That is, the proposed concept can be at least partially based on processes available in semiconductor manufacturing technologies. Applying these techniques can support the fabrication of a large number of identical JJs on a wafer. It should be understood that the illustration in Figure 1 may only show a portion or detail of the arrangement to be fabricated. In particular, a large number of JJs and superconducting circuits can be fabricated side-by-side. The proposed concept provides reliable and reproducible formation of superconducting circuits with low defect density (and particularly, JJs that can be included in such superconducting circuits). Furthermore, the proposed concept provides easy and straightforward scalability in the fabrication of superconducting circuits.
[0047] The fabricated superconducting integrated circuits can be used in a variety of technological fields. For example, quantum computing devices that operate superconducting qubits can be based on the superconducting integrated circuits according to this disclosure. One way to implement circuits for quantum computers is to create qubits that include a superconducting Josephson junction (JJ) as previously described and a capacitor.
[0048] Now for reference Figure 2 The illustration shows a superconducting integrated circuit 200 according to the present disclosure. In the illustrated example, the superconducting integrated circuit 200 may include or may correspond to a transport sub-qubit. The transport sub-qubit may include a qubit having a capacitance C. J and inductor L J The JJ 44. The two superconducting electrodes of the JJ 44 can be made of materials with capacitance C. S A capacitor 46 is used for current shunting. The electrodes of JJ 44 can be connected to ground and potential φ, respectively. In particular, JJ 44 and capacitor 36 can be manufactured based on the method according to this disclosure, such as the method of FIG. 1. In particular, transport qubits can represent integrated components of a superconducting quantum computer. They are capable of maintaining long coherence times, making transport qubits a suitable architecture in quantum computing.
[0049] Now for reference Figure 3The illustrated superconducting integrated circuit 300 according to the present disclosure is shown. In the illustrated example, the superconducting integrated circuit 300 may include or correspond to a TWPA circuit as previously described. In the illustrated example, the TWPA circuit may include unit cells connected in series, indicated by dots on the left and right. The unit cell may include a pair of grounded capacitors C0 and a capacitor having a capacitance C J JJ 44. Additionally, it has a capacitor C. R and inductor L R and coupling capacitor C C A phase-matching resonator can be inserted for phase matching. In particular, JJ 44 and one or more capacitors in the circuit can be manufactured based on the method according to this disclosure, such as the method of Figure 1. Example
[0050] The examples described in this article provide superconducting integrated circuits and methods for manufacturing superconducting integrated circuits.
[0051] Example 1 is a method of manufacturing a superconducting integrated circuit, the method comprising: forming a first superconducting layer; forming a layer stack over the first superconducting layer, wherein the layer stack includes: a Josephson junction (JJ) layer stack, a metal layer disposed over the JJ layer stack, and a fourth superconducting layer disposed over the metal layer, wherein the JJ layer stack includes: a second superconducting layer electrically coupled to the first superconducting layer, a third superconducting layer disposed over the second superconducting layer, and an electrically insulating barrier layer disposed between the second and third superconducting layers; structuring the fourth superconducting layer, including performing a first etching process, wherein the metal layer serves as an etch stop layer and a first portion of the metal layer is exposed; structuring the layer stack to form a JJ structure; forming a dielectric layer over the JJ structure; structuring the dielectric layer, including performing a second etching process, wherein the metal layer serves as an etch stop layer and a second portion of the metal layer is exposed; and forming a fifth superconducting layer over the structured dielectric layer, wherein the fifth superconducting layer is electrically coupled to the third superconducting layer.
[0052] Example 2 is the method of Example 1, wherein the stacking of structured layers to form a JJ structure includes performing an etching process, wherein the structured fourth superconducting layer acts as a hard mask.
[0053] Example 3 is a method of Example 1 or 2, wherein stacking structured layers to form a JJ structure includes performing an ion beam etching process.
[0054] Example 4 is a method of any of the foregoing examples, further comprising: forming a first resist mask on a fourth superconducting layer before performing the first etching process; and simultaneously removing the first resist mask and a first exposed portion of the metal layer after performing the first etching process.
[0055] Example 5 is a method of Example 4, wherein simultaneously removing the first exposed portion of the first resist mask and the metal layer includes: applying a photoresist remover to the first exposed portion of the first resist mask and the metal layer.
[0056] Example 6 is a method of any of the foregoing examples, further comprising: forming a second resist mask on the dielectric layer before performing the second etching process; and simultaneously removing the second resist mask and a second exposed portion of the metal layer after performing the second etching process.
[0057] Example 7 is a method of Example 6, wherein simultaneously removing the second exposed portion of the second resist mask and the metal layer includes: applying a photoresist remover to the second exposed portion of the second resist mask and the metal layer.
[0058] Example 8 is a method of any of the foregoing examples, further comprising: structuring a first superconducting layer to form a structured first superconducting layer; and structuring a fifth superconducting layer to form a structured fifth superconducting layer, wherein the structured first superconducting layer and the structured fifth superconducting layer are structured to form a capacitor comprising a capacitor dielectric material, wherein the capacitor dielectric material comprises a portion of the dielectric layer.
[0059] Example 9 is the method of Example 8, and further includes: electrically coupling a portion of a structured first superconducting layer and a portion of a structured fifth superconducting layer by forming a conductive via connection extending through a dielectric material.
[0060] Example 10 is the method of Example 9, wherein the capacitor is electrically coupled to the JJ structure via a conductive via connection.
[0061] Example 11 is a method of any of the foregoing examples, wherein the first etching process and / or the second etching process are performed with high selectivity to the etch stop layer.
[0062] Example 12 is a superconducting integrated circuit, comprising: a first superconducting layer; a JJ structure disposed on the first superconducting layer, wherein the JJ structure includes: a second superconducting layer electrically coupled to the first superconducting layer, a third superconducting layer disposed on the second superconducting layer, and an electrically insulating barrier layer disposed between the second and third superconducting layers; a metal layer disposed on the JJ structure; a fourth superconducting layer disposed on the metal layer; and a fifth superconducting layer disposed on the fourth superconducting layer, wherein the fifth superconducting layer is electrically coupled to the third superconducting layer.
[0063] Example 13 is a superconducting integrated circuit of Example 12, wherein the metal layer comprises a superconducting material.
[0064] Example 14 is a superconducting integrated circuit of Example 12 or 13, wherein the metal layer includes at least one of Ru or Al.
[0065] Example 15 is a superconducting integrated circuit of any of Examples 12 to 14, wherein the thickness of the metal layer is less than the coherence length of the superconducting material of the third superconducting layer.
[0066] Example 16 is a superconducting integrated circuit of any of Examples 12 to 15, wherein the thickness of the metal layer is in the range of 5 nm to 20 nm.
[0067] Example 17 is a superconducting integrated circuit of any of Examples 12 to 16, further comprising: a dielectric layer, wherein a portion of the dielectric layer is disposed between a fourth superconducting layer and a fifth superconducting layer.
[0068] Example 18 is a superconducting integrated circuit of Example 17, further comprising: a capacitor, wherein a first electrode of the capacitor includes a portion of a first superconducting layer, a second electrode of the capacitor includes a portion of a fifth superconducting layer, and a capacitor dielectric material disposed between the first electrode and the second electrode includes a portion of a dielectric material.
[0069] Example 19 is a superconducting integrated circuit of Example 18, wherein a capacitor and a JJ structure form part of a transporter qubit.
[0070] As used herein, the terms “substantially,” “approximately,” “about,” etc., can mean “within reasonable tolerances for manufacturing.” For example, without departing from the aspects of the examples described herein, the terms “substantially,” “approximately,” “about,” etc., can be used herein to interpret small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in industry. For example, a material layer having an approximate thickness value can actually have a thickness within 5% of that approximate thickness value.
[0071] As used herein, the terms “electrically connected” or “electrically coupled” or similar terms do not imply that elements are in direct contact with each other; intermediate elements may be provided separately between “electrically connected” or “electrically coupled” elements. However, according to this disclosure, the foregoing and similar terms may also optionally have the specific meaning of elements being in direct contact with each other, i.e., intermediate elements are not provided separately between “electrically connected” or “electrically coupled” elements.
[0072] The terms “above,” “above,” “below,” etc., used herein to describe a portion, element, or layer of material formed or located on or arranged “above,” “over,” or “below” a surface may mean that the portion, element, or layer of material is located (e.g., placed, formed, arranged, deposited, etc.) “directly above,” “directly above,” or “directly below” the implied surface, such as being in direct contact with the implied surface. However, the terms “above,” “above,” “below,” etc., used herein to describe a portion, element, or layer of material formed or located on or arranged “above,” “over,” or “below” a surface may mean that the portion, element, or layer of material is located (e.g., placed, formed, arranged, deposited, etc.) “indirectly above,” “indirectly above,” or “indirectly below” the implied surface, wherein one or more additional portions, elements, or layers are arranged between the implied surface and the portion, element, or layer of material.
[0073] Although specific examples have been illustrated and described herein, those skilled in the art will understand that various alternatives and / or equivalent embodiments may be substituted for the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.
[0074] It should be noted that the methods and apparatuses, including those with preferred embodiments outlined in this document, can be used alone or in combination with other methods and apparatuses disclosed in this document. Furthermore, features outlined in the context of the apparatus also apply to the corresponding methods, and vice versa. Moreover, all aspects of the methods and apparatuses outlined in this document can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner.
[0075] It should be noted that the specification and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements, which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined in this document are primarily intended for illustrative purposes only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements of the principles, aspects, and embodiments of the invention, along with specific examples thereof, are provided herein to cover their equivalents.
Claims
1. A method for manufacturing a superconducting integrated circuit, the method comprising: The first superconducting layer is formed (4); A layer stack (10) is formed on top of the first superconducting layer (4), wherein the layer stack (10) comprises: Josephson junction JJ layer stack (12), wherein the JJ layer stack (12) includes: a second superconducting layer (14) electrically coupled to the first superconducting layer (4), a third superconducting layer (18) disposed on the second superconducting layer (14), and an electrically insulating barrier layer (16) disposed between the second superconducting layer (14) and the third superconducting layer (18). A metal layer (20) is disposed on the JJ layer stack (12), and A fourth superconducting layer (22) is disposed on the metal layer (20); Structuring the fourth superconducting layer (22) includes performing a first etching process, wherein the metal layer (20) is used as an etch stop layer and a first portion of the metal layer (20) is exposed; The layer stack (12) is structured to form a JJ structure (28). A dielectric layer (30) is formed on the JJ structure (28); Structuring the dielectric layer (30) includes performing a second etching process, wherein the metal layer (20) serves as an etch stop layer, and a second portion of the metal layer (20) is exposed; and A fifth superconducting layer (42) is formed on the structured dielectric layer (30), wherein the fifth superconducting layer (42) is electrically coupled to the third superconducting layer (18).
2. The method of claim 1, wherein structuring the layer stack (12) to form the JJ structure (28) includes performing an etching process, wherein the structured fourth superconducting layer (22) acts as a hard mask.
3. The method according to claim 1 or 2, wherein structuring the layer stack (12) to form the JJ structure (28) includes performing an ion beam etching process.
4. The method according to any one of the preceding claims further comprises: Before performing the first etching process, a first resist mask (24) is formed on the fourth superconducting layer (22). as well as After performing the first etching process, the first exposed portion of the first resist mask (24) and the metal layer (20) is removed simultaneously.
5. The method of claim 4, wherein simultaneously removing the first exposed portion of the first resist mask (24) and the metal layer (20) comprises: A photoresist remover is applied to the first exposed portion of the first photoresist mask (24) and the metal layer (20).
6. The method according to any one of the preceding claims further comprises: Before performing the second etching process, a second resist mask (32) is formed on the dielectric layer (30). as well as After performing the second etching process, the second resist mask (32) and the second exposed portion of the metal layer (20) are removed simultaneously.
7. The method of claim 6, wherein simultaneously removing the second exposed portion of the second resist mask (32) and the metal layer (20) comprises: The photoresist remover is applied to the second exposed portion of the second photoresist mask (32) and the metal layer (20).
8. The method according to any one of the preceding claims further comprises: The first superconducting layer (4) is structured to form a structured first superconducting layer (4). as well as The fifth superconducting layer (42) is structured to form a structured fifth superconducting layer (42), wherein the structured first superconducting layer (4) and the structured fifth superconducting layer (42) are structured to form a capacitor comprising a capacitor dielectric material, wherein the capacitor dielectric material comprises a portion of the dielectric layer (30).
9. The method according to claim 8, further comprising: A portion of the structured first superconducting layer (4) and a portion of the structured fifth superconducting layer (42) are electrically coupled by forming conductive vias extending through the dielectric material (30).
10. The method of claim 9, wherein the capacitor is electrically coupled to the JJ structure (28) via the conductive via connection.
11. The method according to any one of the preceding claims, wherein the first etching process and / or the second etching process is performed with high selectivity to the etch stop layer.
12. A superconducting integrated circuit, comprising: First superconducting layer (4); JJ structure (28) is disposed on the first superconducting layer (4), wherein the JJ structure (28) includes: a second superconducting layer (14) electrically coupled to the first superconducting layer (4), a third superconducting layer (18) disposed on the second superconducting layer (14), and an electrically insulating barrier layer (16) disposed between the second superconducting layer (14) and the third superconducting layer (18). A metal layer (20) is disposed on the JJ structure (28); A fourth superconducting layer (22) is disposed on the metal layer (20); and A fifth superconducting layer (42) is disposed on the fourth superconducting layer (22), wherein the fifth superconducting layer (42) is electrically coupled to the third superconducting layer (18).
13. The superconducting integrated circuit according to claim 12, wherein the metal layer (20) comprises a superconducting material.
14. The superconducting integrated circuit according to claim 12 or 13, wherein the metal layer (20) comprises at least one of Ru or Al.
15. The superconducting integrated circuit according to any one of claims 12 to 14, wherein the thickness of the metal layer (20) is less than the coherence length of the superconducting material of the third superconducting layer (18).
16. The superconducting integrated circuit according to any one of claims 12 to 15, wherein the thickness of the metal layer (20) is in the range of 5 nm to 20 nm.
17. The superconducting integrated circuit according to any one of claims 12 to 16, further comprising: A dielectric layer (30), wherein a portion of the dielectric layer (30) is disposed between the fourth superconducting layer (22) and the fifth superconducting layer (42).
18. The superconducting integrated circuit according to claim 17, further comprising: A capacitor, wherein the first electrode of the capacitor comprises a portion of the first superconducting layer (4), the second electrode of the capacitor comprises a portion of the fifth superconducting layer (42), and the capacitor dielectric material disposed between the first electrode and the second electrode comprises a portion of the dielectric material (30).
19. The superconducting integrated circuit of claim 18, wherein the capacitor and the JJ structure (28) form part of a transport qubit.