Staged multi-policy instruction scheduling method and system for VLIW architecture

Abstract

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

Description

Technical Field

[0001] This invention relates to the fields of compiler optimization and computer architecture technology, specifically to a staged multi-strategy instruction scheduling method and system for VLIW (Very Long Instruction Word) architecture. Background Technology

[0002] VLIW (Very Long Instruction Word) architecture is an important processor architecture that improves processor performance through instruction-level parallel scheduling at compile time. Unlike superscalar processors, which rely on dynamic hardware scheduling, VLIW processors shift the scheduling complexity to the compiler, which statically determines the parallel execution scheme of instructions at compile time. This design simplifies hardware implementation and reduces power consumption, but places higher demands on the compiler's instruction scheduling capabilities.

[0003] The core objective of VLIW instruction scheduling is to maximize instruction-level parallelism (ILP), that is, to package as many instructions as possible into the same execution cycle for execution while satisfying data dependencies, resource constraints, and register constraints. However, existing VLIW instruction scheduling methods suffer from the following problems: 1. Limited Scheduling Strategies. Traditional instruction schedulers typically employ a single scheduling algorithm, such as list scheduling or modular scheduling. However, a single strategy is insufficient to adapt to the optimization needs of different types of code regions. For example, loop-intensive code is better suited to software pipelining, while code with complex control flow is better suited to global scheduling based on dominance trees. The lack of a strategy selection mechanism limits the optimization effect.

[0004] 2. Coupling between scheduling and register allocation. Instruction scheduling and register allocation are intricately interdependent. Aggressive scheduling may increase register pressure and lead to overflow, while conservative scheduling, while reducing register pressure, sacrifices parallelism. Traditional methods for handling scheduling and register allocation either employ a schedule-then-allocation approach, leading to frequent backtracking, or are overly conservative in scheduling, limiting optimization potential.

[0005] 3. Processor compatibility issues. Different VLIW processors differ significantly in functional unit configuration, instruction latency, and encoding formats. Existing schedulers are typically designed for specific processors, making it difficult to quickly adapt to new processor architectures and limiting compiler portability.

[0006] 4. Complexity of liveness analysis. The multi-cycle instruction latency and predictive execution characteristics of the VLIW architecture increase the complexity of variable liveness analysis. Traditional liveness analysis algorithms assume isomorphic program representations, making it difficult to handle the mixed state of scheduled and unscheduled code regions existing simultaneously during scheduling. Summary of the Invention

[0007] The technical problem to be solved by the present invention is as follows: In view of the technical problems existing in the prior art, the present invention provides a staged multi-policy instruction scheduling method and system for VLIW architecture with strong scalability, high scheduling efficiency and flexible processor adaptation. It can support the flexible combination and competitive selection of multiple scheduling policies, effectively balance scheduling aggressiveness and register constraints, and at the same time have good processor adaptation capabilities.

[0008] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows: A staged multi-policy instruction scheduling method for VLIW architecture includes the following steps: Step S1. Receive the input program and parse it to construct a hierarchical SAS structure. The SAS structure includes a loop block, a basic block, a label block, and a root block. The loop block represents the loop structure in the program, the basic block represents the sequentially executed instruction sequence, the label block represents the jump target, and the root block serves as the function-level entry node. Step S2. Configure three types of scheduling view interfaces and register the corresponding scheduling strategies. The three types of scheduling view interfaces include a global view interface for global optimization analysis of the entire function, a loop view interface for software pipeline optimization of loop blocks, and a linear view interface for instruction packaging optimization of basic blocks. Step S3. Execute loop view scheduling: Traverse all loop blocks in an inward-outward traversal order, and call the scheduling strategies of all registered loop view interfaces in parallel to generate candidate scheduling schemes. Step S4. Perform linear vision scheduling: After all cyclic blocks have been scheduled, traverse the remaining unscheduled basic blocks. For each basic block, call the scheduling strategies of all registered linear vision interfaces in parallel to generate candidate scheduling schemes. Step S5. After sorting all the currently generated candidate scheduling schemes according to execution performance, the optimal candidate scheduling scheme is selected in turn to construct a Variable State Timeline (VST) for hybrid code state activity analysis. Based on the constructed VST, an Interference Graph (IG) is generated and register allocation is performed. The nodes of the interference graph represent variables that need to be allocated registers, and the edges represent that two variables cannot be allocated to the same physical register. Step S6. Output the current optimized SAS structure. The output includes the scheduled block sequence, each block corresponds to the set of instructions executed in parallel within an execution cycle, and the completed register allocation information.

[0009] Further, in step S5, the scheduling scheme is expanded into a sequence of state nodes indexed by execution cycle through the variable state timeline (VST). Each node in the state node sequence maintains the following variable sets: a USE set for recording variables read by the current node, a DEFU set for recording variables newly defined by the current node that take effect immediately, a DEFW set for recording variables defined but not yet available and within the write-back delay window, an IN set for recording active variables when entering the current node, and an OUT set for recording active variables when leaving the current node. Further, in step S5, the variable state timeline (VST) is constructed using an iterative data flow analysis method, including the following steps: Initialize VST nodes: Traverse all scheduled basic blocks, create a state node for each instruction in each basic block, and for each newly created node, extract the variables read from the current instruction and store them in the USE set, extract the variables written and classify them according to the relationship between the write time and the availability time. If the write time and availability time of the current variable are the same, add the current variable to the DEFU set; otherwise, determine the delay effective interval of the variable according to the write time and availability time, and record the current variable within the delay effective interval in the DEFW set. When the availability time is reached, add the current variable to the DEFU set. Then add the current state node to the VST structure. Construct control flow edges: Traverse all basic blocks, obtain the list of successor blocks for each basic block, and establish a connection between the last node of the current basic block and the first node of each successor basic block. Perform iterative activity analysis: Using a reverse data flow analysis method, iteratively calculate the IN and OUT sets of each node from the end of the VST structure backward. In each iteration, for each node, first save the current IN and OUT sets of the node, and then update them according to the following rules: the OUT set is equal to the union of the IN sets of all successor nodes of the current node; the IN set is equal to the union of the difference between the USE set and the OUT set minus the DEFU set; if the IN set or OUT set of any node changes, it is marked that iteration needs to continue; when the IN and OUT sets of all nodes no longer change, the iteration ends; then, the DEFW set is filled according to the delay effective interval between the write time and the available time of each variable, and the activity analysis is completed. Further, in step S5, generating an interferogram based on the constructed variable state timeline VST includes: Create an empty graph structure as an interferogram; Iterate through all variables in the program that require register allocation, and add variables that have not been pre-allocated physical registers as nodes to the interferogram; Traverse each node in the VST structure. For each node, first calculate the current active variable set by the union of the DEFU set, DEFW set, and OUT set. Then, judge each pair of variables in the DEFU set, each pair of variables in the Cartesian product of the DEFU set and the active variable set, or each pair of variables in the DEFW set. If they are different and belong to the same register class, add an edge connecting the variable pair in the interferogram.

[0010] Furthermore, in step S5, an improved graph coloring algorithm is used to perform register allocation, the steps of which include: During the simplification phase, an empty stack is created to store nodes to be colored. When the interferogram is not empty, the following operations are performed in a loop: calculate the priority of each node, which is defined as the ratio of the node degree to the number of available colors. Select the node with the highest priority, push it onto the stack, and then remove it from the interferogram. When removing a node, update the available color set of all neighboring nodes of the node to be removed. If there is a neighboring node whose available color set is empty, then mark the current neighboring node as a potential overflow candidate node. During the selection phase, an empty overflow list is created. When the stack is not empty, the following operations are performed in a loop: pop the top node of the stack as the current node, collect the colors used by all the colored neighbors of the current node, calculate the available color set of the current node, and if the available colors are not empty, select a color that minimizes future conflicts and assign it to the current node; otherwise, add the current node to the overflow list. If the overflow list is empty, the assignment is successful; otherwise, return the overflow list.

[0011] Furthermore, in step S5, a two-layer evaluation mechanism is used to sort all currently generated candidate scheduling schemes. The first layer calculates a performance score based on the number of execution cycles, the number of instructions executed per cycle, and the utilization rate of functional units of the candidate scheduling scheme, and sorts each candidate scheduling scheme according to the performance score. The second layer arranges candidate scheduling schemes with the same performance according to register pressure, which is calculated based on the maximum number of active variables and available physical registers of the candidate scheduling scheme.

[0012] Furthermore, a competitive selection mechanism is used to select the optimal solution from the ranked candidate scheduling schemes. The steps include: The process involves sequentially traversing each candidate scheduling scheme, temporarily applying the current candidate scheduling scheme to the current code block during each traversal, constructing the variable state timeline (VST) of the current candidate scheduling scheme, building an interferogram based on the VST, and performing register allocation. If the overflow after allocation does not exceed the preset threshold, then recursively verify whether subsequent code blocks can also be successfully allocated. If all are successful, then return the current candidate scheduling scheme as the optimal solution. If the current candidate fails to be verified, then roll back the modification and try the next candidate scheduling scheme. If all candidates fail to be verified, then return the baseline scheduling scheme without optimization.

[0013] Further, step S3 includes: processing from the innermost loop layer by layer outwards using an inward-outward traversal order, wherein loop blocks at the same nesting level are scheduled in parallel using a thread pool, and for each unprocessed loop block, the scheduling policies of all registered loop vision interfaces are called in parallel to generate candidate scheduling schemes. The scheduling policies select to accept or reject the processing of the specified loop block based on pattern matching, and new loop blocks are generated during the scheduling process for subsequent rounds to process; when a loop block has been processed by all policies, it is marked as completed, and the loop vision stage is terminated when there are no unprocessed loop blocks.

[0014] A staged multi-policy instruction scheduling system for VLIW architecture to implement the method described above includes: The SAS parsing module is used to parse input programs and construct the hierarchical symbolic assembly structure SAS. The strategy registration module is used to manage the registration of three types of scheduling strategies: global vision, cyclic vision, and linear vision. The scheduling driver module is used to control the phased execution of the cyclic vision scheduling phase and the linear vision scheduling phase; The evaluation and ranking module is used to perform performance evaluation and ranking of candidate scheduling schemes; The VST analysis module is used to construct variable state timelines (VSTs) and perform mixed code state activity analysis. The register allocation module is used to construct the interferogram based on VST and perform register allocation; The processor adaptation module is used to configure the functional units and instruction semantics of different VLIW processors through the instruction abstraction layer.

[0015] A computer system includes a processor and a memory, the memory being used to store a computer program, and the processor being used to execute the computer program to perform the method described above.

[0016] Compared with the prior art, the advantages of the present invention are as follows: 1. By adopting a configuration of three types of vision and an extensible scheduling strategy registration mechanism, this invention can support the flexible combination or plug-in integration of multiple scheduling algorithms. Different types of code regions can be handled by the most suitable strategy, and the same region can be generated by multiple strategies competing to produce the optimal solution, which can significantly improve the flexibility and optimization effect of scheduling.

[0017] 2. This invention solves the problem of activity analysis for mixed code states by constructing a variable state timeline (VST) for activity analysis. It can fully consider the complex mutual influence between instruction scheduling and register allocation, correctly handle the multi-cycle delay and predicate execution characteristics of the VLIW architecture, and ensure the correctness of register allocation.

[0018] 3. This invention implements a processor-independent scheduling framework through an instruction abstraction layer. It can be adapted to different VLIW processors by replacing the processor description, and has good portability and scalability. At the same time, it can support multi-strategy parallel execution and improve scheduling efficiency by using thread pools. It is especially suitable for compiling and optimizing large-scale programs.

[0019] 4. Furthermore, this invention employs a two-layer evaluation mechanism and a sequential backoff allocation mechanism. Through a competitive selection mechanism, it can also achieve automatic screening of the optimal solution, effectively balancing scheduling aggressiveness and register constraints. This avoids the problems of frequent backtracking or excessive conservatism in traditional methods, thereby improving scheduling success rate and code quality. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall process of the phased multi-policy instruction scheduling method for VLIW architecture according to an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of the vision (GlOpt / CyOpt / LiOpt) strategy registration and scheduling framework in Embodiment 3 of the present invention.

[0022] Figure 3 This is a schematic diagram of the variable state timeline (VST) structure and data flow analysis in an embodiment of the present invention.

[0023] Figure 4 This is a flowchart of the competitive selection and two-layer evaluation mechanism in an embodiment of the present invention.

[0024] Figure 5 This is a schematic diagram of the construction of the interferogram and the allocation of the graph coloring register based on VST in an embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram of the VLIW multiprocessor adaptation architecture based on the Instruct abstraction in an embodiment of the present invention. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0027] like Figure 1 As shown in the figure, the phased multi-policy instruction scheduling method for VLIW architecture in this embodiment includes the following steps: Step S1. SAS Parsing: Receive the input program and parse it to construct a hierarchical SAS (Symbolist Assembly Structure) structure. The SAS structure includes loop blocks, basic blocks, label blocks, and root blocks. Loop blocks represent loop structures in the program, basic blocks represent sequentially executed instruction sequences, label blocks represent jump targets, and root blocks serve as function-level entry nodes.

[0028] In this embodiment, the Symbolic Assembly Structure (SAS) is a unified intermediate representation that uses a hierarchical block structure to represent the program. For example, block types in SAS include: `iblock_root` as the function-level root node; `iblock_loop` representing a loop structure and recording the range of loop iterations; `iblock_base` representing a basic block containing a list of instructions to be executed sequentially; and `iblock_label` representing a jump target label. Instructions in SAS are represented using the `instruct` class and support VLIW packing, meaning that one `instruct` object can contain multiple `instruct_meta` objects representing instructions executed in parallel within the same cycle.

[0029] Step S2. Configure scheduling horizon and register strategy: Configure three types of scheduling horizon interfaces and register the corresponding scheduling strategies. The three types of scheduling horizon interfaces include a global horizon interface for global optimization analysis of the entire function, a loop horizon interface for software pipelining optimization of loop blocks, and a linear horizon interface for instruction packaging optimization of basic blocks.

[0030] In this embodiment, three standardized policy interfaces are defined: the Global Vision Interface (GlOpt) performs global optimization analysis on the entire function; the Cyclic Vision Interface (CyOpt) performs software pipelining optimization on loop blocks; and the Linear Vision Interface (LiOpt) performs instruction packaging optimization on basic blocks. Each interface uses a unified function signature and receives the target code block, metadata manager, configuration options, and a list of output candidate schemes as parameters. Scheduling policies are registered in the policy container as plugins, supporting dynamic configuration at runtime.

[0031] Step S3. Execute loop view scheduling: Traverse all loop blocks in an inward-outward traversal order, and call the scheduling strategies of all registered loop view interfaces in parallel to generate candidate scheduling schemes.

[0032] In this embodiment, during the Cyclic Horizon scheduling phase, the scheduler adopts an inward-to-outward traversal order, processing loops from the innermost loop outwards. For loop blocks at the same nesting level, parallel scheduling using a thread pool can be utilized. For each unprocessed loop block, all registered CyOpt policies are invoked in parallel to generate candidate scheduling schemes. Policies can choose to accept or reject specific loop blocks based on pattern matching, and can generate new loop blocks (such as remainder loops generated by loop unrolling) for subsequent rounds during the scheduling process. A loop block is marked as completed when all policies have processed it; the Cyclic Horizon phase terminates when no unprocessed loop blocks remain.

[0033] Step S4. Perform linear vision scheduling: After all cyclic blocks have been scheduled, traverse the remaining unscheduled basic blocks. For each basic block, call the scheduling strategies of all registered linear vision interfaces in parallel to generate candidate scheduling schemes.

[0034] In this embodiment, during the Linear Horizon scheduling phase, after all cyclic blocks have been scheduled, the scheduler traverses the remaining unscheduled basic blocks. For each basic block, all registered LiOpt strategies are invoked in parallel to generate candidate solutions. Strategies can achieve cross-block scheduling optimization by accessing adjacent code regions. Completed basic blocks are marked as finished to prevent duplicate processing.

[0035] Step S5. After sorting all the candidate scheduling schemes generated so far according to the execution performance, the optimal candidate scheduling scheme is selected in turn to construct a variable state timeline (VST) for mixed code state activity analysis. Based on the constructed variable state timeline (VST), an interferogram is generated and register allocation is performed. The nodes of the interferogram represent variables that need to be allocated registers, and the edges represent variables that cannot be allocated to the same physical register.

[0036] In this embodiment, the constructed Variable State Timeline (VST) is a temporary data structure designed to solve the problem of mixed code state activity analysis. It is used to accurately represent the state changes of variables on the scheduling timeline. By simultaneously tracking multiple states of variables, mixed code state activity analysis is achieved, that is, the mixed existence of multiple variable states is uniformly handled on the timeline, and an interferogram is then constructed for register allocation. Specifically, the scheduling scheme is expanded into a sequence of state nodes indexed by execution cycle through the Variable State Timeline (VST). Each node (stnode) in the state node sequence maintains the following set of variables: The USE collection is used to record the variables read by the current node. DEFU set: Used to record variables newly defined in the current node that take effect immediately in the current node, i.e. variables defined in the previous node that are effective immediately; DEFW set: Used to record variables that have been defined but have not yet reached the available time and are in the write-back delay window; The IN set is used to record active variables when entering the current node. OUT set: Used to record active variables when leaving the current node.

[0037] As an optional implementation, the VST construction process employs an iterative data flow analysis method to accurately calculate the active range of variables. The specific steps are as follows: Initialize VST nodes: Traverse all scheduled basic blocks, creating a state node for each instruction in each basic block; for each newly created node, extract the variables read from the current instruction and store them in the USE set, extract the variables written and classify them according to the relationship between the write time and the availability time: if the write time and availability time of the current variable are the same, add it to the DEFU set; otherwise, determine the delay effective interval of the current variable according to the write time and availability time, and record the variables within the delay effective interval in the DEFW set. When the availability time is reached, add the current variable to the DEFU set, and then add the current node to the VST structure; Construct control flow edges: Traverse all basic blocks, obtain the list of successor blocks for each basic block, and then establish a connection relationship between the last node of the current basic block and the first node of each successor basic block; Perform iterative liveness analysis: Using a reverse data flow analysis method, the IN and OUT sets of each node are calculated iteratively from the end of the VST structure backwards. In each iteration, for each node, its current IN and OUT sets are first saved, and then updated according to the following rules: the OUT set is equal to the union of the IN sets of all successor nodes of the current node; the IN set is equal to the union of the difference between the USE set and the OUT set minus the DEFU set. If the IN or OUT set of any node changes, it is marked that iteration needs to continue. The iteration ends when the IN and OUT of all nodes no longer change; then the DEFW set is filled according to the delay effective interval between the write time and the available time of each variable, and the liveness analysis is completed. In this embodiment, a two-layer evaluation mechanism is first used to rank candidate schemes: the first layer uses the performance evaluation function PerfEval to sort them in descending order by the amount of reduction in execution cycle, and the second layer uses the register pressure evaluation function RegEval to sort schemes with the same performance in ascending order by register pressure; then, starting from the candidate with the best ranking, a variable state timeline (VST) is constructed to perform activity analysis, an interferogram is generated based on the VST and graph coloring register allocation is performed, if the allocation is successful, the scheme is submitted, otherwise it falls back to the next candidate to continue trying, until a scheme that can be successfully allocated is found.

[0038] In this embodiment, the nodes in the interferogram represent variables that need to be allocated to registers, and the edges represent variables that cannot be allocated to the same physical register. Specifically, the interferogram construction rules are: (1) variables in the DEFU set conflict with variables in the DEFU, DEFW, and OUT sets; (2) variables in the DEFW set conflict with each other; (3) conflict edges are only established between variables belonging to the same register class. As an optional implementation, the steps for generating an interferogram based on the constructed variable state timeline VST include: First, create an empty graph structure as the interferogram; Then, iterate through all variables in the program that require register allocation, and add variables that have not been pre-allocated physical registers as nodes to the interferogram.

[0039] Next, each node in the VST is traversed. For each node, the current active variable set is first calculated. This set consists of the union of the three sets DEFU, DEFW, and OUT. That is, the current active variable set is calculated from the union of the DEFU, DEFW, and OUT sets. Then, for each pair of variables in the DEFU set, each pair of variables in the Cartesian product of the DEFU set and the active variable set, or each pair of variables in the DEFW set, a judgment is made. If they are different and belong to the same register class, an edge connecting the variable pair is added to the interferogram. Similarly, for each pair of variables in the DEFU set, if they are different and belong to the same register class, an edge connecting them is added to the interferogram. Furthermore, the same process is performed on each pair of variables in the DEFW set.

[0040] As an optional implementation, an improved graph coloring algorithm is used to perform register allocation. The graph coloring register allocation adopts a priority-based coloring strategy, and the specific process can be divided into the following two stages: During the simplification phase, an empty stack is created to store nodes to be colored. When the interferogram is not empty, the following operations are performed in a loop: calculate the priority of each node, which can be defined as the ratio of the node degree to the number of available colors; select the node with the highest priority, push it onto the stack, and remove it from the interferogram; when removing a node, update the available color set of all neighboring nodes of the node to be removed; if the available color set of a neighbor becomes empty, mark it as a potential overflow candidate node. During the selection phase, an empty overflow list is created. While the stack is not empty, the following operations are performed in a loop: pop the top node from the stack as the current node; collect the colors used by all colored neighbors of the current node; calculate the available color set for the current node (i.e., the physical register set of the corresponding register class minus the used colors); if the available colors are not empty, select a color that minimizes future conflicts and assign it to the node; otherwise, add the current node to the overflow list. If the overflow list is empty, the assignment is successful; otherwise, return the overflow list for further processing.

[0041] As an optional implementation, a two-layer evaluation mechanism is used to sort all currently generated candidate scheduling schemes. The first layer calculates a performance score based on the number of execution cycles, the number of instructions executed per cycle, and the utilization rate of functional units of the candidate scheduling scheme, and sorts the candidate scheduling schemes according to the performance score. The second layer ranks candidate scheduling schemes with the same performance based on register pressure, which is calculated based on the maximum number of active variables and available physical registers of the candidate scheduling scheme.

[0042] Specifically, a performance evaluation function can be used to calculate the performance score. The calculation method for the performance evaluation function is as follows: first, count the number of execution cycles of the candidate scheme; then, calculate the number of instructions executed per cycle (IPC); and finally, calculate the utilization rate of the functional units. The final performance score is a weighted combination of these three indicators, where a lower number of cycles results in a higher score (taking the reciprocal), and higher IPC and functional unit utilization result in a higher score. Register pressure estimation can use a fast approximation algorithm. Specifically, by traversing each program point in the candidate scheme, counting the number of simultaneously active variables at that point, and taking the maximum value among all program points as the maximum number of active variables, then subtracting the maximum number of active variables from the total number of available physical registers. If the difference is positive, it indicates that there is register pressure, and the number of variables that need to overflow is this difference.

[0043] Furthermore, a competitive selection mechanism is used to select the optimal solution from the ranked candidate scheduling schemes: The process involves iterating through each candidate scheduling scheme in sequence, temporarily applying the current candidate scheduling scheme to the current code block during each iteration, constructing the variable state timeline (VST) of the current candidate scheduling scheme, building an interferogram based on the VST, and performing register allocation. If the overflow after allocation does not exceed the preset threshold, then recursively verify whether subsequent code blocks can also be successfully allocated. If all are successful, then return the current candidate scheduling scheme as the optimal solution. If the current candidate fails to be verified, then roll back the modification and try the next candidate scheduling scheme. If all candidates fail to be verified, then return the baseline scheduling scheme without optimization.

[0044] Specifically, a competitive selection mechanism is used to choose the optimal solution from candidate scheduling schemes generated by multiple scheduling strategies. The selection process employs a two-layer evaluation mechanism: the first layer (performance evaluation function PerfEval) evaluates the execution performance of candidate schemes, including metrics such as cycle count, instruction-level parallelism (IPC), and functional unit utilization; the second layer (register evaluation function RegEval) verifies the register allocation feasibility of candidate schemes to ensure that the physical register limit is not exceeded. The specific steps of the competitive selection are as follows: First, a first-level performance evaluation and pre-screening is performed on all candidate scheduling schemes: Each candidate scheme is traversed, and the number of register overflows that the current scheme may require is calculated using a fast register pressure estimation method. If the number of overflows does not exceed the maximum allowed overflow threshold, the performance score of the current scheme is calculated and added to the valid candidate list. Then, the valid candidate list is sorted in descending order according to the performance score.

[0045] Next, a second-level detailed register allocation verification is performed on the sorted candidates. Each candidate scheme is traversed sequentially. First, the current scheme is temporarily applied to the current code block. Then, a variable state timeline (VST) is constructed for that scheme. An interferogram is built based on the VST, and graph coloring register allocation is performed. If the overflow after allocation does not exceed a threshold, subsequent code blocks are recursively verified to ensure successful allocation. If all are successful, the current candidate is returned as the optimal solution. If the current candidate verification fails, the modification is rolled back, and the next candidate is tried. If all candidates fail verification, the unoptimized baseline scheduling scheme (NOP scheme) is returned, ensuring the scheduling process always completes.

[0046] Traditional schedulers require precise estimation of register requirements during the scheduling phase; inaccurate estimations can lead to scheduling failures or costly backtracking. This embodiment employs a sequential backtracking register allocation mechanism, enabling generation followed by verification. This allows the scheduling strategy to explore aggressive scheduling schemes without worrying about register constraints. The register evaluation function RegEval pre-screening and the sequential backtracking mechanism ensure that an allocatable scheme is eventually found. Due to the effective pre-screening by RegEval, an allocatable scheme can be quickly found among the first 15-20 candidate scheduling schemes.

[0047] Step S6. Output the current optimized SAS structure. The output includes the scheduled block sequence, each block corresponds to the set of instructions executed in parallel within an execution cycle, and the completed register allocation information.

[0048] In a specific application embodiment, when using the above-described method of the present invention to implement phased multi-policy instruction scheduling for VLIW architecture, during step S2, when configuring the three types of scheduling views and registering scheduling policies, as follows: Figure 2 As shown, three types of standardized policy interfaces are defined: (1) The global view is used to perform analysis and optimization across the entire function, such as dominance tree construction and global code movement. Specifically, the global view interface GiOpt can be defined as: using GiOpt = void(*)(const iblock_root&, const argmgr&, const option&, list<tmpouts_meta> &), where iblock_root is the function-level root node, argmgr is the variable metadata manager, option is the configuration options, and list<tmpouts_meta> Used to store candidate solutions.

[0049] (2) The Cyclic view is used to perform software pipeline-related optimizations, such as Modulo Scheduling and Loop Unrolling. Specifically, the Cyclic view interface CyOpt can be defined as: using CyOpt = void(*)(const iblock_loop&, const argmgr&, const option&, list<tmpouts_meta> &), where iblock_loop is the target loop block.

[0050] (3) Linear vision is used to perform instruction scheduling optimizations within basic blocks, such as list scheduling and TDLS (Top-Down List Scheduling). Specifically, the linear vision interface LiOpt is defined as: using LiOpt = void(*)(const iblock_base&, const argmgr&, const option&, list<tmpouts_meta> &), where iblock_base is the target basic block.

[0051] Scheduling policies are registered to the corresponding policy containers through the Driver class. Specifically, gbox_ stores the GiOpt policy, lbox_ stores the CyOpt policy, and bbox_ stores the LiOpt policy. Policies are stored as function pointers, supporting dynamic configuration at runtime.

[0052] In a specific application embodiment, when using the above-described method of the present invention to implement phased multi-policy instruction scheduling for VLIW architecture, in step S3, the loop-view scheduling stage, the scheduler function loop_optimizer() implements multi-round progressive scheduling, and loop-view scheduling is achieved through temporary VST / OUT analysis and candidate pre-sorting. The detailed steps are as follows: First, traverse_post is called to traverse the SAS, collecting all unscheduled loop blocks that do not contain scheduled blocks into the list lps in post-order traversal, to ensure that the innermost loop is processed first.

[0053] Then, the preparation process begins, which calls _base_block_data_analysis to perform basic block data flow analysis. The set of active exit variables OUT for each basic block is calculated through a temporary VST, providing dependency information for candidate generation in the recurrent vision stage.

[0054] Next, `loop_solution` is called to recursively process the list of loop blocks. For each loop block, the `nop` strategy is first called to generate a baseline solution without optimization. Then, depending on the number of strategies, a thread pool is used for parallel execution. When there are at least two strategies, `ThreadPoolManager` is used to submit tasks for parallel execution of each `CyOpt` strategy; otherwise, they are executed sequentially to reduce thread overhead. The outputs of each strategy are aggregated into `reslist`, and then `tmpouts::insert` is called to pre-sort the candidate solutions based on `beatn_dec`, `varn`, and `evl_unitu` to form a candidate queue for subsequent competitive verification.

[0055] Finally, candidate schemes are tried in the pre-sorted order: `swap_a` is called to apply the scheme to the SAS, and the remaining loop blocks are processed recursively; during the candidate verification phase, `regalloc::alloc2` is used to construct the VST of the current scheduling state, generate an interferogram, and perform register allocation. If verification is successful, `swap_b` is called to confirm the scheme; otherwise, `revoke` is called to roll back and try the next candidate. After the loop block is processed, `disable()` is marked to prevent duplicate processing. When `loop_optimizer` returns, it checks if there are any newly generated loop blocks; if so, a new round of scheduling is executed.

[0056] In a specific application embodiment, when implementing phased multi-policy instruction scheduling for VLIW architecture using the above-described method of the present invention, the detailed steps of the scheduler function base_optimizer() in processing the remaining basic blocks during step S4, when executing the linear vision scheduling phase, are as follows: First, iterate through the SAS to collect all unscheduled basic blocks (excluding barrier blocks and empty blocks) into the list base_bs.

[0057] Then, the `base_solution` method is called recursively to process the list of basic blocks. The processing flow is similar to that of the cyclic vision stage: for each basic block, a nop baseline scheme is first generated, then all LiOpt policies are executed in parallel, candidate schemes are aggregated and organized into a candidate queue according to the pre-evaluation results, and then each candidate is tried in the same order of VST verification and register allocation as in step S5, until a scheme that can be successfully allocated is found. In particular, the linear vision stage can be configured not to perform register allocation verification (with the `_last` flag) when processing the last candidate, allowing the use of the nop scheme to ensure scheduling completion in the worst case.

[0058] like Figure 3 As shown, in a specific application embodiment, the construction process of the variable state timeline (VST) is as follows: First, the instruction sequence in the scheduling scheme is traversed, and a state node (stnode) is created for each execution cycle to record the instruction list for that cycle. The successor relationship between state nodes is determined based on control flow analysis: when executing sequentially, Succ(S[t]) = {S[t+1]}, while branch instructions include the jump target and the fall into the successor.

[0059] Then, according to Algorithm 2, a three-phase process is executed: Phase 1 traverses all instructions to initialize the USE set, and adds the definitions that take effect immediately to the DEFU set of the corresponding state node according to the write time and availability time of the defined variables, while determining the target node for the delayed definition; Phase 2 calculates the IN and OUT sets through reverse iteration until the fixed point, and the data flow equation is OUT(S[t])=∪IN(Succ(S[t])), IN(S[t])=USE(S[t])∪(OUT(S[t])-DEFU(S[t])); Phase 3 fills the DEFW set according to the delayed effective interval between the write time and the availability time of each variable.

[0060] like Figure 4 As shown, in a specific application embodiment, the method employing a two-layer evaluation mechanism and a sequential rollback allocation mechanism is as follows: The two-layer evaluation mechanism implements candidate pre-sorting in the `tmpouts::insert` function. Each candidate scheme calculates evaluation factors (EvalFactors) using `tmpouts_meta::finalize`, including: `beatn_org` (the number of execution cycles in the unscheduled baseline), `beatn_dec` (the number of cycles reduced after scheduling, i.e., optimization gain), `varn` (the number of variables used in the scheme), and `isize` (the total instruction size). During insertion, `beatn_dec` is compared first, with schemes showing a larger cycle reduction ranking higher. For schemes with the same `beatn_dec`, `varn` (as a proxy indicator of register pressure) is compared, with schemes having fewer variables ranking higher. Furthermore, the `evl_unitu` metric is used to evaluate functional unit utilization as a further subdivision criterion.

[0061] Sequential rollback allocation is implemented in the `loop_solution` and `base_solution` functions. For the sorted candidate list, attempts are made starting with the top-ranked candidate: when `regalloc::alloc2` or `alloc3` is called, a VST is constructed for the current scheduling state, an interferogram is generated based on the VST, and register allocation is performed. If the allocation is successful (the number of failures does not exceed the `MAX_REG_SPILL` threshold), the solution is submitted; otherwise, `revoke` is called to roll back and `tmpouts::next` is used to jump to the next advantageous candidate (solving solutions that are not better than the current failed candidate because they are less likely to be allocated successfully).

[0062] like Figure 5 As shown, in a specific application embodiment, the method for constructing an interferogram based on VST and performing graph coloring assignment is as follows: The nodes of the interferogram IG represent all variables that need to be assigned. The construction rule for the interferometer edges is: ∪{DEFU(S[t])×(DEFU(S[t])∪DEFW(S[t])∪OUT(S[t])) ∪ DEFW(S[t])×DEFW(S[t])}, where A×B={(x,y)|x∈A,y∈B,x≠y}. The first term captures conflicts between immediately effective definitions in the current node and exit active variables, delayed effective definitions, and other immediately effective definitions in the same period. The second term captures conflicts between definitions waiting to take effect within the delayed effective window.

[0063] Register allocation uses a standard graph coloring algorithm: colors (physical registers) are assigned to nodes in the interferogram, and adjacent nodes cannot use the same color. The allocation process considers register class constraints (different types of variables use different register files) and pre-coloring constraints (some variables have already been assigned physical registers).

[0064] Furthermore, this embodiment implements a processor-independent scheduling framework based on the instruction abstraction layer. The instruction abstraction layer defines the `instruct` class as an instruction container to support VLIW packaging, the `instruct_meta` class to store instruction metadata (mnemonic, functional unit, execution cycle, encoding bit width), and the `operand` class to abstract operands (registers, immediate values, memory). The processor description layer configures the functional units, instruction semantics, and encoding rules of a specific processor, allowing adaptation to different VLIW processors by replacing the processor description.

[0065] like Figure 6 As shown, this embodiment implements a processor-independent scheduling framework through an instruction abstraction layer. The instruction abstraction layer is defined as follows: the `instruct` class serves as an instruction container, containing a list...<instruct_meta> Supports VLIW packing; the `instruct_meta` class stores instruction metadata, including references to `ms::instruct_case` (providing mnemonic and semantic information), function unit assignments (FUnits), and operand lists. <operand>The `operand` class abstracts operands, including format (register X, immediate I, memory M, etc.) and metadata (variable ID vnu, read / write mode mode). The processor description layer configures specific processor parameters: `ms::funit` describes the number, type, and supported instructions of functional units; `ms::instruct_case` describes the instruction syntax, operand constraints, and encoding rules; `argmgr` manages the mapping between variables and register classes. By replacing the processor description layer configuration, the upper-layer SAS representation and scheduling algorithms can be adapted to different VLIW processors without modification.

[0066] This embodiment further provides a staged multi-policy instruction scheduling system for VLIW architecture to implement the above method. This system includes a SAS parsing module, a policy registration module, a scheduling driver module, an evaluation and sorting module, a VST analysis module, a register allocation module, and a processor adaptation module. The SAS parsing module is responsible for parsing the input program to construct a hierarchical SAS representation; the policy registration module manages the registration of policies for three types of visions: global vision, cyclic vision, and linear vision; the scheduling driver module controls the staged execution of the cyclic vision scheduling stage and the linear vision scheduling stage, implementing the Driver class to control the staged scheduling process; the evaluation and sorting module performs performance evaluation and sorting of candidate scheduling schemes, implementing two-level evaluation and sorting for the tmpouts class; the VST analysis module constructs a variable state timeline (VST) and performs mixed code state activity analysis, implementing activity analysis for the VST and stnode classes; the register allocation module constructs an interferogram based on the VST and performs register allocation, implementing interferogram construction for the IG class and graph coloring allocation for the regalloc class; the processor module configures the functional units and instruction semantics of different VLIW processors through the instruction abstraction layer, and the adaptation module encapsulates the processor description under the ms namespace.

[0067] This embodiment further provides a computer system, including a processor and a memory, wherein the memory is used to store a computer program and the processor is used to execute the computer program to perform the method as described above.

[0068] Those skilled in the art will understand that the above embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, produce implementations of the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process. Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.< / operand>

Claims

1. A staged multi-policy instruction scheduling method for VLIW architecture, characterized by the following steps: include: Step S1. Receive the input program and parse it to construct a hierarchical SAS structure. The SAS structure includes a loop block, a basic block, a label block, and a root block. The loop block represents the loop structure in the program, the basic block represents the sequentially executed instruction sequence, the label block represents the jump target, and the root block serves as the function-level entry node. Step S2. Configure three types of scheduling view interfaces and register the corresponding scheduling strategies. The three types of scheduling view interfaces include a global view interface for global optimization analysis of the entire function, a loop view interface for software pipeline optimization of loop blocks, and a linear view interface for instruction packaging optimization of basic blocks. Step S3. Execute loop view scheduling: Traverse all loop blocks in an inward-outward traversal order, and call the scheduling strategies of all registered loop view interfaces in parallel to generate candidate scheduling schemes. Step S4. Perform linear vision scheduling: After all cyclic blocks have been scheduled, traverse the remaining unscheduled basic blocks. For each basic block, call the scheduling strategies of all registered linear vision interfaces in parallel to generate candidate scheduling schemes. Step S5. After sorting all the candidate scheduling schemes generated so far according to the execution performance, the optimal candidate scheduling scheme is selected in turn to construct a variable state timeline (VST) for mixed code state activity analysis. Based on the constructed variable state timeline (VST), an interferogram is generated and register allocation is performed. The nodes of the interferogram represent variables that need to be allocated registers, and the edges represent that two variables cannot be allocated to the same physical register. Step S6. Output the current optimized SAS structure. The output includes the scheduled block sequence, each block corresponds to the set of instructions executed in parallel within an execution cycle, and the completed register allocation information.

2. The staged multi-policy instruction scheduling method for VLIW architecture according to claim 1, characterized in that, In step S5, the scheduling scheme is expanded into a sequence of state nodes indexed by execution cycle through the variable state timeline VST. Each node in the state node sequence maintains the following variable sets: a USE set for recording variables read by the current node, a DEFU set for recording variables newly defined by the current node that can take effect at the current node, a DEFW set for recording variables that have been defined but have not yet reached the available time and are in the write-back delay window, an IN set for recording active variables when entering the current node, and an OUT set for recording active variables when leaving the current node.

3. The staged multi-policy instruction scheduling method for VLIW architecture according to claim 2, characterized in that, In step S5, the variable state timeline (VST) is constructed using an iterative data flow analysis method. The steps include: Initialize VST nodes: Traverse all scheduled basic blocks, create a state node for each instruction in each basic block, and for each newly created node, extract the variables read from the current instruction and store them in the USE set, extract the variables written and classify them according to the relationship between the write time and the availability time. If the write time and availability time of the current variable are the same, add the current variable to the DEFU set; otherwise, determine the delay effective interval of the variable according to the write time and availability time, and record the current variable within the effective interval in the DEFW set. When the availability time is reached, add the current variable to the DEFU set. Then add the current state node to the VST structure. Construct control flow edges: Traverse all basic blocks, obtain the list of successor blocks for each basic block, and establish a connection between the last node of the current basic block and the first node of each successor basic block. Perform iterative liveness analysis: Using a reverse data flow analysis method, iteratively calculate the IN and OUT sets of each node from the end of the VST structure backward. In each iteration, for each node, first save the current IN and OUT sets of the node, and then update them according to the following rules: the OUT set is equal to the union of the IN sets of all successor nodes of the current node; the IN set is equal to the union of the difference between the USE set and the OUT set minus the DEFU set; if the IN set or OUT set of any node changes, it is marked that iteration needs to continue; when the IN and OUT sets of all nodes no longer change, the iteration ends; fill the DEFW set according to the delay effective interval between the write time and the available time of each variable, and the liveness analysis is completed.

4. The staged multi-policy instruction scheduling method for VLIW architecture according to claim 3, characterized in that, In step S5, generating an interferogram based on the constructed variable state timeline VST includes: Create an empty graph structure as an interferogram; Iterate through all variables in the program that require register allocation, and add variables that have not been pre-allocated physical registers as nodes to the interferogram; Traverse each node in the VST structure. For each node, first calculate the current active variable set by the union of the DEFU set, DEFW set, and OUT set. Then, judge each pair of variables in the DEFU set, each pair of variables in the Cartesian product of the DEFU set and the active variable set, or each pair of variables in the DEFW set. If they are different and belong to the same register class, add an edge connecting the variable pair in the interferogram.

5. The staged multi-policy instruction scheduling method for VLIW architecture according to claim 1, characterized in that, In step S5, an improved graph coloring algorithm is used to perform register allocation. The steps include: During the simplification phase, an empty stack is created to store nodes to be colored. When the interferogram is not empty, the following operations are performed in a loop: calculate the priority of each node, which is defined as the ratio of the node degree to the number of available colors. Select the node with the highest priority, push it onto the stack, and then remove it from the interferogram. When removing a node, update the available color set of all neighboring nodes of the node to be removed. If there is a neighboring node whose available color set is empty, then mark the current neighboring node as a potential overflow candidate node. During the selection phase, an empty overflow list is created. When the stack is not empty, the following operations are performed in a loop: pop the top node of the stack as the current node, collect the colors used by all the colored neighbors of the current node, calculate the available color set of the current node, and if the available colors are not empty, select a color that minimizes future conflicts and assign it to the current node; otherwise, add the current node to the overflow list. If the overflow list is empty, the assignment is successful; otherwise, return the overflow list.

6. The staged multi-policy instruction scheduling method for VLIW architecture according to any one of claims 1 to 5, characterized in that, In step S5, a two-layer evaluation mechanism is used to sort all the candidate scheduling schemes generated so far. The first layer calculates a performance score based on the number of execution cycles, the number of instructions executed per cycle, and the utilization rate of functional units of the candidate scheduling scheme, and sorts each candidate scheduling scheme according to the performance score. The second layer arranges candidate scheduling schemes with the same performance according to register pressure, which is calculated based on the maximum number of active variables and available physical registers of the candidate scheduling scheme.

7. The staged multi-policy instruction scheduling method for VLIW architecture according to claim 6, characterized in that, The optimal solution is selected using a competitive selection mechanism from the ranked candidate scheduling schemes. The steps include: The process involves sequentially traversing each candidate scheduling scheme, temporarily applying the current candidate scheduling scheme to the current code block during each traversal, constructing the variable state timeline (VST) of the current candidate scheduling scheme, building an interferogram based on the VST, and performing register allocation. If the overflow after allocation does not exceed the preset threshold, then recursively verify whether subsequent code blocks can also be successfully allocated. If all are successful, then return the current candidate scheduling scheme as the optimal solution. If the current candidate fails to be verified, then roll back the modification and try the next candidate scheduling scheme. If all candidates fail to be verified, then return the baseline scheduling scheme without optimization.

8. The staged multi-policy instruction scheduling method for VLIW architecture according to any one of claims 1 to 5, characterized in that, Step S3 includes: processing from the innermost loop layer by layer outwards in an inward-to-outward traversal order. This involves using a thread pool to schedule loop blocks at the same nesting level in parallel. For each unprocessed loop block, the scheduling strategies of all registered loop vision interfaces are called in parallel to generate candidate scheduling schemes. The scheduling strategies select to accept or reject the processing of the specified loop block based on pattern matching, and new loop blocks are generated during the scheduling process for subsequent rounds. A loop block is marked as completed after all strategies have processed it. The loop vision phase terminates when there are no unprocessed loop blocks.

9. A staged multi-policy instruction scheduling system for a VLIW-oriented architecture for implementing the method of any one of claims 1 to 7, characterized in that, include: The SAS parsing module is used to parse input programs and build hierarchical SAS structures. The strategy registration module is used to manage the registration of three types of scheduling strategies: global vision, cyclic vision, and linear vision. The scheduling driver module is used to control the phased execution of the cyclic vision scheduling phase and the linear vision scheduling phase; The evaluation and ranking module is used to perform performance evaluation and ranking of candidate scheduling schemes; The VST analysis module is used to construct variable state timelines (VSTs) and perform mixed code state activity analysis. The register allocation module is used to construct the interferogram based on VST and perform register allocation; The processor adaptation module is used to configure the functional units and instruction semantics of different VLIW processors through the instruction abstraction layer.

10. A computer system comprising a processor and a memory, the memory being used to store computer programs, characterized in that, The processor is used to execute the computer program to perform the method as described in any one of claims 1 to 8.

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